Display device and display panel

Abstract

Disclosed are a display device and a display panel. The display device includes: a substrate; a plurality of light emitting elements provided on the substrate and each including a first electrode and a second electrode; a first planarization layer provided on the substrate to surround a part of side surfaces of the plurality of light emitting elements; a first connection electrode provided on the first planarization layer and connected to the first electrode; a passivation layer provided on the first connection electrode; a second planarization layer provided on a part of the first planarization layer, the first connection electrode, and the passivation layer; and a second connection electrode provided on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end portion of the first connection electrode. Thus, short circuit defects can be minimized.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device and display panel in which short-circuit defects between electrodes are minimized. Background Technology

[0002] Display devices used for monitors in mobile phones, televisions, or computers include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0003] Display devices have been used in a variety of applications, including computer monitors and TVs, as well as personal portable devices, and research is underway on display devices with large display areas and reduced size and weight.

[0004] In addition, display devices including light-emitting diodes (LEDs) have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they offer superior reliability and a longer lifespan than liquid crystal displays or organic light-emitting displays. Furthermore, LEDs have a fast emission speed, excellent luminous efficiency, and strong shock resistance, resulting in excellent stability and the ability to display high-brightness images.

[0005] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0006] The inventors have recognized that connection defects between electrodes can occur in display devices in related technologies. Therefore, the object of this disclosure is to provide a display device that enables self-alignment between the connecting electrodes and the light-emitting element.

[0007] The objective of this disclosure is to provide a display device in which short-circuit defects between connecting electrodes are minimized.

[0008] The objective of this disclosure is to provide a display device that suppresses short-circuit defects that require low-power operation in order to reduce power consumption.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to embodiments of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels, each light-emitting element including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connection electrode disposed on and connected to the first planarization layer; a passivation layer disposed on the first connection electrode; a second planarization layer disposed on the first planarization layer, the first connection electrode, and a portion of the passivation layer; and a second connection electrode disposed on and connected to the second electrode in the second planarization layer, wherein the passivation layer exposes an end of the first connection electrode. Therefore, short-circuit defects can be minimized.

[0011] According to another embodiment of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode disposed at a position higher than the first electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a second planarization layer disposed on the first planarization layer and the first connecting electrode; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode.

[0012] According to another embodiment of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels, each light-emitting element including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on at least a portion of the first planarization layer, the first connecting electrode, and the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode, wherein the plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and wherein the height of the uppermost end of the second planarization layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second planarization layer disposed in the first sub-pixel.

[0013] According to another embodiment of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on the first planarization layer, the first connecting electrode, and a portion of the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode.

[0014] According to another embodiment of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode disposed at a position higher than the first electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a second planarization layer disposed on the first planarization layer and the first connecting electrode; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode.

[0015] According to another embodiment of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels, each light-emitting element including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on at least a portion of the first planarization layer, the first connecting electrode, and the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode, wherein the plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and wherein the height of the uppermost end of the second planarization layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second planarization layer disposed in the first sub-pixel.

[0016] Further details of the implementation methods are included in the detailed description and accompanying drawings.

[0017] According to embodiments of this disclosure, the first connecting electrode and the second connecting electrode are connected to the light-emitting element in a self-aligned manner through the ashing process of the first planarization layer and the second planarization layer, without the need for a separate alignment process, thereby ensuring transfer margin.

[0018] According to embodiments of the present disclosure, a passivation layer is disposed on the first connection electrode to separate the first connection electrode and the second connection electrode, thereby preventing short-circuit defects between the first connection electrode and the second connection electrode.

[0019] According to embodiments of this disclosure, a planarization layer fills the space between the passivation layer and the light-emitting element to cover the first connection electrode exposed by the passivation layer, thereby preventing short-circuit defects in the connection between the first connection electrode and the second connection electrode by separating the first connection electrode and the second connection electrode.

[0020] According to embodiments of this disclosure, even if the planarization layer is set below the passivation layer disposed on the first connection electrode, the space between the passivation layer and the light-emitting element is filled with an organic pattern to cover the first connection electrode exposed by the passivation layer, thereby separating the first connection electrode and the second connection electrode to prevent short-circuit defects in the connection between the first connection electrode and the second connection electrode.

[0021] According to embodiments of this disclosure, potential defects caused by short-circuit defects are minimized and the lifespan of the display device is improved, enabling the display device to be driven at low power in terms of reduced power consumption.

[0022] The effects of this disclosure are not limited to the examples above, and many more effects are included in this disclosure. Attached Figure Description

[0023] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0024] Figure 2A This is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0025] Figure 2B This is a perspective view of a splicing display device according to an exemplary embodiment of the present disclosure.

[0026] Figure 3 This is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0027] Figure 4 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0028] Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a flowchart for explaining a method of manufacturing a display device according to another exemplary embodiment of the present disclosure.

[0029] Figure 6 This is a cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure.

[0030] Figure 7 This is a cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure.

[0031] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0032] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The progression of the processing steps and / or operations described are illustrative; however, the order of the steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been chosen merely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0033] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0034] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. shown in the accompanying drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0035] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0036] Furthermore, in the following description of this disclosure, detailed explanations of known related techniques may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “composed of”, and “component of” as used herein are generally intended to allow for the addition of other components, unless the term is used in conjunction with the term “only.” Unless otherwise expressly indicated, any reference to the singular may include the plural.

[0037] Even if not explicitly stated, components are interpreted as including a normal tolerance range.

[0038] When using terms such as “on top of,” “above,” “below,” and “adjacent to” to describe the positional relationship between two parts, one or more parts may be positioned between the two parts, unless these terms are used with the terms “exactly” or “directly.”

[0039] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0040] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, in the technical concept of this disclosure, the first component referred to below may be the second component.

[0041] The word “exemplary” is used to indicate that something is an example or illustration. “Aspect” refers to an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or best of other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the word “may” encompasses all the meanings of the word “able to.”

[0042] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related projects. For example, "at least one of the first, second, or third projects" can mean each of the first, second, or third projects, and can also mean all possible combinations that can be suggested from two or more of the first, second, and third projects.

[0043] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0044] Throughout the disclosure, similar reference numerals generally denote similar elements. In the specification, when adding reference numerals to elements in each figure, care should be taken that whenever possible, the same reference numerals already used to denote an element in other figures are used for that element. Furthermore, for ease of description, the scale of the constituent elements shown in the figures may differ from the actual scale. That is, the scale of the constituent elements shown in the figures should not be interpreted as the same as the scale shown in the figures.

[0045] Features of the various embodiments of this disclosure may be partially or completely bonded or combined with each other, and may be interlocked and operated in technically different ways, and the embodiments may be performed independently or in association with each other.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any aspect of this disclosure can be a drain electrode in another aspect of this disclosure, and a drain electrode in any aspect of this disclosure can be a source electrode in another aspect of this disclosure.

[0048] The contents of this disclosure will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of description, among the various components of the display device 100, only the display panel PN, the gating driver GD, the data driver DD, and the timing controller TC are shown.

[0050] Reference Figure 1 The display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP, a gating driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gating driver GD and the data driver DD.

[0051] The gating driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gating control signals provided by the timing controller TC. Figure 1A gating driver GD is shown configured to be spaced apart from one side of the display panel PN. However, the number and arrangement of gating drivers GD are not limited to this.

[0052] The data driver DD converts image data input from the timing controller TC into a data voltage using a reference gamma voltage, based on multiple data control signals provided from the timing controller TC. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0053] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gating control signals and data control signals using externally input synchronization signals (e.g., dot clock signals, data enable signals, and horizontal / vertical sync signals). Here, the horizontal sync signal indicates the time taken to display a horizontal line on the screen, and the vertical sync signal indicates the time taken to display one frame. The data enable signal can correspond to a signal indicating the time period for supplying data voltage to the pixels. Furthermore, the timing controller TC supplies the generated gating control signals and data control signals to the gating driver GD and the data driver DD, respectively, to control them.

[0054] The display panel PN is configured to display an image to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and each of the multiple subpixels SP is connected to both the scan lines SL and the data lines DL. Additionally, although not shown in the accompanying drawings, each of the multiple subpixels SP may be connected to high-potential power lines, low-potential power lines, and reference lines, etc.

[0055] In the display panel PN, a display area AA and a non-display area NA surrounding the display area AA can be defined.

[0056] The display area AA is the area in the display device 100 where an image is displayed. Within the display area AA, multiple sub-pixels SP constituting multiple pixels PX and circuitry for driving these sub-pixels SP can be provided. The multiple sub-pixels SP are the smallest unit constituting the display area AA, and N sub-pixels SP can form one pixel PX. In each of the multiple sub-pixels SP, a light-emitting element, such as a thin-film transistor for driving the light-emitting element, can be provided.

[0057] The active layer of a transistor can be formed from semiconductor materials, such as oxide semiconductors, amorphous semiconductors, or polycrystalline semiconductors, but is not limited to these.

[0058] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0059] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0060] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0061] Multiple light-emitting elements can be defined differently depending on the type of display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting elements can be light-emitting elements (LEDs) or micro-light-emitting elements (micro-LEDs).

[0062] In the display area AA, multiple signal lines are provided for sending various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL supplying data voltage to each of the multiple sub-pixels SP, and multiple scan lines SL supplying gating voltage to each of the multiple sub-pixels SP, etc. The multiple scan lines SL may extend in one direction and connect to the multiple sub-pixels SP in the display area AA, and the multiple data lines DL may extend in the display area AA and connect to the multiple sub-pixels SP in a direction different from the stated one direction. In addition, low-potential power lines and high-potential power lines may also be provided in the display area AA, but it is not limited to these.

[0063] The non-display area NA is the area in which no image is displayed, and can be defined as the area extending from the display area AA.

[0064] The non-display area NA can be a region adjacent to the display area AA. Further, the non-display area NA can be a region adjacent to and configured to surround the display area AA. For example, the non-display area NA can be located in the edge region surrounding the display area AA displaying the image. However, this disclosure is not limited thereto.

[0065] For example, the non-display area NA may include a first non-display area located outside the display area AA along a first direction, a second non-display area located outside the display area AA along a second direction intersecting the first direction, a third non-display area located outside the display area AA along a direction opposite to the first direction, and a fourth non-display area located outside the display area AA along a direction opposite to the second direction.

[0066] For example, the boundary between the display area AA and the non-display area NA can be curved, allowing the non-display area NA to lie below the display area. In this case, when a user looks at the display device from the front, little or no non-display area NA may be visible to the user.

[0067] In the non-display area NA, link lines and pad electrodes for sending signals to the sub-pixels SP of the display area AA can be provided, or driver ICs such as gating driver ICs or data driver ICs can be provided. The non-display area NA can be located on the rear surface of the display panel PN, that is, the surface on which no sub-pixels SP are set can be omitted or omitted, and is not limited to what is shown in the figure.

[0068] Furthermore, drivers such as the gating driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gating driver GD can be installed in the non-display area NA in a gated-in-panel (GIP) manner, or between multiple sub-pixels SP in the display area AA in a gated-in-display-area (GIA) manner. For example, the data driver DD and timing controller TC are formed in separate flexible films and printed circuit boards, and can be electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. If the gating driver GD is installed in a GIP manner, and the data driver DD and timing controller TC send signals to the display panel PN through the pad electrodes of the non-display area NA, it is necessary to ensure the area of ​​the non-display area NA used to set the gating driver GD and the pad electrodes, and the bezel may be increased.

[0069] Conversely, when the pass driver GD is mounted in the display area AA in a GIA configuration and forms a side line SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. That is, when the pass driver GD, data driver DD, and timing controller TC are connected to the display panel PN as described above, a zero-bezel configuration with virtually no border can be achieved, and the reference... Figure 2A and2B Please provide a more detailed description.

[0070] Figure 2A This is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B This is a perspective view of a splicing display device according to an exemplary embodiment of the present disclosure.

[0071] In the non-display area NA of the display panel PN, multiple pad electrodes are provided for sending various signals to multiple sub-pixels SP. For example, a first pad electrode PAD1 for sending signals to multiple sub-pixels SP is provided in the non-display area NA on the front surface of the display panel PN, and a second pad electrode PAD2 electrically connected to driving components such as flexible films and printed circuit boards is provided in the non-display area NA on the rear surface of the display panel PN.

[0072] In this case, although not shown in the accompanying drawings, various signal lines, such as scan lines SL or data lines DL, connected to multiple sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0073] Furthermore, a side line SRL is disposed along the side surface of the display panel PN. The side line SRL can electrically connect a first pad electrode PAD1 on the front surface of the display panel PN and a second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving components on the rear surface of the display panel PN can be transmitted to multiple sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Thus, a signal transmission path is formed from the front surface to the side and rear surfaces of the display panel PN, minimizing the area of ​​the non-display area NA of the display panel PN.

[0074] In addition, refer to Figure 2B A large-screen splicing display device TD can be realized by connecting multiple display devices 100. In this case, when using, for example... Figure 2A When the display device 100 with minimized bezel is used to implement the splicing display device TD, the seam area where the image is not displayed between the display devices 100 is minimized, thereby improving the display quality.

[0075] For example, multiple sub-pixels SP can form a pixel PX, and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another display device 100 adjacent to one display device 100 can be implemented as equal to the distance D1 between pixels PX in one display device 100. Therefore, the distance between pixels PX between display devices 100 and display devices 100 is constantly configured to minimize the seam area.

[0076] Multiple subpixels SP can be composed of red (R) subpixels, green (G) subpixels, and blue (B) subpixels, or they can be composed of red (R) subpixels, green (G) subpixels, blue (B) subpixels, and white (W) subpixels. However, this disclosure is not limited to this. Multiple subpixel SPs constituting a unit pixel can be modified in various ways in terms of color and configuration as needed.

[0077] For example, each of the plurality of sub-pixels SP can emit light with a different wavelength from each other. For example, the plurality of sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the red, green, and blue sub-pixels may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SP may include red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels may be arranged in a repeating manner, or the red, green, blue, and white sub-pixels may be arranged in a quadrilateral pattern. For example, the red, blue, and green sub-pixels may be arranged sequentially along the row direction, or the red, blue, green, and white sub-pixels may be arranged sequentially along the row direction. However, in embodiments of this disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited and can be configured in various forms according to light-emitting characteristics, device lifetime, and device specifications.

[0078] Furthermore, depending on their light-emitting characteristics, sub-pixels can have different light-emitting areas. For example, a sub-pixel that emits light of a different color than the blue sub-pixel can have a different light-emitting area than the blue sub-pixel. For example, red, blue, and green sub-pixels, or red, blue, white, and green sub-pixels, can each have different light-emitting areas.

[0079] However, Figure 2A and 2B This is illustrative, so that the display device 100 according to the exemplary embodiments of this disclosure may be a general display device with a bezel, but is not limited thereto.

[0080] Figure 3 This is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. For example, Figure 3 It is a cross-sectional view of a sub-pixel SP.

[0081] Reference Figure 3In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a passivation layer 114, an outer coating layer 115, an adhesive layer 116, a first planarization layer 117a, a second planarization layer 117b, a black embankment BB, a third planarization layer 118, a driving transistor DT, a power line VL, a light-emitting element LED, a plurality of reflective electrodes RE, an auxiliary electrode LE, a plurality of first connection electrodes CE1, and a plurality of second connection electrodes CE2 may be provided.

[0082] First, the substrate 110 is a component for supporting various parts included in the display device 100, and can be made of an insulating material. For example, the substrate 110 can be made of glass, resin, etc. Additionally, the substrate 110 can include a polymer or plastic, or can be made of a flexible material. For example, the substrate 110 can include a flexible polymer film. For example, the flexible polymer film can be made of any of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS). For example, the substrate 110 can include a transparent polyimide material, and this disclosure is not limited thereto.

[0083] A light-shielding layer LS can be disposed in each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident from the lower part of the substrate 110 onto the active layer ACT of the driving transistor DT, which will be described below. The light incident onto the active layer ACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize leakage current.

[0084] A buffer layer 111 may be disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). For example, the buffer layer 111 may be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiON) film. For example, the buffer layer 111 may be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple layers of inorganic film may be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si). However, this disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0085] The driving transistor DT can be disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0086] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0087] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE, and may be composed of a single or double layer of silicon oxide (SiOx) or silicon nitride (SiNx). For example, the gate insulating layer 112 may be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiON) film. For example, the gate insulating layer 112 may be formed by a single or multiple inorganic film. For instance, the single inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple inorganic film may be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film, and one or more layers of amorphous silicon (a-Si), but is not limited thereto.

[0088] The gate electrode GE can be disposed on the gate insulating layer 112. The gate electrode GE can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0089] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers used to protect components disposed beneath them, and can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). Each of the first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiON) film. For example, each of the first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be formed by a single or multiple inorganic film. For example, the single inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple inorganic film can be formed by alternately stacking at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiON) films and one or more amorphous silicon (a-Si), but is not limited thereto.

[0090] The source electrode SE and drain electrode DE, which are electrically connected to the active layer ACT, can be disposed on the second interlayer insulating layer 113b. The source electrode SE and drain electrode DE can be made of conductive materials, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0091] Furthermore, in this disclosure, it has been described that a first interlayer insulating layer 113a and a second interlayer insulating layer 113b (that is, multiple insulating layers) are disposed between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, it is possible to provide only one insulating layer between the gate electrode GE, the source electrode SE, and the drain electrode DE, but it is not limited thereto.

[0092] Furthermore, as shown in the figure, when multiple insulating layers, such as a first interlayer insulating layer 113a and a second interlayer insulating layer 113b, are provided between the gate electrode GE, the source electrode SE, and the drain electrode DE, an additional electrode can be formed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The additionally formed electrode can form a capacitor with another configuration disposed below the first interlayer insulating layer 113a or above the second interlayer insulating layer 113b, but is not limited thereto.

[0093] An auxiliary electrode LE can be disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 113b. For example, the light-shielding layer LS can be electrically connected to either the source electrode SE or the drain electrode DE via the auxiliary electrode LE so that it does not operate as a floating gate. Therefore, the threshold voltage fluctuation of the driving transistor DT caused by the floating light-shielding layer LS can be minimized. Although the light-shielding layer LS is shown connected to the source electrode SE in the figures, it can also be connected to the drain electrode DE, but is not limited to this.

[0094] The power line VL can be disposed on the second interlayer insulating layer 113b. The power line VL is electrically connected to the light-emitting element LED together with the driving transistor DT to allow the light-emitting element LED to emit light. The power line VL can be made of conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0095] Passivation layer 114 can be disposed on the driving transistor DT and the power line VL. Passivation layer 114 can protect the driving transistor DT and the power line VL from the penetration of moisture or impurities. For example, passivation layer 114 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, passivation layer 114 may be omitted, but is not limited thereto.

[0096] An outer coating 115 may be disposed on a passivation layer 114. The outer coating 115 may planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The outer coating 115 may be composed of a single layer or a double layer, and may be formed, for example, by a photoresist or an acrylic organic material, but is not limited thereto.

[0097] Multiple reflective electrodes RE spaced apart from each other can be disposed on the outer coating 115. The multiple reflective electrodes RE electrically connect the light-emitting element (LED) to the power line VL and the driving transistor DT, and can also serve as a reflector to reflect light emitted from the LED to the upper part of the LED. The multiple reflective electrodes RE are formed of a conductive material with excellent reflective properties to reflect light emitted from the LED towards the upper part of the LED.

[0098] The plurality of reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 may be electrically connected to the driving transistor DT and the light-emitting element LED. The first reflective electrode RE1 may be connected to the source electrode SE or drain electrode DE of the driving transistor DT through contact holes formed in the passivation layer 114 and the outer coating layer 115. In addition, the first reflective electrode RE1 may be electrically connected to the first electrode 124 of the light-emitting element LED through the first connection electrode CE1.

[0099] The second reflective electrode RE2 can be electrically connected to the power line VL and the light-emitting element LED. The second reflective electrode RE2 can be connected to the power line VL through contact holes formed in the passivation layer 114 and the outer coating layer 115, and can be electrically connected to the second electrode 125 of the light-emitting element LED by the second connection electrode CE2 described below.

[0100] An adhesive layer 116 is formed on the front surface of the substrate 110 on a plurality of reflective electrodes RE to fix the light-emitting element LED disposed on the adhesive layer 116. The adhesive layer 116 may be made of a photocurable adhesive material that can be cured by light. For example, the adhesive layer 116 may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0101] Multiple light-emitting elements (LEDs) can be disposed on the adhesive layer 116 in each of the multiple sub-pixels (SPs). The multiple LEDs are light-emitting elements that emit light through an electric current, and can include LEDs emitting red, green, and blue light, and can be combined to achieve various colored lights, including white light. For example, the multiple LEDs can be light-emitting elements (LEDs) or micro-LEDs (micro-LEDs), but are not limited to these.

[0102] The light-emitting element LED may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126.

[0103] A first semiconductor layer 121 may be disposed on an adhesive layer 116, and a second semiconductor layer 123 may be disposed on a first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping N-type or P-type impurities into a specific material. For example, each of the first semiconductor layer 121 and the second semiconductor layer 123 may be a layer doped with N-type and P-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). Furthermore, P-type impurities may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., while N-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0104] A portion of the first semiconductor layer 121 may be configured to protrude outward from the second semiconductor layer 123. The top surface of the first semiconductor layer 121 may include a portion overlapping the bottom surface of the second semiconductor layer 123 and a portion disposed outside the bottom surface of the second semiconductor layer 123. For example, the first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 in some directions. The light-emitting element LED may be a lateral light-emitting element LED. However, various modifications can be made to the size and shape of the first semiconductor layer 121 and the second semiconductor layer 123, but these modifications are not limited to these modifications.

[0105] The light-emitting layer 122 can be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can receive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light.

[0106] The light-emitting layer 122 can be formed by a single-layer or multiple quantum well (MQW) structure, and can be formed, for example, by indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0107] The first electrode 124 may be disposed on the first semiconductor layer 121. The first electrode 124 is an electrode used for electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with N-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0108] The second electrode 125 can be disposed on the second semiconductor layer 123. The second electrode 125 can be disposed on the top surface of the second semiconductor layer 123. In this case, since the second semiconductor layer 123 is disposed on the first semiconductor layer 121, the second electrode 125 disposed on the top surface of the second semiconductor layer 123 can be disposed above the first electrode 124 disposed on the top surface of the first semiconductor layer 121. The second electrode 125 is an electrode electrically connecting the electric field line VL and the second semiconductor layer 123. In this case, the second semiconductor layer 123 can be a semiconductor layer doped with P-type impurities, and the second electrode 125 can be an anode. The second electrode 125 can be made of a conductive material, such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0109] Next, the passivation film 126 can be configured to surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation film 126 can be formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, contact holes are formed in the passivation film 126 to expose the first electrode 124 and the second electrode 125, and the first connecting electrode CE1 and the second connecting electrode CE2, which are formed later, as well as the first electrode 124 and the second electrode 125, can be electrically connected through these contact holes.

[0110] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, the light-emitting elements (LEDs) disposed in different sub-pixels SP are configured with different shapes to distinguish the plurality of light-emitting elements (LEDs). Therefore, when the light-emitting elements (LEDs) self-assemble, the plurality of light-emitting elements (LEDs) are formed with different shapes to self-assemble at positions corresponding to each of the plurality of sub-pixels SP.

[0111] Furthermore, this disclosure is not limited thereto, and the size and shape of the light-emitting elements (LEDs) can be the same. That is, the light-emitting elements (LEDs) are transferred by a separate transfer substrate rather than a self-assembly method to be positioned at locations corresponding to multiple sub-pixels (SPs).

[0112] The first planarization layer 117a may be disposed on the adhesive layer 116. The first planarization layer 117a is configured to surround a portion of the side surface of a plurality of light-emitting elements LEDs to fix and protect the plurality of light-emitting elements LEDs.

[0113] For example, the first planarization layer 117a can be configured to surround the passivation film 126 disposed on the lower edge of the light-emitting element LED. Therefore, the first connection electrode CE1 can be prevented from disconnecting due to the torn passivation film 126. For example, during the separation of the wafer and the light-emitting element LED, a portion of the passivation film 126 can be torn off at the lower edge of the light-emitting element LED. Therefore, the passivation film 126 can expose a portion of the first semiconductor layer 121 at the lower edge of the light-emitting element LED. Thus, a step can be created in the lower edge of the light-emitting element LED due to the torn passivation film 126. In this case, when the first connection electrode CE1 is configured to surround the side surface of the passivation film 126, the first connection electrode CE1 can be disconnected by the step caused by the torn passivation film 126.

[0114] Therefore, before setting the first connecting electrode CE1, a first planarization layer 117a is formed to surround the lower edge of the light-emitting element LED, thereby separating the lower edge of the light-emitting element LED from the first connecting electrode CE1. Thus, even if an undercut structure is formed on the lower edge of the light-emitting element LED due to the torn passivation film 126, the first planarization layer 117a contacts at least a portion of the side surface of the light-emitting element LED to fill the undercut structure, thereby minimizing the short circuit of the first connecting electrode CE1 caused by the undercut structure.

[0115] The first planarization layer 117a may consist of a single layer or two layers, and may be formed, for example, by a photoresist or an acrylic organic material, but is not limited thereto.

[0116] Furthermore, the first planarization layer 117a can be lower than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a can be adjusted by performing an ashing process. For example, after applying a material layer of the first planarization layer 117a to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the material layer of the first planarization layer 117a, so that the height of the first planarization layer 117a is formed to be lower than the height of the first electrode 124. Therefore, the first planarization layer 117a can expose the first electrode 124. Therefore, the first connection electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without the need for a separate contact hole.

[0117] The first connecting electrode CE1 can be disposed on the first planarization layer 117a. The first connecting electrode CE1 is an electrode disposed in each of the plurality of sub-pixels SP to electrically connect the light-emitting element LED and the driving transistor DT. The first connecting electrode CE1 can be connected to the first reflective electrode RE1 through contact holes formed in the first planarization layer 117a and the adhesive layer 116. Therefore, the first connecting electrode CE1 can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflective electrode RE1. For example, the first connecting electrode CE1 can connect the first electrode 124 of the light-emitting element LED to the source electrode SE of the driving transistor DT, but is not limited thereto.

[0118] Furthermore, the first connecting electrode CE1 can be formed by covering the light-emitting element LED with a material layer of the first connecting electrode CE1, and then partially removing a portion of the top surface and side surface of the second semiconductor layer 123, as well as the material layer of the first connecting electrode CE1 disposed on the second electrode 125. For example, after applying photoresist to the light-emitting element LED, the photoresist disposed on the top surface of the second electrode 125 and a portion of the side surface and top surface of the second semiconductor layer 123 can be removed by an ashing process to expose the second electrode 125. Therefore, only the top surface of the second electrode 125, a portion of the side surface of the second semiconductor layer 123, and a portion of the top surface of the material layer of the first connecting electrode CE1 can be exposed. Furthermore, the material layer of the first connecting electrode CE1 exposed by the ashing process is removed to form the first connecting electrode CE1, but this is not a limitation.

[0119] The second planarization layer 117b can be disposed on the first planarization layer 117a and the plurality of first connection electrodes CE1. The second planarization layer 117b planarizes the upper part of the substrate 110 on which the light-emitting element LED is disposed together with the first planarization layer 117a, and can fix the light-emitting element LED together with the adhesive layer 116 to the substrate 110.

[0120] Furthermore, a second planarization layer 117b can be provided to cover the first connecting electrode CE1, thereby separating the first connecting electrode CE1 and the second connecting electrode CE2 from each other. This prevents short circuits between the first connecting electrode CE1 and the second connecting electrode CE2.

[0121] For example, only the second planarization layer 117b may be disposed between the first connecting electrode CE1 and the second connecting electrode CE2. For example, the second planarization layer 117b may be configured as a single layer or multiple layers and made of a photoresist or an acrylic-based organic material. However, this disclosure is not limited thereto.

[0122] The second connecting electrode CE2 can be disposed on the second planarization layer 117b. The second connecting electrode CE2 is an electrode used for electrically connecting the light-emitting element LED and the power line VL. The second connecting electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the second planarization layer 117b, the first planarization layer 117a, and the adhesive layer 116. Therefore, the second connecting electrode CE2 can be electrically connected to the power line VL through the second reflective electrode RE2. For example, the second connecting electrode CE2 can connect the second electrode 125 of the light-emitting element LED and the power line VL, but is not limited thereto.

[0123] A black dam BB can be disposed on the second planarization layer 117b and the second connecting electrode CE2. The black dam BB can be configured not to overlap with the light-emitting elements LED to define the light-emitting area. For example, the black dam BB can cover the edge of the second connecting electrode CE2 connected to each light-emitting element LED to define the light-emitting area. That is, the black dam BB can divide multiple sub-pixels SP. The black dam BB can be formed of an insulating material to insulate the second connecting electrodes CE2 of adjacent sub-pixels SP from each other. In addition, the black dam BB can include a black component with a high light absorption rate to suppress color mixing between adjacent sub-pixels SP. The black dam BB can be formed of, for example, polyimide resin, acrylic resin, or benzocyclobutene (BCB) resin, but is not limited to these.

[0124] For example, the black dam BB can be patterned in a photolithography process using a photosensitive organic insulating material. Furthermore, spacers with a predetermined height can be formed on the black dam BB. Here, the black dam BB and the spacers can be integrated from the same organic insulating material. Additionally, the spacers ensure the gap between the fine metal mask (FMM) and the anode electrode, and prevent the FMM from contacting the anode electrode during the deposition of light-emitting elements made of organic compounds.

[0125] The third planarization layer 118 may be disposed on the second planarization layer 117b and the black embankment BB. The third planarization layer 118 is configured to cover the top surface of the light-emitting element LED to planarize the upper part of the substrate 110 on which the light-emitting element LED is disposed, and to fix and protect the light-emitting element LED. Therefore, the third planarization layer 118 may be referred to as a protective layer or a cover layer, but is not limited thereto. The third planarization layer 118 may be composed of a single layer or two layers, and may be formed, for example, by a photoresist or an acrylic organic material, but is not limited thereto.

[0126] Furthermore, the encapsulation layer can be disposed on the third planarization layer 118 and can prevent the light-emitting device from being damaged by external impacts and moisture. The encapsulation layer may include alternating layers of inorganic insulating material. For example, organic insulating material layers may be disposed between adjacent inorganic insulating material layers.

[0127] For example, the encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially.

[0128] Alternatively, the encapsulation layer comprises a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked sequentially. However, this disclosure is not limited thereto.

[0129] The first, second, and third inorganic encapsulation layers can be used to block the penetration of moisture or oxygen. The first, second, and third inorganic encapsulation layers can be made of inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, this disclosure is not limited thereto.

[0130] A first organic encapsulation layer is disposed between a first inorganic encapsulation layer and a second inorganic encapsulation layer, and a second organic encapsulation layer is disposed between the second and third inorganic encapsulation layers. The first and second organic encapsulation layers may each have a greater thickness than each of the first, second, and third inorganic encapsulation layers to adsorb or block particles that may be generated during the manufacturing process of the display device. The first and second organic encapsulation layers may fill cracks that may form in the first and second inorganic encapsulation layers. The first and second organic encapsulation layers can planarize the upper portions of the first and second inorganic encapsulation layers by respectively covering particles on the first and second inorganic encapsulation layers. For example, the first organic encapsulation layer can planarize the upper portion of the first inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer can planarize the upper portion of the second inorganic encapsulation layer by covering particles on the second inorganic encapsulation layer. The first and second organic encapsulation layers may be made of organic materials, and for example, epoxy polymers, acrylic polymers, etc., may be used. However, this disclosure is not limited thereto.

[0131] Furthermore, the encapsulation layer is not limited to three or five layers. For example, it can include n layers of alternating inorganic and organic encapsulation layers (where n is an integer greater than 3).

[0132] During the placement or transfer of multiple light-emitting elements onto a substrate, some elements may be misaligned or misplaced. When subsequent processes are performed with some elements misaligned or misplaced, short-circuit defects between electrodes may occur.

[0133] For example, the light-emitting element may fail to emit light properly if the same electrodes are incorrectly aligned to connect the first and second electrodes of the light-emitting element, or if the electrodes connected to the first and second electrodes of the light-emitting element are not separated and overlap to cause a short circuit defect.

[0134] In a display device 100 according to an exemplary embodiment of the present disclosure, a first connecting electrode CE1 and a first electrode 124 of a light-emitting element LED are self-aligned for connection. For example, a material layer of a first planarization layer 117a may be provided to surround the light-emitting element LED. Next, the material layer of the first planarization layer 117a may be ashed to expose the first electrode 124. Subsequently, a material layer of the first connecting electrode CE1 may be disposed on the first planarization layer 117a. At this time, a photoresist is applied to the material layer of the first connecting electrode CE1, and the photoresist can be removed by an ashing process until the second electrode 125 of the light-emitting element LED is exposed. Subsequently, the material layer of the first connecting electrode CE1 exposed by the ashing process is removed, such that only the material layer of the first connecting electrode CE1 disposed on the first electrode 124 and the first planarization layer 117a remains, to form the first connecting electrode CE1. Therefore, the first connecting electrode CE1 and the first electrode 124 can be self-aligned by the ashing process of the first planarization layer 117a and the photoresist, without the need for precise alignment of the positions of the first electrode 124 and the first connecting electrode CE1. Therefore, it can minimize short-circuit defects caused by process errors.

[0135] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second semiconductor layer 123 of the light-emitting element LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED to expose only the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED. In this case, even if the second connection electrode CE2 is formed by forming and patterning a material layer of the second connection electrode CE2 on the front surface of the substrate 110 including the second planarization layer 117b, the second connection electrode CE2 may only contact the top surface of the second electrode 125 exposed from the second planarization layer 117b, and may be spaced apart from the first connection electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121 disposed below the second planarization layer 117b. Therefore, since the second connection electrode CE2 may only contact the top surface of the second electrode 125, when forming the second connection electrode CE2, it is not necessary to consider the positions of the first semiconductor layer 121 and the first connection electrode CE1 to ensure process margin. Therefore, the second connecting electrode CE2 and the first electrode 124 can be self-aligned through the ashing process of the second planarization layer 117b, without the need for precise alignment of the positions of the second electrode 125 and the second connecting electrode CE2. This minimizes short-circuit defects in the first connecting electrode CE1 and the second connecting electrode CE2 caused by process errors.

[0136] Figure 4 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 4 The display device 200 and Figures 1 to 3 The only difference between the display devices 100 is the addition of a passivation layer 219, a second planarization layer 217b, and a second connection electrode CE2, but the other components are basically the same, so a redundant description will be omitted.

[0137] Reference Figure 4 An additional passivation layer 219 may be disposed on the plurality of first connection electrodes CE1. The additional passivation layer 219 may be disposed on the plurality of first connection electrodes CE1 to prevent moisture or impurities from penetrating into the plurality of reflective electrodes RE1 connected to the plurality of first connection electrodes CE1. For example, the additional passivation layer 219 may be configured as a single layer or multiple layers made of inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0138] Furthermore, the additional passivation layer 219 can be configured to cover at least a portion of the first connection electrode CE1, such that the first connection electrode CE1 and the second connection electrode CE2 are separated from each other. Therefore, the additional passivation layer 219 can prevent short circuits between the first connection electrode CE1 and the second connection electrode CE2.

[0139] Furthermore, the additional passivation layer 219 can be configured to surround a portion of the side surface of the light-emitting element LED. In this case, the additional passivation layer 219 is disposed on the first connection electrode CE1, such that the additional passivation layer 219 can be configured to be spaced apart from the light-emitting element LED, and the first connection electrode CE1 is inserted between the additional passivation layer 219 and the light-emitting element LED.

[0140] In this configuration, the height of the uppermost end of the additional passivation layer 219 can be greater than the height of the uppermost end of the first connecting electrode CE1. Therefore, a predetermined space can be formed between the additional passivation layer 219 and the passivation film 126 of the light-emitting element LED. Consequently, the end of the first connecting electrode CE1 disposed in the space between the additional passivation layer 219 and the light-emitting element LED can be exposed. That is, the additional passivation layer 219 can expose a portion of the top surface of the end of the first connecting electrode CE1 disposed on the side surface of the light-emitting element LED.

[0141] The second planarization layer 217b can be disposed on the additional passivation layer 219. The second planarization layer 217b can be disposed to cover the end of the first connection electrode CE1 exposed by the additional passivation layer 219, so that the first connection electrode CE1 and the second connection electrode CE2 can be separated from each other.

[0142] Specifically, a second planarization layer 217b can be provided to fill the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, the second planarization layer 217b can cover the end of the first connecting electrode CE1 disposed in the space between the additional passivation layer 219 and the light-emitting element LED.

[0143] Furthermore, since the second planarization layer 217b is disposed on the additional passivation layer 219, the second planarization layer 217b can be configured to cover not only the first connection electrode CE1 exposed by the additional passivation layer 219, but also the additional passivation layer 219 itself. In other words, the second planarization layer 217b can be configured to cover the passivation film 126 disposed on the side surface of the light-emitting element LED, the end of the first connection electrode CE1 that is configured to surround a portion of the light-emitting element LED, and the adjacent end of the additional passivation layer 219. Therefore, the height of the top surface of the second planarization layer 217b can be higher than the height of the top of the first connection electrode CE1 and the top of the additional passivation layer 219, respectively, but is not limited thereto.

[0144] The second connection electrode CE2 can be disposed on the second planarization layer 217b. Since the second planarization layer 217b is configured to cover the additional passivation layer 219, the second connection electrode CE2 disposed on the second planarization layer 217b can be configured to be spaced apart from the additional passivation layer 219, but is not limited thereto.

[0145] In the following text, reference will be made to Figure 5A , Figure 5B , Figure 5C and Figure 5D A method for manufacturing a display device according to another exemplary embodiment of the present disclosure is described in detail.

[0146] Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a flowchart for explaining a method of manufacturing a display device according to another exemplary embodiment of the present disclosure.

[0147] First, refer to Figure 5A The light-emitting element LED is disposed on the adhesive material layer 116', and the first planarization layer 117a' can be disposed on the adhesive material layer 116' to surround the light-emitting element LED.

[0148] In this case, a process can be performed to etch a portion of the adhesive material layer 116' and the first planarization layer 117a' to form a contact hole. The contact hole formed at this time is the contact hole through which the first reflective electrode RE1 is exposed.

[0149] The first connecting electrode material layer CE1' and the additional passivation material layer 219' can be sequentially disposed on the entire surface of the substrate 110 on the first planarization layer 117a' and the light-emitting element LED.

[0150] Specifically, the first connecting electrode material layer CE1' can be disposed on the entire surface of the substrate 110 to cover the light-emitting element LED and the first planarization layer 117a'. Therefore, the first connecting electrode material layer CE1' can also be disposed in the contact holes formed in the first planarization layer 117a' and the adhesive material layer 116'. In addition, the first connecting electrode material layer CE1' can be configured to cover all side surfaces and top surface portions of the light-emitting element LED.

[0151] An additional passivation material layer 219' can be disposed on the entire surface of the substrate 110 on the first connecting electrode material layer CE1'. The additional passivation material layer 219' can be configured to be spaced apart from the light-emitting element LED, the first planarization layer 117a' and the adhesive material layer 116' through the first connecting electrode material layer CE1'.

[0152] Furthermore, a photoresist PR can be disposed on the additional passivation material layer 219' to surround the light-emitting element LED. The height of the photoresist PR can be lower than the height of the second electrode 125 of the light-emitting element LED. For example, the thickness of the photoresist PR can be adjusted by performing an ashing process. For example, after applying the photoresist PR to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the photoresist PR, so that the height of the photoresist PR is formed to be lower than the height of the second electrode 125. Therefore, in subsequent processes, the second connecting electrode CE2 can be easily connected to the second electrode 125.

[0153] Next, refer to Figure 5B The additional passivation layer 219 can be formed by etching the additional passivation material layer 219'. Specifically, the additional passivation material layer 219' exposed from the photoresist PR can be etched to form the additional passivation layer 219.

[0154] For example, when the thickness of the photoresist PR is less than the thickness of the light-emitting element LED, the additional passivation material layer 219' covering the upper part of the light-emitting element LED can be exposed from the photoresist PR.

[0155] The additional passivation layer 219 can be formed by a dry etching process. Therefore, unlike wet etching, it is possible to remove only the portion of the additional passivation material layer 219' that overlaps with the photoresist PR, rather than removing the portion that is exposed by the photoresist PR.

[0156] After the additional passivation layer 219 is formed, the photoresist PR can be removed.

[0157] Next, refer to Figure 5C The first connection electrode CE1 can be formed by partially removing the first connection electrode material layer CE1'. The additional passivation layer 219 can be formed by etching the first connection electrode material layer CE1' exposed from the additional passivation layer 219. That is, the additional passivation layer 219 can be used as a mask during the etching process of the first connection electrode material layer CE1'.

[0158] Furthermore, the first connection electrode CE1 can be formed using a wet etching process. Therefore, the portion of the first connection electrode material layer CE1' exposed by the additional passivation layer 219, as well as the portion overlapping with the additional passivation layer 219, can be partially removed. Thus, the end of the first connection electrode CE1 can be located inside or below the end of the additional passivation layer 219. Therefore, the height of the uppermost end of the first connection electrode CE1 located on the side surface of the light-emitting element LED can be lower than the height of the uppermost end of the adjacent additional passivation layer 219. That is, the first connection electrode material layer CE1' located between the additional passivation layer 219 and the light-emitting element LED is partially removed, allowing a space to be formed between the additional passivation layer 219 and the light-emitting element LED. Thus, by forming a space between the additional passivation layer 219 and the light-emitting element LED, the second planarization layer 217b can fill this space in a subsequent process to cover the end of the first connection electrode CE1 located between the additional passivation layer 219 and the light-emitting element LED. Therefore, the first connecting electrode CE1 and the second connecting electrode CE2 disposed on the second planarization layer 217b can be separated and configured to be spaced apart from each other.

[0159] Next, refer to Figure 5D The second planarization layer 217b, the second connecting electrode CE2, the black embankment BB, and the third planarization layer 118 are disposed on the additional passivation layer 219 to complete the manufacturing process of the display device 100.

[0160] Specifically, although not shown in the accompanying drawings, the second planarization layer can be disposed on the entire surface of the substrate 110 over the light-emitting element LED, the additional passivation layer 219, and the first planarization layer 117a'. Subsequently, the thickness of the second planarization layer can be adjusted by performing an ashing process. For example, after applying the second planarization layer to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the second planarization layer to form the second planarization layer 217b, and the height of the thus formed second planarization layer 217b can be lower than the height of the second electrode 125. Therefore, the second connection electrode CE2 disposed on the second planarization layer 217b can be easily connected to the second electrode 125.

[0161] Subsequently, a process of etching a portion of the adhesive material layer 116', the first planarization layer 117a', and the second planarization layer can be performed to form a contact hole. The contact hole formed at this time exposes the second reflective electrode RE2.

[0162] As described above, the second planarization layer 217b can be formed through an ashing process and a contact hole formation process. As described above, the second planarization layer 217b can be provided to fill the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, the end of the first connecting electrode CE1 exposed by the additional passivation layer 219 can be covered. Therefore, the first connecting electrode CE1 and the second connecting electrode CE2 disposed on the second planarization layer 217b can be separated. Therefore, short circuits between the first connecting electrode CE1 and the second connecting electrode CE2 can be prevented.

[0163] Next, the second connecting electrode CE2, the black embankment BB, and the third planarization layer 118 are disposed on the second planarization layer 217b to complete the manufacturing process of the display device 100.

[0164] For example, the planarization layer can be grayed to expose the second electrode of the light-emitting element, allowing the second electrode and the second connecting electrode of the light-emitting element to self-align. However, when the planarization layer is over-grayed, the first connecting electrode, which is connected to the first electrode located beneath the planarization layer and is connected to the light-emitting element, may be exposed. In this way, when the second connecting electrode is located on the planarization layer and the first connecting electrode beneath the planarization layer is exposed, a short-circuit defect may occur where the first and second connecting electrodes are not separated and are connected to each other.

[0165] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, an additional passivation layer 219 disposed on the first connection electrode CE1 may be provided to cover at least a portion of the first connection electrode CE1. Thus, the additional passivation layer 219, together with the second planarization layer 217b, can allow the first connection electrode CE1 and the second connection electrode CE2 to be separated from each other. Therefore, the additional passivation layer 219 can prevent short circuits between the first connection electrode CE1 and the second connection electrode CE2.

[0166] Furthermore, since the additional passivation layer 219 is formed of an inorganic insulating material, it can block moisture or impurities from penetrating into the plurality of first connecting electrodes CE1 and the plurality of reflective electrodes RE connected thereto. Therefore, it can prevent peeling and corrosion of the reflective electrodes RE due to moisture penetration.

[0167] Specifically, in a display device 200 according to another exemplary embodiment of the present disclosure, a second planarization layer 217b covers the first connection electrode CE1 exposed by the additional passivation layer 219 to separate the first connection electrode CE1 and the second connection electrode CE2. For example, a portion of the first connection electrode CE1 exposed by the additional passivation layer 219 and a portion overlapping with the additional passivation layer 219 by a wet etching process can be partially removed. Therefore, the height of the uppermost end of the first connection electrode CE1 can be formed to be lower than the height of the uppermost end of the additional passivation layer 219. That is, the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED is partially removed, so that a space can be formed between the additional passivation layer 219 and the light-emitting element LED. Therefore, the second planarization layer 217b disposed on the additional passivation layer 219 can fill the space between the additional passivation layer 219 and the light-emitting element LED to cover the end of the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED. Therefore, the first connecting electrode CE1 and the second connecting electrode CE2 disposed on the second planarization layer 217b can be separated. Thus, short-circuit defects of the first connecting electrode CE1 and the second connecting electrode CE2 can be minimized.

[0168] Figure 6 This is a cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure. Figure 6 The display device 300 and Figures 5A to 5D The only difference between the display devices 200 is the organic pattern OP, the second planarization layer 317b, and the second connecting electrode CE2, but the other components are basically the same, so redundant descriptions will be omitted.

[0169] Reference Figure 6 The second planarization layer 317b may be disposed on the additional passivation layer 219. In this case, the height of the uppermost end of the second planarization layer 317b may be lower than the height of the uppermost end of the additional passivation layer 219. Therefore, the second planarization layer 317b may expose the end of the additional passivation layer 219 disposed on the side surface of the light-emitting element LED. That is, the second planarization layer 317b exposes the end of the additional passivation layer 219, so that the end of the first connecting electrode CE1 exposed by the additional passivation layer 219 may be exposed.

[0170] In other words, the second planarization layer 317b can be configured to expose the end of the first connection electrode CE1 that is configured to surround a portion of the side surface of the light-emitting element LED and the adjacent end of the additional passivation layer 219, but is not limited thereto.

[0171] In addition, an organic pattern OP can be provided to cover the end of the first connecting electrode CE1 exposed by the additional passivation layer 219, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be separated from each other.

[0172] Specifically, an organic pattern OP can be provided to fill the space between the additional passivation layer 219 and the light-emitting element LED. For example, a first connecting electrode CE1 is disposed on the side surface of the first planarization layer 117a and the light-emitting element LED. The additional passivation layer 219 is disposed on the first connecting electrode CE1 and exposes the end of the first connecting electrode CE1. A second planarization layer 317b is disposed on the additional passivation layer 219 and exposes the ends of the first connecting electrode CE1 and the additional passivation layer 219 at the upper surface of the second planarization layer 317b. The exposed end of the first connecting electrode CE1 at the upper surface of the second planarization layer 317b is covered by the organic pattern OP. Therefore, the organic pattern OP can cover the end of the first connecting electrode CE1 disposed in the space between the additional passivation layer 219 and the light-emitting element LED.

[0173] For example, the organic pattern OP can be formed simultaneously with the same material as the second planarization layer 317b. As described above, the second planarization layer 317b can be formed by disposing the second planarization layer on the entire surface of the substrate 110 and performing an ashing process to adjust the thickness of the second planarization layer. At this time, the second planarization layer is transitionally ashing, such that the uppermost end of the second planarization layer 317b can be set below the uppermost end of the additional passivation layer 219. Therefore, the ends of the additional passivation layer 219 and the first connection electrode CE1 can be exposed. Furthermore, even in this case, since there is a space between the additional passivation layer 219 and the light-emitting element LED, the second planarization layer is partially retained in the space between the additional passivation layer 219 and the light-emitting element LED, and thus can cover the end of the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED. In other words, the organic pattern OP can be the portion retained between the additional passivation layer 219 and the light-emitting element LED during the process of forming the second planarization layer 317b. Therefore, the organic pattern OP can be configured to be spaced apart from the second planarization layer 317b, with the additional passivation layer 219 interposed between them, but is not limited thereto.

[0174] In other words, even if the second planarization layer 317b is over-greyed so that it does not cover the end of the first connection electrode CE1 exposed by the additional passivation layer 219, the organic pattern OP can still fill the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, the organic pattern OP can cover the end of the first connection electrode CE1 located between the additional passivation layer 219 and the light-emitting element LED to separate the first connection electrode CE1 and the second connection electrode CE2.

[0175] Furthermore, as mentioned above, the organic pattern OP can be formed from the same material as the second planarization layer 317b, but is not limited to it, and can be formed from another material.

[0176] Furthermore, since the second planarization layer 317b is transitionally grayed, the height of the top surface of the second planarization layer 317b can be lower than the height of the top surface of the organic pattern OP. Therefore, the height of the uppermost end of the second planarization layer 317b can be lower than the height of the uppermost end of the organic pattern OP, but is not limited thereto.

[0177] The second connection electrode CE2 may be disposed on the second planarization layer 317b. Since the second planarization layer 317b is disposed to expose the additional passivation layer 219, the second connection electrode CE2 disposed on the second planarization layer 317b may contact at least a portion of the additional passivation layer 219. For example, the second connection electrode CE2 may contact the end of the additional passivation layer 219 exposed by the second planarization layer 317b, but is not limited thereto.

[0178] In a display device 300 according to yet another exemplary embodiment of the present disclosure, an additional passivation layer 219 may be disposed on the first connection electrode CE1 to cover at least a portion of the first connection electrode CE1. Therefore, the additional passivation layer 219, together with the second planarization layer 317b, allows the first connection electrode CE1 and the second connection electrode CE2 to be separated from each other. Thus, the additional passivation layer 219 can prevent short circuits between the first connection electrode CE1 and the second connection electrode CE2.

[0179] Furthermore, since the additional passivation layer 219 is formed of an inorganic insulating material, it can block moisture or impurities from penetrating into the plurality of first connecting electrodes CE1 and the plurality of reflective electrodes RE connected thereto. Therefore, it can prevent peeling and corrosion of the reflective electrodes RE due to moisture penetration.

[0180] Specifically, in a display device 300 according to another exemplary embodiment of the present disclosure, even if the second planarization layer 317b is transitionally grayed to cover the first connection electrode CE1 exposed by the additional passivation layer 219, the organic pattern OP can also cover the first connection electrode CE1 exposed by the additional passivation layer 219 to separate the first connection electrode CE1 and the second connection electrode CE2. For example, a portion of the first connection electrode CE1 exposed by the additional passivation layer 219 and a portion overlapping with the additional passivation layer 219 by a wet etching process can be partially removed. Therefore, the height of the uppermost end of the first connection electrode CE1 can be formed to be lower than the height of the uppermost end of the additional passivation layer 219. That is, the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED is partially removed, so that a space can be formed between the additional passivation layer 219 and the light-emitting element LED. Therefore, during the formation of the second planarization layer 317b, the organic pattern OP can remain in the space between the additional passivation layer 219 and the light-emitting element LED. In other words, even if the second planarization layer 317b is over-greyed, a space remains between the additional passivation layer 219 and the light-emitting element LED, allowing the organic pattern OP to remain within this space during the formation of the second planarization layer 317b. Therefore, by filling the space between the additional passivation layer 219 and the light-emitting element LED, the organic pattern OP can cover the end of the first connecting electrode CE1 located between the additional passivation layer 219 and the light-emitting element LED. Consequently, the first connecting electrode CE1 and the second connecting electrode CE2 can be separated. Therefore, short-circuit defects in the first connecting electrode CE1 and the second connecting electrode CE2 can be minimized.

[0181] Figure 7 This is a cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure. Figure 7 This is a view used to explain the structure in which a second planarization layer 417b or organic pattern OP is set to cover the first connecting electrode CE1, such that even if the height of the second planarization layer 417b is different between sub-pixels SP, the first connecting electrode CE1 and the second connecting electrode CE2 are separated. Figure 7 The structure of the first sub-pixel SP1 of the display device 400 is basically the same as Figures 5A to 5D The structure of the display device 200 is the same, and the structure of the second sub-pixel SP2 is basically the same. Figure 6 The structure of the display device 300 is the same, so redundant descriptions will be omitted.

[0182] Reference Figure 7Multiple subpixels SP can include a first subpixel SP1 and a second subpixel SP2 located in different regions. The first subpixel SP1 and the second subpixel SP2 can emit light of different colors or the same color.

[0183] In each sub-pixel SP, a second planarization layer 417b can be disposed on the additional passivation layer 219. In this case, the height of the second planarization layer 417b can be different in the first sub-pixel SP1 and the second sub-pixel SP2. For example, the height of the second planarization layer 417b disposed in the second sub-pixel SP2 can be lower than the height of the second planarization layer 417b disposed in the first sub-pixel SP1. For example, the second planarization layer 417b can be formed simultaneously in the first sub-pixel SP1 and the second sub-pixel SP2. However, due to process errors, the second planarization layer 417b may be over-greyed in the second sub-pixel SP2, so that the height of the second planarization layer 417b may be formed to be lower in the second sub-pixel SP2 than in the first sub-pixel SP1.

[0184] For example, in the first sub-pixel SP1, the second planarization layer 417b covers the first connection electrode CE1 exposed by the additional passivation layer 219 to separate the first connection electrode CE1 and the second connection electrode CE2.

[0185] Specifically, a second planarization layer 417b can be provided to fill the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, the second planarization layer 417b can cover the end of the first connecting electrode CE1 disposed in the space between the additional passivation layer 219 and the light-emitting element LED.

[0186] Furthermore, because the second planarization layer 417b is disposed on the additional passivation layer 219, the second planarization layer 417b can be configured to cover not only the first connection electrode CE1 exposed by the additional passivation layer 219, but also the additional passivation layer 219 itself. In other words, the second planarization layer 417b can be configured to cover the end of the first connection electrode CE1 that is configured to surround a portion of the side surface of the light-emitting element LED and the adjacent end of the additional passivation layer 219. Therefore, the height of the top surface of the second planarization layer 417b can be greater than, but is not limited to, the height of the top of the first connection electrode CE1 and the top of the additional passivation layer 219.

[0187] Furthermore, in the first sub-pixel SP1, a second planarization layer 417b is provided to cover the additional passivation layer 219. Therefore, the second connection electrode CE2 provided on the second planarization layer 417b can be configured to be spaced apart from the additional passivation layer 219, but is not limited thereto.

[0188] In the second sub-pixel SP2, the second planarization layer 417b is transitionally grayed out, such that the height of the uppermost end of the second planarization layer 417b may be lower than the height of the uppermost end of the additional passivation layer 219. Therefore, the second planarization layer 417b may expose the end of the additional passivation layer 219 disposed on the side surface of the light-emitting element LED. That is, the second planarization layer 417b exposes the end of the additional passivation layer 219, potentially exposing the end of the first connecting electrode CE1 exposed by the additional passivation layer 219.

[0189] In other words, the second planarization layer 417b can be configured to expose the end of the first connection electrode CE1 that is configured to surround a portion of the side surface of the light-emitting element LED and the adjacent end of the additional passivation layer 219, but is not limited thereto.

[0190] In the second sub-pixel SP2, an organic pattern OP can be provided to cover the end of the first connecting electrode CE1 exposed by the additional passivation layer 219, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be separated from each other.

[0191] Specifically, an organic pattern OP can be provided to fill the space between the additional passivation layer 219 and the light-emitting element LED. For example, a first connecting electrode CE1 is disposed on the side surface of the first planarization layer 117a and the light-emitting element LED. The additional passivation layer 219 is disposed on the first connecting electrode CE1 and exposes the end of the first connecting electrode CE1. A second planarization layer 417b is disposed on the additional passivation layer 219 and exposes the ends of the first connecting electrode CE1 and the additional passivation layer 219 at the upper surface of the second planarization layer 417b. The exposed end of the first connecting electrode CE1 at the upper surface of the second planarization layer 417b is covered by the organic pattern OP. Therefore, the organic pattern OP can cover the end of the first connecting electrode CE1 disposed in the space between the additional passivation layer 219 and the light-emitting element LED. For example, the organic pattern OP can be the portion retained between the additional passivation layer 219 and the light-emitting element LED during the process of forming the second planarization layer 417b. Therefore, the organic pattern OP can be configured to be spaced apart from the second planarization layer 417b, with the additional passivation layer 219 interposed between them, but is not limited thereto.

[0192] In other words, even if the second planarization layer 417b is over-greyed so that it does not cover the end of the first connection electrode CE1 exposed by the additional passivation layer 219, the organic pattern OP can still fill the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, the organic pattern OP can cover the end of the first connection electrode CE1 located between the additional passivation layer 219 and the light-emitting element LED to separate the first connection electrode CE1 and the second connection electrode CE2.

[0193] Furthermore, in the second sub-pixel SP2, the second planarization layer 417b is transitionally grayed out, such that the height of the top surface of the second planarization layer 417b can be lower than the height of the top surface of the organic pattern OP. Therefore, the height of the uppermost point of the second planarization layer 417b can be lower than the height of the uppermost point of the organic pattern OP, but is not limited to this, and can be equal to the height of the uppermost point of the second planarization layer 417b.

[0194] In other words, even if the second planarization layer 417b is formed to have different graying degrees in the first sub-pixel SP1 and the second sub-pixel SP2, in the first sub-pixel SP1, the space between the additional passivation layer 219 and the light-emitting element LED can be filled by the second planarization layer 417b, and the organic pattern OP is filled in the second sub-pixel SP2. The end of the first connecting electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED can be covered to separate the first connecting electrode CE1 and the second connecting electrode CE2.

[0195] Furthermore, in the second sub-pixel SP2, a second planarization layer 417b is provided to expose an additional passivation layer 219, such that a second connection electrode CE2 disposed on the second planarization layer 417b can contact at least a portion of the additional passivation layer 219. For example, the second connection electrode CE2 can contact the end of the additional passivation layer 219 exposed by the second planarization layer 417b, but is not limited thereto.

[0196] In a display device 400 according to yet another exemplary embodiment of the present disclosure, an additional passivation layer 219 may be provided on the first connection electrode CE1 to cover at least a portion of the first connection electrode CE1. Therefore, the additional passivation layer 219, together with the second planarization layer 417b, can allow the first connection electrode CE1 and the second connection electrode CE2 to be separated from each other. Thus, the additional passivation layer 219 can prevent short circuits between the first connection electrode CE1 and the second connection electrode CE2.

[0197] Furthermore, since the additional passivation layer 219 is formed of an inorganic insulating material, it can block moisture or impurities from penetrating into the plurality of first connecting electrodes CE1 and the plurality of reflective electrodes RE connected thereto. Therefore, it can prevent peeling and corrosion of the reflective electrodes RE due to moisture penetration.

[0198] Specifically, in a display device 400 according to another exemplary embodiment of the present disclosure, in at least some sub-pixels SP, a second planarization layer 417b covers the first connection electrode CE1 exposed by the additional passivation layer 219 to separate the first connection electrode CE1 and the second connection electrode CE2. For example, a portion of the first connection electrode CE1 exposed by the additional passivation layer 219 by a wet etching process, as well as a portion overlapping with the additional passivation layer 219, can be partially removed. Therefore, the height of the uppermost end of the first connection electrode CE1 can be formed to be lower than the height of the uppermost end of the additional passivation layer 219. That is, the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED is partially removed, so that a space can be formed between the additional passivation layer 219 and the light-emitting element LED. Therefore, the second planarization layer 417b disposed on the additional passivation layer 219 can fill the space between the additional passivation layer 219 and the light-emitting element LED to cover the end of the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED. Therefore, the first connecting electrode CE1 and the second connecting electrode CE2 disposed on the second planarization layer 417b can be separated. Thus, short-circuit defects of the first connecting electrode CE1 and the second connecting electrode CE2 can be minimized.

[0199] Specifically, in a display device 400 according to another exemplary embodiment of the present disclosure, even if the second planarization layer 417b is over-greyed in some sub-pixels SP to avoid covering the first connection electrode CE1 exposed by the additional passivation layer 219, the organic pattern OP can still cover the first connection electrode CE1 exposed by the additional passivation layer 219 to separate the first connection electrode CE1 and the second connection electrode CE2. As described above, the first connection electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED is partially removed, thereby forming a space between the additional passivation layer 219 and the light-emitting element LED. Therefore, during the formation of the second planarization layer 417b, the organic pattern OP can remain in the space between the additional passivation layer 219 and the light-emitting element LED. In other words, even if the second planarization layer 417b is over-greyed, a space exists between the additional passivation layer 219 and the light-emitting element LED, such that during the formation of the second planarization layer 417b, the organic pattern OP remains in the space between the additional passivation layer 219 and the light-emitting element LED. Therefore, by filling the space between the additional passivation layer 219 and the light-emitting element LED, the organic pattern OP can cover the end of the first connecting electrode CE1 disposed between the additional passivation layer 219 and the light-emitting element LED. Therefore, the first connecting electrode CE1 and the second connecting electrode CE2 can be separated. Therefore, short-circuit defects of the first connecting electrode CE1 and the second connecting electrode CE2 can be minimized.

[0200] Exemplary embodiments of this disclosure can also be described as follows: According to embodiments of the present disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on the first planarization layer, the first connecting electrode, and a portion of the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, the passivation layer exposing an end of the first connecting electrode.

[0201] According to another aspect of this disclosure, the height of the uppermost end of the first connecting electrode may be lower than the height of the uppermost end of the passivation layer.

[0202] According to another aspect of this disclosure, the second planarization layer may cover the end of the first connection electrode exposed by the passivation layer.

[0203] According to another aspect of this disclosure, the second planarization layer may be configured to cover the end of the first connecting electrode, which is configured to surround a portion of the side surface of a plurality of light-emitting elements, and the end of the passivation layer.

[0204] The second connecting electrode can be configured to be spaced apart from the passivation layer.

[0205] According to another aspect of this disclosure, the second planarization layer can fill the space between the plurality of light-emitting elements and the passivation layer.

[0206] According to another aspect of this disclosure, the second planarization layer may expose the end of the passivation layer configured to surround a portion of the side surface of a plurality of light-emitting elements.

[0207] According to another aspect of this disclosure, the display device may further include an organic pattern disposed between a passivation layer and a plurality of light-emitting elements, and configured to cover an end of a first connecting electrode that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

[0208] According to another aspect of this disclosure, the organic pattern can cover the end of the first connecting electrode exposed by the passivation layer.

[0209] According to another aspect of this disclosure, the organic pattern can be configured to be spaced apart from the second planarization layer, wherein the passivation layer is interposed therebetween.

[0210] According to another aspect of this disclosure, the height of the top surface of the second planarization layer may be lower than the height of the top surface of the organic pattern.

[0211] According to another aspect of this disclosure, the second connection electrode may be configured to contact at least a portion of the passivation layer.

[0212] According to another aspect of this disclosure, the second connection electrode may contact the end of the passivation layer exposed by the second planarization layer.

[0213] According to another aspect of this disclosure, the display device may further include an organic pattern. In some of the plurality of sub-pixels, the second planarization layer may further include an organic pattern configured to cover the end of the first connecting electrode, which is configured to surround a portion of the side surface of the plurality of light-emitting elements, and the end of the passivation layer. In some of the other sub-pixels, the organic pattern is configured to cover the end of the first connecting electrode, which is configured to surround a portion of the side surface of the plurality of light-emitting elements. In some of the other sub-pixels, the second planarization layer may be spaced apart from the organic pattern, and a passivation layer may be interposed therebetween, and the second planarization layer may expose the end of the passivation layer configured to surround a portion of the side surface of the plurality of light-emitting elements.

[0214] According to another embodiment of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode disposed at a position higher than the first electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a second planarization layer disposed on the first planarization layer and the first connecting electrode; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode.

[0215] According to another aspect of this disclosure, the display device may further include a passivation layer disposed between the first connecting electrode and the second planarization layer. The passivation layer may be configured to surround a portion of the side surfaces of the plurality of light-emitting elements and expose the end of the first connecting electrode disposed on the side surfaces of the plurality of light-emitting elements.

[0216] According to another aspect of this disclosure, a second planarization layer may be provided to cover the end of the first connection electrode exposed by the passivation layer.

[0217] According to another aspect of this disclosure, the height of the top surface of the second planarization layer can be higher than the height of the uppermost end of the passivation layer. The second planarization layer can be provided to cover the end of the passivation layer adjacent to the end of the first connecting electrode.

[0218] According to another aspect of this disclosure, the display device may further include an organic pattern disposed between a passivation layer and a plurality of light-emitting elements, and configured to cover the end of the first connection electrode exposed by the passivation layer. A second planarization layer may be configured to be spaced apart from the organic pattern, wherein the passivation layer is inserted therebetween, and may expose the end of the passivation layer adjacent to the end of the first connection electrode.

[0219] According to another aspect of this disclosure, the height of the uppermost end of the second planarization layer may be lower than the height of the uppermost end of the organic pattern and the height of the uppermost end of the passivation layer, respectively.

[0220] According to another aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels, each light-emitting element including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on at least a portion of the first planarization layer, the first connecting electrode, and the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode, wherein the plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and wherein the height of the uppermost end of the second planarization layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second planarization layer disposed in the first sub-pixel.

[0221] According to another aspect of this disclosure, in the second sub-pixel, the height of the uppermost end of the second planarization layer is lower than the height of the uppermost end of the passivation layer, and in the first sub-pixel, the height of the uppermost end of the second planarization layer is higher than the height of the uppermost end of the passivation layer.

[0222] According to another aspect of this disclosure, in the second sub-pixel, an organic pattern is disposed between the passivation layer and the plurality of light-emitting elements, the organic pattern being configured to cover the end of the first connecting electrode that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

[0223] According to another aspect of this disclosure, in the second sub-pixel, the height of the uppermost end of the second planarization layer is lower than the height of the uppermost end of the passivation layer and the height of the uppermost end of the organic pattern, and in the first sub-pixel, the height of the uppermost end of the second planarization layer is higher than the height of the uppermost end of the passivation layer.

[0224] According to another embodiment of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on the first planarization layer, the first connecting electrode, and a portion of the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode.

[0225] According to another embodiment of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels and including a first electrode and a second electrode disposed at a position higher than the first electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a second planarization layer disposed on the first planarization layer and the first connecting electrode; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode.

[0226] According to another aspect of this disclosure, a display panel includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting elements disposed on the substrate in the plurality of sub-pixels, each light-emitting element including a first electrode and a second electrode; a first planarization layer disposed on the substrate to surround a portion of a side surface of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connected to the first electrode; a passivation layer disposed on the first connecting electrode; a second planarization layer disposed on at least a portion of the first planarization layer, the first connecting electrode, and the passivation layer; and a second connecting electrode disposed on the second planarization layer and connected to the second electrode, wherein the passivation layer exposes an end of the first connecting electrode, wherein the plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and wherein the height of the uppermost end of the second planarization layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second planarization layer disposed in the first sub-pixel.

[0227] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in various forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all embodiments and do not limit the present disclosure.

[0228] Cross-reference to related applications

[0229] This application claims priority and benefit to Korean Patent Application No. 10-2025-0053732, filed with the Korean Intellectual Property Office on April 24, 2025, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A display device, the display device comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in the plurality of sub-pixels, and each light-emitting element includes a first electrode and a second electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A passivation layer is disposed on the first connection electrode; A second planarization layer is disposed on the first planarization layer, the first connection electrode, and a portion of the passivation layer; as well as The second connection electrode is disposed on the second planarization layer and connected to the second electrode. The passivation layer exposes the end of the first connection electrode.

2. The display device according to claim 1, wherein, The height of the uppermost end of the first connecting electrode is lower than the height of the uppermost end of the passivation layer.

3. The display device according to claim 1, wherein, The second planarization layer covers the end of the first connection electrode exposed by the passivation layer.

4. The display device according to claim 3, wherein, The second planarization layer is configured to cover the end of the first connecting electrode, which is configured to surround a portion of the side surface of the plurality of light-emitting elements, and the end of the passivation layer.

5. The display device according to claim 4, wherein, The second connection electrode is configured to be spaced apart from the passivation layer.

6. The display device according to claim 1, wherein, The second planarization layer fills the space between the plurality of light-emitting elements and the passivation layer.

7. The display device according to claim 1, wherein, The second planarization layer exposes the end of the passivation layer that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

8. The display device according to claim 7, further comprising: An organic pattern is disposed between the passivation layer and the plurality of light-emitting elements, and is configured to cover the end of the first connecting electrode that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

9. The display device according to claim 8, wherein, The organic pattern covers the end of the first connecting electrode exposed by the passivation layer.

10. The display device according to claim 8, wherein, The organic pattern is positioned spaced apart from the second planarization layer, and the passivation layer is interposed between the organic pattern and the second planarization layer.

11. The display device according to claim 8, wherein, The height of the top surface of the second planarization layer is lower than the height of the top surface of the organic pattern.

12. The display device according to claim 7, wherein, The second connection electrode is configured to contact at least a portion of the passivation layer.

13. The display device according to claim 12, wherein, The second connecting electrode contacts the end of the passivation layer exposed by the second planarization layer.

14. The display device according to claim 1, further comprising: Organic patterns In some of the plurality of sub-pixels, the second planarization layer is configured to cover the end of the first connecting electrode, which is configured to surround a portion of the side surface of the plurality of light-emitting elements, and the end of the passivation layer. In some other sub-pixels among the plurality of sub-pixels, the organic pattern is configured to cover the end of the first connecting electrode that is configured to surround a portion of the side surface of the plurality of light-emitting elements, and In some of the other sub-pixels among the plurality of sub-pixels, the second planarization layer is configured to be spaced apart from the organic pattern, the passivation layer is interposed between the second planarization layer and the organic pattern, and the second planarization layer exposes the end of the passivation layer that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

15. A display device comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in a plurality of sub-pixels and include a first electrode and a second electrode disposed at a position higher than the first electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A second planarization layer is disposed on the first planarization layer and the first connection electrode; as well as The second connecting electrode is disposed on the second planarization layer and connected to the second electrode.

16. The display device according to claim 15, further comprising: A passivation layer is disposed between the first connecting electrode and the second planarization layer. The passivation layer is configured to surround a portion of the side surface of the plurality of light-emitting elements and expose the end of the first connecting electrode disposed on the side surface of the plurality of light-emitting elements.

17. The display device according to claim 16, wherein, The second planarization layer is configured to cover the end of the first connection electrode exposed by the passivation layer.

18. The display device according to claim 17, wherein, The height of the top surface of the second planarization layer is higher than the height of the uppermost end of the passivation layer, and The second planarization layer is configured to cover the end of the passivation layer adjacent to the end of the first connection electrode.

19. The display device according to claim 16, further comprising: An organic pattern is disposed between the passivation layer and the plurality of light-emitting elements, and is configured to cover the end of the first connecting electrode exposed by the passivation layer. The second planarization layer is configured to be spaced apart from the organic pattern, the passivation layer is interposed between the second planarization layer and the organic pattern, and the second planarization layer exposes the end of the passivation layer adjacent to the end of the first connecting electrode.

20. The display device according to claim 19, wherein, The height of the uppermost end of the second planarization layer is lower than the height of the uppermost end of the organic pattern and the uppermost end of the passivation layer, respectively.

21. A display device comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in the plurality of sub-pixels, and each light-emitting element includes a first electrode and a second electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A passivation layer is disposed on the first connection electrode; A second planarization layer is disposed on at least a portion of the first planarization layer, the first connection electrode, and the passivation layer; as well as The second connection electrode is disposed on the second planarization layer and connected to the second electrode. The passivation layer exposes the end of the first connection electrode. The plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and The height of the uppermost end of the second flattening layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second flattening layer disposed in the first sub-pixel.

22. The display device according to claim 21, in, In the second sub-pixel, the height of the uppermost point of the second planarization layer is lower than the height of the uppermost point of the passivation layer, and In the first sub-pixel, the height of the uppermost end of the second planarization layer is higher than the height of the uppermost end of the passivation layer.

23. The display device according to claim 21, wherein, In the second sub-pixel, an organic pattern is disposed between the passivation layer and the plurality of light-emitting elements, and the organic pattern is configured to cover the end of the first connecting electrode that is configured to surround a portion of the side surface of the plurality of light-emitting elements.

24. The display device according to claim 23, in, In the second sub-pixel, the height of the uppermost point of the second planarization layer is lower than the height of the uppermost point of the passivation layer and the height of the uppermost point of the organic pattern, and In the first sub-pixel, the height of the uppermost end of the second planarization layer is higher than the height of the uppermost end of the passivation layer.

25. A display panel comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in the plurality of sub-pixels, and each light-emitting element includes a first electrode and a second electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A passivation layer is disposed on the first connection electrode; A second planarization layer is disposed on the first planarization layer, the first connection electrode, and a portion of the passivation layer; as well as The second connection electrode is disposed on the second planarization layer and connected to the second electrode. The passivation layer exposes the end of the first connection electrode.

26. A display panel comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in a plurality of sub-pixels and include a first electrode and a second electrode disposed at a position higher than the first electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A second planarization layer is disposed on the first planarization layer and the first connection electrode; as well as The second connecting electrode is disposed on the second planarization layer and connected to the second electrode.

27. A display panel comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; A plurality of light-emitting elements are disposed on the substrate in the plurality of sub-pixels, and each light-emitting element includes a first electrode and a second electrode; A first planarization layer is disposed on the substrate to surround a portion of the side surface of the plurality of light-emitting elements; A first connecting electrode is disposed on the first planarization layer and connected to the first electrode; A passivation layer is disposed on the first connection electrode; A second planarization layer is disposed on at least a portion of the first planarization layer, the first connection electrode, and the passivation layer; as well as The second connection electrode is disposed on the second planarization layer and connected to the second electrode. The passivation layer exposes the end of the first connection electrode. The plurality of sub-pixels includes first sub-pixels and second sub-pixels disposed in different regions of the substrate, and The height of the uppermost end of the second flattening layer disposed in the second sub-pixel is lower than the height of the uppermost end of the second flattening layer disposed in the first sub-pixel.

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