A light emitting diode chip, a preparation method thereof, and a display device

Abstract

The application provides a light emitting diode chip, a preparation method thereof and a display device. The light emitting diode chip comprises a conductive substrate, a first conductive type common layer, a plurality of light emitting unit groups, a first tunnel junction, a second tunnel junction, a mask layer, a first anode wire, a second anode wire, a third anode wire and a common cathode. Each light emitting unit group comprises a first light emitting unit, a second light emitting unit and a third light emitting unit which are sequentially stacked. Specifically, the first conductive type common layer is arranged, and the first tunnel junction and the second tunnel junction are arranged between adjacent light emitting units. The second light emitting unit and the third light emitting unit can access the common conductive network formed by the first conductive type common layer through the corresponding tunnel junctions, the electrical connection relationship between the plurality of light emitting units and the electrode arrangement are simplified, and the integration in the direction of high pixel density is facilitated.

Description

Technical Field

[0001] This application relates to the field of light-emitting diode (LED) chips and their fabrication methods, and in particular to a light-emitting diode chip, its fabrication method, and a display device. Background Technology

[0002] Light-emitting diode (LED) chips offer advantages such as high brightness, low power consumption, and long lifespan. In full-color display applications, multiple light-emitting units of different colors can be stacked vertically within the same pixel area to increase pixel density. However, as multiple light-emitting units are stacked vertically, the electrical connections between them and the electrode arrangement become more complex, hindering the simplification of chip structure and fabrication processes. Summary of the Invention

[0003] To address the aforementioned problems, this application provides a light-emitting diode (LED) chip that solves the problem of complex electrical connection structures in existing LED chips.

[0004] To address the aforementioned problems, the first technical solution provided in this application is: to provide a light-emitting diode chip, comprising: Conductive substrate; A first conductivity type common layer is disposed on one side of the conductive substrate; Multiple light-emitting unit groups are disposed on the side of the first conductivity type common layer away from the conductive substrate; each light-emitting unit group includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit stacked sequentially along a direction away from the conductive substrate; each of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; the first conductivity type common layer is in contact with the first conductivity type semiconductor layer of the first light-emitting unit; A first tunnel junction is disposed between the first light-emitting unit and the second light-emitting unit; The second tunnel junction is disposed between the second light-emitting unit and the third light-emitting unit; A mask layer covers the sides of the light-emitting unit group and the surface of the light-emitting unit group away from the conductive substrate; A first anode line, a second anode line, and a third anode line are disposed on the surface of the mask layer away from the conductive substrate; the first anode line is electrically connected to a second conductivity type semiconductor layer of the first light-emitting unit, the second anode line is electrically connected to a second conductivity type semiconductor layer of the second light-emitting unit, and the third anode line is electrically connected to a second conductivity type semiconductor layer of the third light-emitting unit; and A common cathode, which is electrically connected to a common layer of the first conductivity type.

[0005] In one embodiment, along a direction parallel to the conductive substrate, at least a portion of the edge of the first light-emitting unit protrudes from the side of the second light-emitting unit, such that a portion of the second conductivity type semiconductor layer of the first light-emitting unit is exposed to form a first exposure area; Along a direction parallel to the conductive substrate, at least a portion of the edge of the second light-emitting unit protrudes from the side of the third light-emitting unit, such that a portion of the second conductivity type semiconductor layer of the second light-emitting unit is exposed to form a second exposure area; The mask layer has a first conductive via, a second conductive via, and a third conductive via; the first anode trace is electrically connected to the first exposed area through the first conductive via, the second anode trace is electrically connected to the second exposed area through the second conductive via, and the third anode trace is electrically connected to the second conductive semiconductor layer of the third light-emitting unit through the third conductive via.

[0006] In one embodiment, the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit have the same shape and coincide in center when projected onto the conductive substrate; Both the first and second exposure areas are annular.

[0007] In one embodiment, the second light-emitting unit has the same shape as the orthographic projection of the first light-emitting unit onto the conductive substrate, but their centers are offset. The third light-emitting unit has the same shape as the orthographic projection of the second light-emitting unit onto the conductive substrate, but their centers are offset.

[0008] In one embodiment, along a direction parallel to the conductive substrate, the edge of the second conductivity type semiconductor layer of the first light-emitting unit protrudes from the side of the active layer of the first light-emitting unit, thereby forming a first extension. Along a direction parallel to the conductive substrate, the edge of the second conductivity type semiconductor layer of the second light-emitting unit protrudes from the side of the active layer of the second light-emitting unit, thereby forming a second extension. The first anode trace is electrically connected to the first extension through the first conductive via, and the second anode trace is electrically connected to the second extension through the second conductive via.

[0009] In one embodiment, the mask layer includes: A first mask layer covers the first conductivity type common layer; the first mask layer has a first opening, the first light-emitting unit is disposed in the first opening and protrudes from the first opening; the first extension is disposed on the surface of the first mask layer away from the conductive substrate; A second mask layer covers the first mask layer and the first light-emitting unit; the second mask layer has a second opening, the second light-emitting unit is disposed within the second opening and protrudes from the second opening; a second extension is disposed on the surface of the second mask layer away from the conductive substrate; and A third mask layer covers the second mask layer and the second light-emitting unit; the third mask layer has a third opening, and the third light-emitting unit is disposed within the third opening; A fourth mask layer covers the third mask layer and the third light-emitting unit.

[0010] In one embodiment, the first conductivity type common layer extends to and is spaced from the edge of the conductive substrate; the edge of the mask layer is spaced from the edge of the conductive substrate, such that the side surface of the first conductivity type common layer is exposed. The common cathode is disposed at the edge of the conductive substrate and is electrically connected to at least the side of the first conductivity type common layer.

[0011] To address the aforementioned problems, the second technical solution provided in this application is: a method for fabricating a light-emitting diode chip, comprising: Provide a conductive substrate; A first conductivity type common layer is formed on one side of the conductive substrate; A first mask layer is formed on the side of the first conductivity type common layer away from the conductive substrate, and a first opening is made in the first mask layer to expose part of the first conductivity type common layer. A first light-emitting unit is formed within the first opening; the first light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. A second mask layer is formed on the side of the first mask layer away from the conductive substrate, and a second opening is formed on the second mask layer to expose the first light-emitting unit. A first tunnel junction and a second light-emitting unit are sequentially formed within the second opening; the second light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. A third mask layer is formed on the side of the second mask layer away from the conductive substrate, and a third opening is formed on the third mask layer to expose the second light-emitting unit. A second tunnel junction and a third light-emitting unit are sequentially formed within the third opening; the third light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. A fourth mask layer is formed on the side of the third mask layer away from the conductive substrate; the fourth mask layer covers the third mask layer and the third light-emitting unit; A first anode trace, a second anode trace, and a third anode trace are formed on the side of the fourth mask layer away from the conductive substrate; wherein, the first anode trace is electrically connected to the second conductivity type semiconductor layer of the first light-emitting unit, the second anode trace is electrically connected to the second conductivity type semiconductor layer of the second light-emitting unit, and the third anode trace is electrically connected to the second conductivity type semiconductor layer of the third light-emitting unit; and A common cathode is formed that is electrically connected to the common layer of the first conductivity type.

[0012] In one embodiment, the step of forming a first light-emitting unit within the first opening includes: This causes the second conductivity type semiconductor layer of the first light-emitting unit to protrude from the first opening; and The second conductivity type semiconductor layer of the first light-emitting unit is grown laterally, and a first extension is formed on the surface of the first mask layer away from the conductive substrate; The step of forming the second light-emitting unit within the second opening includes: This causes the second conductivity type semiconductor layer of the second light-emitting unit to protrude from the second opening; and This causes the second conductive type semiconductor layer of the second light-emitting unit to grow laterally, forming a second extension on the surface of the second mask layer away from the conductive substrate.

[0013] To address the aforementioned issues, the third technical solution provided in this application is to provide a display device comprising the light-emitting diode chip described in any of the above embodiments.

[0014] The beneficial effect of this application is that, unlike the prior art, the light-emitting diode chip provided in this application includes a conductive substrate, a first conductivity type common layer disposed on one side of the conductive substrate, a plurality of light-emitting unit groups disposed on the side of the first conductivity type common layer away from the conductive substrate, each light-emitting unit group including a first light-emitting unit, a second light-emitting unit and a third light-emitting unit stacked sequentially along the direction away from the conductive substrate, a first tunnel junction disposed between the first light-emitting unit and the second light-emitting unit, a second tunnel junction disposed between the second light-emitting unit and the third light-emitting unit, a mask layer covering the side of the light-emitting unit group and the surface of the light-emitting unit group away from the conductive substrate, a first anode trace, a second anode trace and a third anode trace disposed on the surface of the mask layer away from the conductive substrate, and a common cathode electrically connected to the first conductivity type common layer. Specifically, this application sets up a first conductivity type common layer and sets up a first tunnel junction and a second tunnel junction between adjacent light-emitting units along the direction away from the conductive substrate, so that the second light-emitting unit and the third light-emitting unit can be connected to the common conductive network formed by the first conductivity type common layer through the corresponding tunnel junctions. This allows multiple light-emitting units to share a common cathode, simplifies the electrical connection relationship and electrode arrangement between multiple light-emitting units, and is beneficial for the integration of light-emitting diode chips towards high pixel density. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a top view of the structure of the light-emitting diode chip provided in the first embodiment of this application; Figure 2 for Figure 1 The first embodiment shown is a schematic diagram of the cross-sectional structure of the light-emitting diode chip along line AA. Figure 3 A perspective view of the light-emitting diode chip provided in the second embodiment of this application; Figure 4 for Figure 3 The diagram shown in the second embodiment is a cross-sectional view of the LED chip along the BB line. Figure 5 This is a top view of the light-emitting diode chip provided in the second embodiment of this application; Figure 6 A schematic diagram showing three anode traces extending in different directions, as provided in the second embodiment of this application; Figure 7AA top view of the first eccentric setting method provided in the third embodiment of this application; Figure 7B A top view of the second eccentric setting method provided in the third embodiment of this application; Figure 7C A top view of the third eccentric setting method provided in the third embodiment of this application; Figure 8 for Figure 3 The fourth embodiment shown is a schematic diagram of the cross-sectional structure of the light-emitting diode chip along the BB line; Figure 9 for Figure 8 Enlarged structural diagram at point A; Figure 10 For Figure 8 The diagram below illustrates the fabrication process of a light-emitting diode chip as an example. Figure 11 This is a flowchart of the preparation method provided in the fourth embodiment of this application; Figure 12 This is a schematic diagram of the process for forming the first extension provided in the fourth embodiment of this application; Figure 13 This is a schematic diagram of the process for forming the second extension provided in the fourth embodiment of this application; Figure 14 This is a schematic diagram of the structure of the display device provided in this application.

[0016] Label Explanation: 10. Display panel; 20. Display device; 30. Light-emitting diode chip; 100. Conductive substrate; 200. First conductivity type common layer; 201. Side surface; 300. Light-emitting unit group; 310. First light-emitting unit; 301. First conductivity type semiconductor layer; 302. Active layer; 303. Second conductivity type semiconductor layer; 311. First main body portion; 312. First extension portion; 313. First exposed area; 320. Second light-emitting unit; 321. Second main body portion; 322. Second extension portion; 323. Second exposed area; 3 30. Third light-emitting unit; 340. First tunnel junction; 350. Second tunnel junction; 400. Mask layer; 410. First mask layer; 420. Second mask layer; 430. Third mask layer; 440. Fourth mask layer; 411. First opening; 412. Second opening; 413. Third opening; 401. First conductive via; 402. Second conductive via; 403. Third conductive via; 510. First anode trace; 520. Second anode trace; 530. Third anode trace; 600. Common cathode; 700. Driver board. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0021] Display devices include a display panel, which comprises multiple pixel units. Each pixel unit can achieve color display through light-emitting units of different colors. As display devices develop towards higher resolution and higher pixel density, multiple light-emitting units can be stacked vertically to increase pixel density, allowing for more pixel units to be placed within a limited display area. However, stacking multiple light-emitting units vertically increases the complexity of electrical connections and electrode arrangements due to their different layers, thus increasing the structural complexity of the LED chip and affecting its integration and fabrication.

[0022] In this regard, the first embodiment of this application provides a light-emitting diode chip 30, see [link to relevant documentation]. Figure 1 and Figure 2 , Figure 1 This is a top view of the light-emitting diode chip provided in the first embodiment of this application. Figure 2 for Figure 1 The diagram shown is a cross-sectional view of the LED chip along line AA in the first embodiment. The LED chip 30 includes a conductive substrate 100, a first conductivity type common layer 200, multiple light-emitting unit groups 300, a first tunnel junction 340, a second tunnel junction 350, a mask layer 400, a first anode trace 510, a second anode trace 520, a third anode trace 530, and a common cathode 600.

[0023] The conductive substrate 100 is formed of a semiconductor material with conductive properties, supports each film layer and the light-emitting structure, and participates in the conduction of the light-emitting diode chip 30.

[0024] Optionally, the conductive substrate 100 can be an n-GaN substrate.

[0025] In one specific embodiment, the conductive substrate 100 is a c-plane (0001) single-crystal conductive n-GaN self-supporting substrate, and the Si doping concentration of the conductive substrate 100 is approximately 8 × 10⁻⁶. 17 cm -3 The resistivity is less than 0.02 Ω·cm.

[0026] The first conductivity type common layer 200 is disposed on one side of the conductive substrate 100, so that multiple light-emitting unit groups 300 establish a common conductive path through the first conductivity type common layer 200. At the same time, the common cathode 600 is electrically connected to the first conductivity type common layer 200, so that the charge carriers input to the common cathode 600 can be transmitted to different light-emitting unit groups 300 through the first conductivity type common layer 200.

[0027] Optionally, the first conductivity type can be either n-type or p-type, and the second conductivity type is a conductivity type different from the first conductivity type.

[0028] In one specific embodiment, the first conductivity type is n-type, the second conductivity type is p-type, the first conductivity type common layer 200 is an n-GaN common layer, and the thickness of the first conductivity type common layer 200 is approximately 2.5 μm, with a carrier concentration of approximately 8 × 10⁻⁶. 18 cm -3 .

[0029] With the above settings, the first conductivity type common layer 200 can have better conductivity and lateral current expansion capability, so as to transmit the current input from the common cathode 600 to different light-emitting unit groups 300 and reduce the voltage drop during the lateral transmission of current.

[0030] In this configuration, multiple light-emitting unit groups 300 are disposed on the side of the first conductivity type common layer 200 away from the conductive substrate 100, and the multiple light-emitting unit groups 300 are spaced apart along a direction parallel to the conductive substrate 100, with each light-emitting unit group 300 corresponding to a pixel unit of the display device.

[0031] Specifically, each light-emitting unit group 300 includes a first light-emitting unit 310, a second light-emitting unit 320 and a third light-emitting unit 330 stacked sequentially along a direction away from the conductive substrate 100. Stacking multiple light-emitting units along a direction away from the conductive substrate 100 can reduce the area occupied by multiple light-emitting units in the direction parallel to the conductive substrate 100, which is beneficial to improving the pixel density of the display device.

[0032] Optionally, in this embodiment, the first light-emitting unit 310 can be a blue light-emitting unit, the second light-emitting unit 320 can be a green light-emitting unit, and the third light-emitting unit 330 can be a red light-emitting unit. The first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330 each correspond to a sub-pixel of the display device.

[0033] Specifically, the first light-emitting unit 310, the second light-emitting unit 320 and the third light-emitting unit 330 each include a first conductivity type semiconductor layer 301, an active layer 302 and a second conductivity type semiconductor layer 303. The active layer is disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer are used to provide different types of charge carriers from both sides of the active layer, so that different types of charge carriers enter the active layer and undergo radiative recombination, thereby emitting light.

[0034] Optionally, the first conductivity type semiconductor layer can be an n-type semiconductor layer, used to provide electrons to the active layer; the second conductivity type semiconductor layer can be a p-type semiconductor layer, used to provide holes to the active layer. After electrons and holes enter the active layer, they undergo radiative recombination, thereby causing the corresponding light-emitting unit to emit light.

[0035] Optionally, the active layer in this embodiment adopts an InGaN / GaN multi-quantum-well structure, and different light-emitting units can generate light of different wavelengths by adjusting parameters such as the composition and thickness of the material in the quantum well.

[0036] In one specific embodiment, the center-to-center spacing of adjacent light-emitting unit groups 300 can be 20±1μm, which is beneficial to improving pixel density and reserving space for the arrangement of adjacent light-emitting unit groups 300.

[0037] The first conductivity type semiconductor layer 301 of the first light-emitting unit 310 can be an n-GaN layer with a thickness of 30±5nm and a Si doping concentration of 5×10⁻⁶. 18 cm -3 The active layer 302 of the first light-emitting unit 310 can be two pairs of InO. 15 Ga0. 85 The N / GaN multiple quantum well has a peak emission wavelength of 450±5nm; the active layer 302 of the second light-emitting unit 320 can be two pairs of InO. 25 Ga0. 75 The N / GaN multiple quantum well has a peak emission wavelength of 520±5nm; the active layer 302 of the third light-emitting unit 330 can be 3 pairs of InO. 28 Ga0. 72 The N / GaN multiple quantum well has a peak emission wavelength of 590 nm to 610 nm. With the above configuration, the three light-emitting units can produce light of different colors to achieve color display.

[0038] Understandably, the first conductivity type common layer 200 is in contact with the first conductivity type semiconductor layer 301 of the first light-emitting unit 310, so that a direct conductive path is formed between the first conductivity type common layer 200 and the first light-emitting unit 310, so that the charge carriers input from the common cathode 600 can enter the first conductivity type semiconductor layer 301 of the first light-emitting unit 310 through the first conductivity type common layer 200, and further enter the active layer 302 of the first light-emitting unit 310.

[0039] The first tunnel junction 340 is disposed between the first light-emitting unit 310 and the second light-emitting unit 320, and the second tunnel junction 350 is disposed between the second light-emitting unit 320 and the third light-emitting unit 330.

[0040] Specifically, the first tunnel junction 340 can establish a conductive connection between the first light-emitting unit 310 and the second light-emitting unit 320, and the second tunnel junction 350 can establish a conductive connection between the second light-emitting unit 320 and the third light-emitting unit 330.

[0041] Understandably, when the first conductivity type is n-type, the n-type semiconductor layer of the first light-emitting unit 310 can be directly connected to the n-type common layer, which is also of the first conductivity type; the n-type semiconductor layer of the second light-emitting unit 320 can be connected to the n-type conductive network below through the first tunnel junction 340; and the n-type semiconductor layer of the third light-emitting unit 330 can be connected to the n-type conductive network below through the second tunnel junction 350 and the first tunnel junction 340. The three light-emitting units do not need to be equipped with independent cathodes.

[0042] In one specific embodiment, both the first tunnel joint 340 and the second tunnel joint 350 include p arranged sequentially. ++ -GaN and n ++ -GaN layer.

[0043] Where, p ++ -GaN thickness is approximately 20 nm, Mg doping ≥ 1 × 10⁻⁶ 20 cm -3 And using δ-doping layer-by-layer doping, n ++ The GaN thickness is approximately 20 nm, and the Si doping is ≥5 × 10⁻⁶. 19 cm -3 Furthermore, the tunneling resistance of both the first tunnel junction 340 and the second tunnel junction 350 is less than 5 × 10⁻⁶. -3 The heavy doping setting described above can improve the tunneling transport capability of charge carriers and reduce the series resistance between adjacent light-emitting units.

[0044] The mask layer 400 covers the side surface of the light-emitting unit group 300 and the surface of the light-emitting unit group 300 away from the conductive substrate 100.

[0045] Specifically, the mask layer 400 can be formed using an insulating dielectric material to cover and protect part of the surface and sides of the light-emitting unit, reducing the possibility of damage to the light-emitting structure during subsequent processing.

[0046] Optionally, the mask layer 400 may include at least one of the dielectric materials such as AlN, SiO2, and Al2O3.

[0047] Specifically, the first anode line 510, the second anode line 520, and the third anode line 530 are disposed on the surface of the mask layer 400 away from the conductive substrate 100. The first anode line 510 is electrically connected to the second conductive type semiconductor layer 303 of the first light-emitting unit 310, the second anode line 520 is electrically connected to the second conductive type semiconductor layer 303 of the second light-emitting unit 320, and the third anode line 530 is electrically connected to the second conductive type semiconductor layer 303 of the third light-emitting unit 330.

[0048] Understandably, the first anode trace 510, the second anode trace 520, and the third anode trace 530 each form an independent anode driving path for three light-emitting units.

[0049] In this embodiment, when the first anode trace 510 is driven, the charge carriers provided by the common cathode 600 enter the first light-emitting unit 310 through the first conductivity type common layer 200, and the other type of charge carriers enter the first light-emitting unit 310 through the first anode trace 510, so that the two types of charge carriers undergo radiative recombination in the active layer 302 of the first light-emitting unit 310, thereby causing the first light-emitting unit 310 to emit light.

[0050] For example, when the first conductivity type is n-type and the second conductivity type is p-type, electrons enter the first light-emitting unit 310 from the common cathode 600 through the n-type common layer, and holes are injected into the active layer 302 of the first light-emitting unit 310 through the p-type semiconductor layer from the first anode trace 510, thereby generating blue light.

[0051] When the second anode line 520 is driven, electrons can enter the first conductivity type common layer 200 from the common cathode 600 and be transported to the first conductivity type semiconductor layer 301 of the second light-emitting unit 320 through the first tunnel junction 340; holes enter the second conductivity type semiconductor layer 303 of the second light-emitting unit 320 from the second anode line 520, thereby causing electrons and holes to recombine in the active layer 302 of the second light-emitting unit 320, making the second light-emitting unit 320 emit light. When the third anode line 530 is driven, electrons can be transported sequentially through the first conductivity type common layer 200, the first tunnel junction 340, and the second tunnel junction 350 to the third light-emitting unit 330, and recombine with the holes injected by the third anode line 530 in the active layer 302 of the third light-emitting unit 330, making the third light-emitting unit 330 emit light.

[0052] In other embodiments, the first light-emitting unit 310, the second light-emitting unit 320 and the third light-emitting unit 330 can cooperate to obtain the target display color by mixing different colored lights.

[0053] In this embodiment, by providing a first conductivity type common layer 200 and providing a first tunnel junction 340 and a second tunnel junction 350 between adjacent light-emitting units along the direction away from the conductive substrate 100, the second light-emitting unit 320 and the third light-emitting unit 330 can be connected to the common conductive network formed by the first conductivity type common layer 200 through the corresponding tunnel junctions. Simultaneously, the three light-emitting units can be driven respectively through the first anode trace 510, the second anode trace 520, and the third anode trace 530. Therefore, multiple light-emitting units can share a common cathode 600, simplifying the electrical connection relationship and electrode arrangement between multiple light-emitting units, and facilitating the integration of the light-emitting diode chip 30 towards higher pixel density.

[0054] See Figure 3 and Figure 4 , Figure 3 This is a perspective view of the light-emitting diode chip provided in the second embodiment of this application. Figure 4 for Figure 3 The diagram shows a cross-sectional view of the LED chip along line BB in the second embodiment.

[0055] In the second embodiment, along a direction parallel to the conductive substrate 100, at least a portion of the edge of the first light-emitting unit 310 protrudes from the side surface of the second light-emitting unit 320, so that a portion of the surface of the second conductivity type semiconductor layer 303 of the first light-emitting unit 310 is not covered by the second light-emitting unit 320, and this portion forms the first exposure area 313; at least a portion of the edge of the second light-emitting unit 320 protrudes from the side surface of the third light-emitting unit 330, so that a portion of the surface of the second conductivity type semiconductor layer 303 of the second light-emitting unit 320 is not covered by the third light-emitting unit 330, and this portion forms the second exposure area 323.

[0056] Understandably, the first exposure area 313 and the second exposure area 323 can be used to form the electrical connection area of ​​the corresponding light-emitting unit.

[0057] Specifically, the mask layer 400 has a first conductive via 401, a second conductive via 402, and a third conductive via 403, and the first conductive via 401, the second conductive via 402, and the third conductive via 403 are only provided in the mask layer 400.

[0058] The first conductive via 401 is provided corresponding to the first exposed area 313, the second conductive via 402 is provided corresponding to the second exposed area 323, and the third conductive via 403 is provided corresponding to the second conductive semiconductor layer 303 of the third light-emitting unit 330.

[0059] Specifically, the first anode trace 510 is electrically connected to the first exposed area 313 through the first conductive via 401, the second anode trace 520 is electrically connected to the second exposed area 323 through the second conductive via 402, and the third anode trace 530 is electrically connected to the second conductive semiconductor layer 303 of the third light-emitting unit 330 through the third conductive via 403.

[0060] Understandably, the distance between the first conductive via 401 and the side of the second light-emitting unit 320 is 0.35μm to avoid interference between the first conductive via 401 and the second light-emitting unit 320, and to reserve process margin for subsequent processes.

[0061] In one specific embodiment, the first conductive via 401, the second conductive via 402, and the third conductive via 403 are all circular with a diameter of approximately 1.3 μm.

[0062] In this embodiment, by making adjacent light-emitting units have different extension ranges in a direction parallel to the conductive substrate 100, an exposed area for electrical connection can be formed on the lower light-emitting unit. This allows the first conductive via 401 and the second conductive via 402 to be formed only in the mask layer 400, reducing the risk of damage to the light-emitting unit caused by deep opening or etching in the active region of the light-emitting unit. Furthermore, the first anode trace 510 and the second anode trace 520 can be connected to the second conductivity type semiconductor layer 303 of the first light-emitting unit 310 and the second light-emitting unit 320, respectively, which is beneficial for forming anode connection structures of different levels of light-emitting units in a vertically stacked structure.

[0063] In the second embodiment, the first light-emitting unit 310, the second light-emitting unit 320 and the third light-emitting unit 330 have the same shape and coincide in center on the orthogonal projection on the conductive substrate 100, and the first exposure area 313 and the second exposure area 323 are both annular.

[0064] Specifically, see Figure 4 and Figure 5 , Figure 5 This is a top view of the light-emitting diode chip provided in the second embodiment of this application. The first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330 may have gradually decreasing lateral dimensions along the direction away from the conductive substrate 100. The first exposed area 313 and the second exposed area 323 are both annular.

[0065] Optionally, the orthographic projections of the first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330 onto the conductive substrate 100 can be circular, elliptical, or the like, and are not limited here.

[0066] In this embodiment, when the orthographic projection is circular, the three light-emitting units can form a concentric structure with a radius that gradually decreases along the direction away from the conductive substrate 100.

[0067] Further, see Figure 6 , Figure 6 This is a schematic diagram illustrating the three anode traces extending in different directions according to the second embodiment of this application. After the first anode trace 510 is electrically connected to the first exposed area 313, the second anode trace 520 is electrically connected to the second exposed area 323, and the third anode trace 530 is electrically connected to the second conductivity type semiconductor layer 303 of the third light-emitting unit 330, the first anode trace 510, the second anode trace 520, and the third anode trace 530 extend in different directions parallel to the first conductivity type common layer 200. This arrangement reduces the possibility of the three anode traces crossing or interfering with each other, facilitates the separate routing of each anode trace, and improves the flexibility of the anode trace arrangement.

[0068] In one specific embodiment, the diameter of the first light-emitting unit 310 is 7.0±0.2μm, the diameter of the second light-emitting unit 320 is 5.0±0.2μm, and the diameter of the third light-emitting unit 330 is 3.0±0.2μm.

[0069] In this embodiment, by aligning the orthographic projection centers of the first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330, the light-emitting units can be arranged more regularly along the stacking direction. At the same time, an exposed area surrounding the upper light-emitting unit is formed between adjacent light-emitting units, forming an anode connection position.

[0070] In the third embodiment, the second light-emitting unit 320 and the first light-emitting unit 310 have the same shape as the orthogonal projection on the conductive substrate 100 but their centers are offset, and the third light-emitting unit 330 has the same shape as the orthogonal projection on the conductive substrate 100 but their centers are offset.

[0071] Understandable, see Figure 7A , Figure 7A The diagram above shows a top view of the first eccentric setting method provided in the third embodiment of this application. With the orthographic projection center of the first light-emitting unit 310 as a reference, the orthographic projection center of the second light-emitting unit 320 is offset relative to the orthographic projection center of the first light-emitting unit 310 along a first direction; the orthographic projection center of the third light-emitting unit 330 is also offset relative to the orthographic projection center of the second light-emitting unit 320 along the first direction.

[0072] In this application, the specific offset direction and offset distance of the first direction are not limited, and can be set according to the light-emitting area, the electrode connection area and the display requirements.

[0073] Specifically, by shifting the first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330 sequentially in the same direction, an exposed area with different widths can be formed between adjacent light-emitting units, providing more arrangement space for the first conductive via 401, the second conductive via 402, and the third conductive via 403, and also increasing the distance between the conductive via and the side of the adjacent light-emitting unit.

[0074] In this embodiment, the above-mentioned offset setting can improve the arrangement flexibility of the electrode connection structure while taking into account the light-emitting area, which helps to reduce the possibility of interference between the conductive via and the adjacent light-emitting unit.

[0075] Further, see Figure 7B and Figure 7C , Figure 7B A top view of the second eccentric setting method provided in the third embodiment of this application. Figure 7C This is a top view of the third eccentric setting method provided in the third embodiment of this application.

[0076] Specifically, with the orthographic projection center of the first light-emitting unit 310 as a reference, the orthographic projection center of the second light-emitting unit 320 is offset relative to the orthographic projection center of the first light-emitting unit 310 along a first direction; and the orthographic projection center of the third light-emitting unit 330 is offset relative to the orthographic projection center of the second light-emitting unit 320 along a second direction.

[0077] The first direction and the second direction are opposite in orientation, see [link / reference]. Figure 7B The centers of the orthographic projections of the first conductive via 401, the second conductive via 402, and the third conductive via 403 on the conductive substrate 100 are located on the same straight line, which helps to simplify the layout design and the subsequent arrangement of metal traces.

[0078] See Figure 7C The centers of the orthographic projections of the first conductive via 401, the second conductive via 402, and the third conductive via 403 on the conductive substrate 100 are not on the same straight line, so that the three conductive vias are staggered along the circumference of the light-emitting unit group 300, reducing the possibility of intersection or interference between different anode traces.

[0079] Understandably, this application does not limit the specific offset direction and offset distance, which can be set according to the light-emitting area, electrode connection area and display requirements.

[0080] In this embodiment, by placing the orthographic projection centers of the first light-emitting unit 310, the second light-emitting unit 320, and the third light-emitting unit 330 on the same straight line, and placing the orthographic projection center of the second light-emitting unit 320 between the orthographic projection centers of the first light-emitting unit 310 and the third light-emitting unit 330, and by shifting the second light-emitting unit 320 relative to the first light-emitting unit 310 along a first direction, and by shifting the third light-emitting unit 330 relative to the second light-emitting unit 320 along a second direction opposite to the first direction, the overall offset of the light-emitting area caused by the three light-emitting units shifting in the same direction can be reduced. This is beneficial for the more uniform mixing of different colors of light in space and improves the uniformity of light mixing.

[0081] See Figure 3 and Figure 8 , Figure 8 for Figure 3 The diagram shows a cross-sectional view of the LED chip along the BB line in the fourth embodiment. In the fourth embodiment, the first light-emitting unit 310 includes a first main body 311 and a first extension 312, and the second light-emitting unit 320 includes a second main body 321 and a second extension 322. The first extension 312 and the second extension 322 are mainly formed by extending a second conductivity type semiconductor layer corresponding to the light-emitting unit to the periphery of the light-emitting region.

[0082] Specifically, along a direction parallel to the conductive substrate 100, the edge of the second conductivity type semiconductor layer 303 of the first light-emitting unit 310 protrudes from the side of the active layer 302 of the first light-emitting unit 310, forming a first extension 312; the edge of the second conductivity type semiconductor layer 303 of the second light-emitting unit 320 protrudes from the side of the active layer 302 of the second light-emitting unit 320, forming a second extension 322.

[0083] Understandably, the first main body portion 311 is the main stacked region in the first light-emitting unit 310 where a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer located above the active layer are formed. The first extension portion 312 is formed by the second conductivity type semiconductor layer 303 of the first light-emitting unit 310 extending from the first main body portion 311 to the periphery. The second main body portion 321 is the main light-emitting stacked region of the second light-emitting unit 320. The second extension portion 322 is formed by the second conductivity type semiconductor layer 303 of the second light-emitting unit 320 extending from the second main body portion 321 to the periphery.

[0084] Specifically, the first anode trace 510 is electrically connected to the first extension 312 through the first conductive via 401, and the second anode trace 520 is electrically connected to the second extension 322 through the second conductive via 402.

[0085] In one specific embodiment, the first extension 312 of the first light-emitting unit 310 extends outward by about 2.5 μm, and the second extension 322 of the second light-emitting unit 320 extends outward by about 1.5 μm.

[0086] In this embodiment, by extending the second conductivity type semiconductor layer into an active layer in a direction parallel to the conductive substrate 100, the region for anode connection can be spatially separated from the main light-emitting region, so that the anode connection structure can be formed on the periphery of the active layer.

[0087] In the fourth embodiment, the third light-emitting unit 330, the second main body 321 and the first main body 311 have the same shape and coincide in center when projected onto the conductive substrate 100.

[0088] Optionally, the orthographic projections of the first main body portion 311, the second main body portion 321, and the third light-emitting unit 330 onto the conductive substrate 100 can all be circular, and the centers of the three overlap.

[0089] Optionally, the lateral dimensions of the first main body 311, the second main body 321, and the third light-emitting unit 330 may be the same or different.

[0090] In one specific embodiment, the lateral dimensions of the first main body portion 311, the second main body portion 321, and the third light-emitting unit 330 decrease layer by layer.

[0091] In this embodiment of the application, by arranging the main body of each light-emitting unit in a corresponding manner along the stacking direction, and by extending the first extension 312 and the second extension 322 from the corresponding main body to the periphery, the main light-emitting area can maintain a relatively concentrated vertical stacking structure.

[0092] In the fourth embodiment, the mask layer 400 includes a first mask layer 410, a second mask layer 420, a third mask layer 430 and a fourth mask layer 440 disposed sequentially along a direction away from the conductive substrate 100.

[0093] The first mask layer 410 covers the first conductivity type common layer 200 and has a first opening 411. The first light-emitting unit 310 is disposed in the first opening 411 and protrudes from the first opening 411 in a direction away from the conductive substrate 100.

[0094] Understandably, the second conductive semiconductor layer 303 of the first light-emitting unit 310 can continue to extend laterally along the surface of the first mask layer 410 after protruding the first opening 411, so that the first extension 312 is disposed on the surface of the first mask layer 410 away from the conductive substrate 100.

[0095] The second mask layer 420 covers the first mask layer 410 and the first light-emitting unit 310, and has a second opening 412. The second light-emitting unit 320 is disposed in the second opening 412 and protrudes from the second opening 412 in a direction away from the conductive substrate 100. The second extension 322 can be disposed on the surface of the second mask layer 420 away from the conductive substrate 100.

[0096] The third mask layer 430 covers the second mask layer 420 and the second light-emitting unit 320, and has a third opening 413, in which the third light-emitting unit 330 is disposed.

[0097] The fourth mask layer 440 covers the third mask layer 430 and the third light-emitting unit 330, thereby covering and protecting the already formed light-emitting structure, and can be used to achieve electrical isolation between the light-emitting structure and the metal traces above it.

[0098] Optionally, each mask layer 400 can be formed using a single insulating material or a composite structure formed using multiple insulating materials.

[0099] In one specific embodiment, the first mask layer 410, the second mask layer 420, and the third mask layer 430 can all adopt an AlN / SiO2 composite structure, wherein AlN can serve as an etching stop layer and a stress buffer layer, and SiO2 serves as the main mask material. Taking the first mask layer 410 as an example, it can include an AlN layer of approximately 15 nm and a SiO2 layer of approximately 100 nm.

[0100] In this embodiment, by setting multiple levels of mask layers 400 and using the openings in each level of mask layer 400 to define the formation areas of different light-emitting units, multiple light-emitting units can be formed sequentially in the vertical direction and selective growth of each light-emitting unit can be achieved. At the same time, each level of mask layer 400 can also cover and protect the already formed light-emitting structure and provide lateral growth and bearing areas for the first extension 312 and the second extension 322, thereby facilitating the formation of vertically stacked light-emitting structures and corresponding electrode connection structures.

[0101] In the first, second, third, and fourth embodiments, the first conductivity type common layer 200 extends to the edge region of the conductive substrate 100 and is spaced apart from the edge of the conductive substrate 100, and the edge of the mask layer 400 is spaced apart from the edge of the conductive substrate 100, so that the side surface of the first conductivity type common layer 200 is at least partially exposed.

[0102] The common cathode 600 is disposed at the edge of the conductive substrate 100 and is electrically connected to at least the exposed side of the first conductivity type common layer 200.

[0103] Understandable, see Figure 9 , Figure 9 for Figure 8 An enlarged structural diagram at point A. A stepped structure can be formed in the edge region of the conductive substrate 100, so that the first conductivity type common layer 200 forms a side surface 201 at the stepped position that can be contacted from the outside of the chip. After the fabrication of the light-emitting unit and its above structure is completed, the mask material covering this area is removed, thereby exposing the side surface 201 of the first conductivity type common layer 200.

[0104] In one specific embodiment, an annular step with a width of approximately 200 μm and a depth of approximately 3 μm can be reserved at the edge of the conductive substrate 100 to form the n-GaN common layer side surface 201, and the step is kept at a certain distance from the effective pixel area. After removing the dielectric layer and parasitic material on the side surface 201, a Ti / Al / Ni / Au metal layer can be formed on the exposed n-GaN side surface to form the common cathode 600.

[0105] In this embodiment, by placing the common cathode 600 at the edge of the conductive substrate 100 and electrically connecting the common cathode 600 to the side 201 of the first conductive type common layer 200, an electrical connection between the external driving circuit and the first conductive type common layer 200 can be established from the chip edge. The first conductive type common layer 200 is then used to transmit current to multiple light-emitting unit groups 300, thereby reducing the occupation of the effective pixel area by the common cathode 600 and facilitating the sharing of the common cathode 600 by multiple light-emitting unit groups 300.

[0106] See Figure 10 , Figure 10 For Figure 8 The diagram shows a fabrication process using a light-emitting diode chip as an example. Figure 10 As shown in (a), a first conductivity type common layer 200 is first formed on one side of the conductive substrate 100; as Figure 10 (b) to Figure 10 As shown in (d), a first mask layer 410 and a first opening 411 are formed on the first conductivity type common layer 200, and a first conductivity type semiconductor layer 301, an active layer 302, a second conductivity type semiconductor layer 303, and a first extension 312 of the first light-emitting unit 310 are sequentially formed within the first opening 411; as shown in (d), a first mask layer 410 and a first opening 411 are formed on the first conductivity type common layer 200, and a first extension 312 of the first light-emitting unit 310; Figure 10 (e) and Figure 10 As shown in (f), a second mask layer 420 and a second opening 412 are formed, and a first tunnel junction 340, a second light-emitting unit 320, and a second extension 322 are sequentially formed within the second opening 412; as shown in (f), a second mask layer 420 and a second opening 412 are formed. Figure 10 (g) and Figure 10 As shown in (h), a third mask layer 430 and a third opening 413 are formed, and a second tunnel junction and a third light-emitting unit 330 are sequentially formed within the third opening 413; as shown in (h). Figure 10 As shown in (i), a fourth mask layer 440 and a first anode trace 510, a second anode trace 520 and a third anode trace 530 are formed; as Figure 10 As shown in (j), a common cathode 600 electrically connected to a first conductivity type common layer 200 is formed at the edge of the conductive substrate 100, thereby obtaining a light-emitting diode chip 30. Further, as... Figure 10 As shown in (k), the substrate of the fabricated light-emitting diode chip 30 is thinned and bonded to the driver board 700 so that the three anodes and the common cathode are electrically connected to the corresponding driving terminals of the driver board 700.

[0107] Specifically, in this embodiment, the driving board 700 is a complementary metal-oxide-semiconductor (CMOS) driving board. The driving board 700 includes a plurality of driving units corresponding one-to-one with a plurality of light-emitting unit groups 300. Each driving unit is electrically connected to the first anode trace 510, the second anode trace 520, the third anode trace 530 and the common cathode 600, respectively.

[0108] See Figure 11 , Figure 11 This is a flowchart illustrating the fabrication method provided in the fourth embodiment of this application. This application also provides a method for fabricating a light-emitting diode (LED) chip, which can be used to fabricate the LED chip 30 in any of the above embodiments. The fabrication method includes the following steps.

[0109] Step S1: Provide a conductive substrate and form a common layer of a first conductivity type on one side of the conductive substrate.

[0110] Optionally, the conductive substrate can be a conductive GaN substrate, and if the first conductivity type is n-type, the first conductivity type common layer can be an n-GaN common layer.

[0111] In one specific embodiment, a c-plane (0001) single-crystal conductive n-GaN self-supporting substrate can be used, and an n-GaN common layer can be epitaxially formed on the conductive substrate using a metal-organic chemical vapor deposition (MOCVD) process.

[0112] Specifically, an n-GaN common layer can be grown at approximately 1080°C, approximately 250 mbar, and a molar flow ratio of approximately 3000 for the group V precursor and the group III precursor. The thickness of the resulting n-GaN common layer is approximately 2.5 μm, and the carrier concentration can be approximately 8 × 10¹¹. 8 cm -3 .

[0113] Optionally, an annular step can be pre-formed at the edge of the conductive substrate so that the first conductivity type common layer can be exposed from the chip edge in subsequent processes, thereby reserving a position for the formation of the common cathode. The width of the annular step can be 200±20μm and the depth can be 3.0±0.3μm.

[0114] Step S2: A first mask layer is formed on the side of the first conductivity type common layer away from the conductive substrate, and a first opening is formed in the first mask layer to expose part of the first conductivity type common layer.

[0115] In one specific embodiment, an AlN layer with a thickness of approximately 15±2 nm can be formed using atomic layer deposition (ALD), and a SiO2 layer with a thickness of approximately 100±10 nm can be formed using plasma-enhanced chemical vapor deposition (PECVD), so that the total thickness of the first mask layer is approximately 115±12 nm, and the first opening is a circular opening with a diameter of approximately 7.0±0.2 μm.

[0116] Optionally, a step-by-step etching method can be used to remove the SiO2 layer and AlN layer at the first opening in sequence to expose the underlying first conductivity type common layer, thereby reducing the etching damage to the first conductivity type common layer during the opening process.

[0117] Step S3: Form the first light-emitting unit within the first opening.

[0118] Specifically, a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer can be sequentially formed within the first opening in a direction away from the conductive substrate.

[0119] In one specific embodiment, when the first conductivity type is n-type and the second conductivity type is p-type, an n-GaN layer with a thickness of 30±5nm can be formed first on the exposed n-GaN common layer to repair surface damage that may occur during the opening process and provide a relatively flat growth interface for the subsequent active layer; then an InGaN / GaN multi-quantum-well active layer for generating blue light is formed, and a p-type semiconductor layer is further formed.

[0120] Step S4: A second mask layer is formed on the side of the first mask layer and the first light-emitting unit away from the conductive substrate, and a second opening is formed in the second mask layer to expose the first light-emitting unit.

[0121] Specifically, the second mask layer adopts a composite mask structure that is the same as or similar to the first mask layer, and the second opening is set in the second conductive type semiconductor layer corresponding to the first light-emitting unit, providing a formation area for the first tunnel junction and the second light-emitting unit.

[0122] Step S5: The first tunnel junction and the second light-emitting unit are formed sequentially within the second opening.

[0123] The second light-emitting unit also includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer.

[0124] In one specific embodiment, the first tunnel junction may be formed on the p-GaN surface of the first light-emitting unit and includes p ++ -GaN layer and n ++ -GaN layer, where p ++ -GaN layer and n ++ The thickness of the GaN layer can be approximately 20 nm. Subsequently, a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer of the second light-emitting unit are sequentially formed on the first tunnel junction. The active layer of the second light-emitting unit can adopt an InGaN / GaN multiple quantum well structure to generate green light.

[0125] Step S6: A third mask layer is formed on the side of the second mask layer and the second light-emitting unit away from the conductive substrate, and a third opening is formed in the third mask layer to partially expose the second light-emitting unit.

[0126] Specifically, the third mask layer can adopt a composite mask structure similar to the first mask layer and the second mask layer, and the third opening can be set in the second conductive type semiconductor layer of the second light-emitting unit to define the formation area of ​​the second tunnel junction and the third light-emitting unit.

[0127] Step S7: The second tunnel junction and the third light-emitting unit are formed sequentially in the third opening.

[0128] In one specific embodiment, a second tunnel junction with the same or similar structure as the first tunnel junction can be formed first, and then the active layer of the third light-emitting unit and the second conductivity type semiconductor layer can be formed. The active layer of the third light-emitting unit can be 3 pairs of InO. 28 Ga0. 72 N / GaN quantum wells can have emission peak wavelengths ranging from 590 nm to 610 nm.

[0129] Step S8: A fourth mask layer is formed on the side of the third mask layer away from the conductive substrate, so that the fourth mask layer covers the third mask layer and the third light-emitting unit.

[0130] The fourth mask layer can insulate and protect the completed light-emitting structure and provide a supporting surface for the subsequent formation of anode traces.

[0131] In one specific embodiment, the fourth mask layer may include an Al2O3 layer and a SiO2 layer, wherein the thickness of the Al2O3 layer may be 20±2nm, the thickness of the SiO2 layer may be 150±10nm, and the total thickness of the fourth mask layer may be approximately 170nm.

[0132] Step S9: Form the first anode trace, the second anode trace, and the third anode trace on the side of the fourth mask layer away from the conductive substrate.

[0133] The first anode trace is electrically connected to the second conductivity type semiconductor layer of the first light-emitting unit, the second anode trace is electrically connected to the second conductivity type semiconductor layer of the second light-emitting unit, and the third anode trace is electrically connected to the second conductivity type semiconductor layer of the third light-emitting unit.

[0134] Specifically, conductive vias corresponding to the first, second, and third light-emitting units can be formed respectively, and conductive material can be formed in the conductive vias to establish an electrical connection between each light-emitting unit and its corresponding anode trace.

[0135] In one specific embodiment, three conductive vias are defined in a single photolithography step. The diameter of each of the three conductive vias can be approximately 1.3 μm. After exposing the surface of the corresponding second conductivity type semiconductor layer, a Ni / Au seed layer can be formed, and Au is used to fill the conductive vias to form conductive pillars. Then, a metal trace is formed at the end of the conductive pillar away from the conductive substrate. For example, Ti / Al / Ti / Au can be used to form the first anode trace, the second anode trace, and the third anode trace.

[0136] Step S10: Form a common cathode that is electrically connected to the common layer of the first conductivity type.

[0137] Optionally, the side of the first conductivity type common layer may be exposed in the edge region of the conductive substrate, and a common cathode may be formed on that side.

[0138] In one specific embodiment, dielectric materials such as SiO2, AlN, and Al2O3 in the edge step region can be removed sequentially, and parasitic GaN on the surface can be removed by light etching, thereby exposing the side of the n-GaN common layer; subsequently, a Ti / Al / Ni / Au metal layer can be formed on this side and rapid thermal annealing can be performed to form a low-resistance ohmic contact.

[0139] In this embodiment, by using multi-level masks to sequentially define the formation positions of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, and forming corresponding tunnel junctions between adjacent light-emitting units, multiple light-emitting units stacked vertically can be formed on the same conductive substrate. At the same time, by forming three independent anode traces and a common cathode connected to the common layer of the first conductivity type, an electrical connection structure in which multiple light-emitting units share a cathode and the anodes are independently controlled can be formed, which helps to simplify the electrical connection structure of vertically stacked light-emitting diode chips.

[0140] Based on the above preparation method, the second conductive type semiconductor layer of the first light-emitting unit and the second light-emitting unit can also be formed by lateral overgrowth to form the first extension and the second extension.

[0141] Specifically, see Figure 8 Step S3 may further include the following steps: Step S31: Form the first main body of the first light-emitting unit.

[0142] Specifically, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer of the first light-emitting unit are sequentially formed within the first opening, and the second conductive type semiconductor layer protrudes from the first opening in a direction away from the conductive substrate.

[0143] Step S32: Form the first extension.

[0144] Specifically, the second conductive type semiconductor layer of the first light-emitting unit continues to grow, such that the second conductive type semiconductor layer of the first light-emitting unit grows laterally, and a first extension is formed on the surface of the first mask layer away from the conductive substrate.

[0145] Optionally, if the first conductivity type is n-type and the second conductivity type is p-type, the semiconductor layer of the second conductivity type can be a p-GaN layer.

[0146] In one specific embodiment, the growth conditions can be adjusted to a Ga-rich growth environment of approximately 920°C, approximately 50 mbar, and a V / III ratio of approximately 2000, allowing p-GaN to grow upwards from the first opening and cross the edge of the first opening, laterally migrating and crystallizing on the surface of the first mask layer. The diameter of the first opening can be approximately 7.0 μm, and the diameter of the formed p-GaN structure can be approximately 12.0 μm, that is, extending radially outwards from the edge of the first opening by approximately 2.5 μm.

[0147] Specifically, see Figure 8 Step S5 may further include the following steps: Step S51: Form the second main body of the second light-emitting unit.

[0148] Specifically, a first tunnel junction is formed in the second opening, and a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer of the second light-emitting unit are sequentially formed on the first tunnel junction, such that the second conductive type semiconductor layer protrudes from the second opening in a direction away from the conductive substrate.

[0149] Step S52: Form the second extension.

[0150] Specifically, the second conductive type semiconductor layer of the second light-emitting unit continues to grow, such that the second conductive type semiconductor layer of the second light-emitting unit grows laterally, and a second extension is formed on the surface of the second mask layer away from the conductive substrate.

[0151] In one specific embodiment, the p-GaN layer of the second light-emitting unit can also be laterally overgrown at approximately 920°C, approximately 50 mbar, and a V / III ratio of approximately 2000. The diameter of the second opening can be approximately 5.0 μm, and the diameter of the formed p-GaN structure can be approximately 8.0 μm, that is, extending radially outward from the edge of the second opening by approximately 1.5 μm.

[0152] Through the above-described lateral overgrowth method, the first extension and the second extension can be formed on the periphery of the corresponding active layer and can serve as the anode connection area of ​​the first light-emitting unit and the second light-emitting unit. This spatially separates the anode connection area from the main light-emitting area, reducing the need for deep etching of the active area to form the anode connection structure, thereby reducing the possibility of damage to the active layer during the processing.

[0153] See Figure 14 , Figure 14 The present application provides a schematic diagram of the structure of the display device provided in this application. The present application also provides a display device 20, which can be applied to mobile phones, tablet computers, televisions, monitors, wearable devices, vehicle terminals and other electronic display products, and is not limited thereto.

[0154] The display device 20 includes a display panel 10, which is a light-emitting diode chip 30 provided in any of the above embodiments.

[0155] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A light-emitting diode chip, characterized in that, include: Conductive substrate; A first conductivity type common layer is disposed on one side of the conductive substrate; Multiple light-emitting unit groups are disposed on the side of the first conductivity type common layer away from the conductive substrate; each light-emitting unit group includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit stacked sequentially along a direction away from the conductive substrate; each of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; the first conductivity type common layer is in contact with the first conductivity type semiconductor layer of the first light-emitting unit; A first tunnel junction is disposed between the first light-emitting unit and the second light-emitting unit; The second tunnel junction is disposed between the second light-emitting unit and the third light-emitting unit; A mask layer covers the sides of the light-emitting unit group and the surface of the light-emitting unit group away from the conductive substrate; A first anode trace, a second anode trace, and a third anode trace are disposed on the surface of the mask layer away from the conductive substrate; the first anode trace is electrically connected to the second conductivity type semiconductor layer of the first light-emitting unit, the second anode trace is electrically connected to the second conductivity type semiconductor layer of the second light-emitting unit, and the third anode trace is electrically connected to the second conductivity type semiconductor layer of the third light-emitting unit. as well as A common cathode, which is electrically connected to a common layer of the first conductivity type.

2. The light-emitting diode chip according to claim 1, characterized in that, Along a direction parallel to the conductive substrate, at least a portion of the edge of the first light-emitting unit protrudes from the side of the second light-emitting unit, such that a portion of the second conductivity type semiconductor layer of the first light-emitting unit is exposed to form a first exposure area; Along a direction parallel to the conductive substrate, at least a portion of the edge of the second light-emitting unit protrudes from the side of the third light-emitting unit, such that a portion of the second conductivity type semiconductor layer of the second light-emitting unit is exposed to form a second exposure area; The mask layer has a first conductive via, a second conductive via, and a third conductive via; the first anode trace is electrically connected to the first exposed area through the first conductive via, the second anode trace is electrically connected to the second exposed area through the second conductive via, and the third anode trace is electrically connected to the second conductive semiconductor layer of the third light-emitting unit through the third conductive via.

3. The light-emitting diode chip according to claim 2, characterized in that, The first light-emitting unit, the second light-emitting unit, and the third light-emitting unit have the same shape and coincide in center when projected onto the conductive substrate; Both the first and second exposure areas are annular.

4. The light-emitting diode chip according to claim 2, characterized in that, The second light-emitting unit has the same shape as the orthographic projection of the first light-emitting unit onto the conductive substrate, but their centers are offset. The third light-emitting unit has the same shape as the orthographic projection of the second light-emitting unit onto the conductive substrate, but their centers are offset.

5. The light-emitting diode chip according to claim 2, characterized in that, Along a direction parallel to the conductive substrate, the edge of the second conductivity type semiconductor layer of the first light-emitting unit protrudes from the side of the active layer of the first light-emitting unit, thereby forming a first extension. Along a direction parallel to the conductive substrate, the edge of the second conductivity type semiconductor layer of the second light-emitting unit protrudes from the side of the active layer of the second light-emitting unit, thereby forming a second extension. The first anode trace is electrically connected to the first extension through the first conductive via, and the second anode trace is electrically connected to the second extension through the second conductive via.

6. The light-emitting diode chip according to claim 5, characterized in that, The mask layer includes: A first mask layer covers the first conductivity type common layer; the first mask layer has a first opening, the first light-emitting unit is disposed in the first opening and protrudes from the first opening; the first extension is disposed on the surface of the first mask layer away from the conductive substrate; A second mask layer covers the first mask layer and the first light-emitting unit; the second mask layer has a second opening, the second light-emitting unit is disposed within the second opening and protrudes from the second opening; a second extension is disposed on the surface of the second mask layer away from the conductive substrate; and A third mask layer covers the second mask layer and the second light-emitting unit; the third mask layer has a third opening, and the third light-emitting unit is disposed within the third opening; A fourth mask layer covers the third mask layer and the third light-emitting unit.

7. The light-emitting diode chip according to any one of claims 1-6, characterized in that, The first conductivity type common layer extends to the edge of the conductive substrate and is spaced from the edge of the conductive substrate; the edge of the mask layer is spaced from the edge of the conductive substrate, such that the side surface of the first conductivity type common layer is exposed; The common cathode is disposed at the edge of the conductive substrate and is electrically connected to at least the side of the first conductivity type common layer.

8. A method for fabricating a light-emitting diode chip, characterized in that, include: Provide a conductive substrate; A first conductivity type common layer is formed on one side of the conductive substrate; A first mask layer is formed on the side of the first conductivity type common layer away from the conductive substrate, and a first opening is made in the first mask layer to expose part of the first conductivity type common layer. A first light-emitting unit is formed within the first opening; The first light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; A second mask layer is formed on the side of the first mask layer away from the conductive substrate, and a second opening is formed on the second mask layer to expose the first light-emitting unit. A first tunnel junction and a second light-emitting unit are formed sequentially within the second opening; The second light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; A third mask layer is formed on the side of the second mask layer away from the conductive substrate, and a third opening is formed on the third mask layer to expose the second light-emitting unit. A second tunnel junction and a third light-emitting unit are sequentially formed within the third opening; the third light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. A fourth mask layer is formed on the side of the third mask layer away from the conductive substrate; The fourth mask layer covers the third mask layer and the third light-emitting unit; A first anode trace, a second anode trace, and a third anode trace are formed on the side of the fourth mask layer away from the conductive substrate; wherein, the first anode trace is electrically connected to the second conductivity type semiconductor layer of the first light-emitting unit, the second anode trace is electrically connected to the second conductivity type semiconductor layer of the second light-emitting unit, and the third anode trace is electrically connected to the second conductivity type semiconductor layer of the third light-emitting unit; and A common cathode is formed that is electrically connected to the common layer of the first conductivity type.

9. The preparation method according to claim 8, characterized in that, The step of forming the first light-emitting unit within the first opening includes: This causes the second conductivity type semiconductor layer of the first light-emitting unit to protrude from the first opening; and The second conductivity type semiconductor layer of the first light-emitting unit is grown laterally, and a first extension is formed on the surface of the first mask layer away from the conductive substrate; The step of forming the second light-emitting unit within the second opening includes: This causes the second conductivity type semiconductor layer of the second light-emitting unit to protrude from the second opening; and This causes the second conductive type semiconductor layer of the second light-emitting unit to grow laterally, forming a second extension on the surface of the second mask layer away from the conductive substrate.

10. A display device, characterized in that, Includes the light-emitting diode chip according to any one of claims 1-7.

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