A display circuit board and display panel

Abstract

The application discloses a display circuit board and a display panel, the display circuit board comprising a substrate, a first column of MIP chip mounting positions and a second column of MIP chip mounting positions; a group of electrode lines connecting the electrodes of a row of MIP chip mounting positions; a group of common electrode lines, comprising a first common electrode line and a second common electrode line, both of which are located between the first column of MIP chip mounting positions and the second column of MIP chip mounting positions; the first common electrode line connects the common electrodes of the first column of MIP chip mounting positions; and the second common electrode line connects the common electrodes of the second column of MIP chip mounting positions. Due to the transverse extension arrangement of the group of electrode lines, the longitudinal extension arrangement of the group of common electrode lines, and the fact that the first common electrode line and the second common electrode line are both located between the first column of MIP chip mounting positions and the second column of MIP chip mounting positions, a relatively large space is left between the two adjacent groups of common electrode lines and between the two adjacent groups of electrode lines, which is used for arranging other lines, thereby simplifying the wiring and improving the yield.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display circuit board and a display panel. Background Technology

[0002] MIP (Mini / Micro LED In Package) is a packaging technology that combines an integrated circuit chip with a packaging substrate. The principle involves manufacturing LED chips of different colors and a substrate separately, then embedding the chips into the substrate. The LED chips and substrate are then connected together using processes such as thermoforming to form a MIP chip. Finally, SMT (Surface Mount Technology) is used to solder and package the MIP chip to a PCB (Printed Circuit Board) substrate, ultimately forming a new type of display product.

[0003] Due to limitations in the distribution and specifications of MIP chip pads, PCB substrates have complex traces, resulting in a low yield rate. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display circuit board and a display panel, which aims to solve the problem of low yield caused by the complex PCB substrate wiring of MIP chips.

[0005] The technical solution adopted by this invention to solve the technical problem is as follows: A display circuit board, comprising: A substrate is formed to create at least one mounting group; the mounting group includes a first column of MIP chip mounting positions and a second column of MIP chip mounting positions. At least one electrode line group is disposed on the substrate and connected to a row of electrodes of the MIP chip mounting position; At least one common-pole circuit group is disposed on the substrate; the common-pole circuit group includes a first common-pole circuit and a second common-pole circuit. The first common-pole line and the second common-pole line are both located between the first column of MIP chip mounting positions and the second column of MIP chip mounting positions. The first common-pole line is connected to the common-pole of the first column of MIP chip mounting positions; The second common-pole line is connected to the common-pole of the second column of MIP chip mounting positions.

[0006] Optionally, the mounting group further includes a third column of MIP chip mounting bits and / or a fourth column of MIP chip mounting bits; The first column of MIP chip mounting positions is located between the second column of MIP chip mounting positions and the third column of MIP chip mounting positions; The second column of MIP chip mounting positions is located between the first column of MIP chip mounting positions and the fourth column of MIP chip mounting positions; The common pole line group further includes a third common pole line and / or a fourth common pole line; The third common-pole line is located between the first column of MIP chip mounting positions and the third column of MIP chip mounting positions, and is connected to the common pole of the third column of MIP chip mounting positions; The fourth common-pole line is located between the second column of MIP chip mounting positions and the fourth column of MIP chip mounting positions, and is connected to the common pole of the fourth column of MIP chip mounting positions.

[0007] Optionally, a through hole is formed on the substrate, and a conductive element is disposed in the through hole.

[0008] Optionally, the through hole includes a first through hole, a second through hole, a third through hole, and a fourth through hole; the conductive element includes a first conductive element, a second conductive element, a third conductive element, and a fourth conductive element; The first conductive element is located in the first through hole, the second conductive element is located in the second through hole, the third conductive element is located in the third through hole, and the fourth conductive element is located in the fourth through hole; Both the electrode circuit group and the mounting group are disposed on the first side of the substrate; The common electrode circuit group is disposed on the second side of the substrate; The first common-pole line is connected to the common-pole of the first column of MIP chip mounting positions through the first conductive element; The second common-pole line is connected to the common-pole of the second column of MIP chip mounting positions through the second conductive element; The third common-pole line is connected to the common-pole of the third column of MIP chip mounting positions through the third conductive element; The fourth common-pole line is connected to the common-pole of the fourth column of MIP chip mounting positions through the fourth conductive element.

[0009] Optionally, the electrode includes: a first electrode, a second electrode, and a third electrode; Wherein, the first electrode and the common electrode are located in the same row, and the common electrode is located between the through holes corresponding to the first electrode and the common electrode; The second electrode and the third electrode are located in adjacent rows of the common electrode.

[0010] Optionally, the electrode circuit group includes: The first electrode circuit is connected to a row of first electrodes respectively; The second electrode circuit is connected to a row of second electrodes respectively; The third electrode circuit connects to a row of third electrodes.

[0011] Optionally, the through hole includes a fifth through hole and a sixth through hole; the conductive element includes a fifth conductive element and a sixth conductive element; the fifth conductive element is located in the fifth through hole, and the sixth conductive element is located in the sixth through hole; The display circuit board also includes: Electrode connection lines are disposed on the second side of the substrate; A common-pole connection line is disposed on the first side of the substrate; The electrode connection line is connected to the electrode line group through the fifth conductive element; The common-pole connection line is connected to the common-pole line group through the sixth conductive element.

[0012] Optionally, the substrate further includes: First solder resist layer and second solder resist layer; The first solder mask layer is located on the side of the electrode circuit group that is away from the substrate. The second solder mask layer is located on the side of the common electrode circuit that is away from the substrate.

[0013] Optionally, the display circuit board further includes: The power supply line and the first signal line are both disposed on the first side of the substrate; A second signal line is disposed on the second side of the substrate; The power supply line is located between two adjacent electrode line groups; The first signal line is located between two adjacent electrode line groups; The second signal line is located between two adjacent common pole line groups.

[0014] A display panel, comprising: Multiple MIP chips; Display circuit board as described in any of the above; The MIP chip is mounted on the MIP chip mounting position of the display circuit board.

[0015] In this invention, since the electrode line group extends laterally (i.e., along the row direction of the MIP chip mounting position array) and the common line group extends longitudinally (i.e., along the column direction of the MIP chip mounting position array), and both the first common line and the second common line are located between the first column of MIP chip mounting positions and the second column of MIP chip mounting positions, there is a large amount of space between adjacent common line groups and between adjacent electrode line groups, which can be used to arrange other lines, simplifying the wiring and improving the yield. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit principle of the display circuit board in this invention; Figure 2 This is a schematic diagram of the circuit principle of another display circuit board in this invention; Figure 3 This is a first cross-sectional view of the display circuit board in this invention; Figure 4 This is a schematic diagram of the first structure of the MIP chip in this invention; Figure 5 This is a schematic diagram of the second structure of the MIP chip in this invention; Figure 6 This is a top view of the display circuit board in this invention; Figure 7 This is a schematic diagram of the electrode circuit group and the common electrode circuit group in this invention; Figure 8 This is a second cross-sectional view of the display circuit board in this invention; Figure 9 This is a first structural schematic diagram of the display circuit board of the present invention; Figure 10 This is a schematic diagram of the second structure of the display circuit board of the present invention.

[0017] Explanation of reference numerals in the attached figures: 10-Substrate; 11-First column MIP chip mounting position; 12-Second column MIP chip mounting position; 13-Third column MIP chip mounting position; 14-Fourth column MIP chip mounting position; 101-First electrode; 102-Second electrode; 103-Third electrode; 104-Common electrode; 20 - Electrode circuit group; 21 - First electrode circuit; 22 - Second electrode circuit; 23 - Third electrode circuit; 30 - Common pole line group; 31 - First common pole line; 32 - Second common pole line; 33 - Third common pole line; 34 - Fourth common pole line; 41-First conductive element; 42-Second conductive element; 43-Third conductive element; 44-Fourth conductive element; 51 - First solder mask layer; 52 - Second solder mask layer; 60-MIP chip. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] Please also refer to Figures 1-10 The present invention provides some preferred embodiments of a display circuit board.

[0020] like Figures 1-3 As shown, the display circuit board includes: The substrate 10 forms at least one mounting group; the mounting group includes a first column of MIP chip mounting positions 11 and a second column of MIP chip mounting positions 12. At least one electrode line group 20 is disposed on the substrate 10 and connected to a row of electrodes of the MIP chip mounting position; At least one common line group 30 is disposed on the substrate 10; the common line group 30 includes a first common line 31 and a second common line 32. The first common-pole line 31 and the second common-pole line 32 are both located between the first column MIP chip mounting position 11 and the second column MIP chip mounting position 12; the first common-pole line 31 is connected to the common pole 104 of the first column MIP chip mounting position 11; and the second common-pole line 32 is connected to the common pole 104 of the second column MIP chip mounting position 12.

[0021] Specifically, a display circuit board is a circuit board used in display devices. The display device can be a display panel, which can be used for displays, monitors, etc. MIP (Mini / Micro LED In Package) chips can be mounted on the display circuit board, utilizing the light emission of the MIP chips 60 to achieve the display. The MIP chip 60 is created by first flip-chipping Mini / Micro LED chips into a package to form independent, stable light-emitting units, and then performing module-level integration or mounting. For example... Figures 4-6As shown, MIP chip mounting positions are formed on the substrate 10 to mount MIP chips 60. The MIP chip mounting positions are typically arranged in an array, forming multiple columns and rows. Within the same column, the spacing between adjacent MIP chip mounting positions can be the same; similarly, within the same row, the spacing between adjacent MIP chip mounting positions can also be the same. A single MIP chip 60 can package different LED chips together. For example, a single MIP chip 60 can serve as a pixel unit, packaging red, blue, and green LED chips together. Each LED chip has a positive and a negative electrode. The three types of LED chips can share a single positive or negative electrode, forming three electrodes and a common electrode, enabling individual control of the three types of LED chips. Correspondingly, the MIP chip mounting positions also have electrodes and a common electrode 104. The common electrode 104 of the MIP chip mounting position is located close to the common electrode line of the corresponding common electrode line group 30. The common electrode 104 of the first column of MIP chip mounting positions 11 is close to the first common electrode line 31, and the common electrode 104 of the second column of MIP chip mounting positions 12 is close to the second common electrode line 32.

[0022] Electrode line groups 20 are configured on substrate 10 to connect electrodes at different MIP chip mounting positions. Common electrode line groups 30 are configured on substrate 10 to connect common electrodes 104 at different MIP chip mounting positions. Electrode line groups 20 connect electrodes at the same row of MIP chip mounting positions. MIP chip mounting positions are grouped to form mounting groups, which may include two columns of MIP chip mounting positions, specifically a first column of MIP chip mounting positions 11 and a second column of MIP chip mounting positions 12. Common electrode line groups are grouped to form common electrode line groups 30, which may include two common electrode lines, specifically a first common electrode line 31 and a second common electrode line 32. The first common electrode line 31 connects the common electrodes 104 at the same column of MIP chip mounting positions, and the second common electrode line 32 connects the common electrodes 104 at the same column of MIP chip mounting positions.

[0023] Since the electrode line group 20 extends laterally (i.e., along the row direction of the MIP chip mounting position array) and the common line group 30 extends longitudinally (i.e., along the column direction of the MIP chip mounting position array), and the first common line 31 and the second common line 32 are both located between the first column of MIP chip mounting positions 11 and the second column of MIP chip mounting positions 12, there is a large amount of space between two adjacent common line groups 30 and between two adjacent electrode line groups 20, which can be used to arrange other lines, simplifying the wiring and improving the yield.

[0024] In a preferred embodiment of the present invention, please also refer to Figures 1-2The mounting group further includes a third column of MIP chip mounting positions 13; the first column of MIP chip mounting positions 11 is located between the second column of MIP chip mounting positions 12 and the third column of MIP chip mounting positions 13.

[0025] Specifically, the mounting group may also include a third column of MIP chip mounting positions 13, which are located on the side of the first column of MIP chip mounting positions 11 away from the second column of MIP chip mounting positions 12, and the three columns of MIP chip mounting positions form a mounting group.

[0026] In a preferred embodiment of the present invention, please also refer to Figures 1-2 The mounting group further includes a fourth column of MIP chip mounting positions 14; the second column of MIP chip mounting positions 12 is located between the first column of MIP chip mounting positions 11 and the fourth column of MIP chip mounting positions 14.

[0027] Specifically, the mounting group also includes a fourth column of MIP chip mounting positions 14, which is located on the side of the second column of MIP chip mounting positions 12 away from the first column of MIP chip mounting positions 11. The three columns of MIP chip mounting positions form the mounting group.

[0028] The mounting group may include a third column of MIP chip mounting positions 13 and a fourth column of MIP chip mounting positions 14. The third column of MIP chip mounting positions 13, the first column of MIP chip mounting positions 11, the second column of MIP chip mounting positions 12 and the fourth column of MIP chip mounting positions 14 are arranged in sequence, and the four columns of MIP chip mounting positions form a mounting group.

[0029] In a preferred embodiment of the present invention, please also refer to Figures 1-2 The common electrode line group 30 further includes a third common electrode line 33; the third common electrode line 33 is located between the first column of MIP chip mounting positions 11 and the third column of MIP chip mounting positions 13, and is connected to the common electrode 104 of the third column of MIP chip mounting positions 13.

[0030] Specifically, a third common-pole line 33 is configured for the third column of MIP chip mounting positions 13, and the third common-pole line 33 is connected to the common pole 104 of the third column of MIP chip mounting positions 13. The third common-pole line 33 is located between the first column of MIP chip mounting positions 11 and the third column of MIP chip mounting positions 13, and is closer to the first column of MIP chip mounting positions 11, so that there is more free space between adjacent common-pole line groups 30. The common pole 104 of the third column of MIP chip mounting positions 13 is close to the third common-pole line 33. The electrodes of the third column of MIP chip mounting positions 13 are connected to the corresponding electrode line groups 20.

[0031] In a preferred embodiment of the present invention, please also refer to Figures 1-2 The common-pole circuit group 30 further includes a fourth common-pole circuit 34; the fourth common-pole circuit 34 is located between the second column MIP chip mounting position 12 and the fourth column MIP chip mounting position 14, and is connected to the common pole 104 of the fourth column MIP chip mounting position 14.

[0032] Specifically, a fourth common-pole line 34 is configured for the fourth column MIP chip mounting position 14, and the fourth common-pole line 34 is connected to the common pole 104 of the fourth column MIP chip mounting position 14. The fourth common-pole line 34 is located between the second column MIP chip mounting position 12 and the fourth column MIP chip mounting position 14, and is closer to the second column MIP chip mounting position 12, thus allowing for more free space between adjacent common-pole line groups 30. The common pole 104 of the fourth column MIP chip mounting position 14 is close to the fourth common-pole line 34. The electrodes of the fourth column MIP chip mounting position 14 are connected to the corresponding electrode line groups 20.

[0033] In a preferred embodiment of the present invention, a through hole is formed on the substrate 10, and a conductive element is disposed in the through hole.

[0034] Specifically, through holes are formed on the substrate 10, and conductive elements are disposed within the through holes. The conductive elements are configured to connect various lines. For example, the conductive elements are used to connect the electrode lines of the electrode line group 20 or the common line of the common line group 30. The conductive elements can also connect the common electrode 104, connecting lines (including common connecting lines or electrode connecting lines), etc.

[0035] In a preferred embodiment of the present invention, please also refer to Figure 3 , Figure 6 and Figure 8 The electrode circuit group 20 and the mounting group are both disposed on the first side of the substrate 10; the common electrode circuit group 30 is disposed on the second side of the substrate 10.

[0036] Specifically, the electrode line group 20 and the MIP chip mounting position are disposed on the first side of the substrate 10, and the common electrode line group 30 is disposed on the second side of the substrate 10. Since the common electrode 104 of the MIP chip mounting position and the common electrode line group 30 are located on different sides of the substrate 10, the connection between the common electrode 104 and the common electrode line group 30 can be achieved through the conductive elements in the through holes.

[0037] In a preferred embodiment of the present invention, please also refer to Figure 1 , Figures 6-7The through-hole includes a first through-hole and a second through-hole; the conductive element includes a first conductive element 41 and a second conductive element 42; the first conductive element 41 is located in the first through-hole, and the second conductive element 42 is located in the second through-hole; the first common electrode line 31 is connected to the common electrode 104 of the first column MIP chip mounting position 11 through the first conductive element 41; the second common electrode line 32 is connected to the common electrode 104 of the second column MIP chip mounting position 12 through the second conductive element 42.

[0038] Specifically, a first through-hole is formed on the substrate 10 to accommodate a first conductive element 41, and the first conductive element 41 connects the common electrode 104 of the first row of MIP chip mounting positions 11 and the first common electrode line 31. The first through-hole is located at the corresponding position of the first common electrode line 31, and there is a gap between the first through-hole and the common electrode 104. Specifically, the connection between the first conductive element 41 and the corresponding common electrode 104 can be achieved through auxiliary lines. A second through-hole is formed on the substrate 10 to accommodate a second conductive element 42, and the second conductive element 42 connects the common electrode 104 of the second row of MIP chip mounting positions 12 and the second common electrode line 32. The second through-hole is located at the corresponding position of the second common electrode line 32, and there is a gap between the second through-hole and the common electrode 104. Specifically, the connection between the second conductive element 42 and the corresponding common electrode 104 can be achieved through auxiliary lines. Both the first and second through-holes correspond to the positions of the common electrode lines. The common electrode lines are relatively wide, and the diameters of the first and second through-holes are relatively large, reducing the manufacturing cost of the substrate with through-holes.

[0039] In a preferred embodiment of the present invention, please also refer to Figure 1 , Figures 6-7 The through hole includes a third through hole; the conductive element includes a third conductive element 43; the third common line 33 is connected to the common 104 of the third column MIP chip mounting position 13 through the third conductive element 43.

[0040] Specifically, a third through-hole is formed on the substrate 10 to accommodate the third conductive element 43, and the common electrode 104 of the third column of MIP chip mounting positions 13 and the third common electrode line 33 are connected through the third conductive element 43. The third through-hole is located at the corresponding position of the third common electrode line 33, and there is a gap between the third through-hole and the common electrode 104. Specifically, the connection between the third conductive element 43 and the corresponding common electrode 104 can be achieved through auxiliary lines.

[0041] In a preferred embodiment of the present invention, please also refer to Figure 1 , Figures 6-7 The through hole includes a fourth through hole; the conductive element includes a fourth conductive element 44; the fourth common line 34 is connected to the common 104 of the fourth column MIP chip mounting position 14 through the fourth conductive element 44.

[0042] Specifically, a fourth through-hole is formed on the substrate 10 to accommodate the fourth conductive element 44, and the fourth conductive element 44 connects the common electrode 104 of the fourth column of MIP chip mounting positions 14 and the fourth common electrode line 34. The fourth through-hole is located at the corresponding position of the fourth common electrode line 34, and there is a gap between the fourth through-hole and the common electrode 104. Specifically, the connection between the fourth conductive element 44 and the corresponding common electrode 104 can be achieved through auxiliary lines.

[0043] In a preferred embodiment of the present invention, please also refer to Figures 1-2 The electrodes include: a first electrode 101, a second electrode 102, and a third electrode 103; The first electrode 101 and the common electrode 104 are located in the same row, and the common electrode 104 is located between the through holes corresponding to the first electrode 101 and the common electrode 104; the second electrode 102 and the third electrode 103 are located in adjacent rows of the common electrode 104.

[0044] Specifically, the electrode located in the same row as the common electrode 104 is the first electrode 101. The first electrode 101 can be an electrode connecting to one of the following LED chips: a red LED chip, a blue LED chip, and a green LED chip. The second electrode 102 and the third electrode 103 are located in an adjacent row to the common electrode 104. The second electrode 102 can be located in the same column as the first electrode 101, or it can be located in the same column as the common electrode 104. The third electrode 103 can be located in the same column as the first electrode 101, or it can be located in the same column as the common electrode 104. The second electrode 102 can be an electrode connecting to one of the following LED chips: a red LED chip, a blue LED chip, and a green LED chip. The third electrode 103 can be an electrode connecting to one of the following LED chips: a red LED chip, a blue LED chip, and a green LED chip. Typically, the first electrode 101, the second electrode 102, and the third electrode 103 are connected to the three different types of LED chips: red LED chips, blue LED chips, and green LED chips, respectively.

[0045] In the same mounting group, the first column of MIP chip mounting bits 11 and the second column of MIP chip mounting bits 12 appear in pairs. For example... Figure 1As shown, the third column of MIP chip mounting positions 13 in the same mounting group can be the same as the first column of MIP chip mounting positions 11; the fourth column of MIP chip mounting positions 14 in the same mounting group can be the same as the second column of MIP chip mounting positions 12. When only considering the arrangement of the first electrode 101 and the common electrode 104 in the MIP chip mounting positions, the positions of the first electrode 101 and the common electrode 104 of the first column of MIP chip mounting positions 11 are mirror-symmetrical with the positions of the first electrode 101 and the common electrode 104 of the second column of MIP chip mounting positions 12 (specifically, the mirror symmetry of the longitudinally arranged mirror surfaces). Depending on the chip corresponding to the first electrode 101, there can be 3 pairs of MIP chip mounting positions. In each pair of MIP chip mounting positions, the second electrode 102 and the third electrode 103 can be mirror-symmetrically distributed or not. Several pairs of MIP chip mounting positions are illustrated below, with different colors representing the electrodes corresponding to the LED chips of the corresponding colors.

[0046] and ; and ; and ; and .

[0047] Adjacent rows of MIP chip mounting positions can also be mirror-symmetrically distributed (specifically, horizontally arranged mirror-symmetrically distributed, such as...). Figure 2 As shown), it can also be non-mirror symmetrically distributed (e.g. Figure 1 (As shown). The following example illustrates a mirror-symmetric arrangement of two rows of MIP chip mounting positions (specifically, a mirror-symmetric arrangement of horizontally placed mirror surfaces). Only two types of MIP chips are used here. The two MIP chips at the diagonal positions use the same type of MIP chip 60. Different placement angles result in different arrangement patterns.

[0048] .

[0049] In a preferred embodiment of the present invention, such as Figures 1-2 As shown, the electrode circuit group 20 includes: The first electrode line 21 is connected to a row of first electrodes 101 respectively; The second electrode line 22 is connected to a row of second electrodes 102 respectively; The third electrode line 23 is connected to a row of third electrodes 103.

[0050] Specifically, the first electrode line 21 connects the first electrodes 101 of a row of MIP chip mounting positions. The second electrode line 22 connects the second electrodes 102 of a row of MIP chip mounting positions. The third electrode line 23 connects the third electrodes 103 of a row of MIP chip mounting positions. The first electrode line 21 can be a straight line and multiple branch lines, with the branch lines connecting the first electrodes 101 to the straight lines. The second electrode line 22 can be multiple segments, with each segment connecting the second electrodes 102 of two adjacent MIP chip mounting positions. The third electrode line 23 can be a straight line and multiple branch lines, with the branch lines connecting the third electrodes 103 to the straight lines.

[0051] In a preferred embodiment of the present invention, such as Figure 10 As shown, the through hole includes a fifth through hole; the conductive element includes a fifth conductive element; the fifth conductive element is located within the fifth through hole; the display circuit board further includes: Electrode connection lines are disposed on the second side of the substrate 10; The electrode connection line is connected to the electrode line group 20 through the fifth conductive element.

[0052] Specifically, in order to avoid other structures (such as connectors), electrode connection lines are arranged on the second side of the substrate 10, and the electrode connection lines are connected to the electrode lines of the electrode line group 20 through a fifth conductive element. Figure 10 The thin red line represents the electrode connection line, and the thin green line represents the electrode line of electrode line group 20. The red circle, green circle, and blue circle represent the fifth conductive element.

[0053] In a preferred embodiment of the present invention, such as Figure 10 As shown, the through hole includes a sixth through hole; the conductive element includes a sixth conductive element; the sixth conductive element is located within the sixth through hole; the display circuit board further includes: A common-pole connection line is disposed on the first side of the substrate 10; The common-pole connection line is connected to the common-pole line group 30 through the sixth conductive element.

[0054] Specifically, to avoid obstructing other structures (such as connectors), a common-pole connection line is disposed on the first side of the substrate 10. This common-pole connection line is connected to the common-pole line of the common-pole line group 30 via a sixth conductive element. For example... Figure 10 As shown, the wide green line represents the common-pole connection line, and the wide red line represents the common-pole line of common-pole line group 30. The pink rings at both ends of the wide green line are the sixth conductive element.

[0055] In a preferred embodiment of the present invention, such as Figure 3 As shown, the substrate 10 further includes: First solder resist layer 51; The first solder mask layer 51 is located on the side of the electrode line group 20 away from the substrate 10.

[0056] Specifically, a first solder resist layer 51 is formed on the surface of the display circuit board, and the first solder resist layer 51 covers the first side of the substrate 10, the electrode line group 20, and the common electrode connection line.

[0057] In a preferred embodiment of the present invention, such as Figure 3 As shown, the substrate 10 further includes: Second solder resist layer 52; The second solder mask layer 52 is located on the side of the common electrode line group 30 away from the substrate 10.

[0058] Specifically, a second solder resist layer 52 is formed on the surface of the display circuit board, and the second solder resist layer 52 covers the second side of the substrate 10, the common electrode line group 30, and the electrode connection line.

[0059] In a preferred embodiment of the present invention, such as Figure 9 As shown, the display circuit board further includes: A power supply line is disposed on the first side of the substrate 10; The power supply line is located between two adjacent electrode line groups 20.

[0060] Specifically, power lines can be arranged on the first side of the substrate 10, and power lines can be arranged between two adjacent electrode line groups 20. For example... Figure 9 As shown, the wide yellow lines represent power supply lines.

[0061] In a preferred embodiment of the present invention, such as Figure 9 and Figure 10 As shown, the display circuit board further includes: A first signal line is disposed on a first side of the substrate 10; The first signal line is located between two adjacent electrode line groups 20.

[0062] Specifically, the first signal line can be arranged on the first side of the substrate 10, and the first signal line can be arranged between two adjacent electrode line groups 20. For example... Figure 9 As shown, the thin yellow line represents the first signal line.

[0063] In a preferred embodiment of the present invention, such as Figure 9 and 10 As shown, the display circuit board further includes: The second signal line is disposed on the second side of the substrate 10; The second signal line is located between two adjacent common pole line groups 30.

[0064] Specifically, the second signal line can be arranged on the second side of the substrate 10, and the second signal line can be arranged between two adjacent common-pole line groups 30. For example... Figure 9 As shown, the thin red line represents the second signal line.

[0065] This application uses a two-layer board, distributing the two layers of circuitry on two sides of the substrate 10 respectively, which can reduce costs and make the display circuit board thinner and lighter. The first solder mask layer 51 can also cover the power lines and the first signal lines, and the second solder mask layer 52 can also cover the second signal lines.

[0066] Based on the display circuit board described in any of the above embodiments, the present invention also provides a preferred embodiment of a display panel.

[0067] The display panel of this invention includes: Multiple MIP chips; The display circuit board as described in any of the above embodiments; The MIP chip is mounted on the MIP chip mounting position of the display circuit board.

[0068] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display circuit board, characterized in that, It includes: A substrate is formed to create at least one mounting group; the mounting group includes a first column of MIP chip mounting positions and a second column of MIP chip mounting positions. At least one electrode line group is disposed on the substrate and connected to a row of electrodes of the MIP chip mounting position; At least one common-pole circuit group is disposed on the substrate; The common pole line group includes a first common pole line and a second common pole line; The first common-pole line and the second common-pole line are both located between the first column of MIP chip mounting positions and the second column of MIP chip mounting positions. The first common-pole line is connected to the common-pole of the first column of MIP chip mounting positions; The second common-pole line is connected to the common-pole of the second column of MIP chip mounting positions.

2. The display circuit board according to claim 1, characterized in that, The mounting group also includes a third column of MIP chip mounting positions and / or a fourth column of MIP chip mounting positions; The first column of MIP chip mounting positions is located between the second column of MIP chip mounting positions and the third column of MIP chip mounting positions; The second column of MIP chip mounting positions is located between the first column of MIP chip mounting positions and the fourth column of MIP chip mounting positions; The common pole line group further includes a third common pole line and / or a fourth common pole line; The third common-pole line is located between the first column of MIP chip mounting positions and the third column of MIP chip mounting positions, and is connected to the common pole of the third column of MIP chip mounting positions; The fourth common-pole line is located between the second column of MIP chip mounting positions and the fourth column of MIP chip mounting positions, and is connected to the common pole of the fourth column of MIP chip mounting positions.

3. The display circuit board according to claim 2, characterized in that, A through hole is formed on the substrate, and a conductive element is disposed in the through hole.

4. The display circuit board according to claim 3, characterized in that, The through hole includes a first through hole, a second through hole, a third through hole, and a fourth through hole; the conductive element includes a first conductive element, a second conductive element, a third conductive element, and a fourth conductive element; The first conductive element is located in the first through hole, the second conductive element is located in the second through hole, the third conductive element is located in the third through hole, and the fourth conductive element is located in the fourth through hole; Both the electrode circuit group and the mounting group are disposed on the first side of the substrate; The common electrode circuit group is disposed on the second side of the substrate; The first common-pole line is connected to the common-pole of the first column of MIP chip mounting positions through the first conductive element; The second common-pole line is connected to the common-pole of the second column of MIP chip mounting positions through the second conductive element; The third common-pole line is connected to the common-pole of the third column of MIP chip mounting positions through the third conductive element; The fourth common-pole line is connected to the common-pole of the fourth column of MIP chip mounting positions through the fourth conductive element.

5. The display circuit board according to claim 3, characterized in that, The electrodes include: a first electrode, a second electrode, and a third electrode; Wherein, the first electrode and the common electrode are located in the same row, and the common electrode is located between the through holes corresponding to the first electrode and the common electrode; The second electrode and the third electrode are located in adjacent rows of the common electrode.

6. The display circuit board according to claim 5, characterized in that, The electrode circuit group includes: The first electrode circuit is connected to a row of first electrodes respectively; The second electrode circuit is connected to a row of second electrodes respectively; The third electrode circuit connects to a row of third electrodes.

7. The display circuit board according to any one of claims 3 to 6, characterized in that, The through hole includes a fifth through hole and a sixth through hole; the conductive element includes a fifth conductive element and a sixth conductive element; the fifth conductive element is located inside the fifth through hole, and the sixth conductive element is located inside the sixth through hole; The display circuit board also includes: Electrode connection lines are disposed on the second side of the substrate; A common-pole connection line is disposed on the first side of the substrate; The electrode connection line is connected to the electrode line group through the fifth conductive element; The common-pole connection line is connected to the common-pole line group through the sixth conductive element.

8. The display circuit board according to any one of claims 1 to 6, characterized in that, The substrate further includes: First solder resist layer and second solder resist layer; The first solder mask layer is located on the side of the electrode circuit group that is away from the substrate. The second solder mask layer is located on the side of the common electrode circuit that is away from the substrate.

9. The display circuit board according to any one of claims 1 to 6, characterized in that, The display circuit board also includes: The power supply line and the first signal line are both disposed on the first side of the substrate; A second signal line is disposed on the second side of the substrate; The power supply line is located between two adjacent electrode line groups; The first signal line is located between two adjacent electrode line groups; The second signal line is located between two adjacent common pole line groups.

10. A display panel, characterized in that, include: Multiple MIP chips; The display circuit board as described in any one of claims 1 to 9; The MIP chip is mounted on the MIP chip mounting position of the display circuit board.

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