A method for manufacturing a 2T1C pixel structure active matrix of a low-voltage organic tunneling transistor
Patent Information
- Application Number
- CN202611049648.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-15
- Publication Date
- 2026-10-27
AI Technical Summary
[0004]本发明的目的在于克服光刻对有机材料的损伤和常规OFET阵列器件密度低、功耗高的难题，提供一种基于C8-BTBT有机半导体的2T1C结构AMOLED显示器件，通过界面能级调控、无损图形化工艺与像素电路协同优化，实现超陡亚阈值摆幅、低压驱动与高分辨率均匀显示
[0011]本发明通过结构设计与工艺创新，实现了有机晶体管在AMOLED驱动中的高性能应用。采用高介电常数的HfO2绝缘层与界面能级调控，使器件具备超陡亚阈值摆幅（＜60 mVdec-1）与高开关比(＞107)，显著降低驱动电压（-3 V可以达到μA量级的电流）与静态功耗。
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Figure CN122995388A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of organic semiconductor display device technology, and in particular to a method for fabricating an active matrix of a 2T1C pixel structure of a low-voltage organic tunneling transistor. Background Technology
[0002] Organic field-effect transistors (OFETs) possess significant application potential in next-generation low-power display drivers due to their advantages such as low-temperature fabrication, solution-processability, and strong structural adaptability. Among them, C8-BTBT, with its high carrier mobility and good environmental stability, has become the preferred organic semiconductor material for driving AMOLED light-emitting units. However, traditional organic semiconductor-driven display devices still face multiple technical bottlenecks in their path to practical application: On the one hand, C8-BTBT materials have limited chemical stability and are quite sensitive to conventional micro-nano processing techniques such as photoresist, developer, and high-temperature curing. Directly using standard photolithography processes can easily cause damage to the material's crystal morphology, increase the number of interface states, and degrade the electrical performance of the device. On the other hand, traditional vapor deposition or all-solution processes struggle to achieve high-precision, high-uniformity patterning at the pixel array scale, resulting in significant differences in driving capabilities between pixels and poor uniformity of the displayed image. Furthermore, conventional organic transistors have large subthreshold swings and high operating voltages, making it difficult to meet the demands of low-power displays. The interconnection of switching and driving transistors, the integration of storage capacitors, and the compatibility issues of multi-layer structure patterning in 2T1C pixel circuits further limit the realization of high-resolution, high-integration AMOLEDs.
[0003] Therefore, developing a 2T1C structure AMOLED device and its fabrication method that can avoid photolithographic damage, achieve high-precision patterning, and be compatible with low-voltage and low-power driving is of great significance for promoting the development of high-performance organic display technology. Summary of the Invention
[0004] The purpose of this invention is to overcome the damage to organic materials caused by photolithography and the problems of low density and high power consumption of conventional OFET array devices, and to provide an AMOLED display device with a 2T1C structure based on C8-BTBT organic semiconductors. Through interface energy level control, non-destructive patterning process and pixel circuit synergistic optimization, it achieves ultra-steep subthreshold swing, low-voltage drive and high-resolution uniform display.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: This invention discloses a method for fabricating a 2T1C pixel structure active matrix of a low-voltage organic tunneling transistor, which combines photolithography with methods for protecting organic monomers to non-destructively fabricate high-density source and drain electrodes on a single crystal, comprising: (1) Patterned gate and Scan line fabrication: After processing the glass substrate surface, photoresist is spin-coated onto the surface, and a predetermined electrode pattern is obtained by ultraviolet light exposure and development with a developer. Ti and Au are deposited by electron beam sputtering, and the photoresist is removed with acetone to prepare the gate and scan line of the Sw-OTFT and the gate of the Dr-OTFT. (2) Patterned HfO2: A hydrophobic isolation layer is spin-coated on the substrate with the prepared gate, and Parylene is deposited and photolithographically etched on it. A photoresist protective layer is formed by photolithography using photoresist. The Parylene area not covered by the photoresist protective layer is subjected to reactive ion etching to clean the area. After etching, HfO2 is deposited on the gate using ALD. After deposition, the substrate is ultrasonically removed to remove the Parylene that was not etched due to photoresist protection and the HfO2 on the Parylene, resulting in patterned HfO2. (3) Data line and V DD preparation: On a substrate with pre-patterned HfO2, lift-off photoresist is spin-coated, and photolithography and development expose the data line and V. DD Lead window; Ti and Au were deposited by electron beam sputtering, and the resist was removed with acetone to prepare the data line and V. DD ; (4) Non-destructive patterning process for fabricating patterned C8-BTBT and source / drain electrodes ( Figure 3 , Figure 4 ): First, we proceed with preparing the data line and V. DD C8-BTBT was coated onto a substrate, and a Cytop protective layer was spin-coated onto the surface of the C8-BTBT single crystal thin film; then, the Cytop protective layer was patterned using ultraviolet lithography. The same steps described above are used to construct source and drain electrode patterns. HAT-CN, MoO3 and Ag electrodes are deposited sequentially. After being soaked and peeled off in a diluent, a non-destructive patterned top electrode is obtained, including the source and drain electrodes of Sw-OFET and the drain electrode of Dr-OTFT. After photolithography alignment as described above, the prepared top electrode is interconnected with the leads below. (5) Evaporation deposition of OLED, encapsulation of display backplane ( Figure 3 Step 5): A cytop protective layer is spin-coated, and the OLED region is obtained by photolithography according to the above method. The OLED light-emitting unit (which is also the source of the Dr-OTFT) is deposited by evaporation and connected to the C8-BTBT below. The mask is replaced, the cath line is prepared, and finally the encapsulation is completed to obtain a high-resolution, low-voltage driven AMOLED display active matrix.
[0006] As a further preferred option, in step (1), the Glass substrate is ultrasonically cleaned in sequence with acetone, ethanol and deionized water, and then subjected to ultraviolet ozone surface activation to improve surface cleanliness and adhesion. The predetermined electrode pattern was obtained by spin-coating a Rol-7133 photoresist onto a substrate, exposing it with 365 nm ultraviolet light for 2 s, and developing it with ZXM-238 developer for 10 s. The gate and scan line of Sw-OTFT and the gate of Dr-OTFT were prepared by electron beam sputtering of 5 nm Ti and 20 nm Au and then removing the resist with acetone.
[0007] As a further preferred embodiment, in step (2), a hydrophobic isolation layer is prepared by spin-coating a cytop solution and diluent in a ratio of 1:10 on the substrate with the prepared gate. The hydrophobic isolation layer is composed of a cytop solution (CTL-809M) and a matching diluent (CT-SOLV180) in a mass ratio of 1:1. 3g of Parylene is then deposited, and photolithography is performed on it. A protective layer is formed using a Roll-7133 photolithography system. The Parylene region that is not covered by the photolithography is subjected to reactive ion etching (RIE) to clean the region.
[0008] As a further preferred option, in step (2), the etching is performed using O plasma with the following process parameters: chamber pressure 100 Pa, oxygen flow rate 50 sccm, radio frequency power 150 W, and etching time 10 min. After etching, HfO2 is deposited using ALD. After deposition, the substrate is ultrasonically removed to remove the remaining Parylene and the HfO2 on it, resulting in patterned HfO2.
[0009] As a further preferred option, in step (3), a lift-off photoresist (Rol-7133) is spin-coated onto the patterned HfO2 substrate, and photolithography is performed to expose the data line and V. DD Lead window; 5 nm Ti and 20 nm Au were deposited by electron beam sputtering, and the resist was removed with acetone to prepare the data line and V. DD In step (5), source and drain electrodes are prepared.
[0010] As a further preferred option, in step (4), positive photoresist AR-P-5350 is spin-coated onto the Cytop at 3000 rpm for 30 s; pre-baking is performed at 100 ℃ for 2 min; exposure is performed with 365 nm ultraviolet light for 2 s, followed by exposure in a developer (AR 300-26: deionized water = 1:5) for 10 s to obtain a preset protected geometry (protecting the Cytop and C8-BTBT below the photoresist), thereby obtaining a predetermined protected pattern; after development, the sample is immersed in CT-SOLV180 solution for 30 s to selectively dissolve the Cytop layer in the unprotected area, thereby exposing the corresponding C8-BTBT single crystal film below; Subsequently, reactive ion etching was used to etch the exposed area to remove the C8-BTBT material and form an organic semiconductor channel with a predetermined pattern. After etching, the area was immersed in CT-SOLV180 solution for 10 minutes to remove the residual Cytop protective layer and photoresist, thus obtaining a complete and undamaged C8-BTBT channel pattern.
[0011] This invention achieves high-performance application of organic transistors in AMOLED driving through structural design and process innovation. By employing a high-dielectric-constant HfO2 insulating layer and interface energy level modulation, the device exhibits an ultra-steep subthreshold swing (<60 mVdec). -1 High on / off ratio (>10) 7 This significantly reduces the drive voltage (-3 V can achieve current in the μA range) and static power consumption.
[0012] The combined process of hydrophilic / hydrophobic confined coating and Cytop protective photolithography fundamentally solves the problems of C8-BTBT's poor photolithography resistance and susceptibility to processing damage, significantly improving device uniformity and yield. The 2T1C pixel architecture, combined with the gate insulating layer via interconnection, achieves stable voltage maintenance and current drive, enabling the display panel to achieve flicker-free and highly uniform light emission even at high resolution. This invention offers strong process compatibility and excellent performance, providing a feasible technical solution for low-power, highly integrated organic AMOLED displays. Attached Figure Description
[0013] Figure 1 The images show an array of organic 2T1C devices (64×64, 95PPI), where a is a diagram of the device array, b is a diagram of the device array connected to the corresponding FPC flexible flat cable, c is a circuit diagram of a single 2T1C device, and d is a diagram of the device array dimensions. Figure 2 Flowchart (top view) for fabrication of 2T1C pixel driving display circuit; Figure 3Flowchart (side view) for fabrication of 2T1C pixel driving display circuit; Figure 4 Flowchart for fabricating patterned C8-BTBT and source / drain electrodes using a non-destructive patterning process; Figure 5 This is a patterned perforation effect diagram of HfO2; Figure 6 The graph shows the transfer characteristics, output characteristics, and subthreshold swing curves of the driving transistor, where a is the device transfer curve, and b is the device subthreshold swing curve. I DS The ratio plot shows that c is an enlarged transfer curve (subthreshold region) and d is the device output curve. Figure 7 The images are optical micrographs of a 64×64 pixel array, where a is the gate and capacitor diagram, b is the patterned HfO2 perforation diagram on the gate, c is the patterned C8-BTBT effect diagram, and d is the 2T1C device array diagram after the source and drain electrodes are deposited. Detailed Implementation
[0014] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0015] Fabrication of active matrix of 2T1C pixel structure for low-voltage organic tunneling transistors (e.g.) Figure 1 , 2 ) (1) Patterned gate and Scan line fabrication The glass substrate was sequentially ultrasonically cleaned with acetone, ethanol, and deionized water, followed by UV ozone surface activation to improve surface cleanliness and adhesion. A lift-off photoresist (Rol-7133) was spin-coated onto the substrate, exposed to 365 nm UV light for 2 seconds, and developed with ZXM-238 developer for 10 seconds to obtain the predetermined electrode pattern. 5 nm Ti and 20 nm Au were deposited by electron beam sputtering, and the photoresist was removed with acetone to fabricate the gate and scan line of the Sw-OTFT, as well as the gate of the Dr-OTFT.
[0016] (2) Patterned HfO2 (e.g.) Figure 4 ) A hydrophobic isolation layer, consisting of a 1:10 mixture of cytoplasm and diluent (CTL-809M by mass ratio), was spin-coated onto the substrate with the prepared gate. This layer was composed of a 1:1 mass ratio of cytoplasm (CTL-809M) and a matching diluent (CT-SOLV180). 3g of parylene was then deposited, followed by photolithography. A protective layer was formed using a Roll-7133 photolithography machine. The parylene regions not covered by the photolithography were then subjected to reactive ion etching (RIE) to completely remove them. Etching was performed using O plasma with the following parameters: chamber pressure 100 Pa, oxygen flow rate 50 sccm, RF power 150 W, and etching time 10 min. After etching, HfO2 was deposited using an ALD (Alternating Discharge Machining) system. Following deposition, the substrate was ultrasonically treated to remove any remaining parylene and HfO2, resulting in patterned HfO2.
[0017] (3) Data line and V DD preparation On a substrate with pre-patterned HfO2, a lift-off photoresist (Rol-7133) is spin-coated, and photolithography and development are performed to expose the data line and V. DD Lead window. 5 nm Ti and 20 nm Au were deposited by electron beam sputtering, followed by acetone removal to prepare the data line and V. DD .
[0018] (4) Non-destructive patterning process for fabricating patterned C8-BTBT and source / drain electrodes (e.g.) Figure 2 , 3 ) Following the previous step of coating C8-BTBT, a protective layer is first spin-coated onto the surface of the C8-BTBT single-crystal thin film. This protective layer is composed of a 1:1 mass ratio of Cytop (CTL-809M) and a matching diluent (CT-SOLV180). After spin-coating at 700 rpm for 20 seconds, the mixture is annealed at 50 °C for 30 minutes to form a Cytop thin film with a thickness of approximately 50 nm.
[0019] Subsequently, the Cytop layer was patterned using photolithography. Specifically, positive photoresist AR-P-5350 was spin-coated onto the Cytop at 3000 rpm for 30 seconds; pre-baking was performed at 100 °C for 2 minutes; exposure to 365 nm UV light was performed for 2 seconds, followed by exposure to a developer (AR 300-26:deionized water = 1:5) for 10 seconds to obtain the predetermined geometry, thus obtaining the predetermined channel pattern. After development, the sample was immersed in CT-SOLV180 solution for 30 seconds to selectively dissolve the Cytop layer in the unprotected areas, thereby exposing the corresponding C8-BTBT single crystal film below. Reactive ion etching (RIE) was then used to etch the exposed areas using O2 as the etching gas, an oxygen flow rate of 50 sccm, an RF power of 100 W, and a chamber pressure of 1 × 10⁻⁶. -5 Torr etching for 15 s was used to remove C8-BTBT material from the exposed areas, forming an organic semiconductor channel with a predetermined pattern. After etching, the sample was immersed in CT-SOLV180 solution at 40 ℃ for 10 min to remove residual Cytop protective layer and photoresist. It was then rinsed with CT-SOLV180 and dried with nitrogen gas to obtain a complete and undamaged C8-BTBT channel pattern.
[0020] C8-BTBT semiconductor layer patterning method: Patterning is achieved by using a hydrophilic and hydrophobic mask combined with a meniscus-induced scraping process, without direct contact with photoresist throughout the process, and without high-temperature curing damage.
[0021] The same steps described above are used to construct source and drain electrode patterns. 0.4 nm HAT-CN, 2 nm MoO3 and 40 nm Ag electrodes are deposited sequentially. After being soaked and peeled off in a diluent, a non-destructive patterned top electrode is obtained, which includes the source and drain electrodes of the Sw-OFET and the drain electrode of the Dr-OTFT. After photolithographic alignment as described above, the prepared top electrode is interconnected with the leads below.
[0022] The top source and drain electrodes are prepared using Cytop as a protective layer for auxiliary photolithography, which physically isolates the organic semiconductor from the photoresist and achieves non-destructive patterning.
[0023] (5) Evaporation of OLED and encapsulation of display backplane Spin-coat the cytop protective layer, perform photolithography as described above to obtain the OLED region, evaporate the OLED light-emitting unit (which is also the source of the Dr-OTFT), and connect it to the C8-BTBT below; replace the mask, prepare the cath line, and finally complete the encapsulation to obtain a high-resolution, low-voltage driven AMOLED display active matrix.
[0024] The fabricated device comprises a rigid substrate, a bottom gate electrode, an HfO2 gate insulating layer, a C8-BTBT organic semiconductor layer, HAT-CN and MoO3 / Ag top source / drain electrodes, a 2T1C pixel driving circuit, and an OLED light-emitting unit. The device achieves electrical interconnection between the switching transistor and the driving transistor through openings in the gate insulating layer. Supported by a rigid glass substrate, the device employs a bottom gate structure and a high-dielectric-constant HfO2 gate insulating layer, with C8-BTBT as the core organic semiconductor channel. Interface energy level modulation and hole injection efficiency optimization are achieved through charge insertion layers HAT-CN and MoO3, constructing an organic tunneling field-effect transistor with a band-to-band tunneling transport mechanism. The pixel driving unit adopts a 2T1C architecture, achieving effective interconnection between the switching transistor and the driving transistor through precise openings in the gate insulating layer. Combined with a storage capacitor, voltage maintenance is achieved within one frame cycle, forming an addressable, low-power, and highly stable active matrix driving circuit.
[0025] Testing showed that the devices fabricated using this method exhibit typical band tunneling transport behavior, possess ultra-steep subthreshold swing and high on / off ratio, achieve stable drive at low voltages, and can be used to fabricate high-density devices (such as...). Figure 5 , 6 The device exhibits good consistency and stability.
[0026] Interface layer control method ( Figure 6 The source / drain electrode structure HAT-CN and MoO3 / Ag enables the device to have a tunneling transport mechanism and an ultra-steep subthreshold swing (subthreshold swing). SS Less than the thermionic emission limit of 60 mV dec -1 ).
[0027] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor, characterized in that, include: (1) Patterned gate and Scan line fabrication: Photoresist is spin-coated onto the glass surface, and a predetermined electrode pattern is obtained through exposure and development. Ti and Au were deposited by electron beam sputtering, and the photoresist was removed with acetone to prepare the gate and scan line of Sw-OTFT and the gate of Dr-OTFT. (2) Patterned HfO2: A hydrophobic isolation layer is spin-coated on the substrate with the prepared gate, and Parylene is deposited and photolithographically etched on it. A photoresist protective layer is formed by photolithography using photoresist. The Parylene area not covered by the photoresist protective layer is subjected to reactive ion etching to clean the area. After etching, HfO2 is deposited on the gate using ALD. After the etching is completed, the Parylene that was not etched due to the protection of the photoresist and the HfO2 on the Parylene are removed to obtain patterned HfO2. (3) Data line and V DD preparation: On a substrate with pre-patterned HfO2, lift-off photoresist is spin-coated, and photolithography and development expose the data line and V. DD Lead window; Ti and Au were deposited by electron beam sputtering, and the resist was removed with acetone to prepare the data line and V. DD ; (4) Non-destructive patterning process for fabricating patterned C8-BTBT and source / drain electrodes: First, we proceed with preparing the data line and V. DD C8-BTBT was coated onto a substrate, and a Cytop protective layer was spin-coated onto the surface of the C8-BTBT single crystal thin film; then, the Cytop protective layer was patterned using photolithography. The same steps described above are used to construct source and drain electrode patterns. HAT-CN, MoO3 and Ag electrodes are deposited sequentially. After being soaked and peeled off in a diluent, a non-destructive patterned top electrode is obtained, including the source and drain electrodes of Sw-OFET and the drain electrode of Dr-OTFT. After photolithography alignment, the fabricated top electrode is interconnected with the leads below. (5) Evaporation deposition of OLED, encapsulation of display backplane: A cytop protective layer is spin-coated, and the OLED region is obtained by photolithography according to the above method. OLED light-emitting units are deposited by evaporation and connected to the C8-BTBT below. The mask is replaced, the cath line is prepared, and finally the encapsulation is completed to obtain the AMOLED display active matrix.
2. The method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor according to claim 1, characterized in that: In step (1), the Glass substrate is ultrasonically cleaned with acetone, ethanol and deionized water in sequence, and then subjected to ultraviolet ozone surface activation to improve surface cleanliness and adhesion. The predetermined electrode pattern was obtained by spin-coating a Rol-7133 photoresist onto a substrate, exposing it with 365 nm ultraviolet light for 2 s, and developing it with ZXM-238 developer for 10 s. The gate and scanline of Sw-OTFT and the gate of Dr-OTFT were prepared by electron beam sputtering of 5 nm Ti and 20 nm Au and then removing the resist with acetone.
3. The method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor according to claim 1, characterized in that: In step (2), a hydrophobic isolation layer is prepared by spin-coating a cytop solution and diluent in a ratio of 1:10 on the substrate with the prepared gate. The hydrophobic isolation layer is made by mixing cytop solution and diluent in a mass ratio of 1:
1. 3g of Parylene is then deposited, and photolithography is performed on it. A protective layer is formed using a Roll-7133 photolithography system. The Parylene area that is not covered by the photolithography is subjected to reactive ion etching to clean the area.
4. The method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor according to claim 1, characterized in that: In step (2), the etching is performed using O plasma, and the process parameters are: chamber pressure 100 Pa, oxygen flow rate 50 sccm, radio frequency power 150 W, and etching time 10 min. After etching, HfO2 was deposited using ALD; After deposition, the substrate is ultrasonicated to remove the remaining Parylene and the HfO2 on it, resulting in patterned HfO2.
5. The method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor according to claim 1, characterized in that: In step (3), on the patterned HfO2 substrate, lift-off photoresist is spin-coated, and photolithography and development are performed to expose the data line and V. DD Lead window; 5 nm Ti and 20 nm Au were deposited by electron beam sputtering, and the resist was removed with acetone to prepare the data line and V. DD In step (5), source and drain electrodes are prepared.
6. The method for fabricating an active matrix of a 2T1C pixel structure for a low-voltage organic tunneling transistor according to claim 1, characterized in that: In step (4), positive photoresist AR-P-5350 is spin-coated on Cytop under spin-coating conditions of 3000 rpm for 30 s; pre-baking is performed at 100 ℃ for 2 min; exposure is performed with 365 nm ultraviolet light for 2 s, and exposure is performed in developer for 10 s to obtain the preset protected geometry, thereby obtaining the predetermined protected pattern. After development, the sample was immersed in CT-SOLV180 solution for 30 seconds to selectively dissolve the Cytop layer in the unprotected area, thereby exposing the C8-BTBT single crystal film in the corresponding area below. Subsequently, reactive ion etching is used to etch the exposed area to remove the C8-BTBT material in the exposed area, forming an organic semiconductor channel with a predetermined pattern. After etching, the sample is immersed in CT-SOLV180 solution for 10 minutes to remove the residual Cytop protective layer and photoresist, thus obtaining a complete and undamaged C8-BTBT channel pattern.