Ga2o3 / idtbt single-gate reconfigurable transistor for multimodal simulation of brain and preparation method and application thereof

Abstract

The application relates to the field of artificial intelligence hardware and brain-like computing chips, and discloses a Ga2O3 / IDTBT single-gate reconfigurable transistor for multi-modal simulation of a brain as well as a preparation method and application thereof. In view of the problems of existing brain-like computing hardware, such as dependence on a complex multi-gate structure and high process cost, the application provides an organic / inorganic single-gate reconfigurable transistor based on gate control, and the device structure comprises a substrate, a dielectric film layer of Ga2O3 and an IDTBT film layer which are sequentially stacked. The application breaks through the limitation of a single function of a traditional transistor, and can realize dynamic reconfiguration of four working modes of a field effect transistor, a rectifier diode, a wideband light detector and an artificial synapse in a single physical space only by regulating an applied bias voltage. In addition, the preparation method of the application prepares the key Ga2O3 dielectric film layer in an aqueous solution and at a low annealing temperature, and has the characteristics of low temperature and environmental protection.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence hardware, neuromorphic computing chips, and optoelectronic devices, specifically to a Ga2O3 / IDTBT single-gate reconfigurable transistor for multimodal brain simulation, its fabrication method, and its application. Background Technology

[0002] In recent years, with the explosive growth of the Internet of Things (IoT), big data, and artificial intelligence (AI), edge computing, as a technology that pushes computing power, storage capacity, and sensing capabilities down to the network edge, has received considerable attention. Traditional edge computing hardware is generally based on the traditional von Neumann architecture. Because the sensing, storage, and computing units are physically separated, significant energy loss and time delays occur when data is frequently transmitted between heterogeneous units, resulting in a severe "von Neumann bottleneck." To overcome this challenge, "sensing-computing integrated" neuromorphic optoelectronic devices, which can integrate sensing, storage, and computing functions simultaneously within a single physical device, have become a research hotspot in both academia and industry.

[0003] Among various neuromorphic devices, reconfigurable transistors (RTTs) are considered the core foundation for building highly compact, low-power, and integrated sensing and computing intelligent hardware systems because they can switch between multiple functional modes within a single physical node through dynamic adjustment of external excitation signals. However, existing reconfigurable transistor technologies still face the following bottlenecks that urgently need to be addressed: First, the device architecture is complex, and the peripheral driving circuitry is redundant. Traditional synaptic transistors or reconfigurable optoelectronic devices typically rely heavily on complex multi-terminal architectures, multi-gate collaborative control structures (such as dual-gate, floating gate, and split gate), or extremely cumbersome heterogeneous interface modification layers. These complex physical structures not only result in a large spatial footprint for individual pixels, greatly limiting the integration of large-scale, high-density arrays, but also pose stringent challenges to the complexity and power consumption of subsequent peripheral driving and control circuits due to their multiple control signals. Second, the fabrication process is costly, making large-area, low-cost manufacturing difficult. Existing inorganic oxide semiconductors (such as Ga2O3 and other high-bandgap semiconductors) are typically fabricated using high-vacuum, high-cost, and complex physical vapor deposition methods (such as pulsed laser deposition, radio frequency magnetron sputtering, and molecular beam epitaxy, MBE). This process route, which relies on large-scale vacuum equipment, not only significantly increases the manufacturing cost of devices but also makes it difficult to achieve large-area, low-cost continuous solution processing on flexible substrates, limiting its practical industrial application in flexible wearable edge smart devices. Furthermore, multimodal reconfiguration capabilities are insufficient. Most existing single-gate transistors, due to their relatively simple channel or charge transport mechanisms, can only perform limited single-dimensional reconfiguration between simple electrical behaviors (such as switching between switching and rectification characteristics) or simple optical behaviors (such as photosensitive detection). It is extremely difficult to simultaneously achieve four or more multimodal reconfiguration behaviors, such as field-effect switching, diode rectification, full-spectrum broadband optical detection, and neuromorphic photosynapses with advanced non-volatile memory functions, under a single gate structure. Finally, there is the ambiguity in the actual hardware definition of traditional patents and technical descriptions. Currently, some existing patents or documents, when describing similar multifunctional hardware, frequently misuse generalized or informal macroscopic academic terms such as "edge intelligent device." This definition not only lacks rigorous support from microscopic physical mechanisms but also fails to accurately define the core inventive point of decoupling and controlling various working modes within the physical space. This easily leads to ambiguities in the analysis of technical principles and potential legal risks of overlapping protection scopes in subsequent patent examinations or actual industrial applications.In view of the technical shortcomings of the existing technologies, such as complex architecture, high process cost, lack of multi-modal reconfiguration capability, and lack of microscopic physical defect control mechanism, there is an urgent need to develop a single-gate multi-modal reconfigurable transistor device with a highly simplified structure, fabricated entirely based on low-cost all-solution processed method, and capable of precise control through fine defect engineering and gate bias. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the present invention aims to provide a Ga2O3 / IDTBT single-gate reconfigurable transistor, its fabrication method, and its applications. The Ga2O3 / IDTBT single-gate reconfigurable transistor of the present invention abandons the complex physical multi-gate structure and external ion doping, cleverly utilizing the intrinsic defects of the material to successfully achieve dynamic switching of four operating modes within a single physical space. This device not only successfully simulates typical synaptic behavior but also achieves high recognition accuracy in the pattern recognition capabilities of artificial neural networks (ANNs), showing great application potential in multimodal neuromorphic optoelectronics and neuromorphic computing.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A first aspect of the present invention provides a Ga2O3 / IDTBT single-gate reconfigurable transistor, comprising:

[0007] A substrate, a Ga2O3 dielectric thin film layer, an IDTBT semiconductor thin film layer are stacked sequentially, and a source electrode and a drain electrode are spaced apart on the side of the IDTBT semiconductor thin film layer away from the Ga2O3 dielectric thin film layer.

[0008] The Ga2O3 dielectric thin film layer retains intrinsic hydroxyl (-OH) defect states inside and on the surface. These hydroxyl defect states serve as deep-level charge trapping centers, modulating the interface barrier and enabling the dynamic trapping and release of photogenerated carriers.

[0009] The thickness of the Ga2O3 dielectric thin film layer is 25~40 nm; the IDTBT semiconductor thin film layer is an organic conjugated polymer layer based on indenedithiophene-co-benzothiadiazole IDTBT.

[0010] The substrate is a heavily doped silicon wafer (p... ++ -Si), wherein the source electrode and drain electrode are gold (Au) electrodes.

[0011] The single-gate reconfigurable transistor can be dynamically switched between field-effect transistor mode, rectifier diode mode, broadband photodetector mode, and artificial synapse mode, entirely based on the bias voltage applied to the gate and drain.

[0012] The semiconductor thin film layer is made of IDTBT (indobisthiophene-co-benzothiadiazole) organic conjugated polymer.

[0013] A second aspect of the present invention provides a method for fabricating the Ga2O3 / IDTBT single-gate reconfigurable transistor as described above, comprising:

[0014] Step S1: Provide gallium salt and IDTBT polymer. Dissolve gallium salt in water to obtain a Ga2O3 precursor solution. Dissolve IDTBT polymer in chloroform to obtain an IDTBT polymer solution.

[0015] Step S2: Provide a heavily doped silicon wafer (p ++ Using Si as a substrate and performing surface hydrophilization treatment, the precursor solution of Ga2O3 is spin-coated onto the substrate and annealed to form a Ga2O3 dielectric thin film layer retaining hydroxyl defect states on the substrate.

[0016] Step S3: Spin-coat the IDTBT semiconductor solution onto the Ga2O3 dielectric thin film layer, and form the IDTBT semiconductor thin film layer after annealing.

[0017] Step S4: Form source and drain electrodes spaced apart on the IDTBT semiconductor thin film layer to obtain the Ga2O3 / IDTBT single-gate reconfigurable transistor.

[0018] Optionally, the gallium salt is gallium nitrate hydrate, the concentration of metal ions in the Ga2O3 precursor solution is 1.5~2.5 M, and the concentration of the IDTBT semiconductor solution is 3~7 mg / mL.

[0019] Optionally, in step S2, the annealing temperature is 280~320℃ and the annealing time is 55~70 min.

[0020] Optionally, step S3 specifically includes:

[0021] An IDT semiconductor thin film precursor solution is provided, and the IDT semiconductor thin film precursor solution is spin-coated onto the Ga2O3 dielectric thin film layer. The solution is then annealed at a temperature of 110~130 °C for 5~15 min to form an IDT semiconductor thin film layer on the Ga2O3 dielectric thin film layer.

[0022] A third aspect of this invention provides an application of the Ga2O3 / IDTBT single-gate reconfigurable transistor described above in multimodal neuromorphic optoelectronics and neuromorphic computing. Beneficial effects: This invention provides a Ga2O3 / IDTBT that effectively solves the dependence of traditional reconfigurable devices on multi-gate or floating-gate structures. By simply adjusting the single-gate bias voltage, it can dynamically switch between four operating modes—field-effect transistor (FET), diode rectifier, artificial synapse, and broadband photodetector—within a single physical space. In neuromorphic computing, the device successfully simulates core synaptic behaviors such as short-term to long-term plasticity (STP-to-LTM), paired impulse facilitation (PPF), and impulse-dependent learning ability (SNDP) through a -OH-mediated interface charge dynamics mechanism. The extracted synaptic weights achieved a recognition accuracy of over 90.8% in MNIST handwriting recognition simulations, demonstrating significant application potential in multimodal sensor-computation integration and edge intelligence. This invention discloses a core architecture based on a low-temperature aqueous solution method, which utilizes the intrinsic hydroxyl (-OH) defects of the dielectric layer to achieve charge trapping. Due to the low overall process thermal budget (maximum 300°C), this scheme provides efficient hardware support for low-cost, flexible substrate compatible, and large-area roll-to-roll fabrication of neuromorphic optoelectronic systems. Attached Figure Description

[0023] Figure 1 The comprehensive morphology and electrical characterization diagram of the device in Embodiment 1 of the present invention (including 3D structure, TEM cross-sectional structure and thickness, AFM surface roughness, XPS full spectrum, and typical characteristic curves in FET and Diode operating modes).

[0024] Figure 2 : Schematic diagram of the asymmetric barrier modulation band and trap-assisted tunneling (TAT) optocoupler mechanism of the device of the present invention under different operating modes.

[0025] Figure 3 The graph shows the evolution of the absorption, transient photocurrent and photoresponsivity of the device in photodetector mode under multi-wavelength (254-635 nm) light.

[0026] Figure 4 : Multi-wavelength behavior diagram of the device of the present invention in artificial synaptic mode (including pulse width dependent EPSC, multi-pulse conductance accumulation STM-LTM conversion, and paired pulse-promoted PPF attenuation fitting curve under multiple wavelengths).

[0027] Figure 5 The integrated graph of the truth response of the artificial neural network (ANN) constructed based on the device of this invention under multiple wavelengths, including LTP / LTD weight update, MNIST handwritten digit recognition rate evolution, and reconfigurable optoelectronic logic gate (AND / OR).

[0028] Figure 6 : Fine characterization curve of X-ray reflectance (XRR) of Ga2O3 dielectric thin film layer in the embodiments of the present invention.

[0029] Figure 7 In this embodiment of the invention, the O 1s XPS spectrogram fitting diagram of the Ga2O3 dielectric layer intentionally retaining the hydroxyl (-OH) defect state under annealing at 300 °C is shown.

[0030] Figure 8 The breakdown field strength and leakage current curves of the Ga2O3 dielectric layer and the frequency characteristics of the embedded CF in the embodiments of the present invention.

[0031] Figure 9 Comparison of the current gain factor as a function of the number of optical pulses in detector mode and synaptic memory mode.

[0032] Figure 10 Comparison of transient optoelectronic memory at multiple wavelengths using devices annealed at 300 ℃, annealed at 500 ℃, and with pure SiO2 as the dielectric layer.

[0033] Figure 11 : Simulation diagram of two-dimensional electrostatic potential and electric field distribution of the device in the vertical and horizontal directions in the field-effect transistor mode.

[0034] Figure 12 Device read bias at different drain terminals (V) DS The peak linear modulation law of EPSC under ( ).

[0035] Figure 13 : Cyclic stability test diagram of dynamic bidirectional adjustment of synaptic weights of the device under 40 consecutive positive / reverse pulse stimulations.

[0036] Figure 14 Threshold voltage drift characteristic of the device transfer characteristic curve under 405 nm light intensity modulation.

[0037] Figure 15 The evolution curves of the photodetector ratio and detectivity of the device under light intensity modulation at 520 nm and 635 nm. Detailed Implementation

[0038] This invention provides a Ga2O3 / IDTBT single-gate reconfigurable transistor, its fabrication method, and its applications. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] This invention provides a Ga2O3 / IDTBT single-gate reconfigurable transistor, characterized in that it comprises: a substrate (p) sequentially stacked... ++ The device consists of a Ga2O3 dielectric thin film layer (Si), an IDTBT semiconductor thin film layer, and source and drain electrodes spaced apart on the surface of the channel layer. This device abandons the complex multi-gate structure and can dynamically switch between four modes—FET, diode, photodetector, and artificial synapse—within a single physical space by adjusting the bias voltage of a single gate and drain. Its core mechanism originates from the intrinsic hydroxyl (-OH) defect states retained in the Ga2O3 dielectric layer using a low-temperature solution method. These defects act as charge trapping centers, modulating interface dynamics and driving multimodal reconstruction and synaptic memory functions. Experiments show that the device achieves 90.8% accuracy in MNIST recognition simulations and successfully executes reconfigurable optical logic operations. Due to its extremely low overall fabrication thermal budget, this approach offers significant advantages such as simple process, low cost, and compatibility with large-area flexible manufacturing.

[0040] The working principle of the Ga2O3 / IDTBT single-gate reconfigurable transistor provided in this invention embodiment is as follows: The core function of the Ga2O3 / IDTBT single-gate reconfigurable transistor relies on the synergy of the voltage applied to the gate and the illumination conditions. It utilizes the intrinsic hydroxyl (-OH) defect states preserved within the Ga2O3 dielectric layer to regulate the carrier dynamics of the IDTBT semiconductor channel layer: When operating as a field-effect transistor or photodetector (with a forward depletion bias applied), a strong vertical electric field drives the rapid extraction of photogenerated carriers, suppressing the trapping process of the Ga2O3 interface charge, resulting in stable switching characteristics and a fast response without continuous photoconductivity; while when operating as a diode (without any applied voltage),... During gate scanning, the -OH defect states at the Ga2O3 dielectric layer interface participate in charge trapping, inducing a non-uniform charge distribution in the channel and changing the local electrostatic potential of the drain, thereby forming an asymmetric Schottky barrier to achieve unidirectional conductivity. In photosynaptic mode, a specific bias voltage provides photogenerated electrons with sufficient energy, allowing them to be permanently trapped by deep-level -OH defects in the Ga2O3 lattice through trap-assisted tunneling (TAT). Due to the high release barrier, these charges continue to produce a persistent grating control effect on the channel after the photostimulation ends, thereby realizing the transformation from short-term plasticity (STP) to long-term plasticity (LTP), perfectly simulating the dynamic learning and memory functions of biological synapses.

[0041] The specific functions of each layer in the Ga2O3 / IDTBT single-gate reconfigurable transistor of this invention are as follows:

[0042] 1. Source and drain: These serve as the input and output terminals of the current, respectively, providing the path for carrier transport in the IDT semiconductor thin film layer (channel layer), ensuring the basic electrical connection of the device, signal transmission, and the formation of the Schottky barrier at the metal-semiconductor interface;

[0043] 2. IDTBT Semiconductor Thin Film Layer (Channel Layer): The semiconductor material is IDTBT (indobisthiophene-co-benzothiadiazole) organic conjugated polymer, which is the main region for carrier transport. It is also the main absorption layer for broadband photons in the visible light band. Its conductivity is directly modulated by the charge trapping effect of the -OH defect state in the dielectric thin film layer, thus determining the output characteristics of the device.

[0044] 3. Ga2O3 dielectric thin film layer (electrolyte layer): As a key gate control dielectric and charge storage layer, it replaces the traditional perfect insulating layer. The interior and surface of this layer are rich in intrinsic hydroxyl groups (-OH) retained by the low-temperature solution method, which can act as deep-level traps. Its characteristic lies in capturing and releasing photogenerated electrons through trap-assisted tunneling (TAT), inducing a persistent photogating effect and non-uniform distribution of local electrostatic potential at low operating voltages. This is the core physical basis for the device to achieve diode rectification characteristics and simulate synaptic time-dependent behavior (memory function).

[0045] 4. Gate (the substrate in this invention also provides the gate electrode): By applying a control voltage, an electrostatic field is generated in the vertical direction, which drives the accumulation or depletion of channel carriers and regulates the extraction and capture rate of photogenerated electrons into the defect state. It is the global control interface for realizing the switching of the device between four modes: field-effect transistor, rectifier, photodetector and synapse.

[0046] In some embodiments, the portion of the semiconductor thin film layer that is not covered by the source electrode and the drain electrode is a channel. The length of the channel is 90~110μm (for example, it can be 90μm, 100μm, or 110μm), and the width is 1450~1550μm (for example, it can be 1450μm, 1500μm, or 1550μm).

[0047] In some implementations, the key process condition determining the concentration of intrinsic hydroxyl (-OH) defect states in the Ga2O3 dielectric thin film is the annealing temperature of the dielectric thin film. The annealing temperature is set to 280°C–320°C. This choice is based on a comprehensive consideration of dielectric insulation properties and multimodal reconstruction capabilities (synaptic plasticity, rectification ratio). Studies have shown that low-temperature annealing at 300°C retains approximately 62% of the -OH composition within the Ga2O3 lattice. Compared to high-temperature annealing at 500°C (where the -OH composition decreases to 52% and synaptic memory and rectification characteristics are completely lost), the 300°C annealing condition achieves the optimal balance: ensuring sufficient breakdown resistance while providing ample deep-level charge trapping centers. Under these optimal conditions, the present invention achieves the following technical effects: First, a large number of -OH defects support the effective capture of photogenerated electrons, accurately simulating the short-term and long-term plasticity of biological synapses; second, it can induce a high diode rectification ratio through local charge distribution; and finally, the extremely low thermal budget significantly reduces manufacturing costs.

[0048] In some embodiments, the thickness of the Ga2O3 dielectric thin film layer is set to 25~40 nm (e.g., 25 nm, 28 nm, 30 nm, 30.6 nm, 32 nm, 35 nm, 38 nm, 40 nm), and the thickness of the IDTBT semiconductor thin film layer is 10~50 nm (e.g., 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm).

[0049] In some embodiments, the thickness of the Ga2O3 dielectric thin film is set to 25–40 nm (30.6 nm, determined by X-ray reflectivity (XRR)). This design is based on a comprehensive consideration of electric field modulation efficiency, low-voltage operation, and defect state charge coupling capability. The 30.6 nm dielectric thin film thickness provides a moderate capacitance density at 1 kHz, ensuring sufficient insulation to block leakage current while allowing the gate electric field to effectively penetrate into the channel at a low voltage (≤3 V). Simultaneously, this ultra-thin design allows the electrostatic field induced by the -OH defect states enriched at the Ga2O3 interface to act maximally on the IDTBT channel layer carriers, thereby achieving highly sensitive synaptic weight modulation under optical signal stimulation. This device combination provides an ideal physical structure for low-power, highly integrated multimodal edge smart hardware.

[0050] In some embodiments, the substrate is a heavily doped silicon wafer (p... ++The substrate is selected from, but is not limited to, p++-Si or ITO transparent conductive glass. In some specific embodiments, the substrate is a heavily doped silicon wafer (p++-Si), which serves as both the substrate and gate electrode of the transistor.

[0051] In some embodiments, the semiconductor thin film layer is made of an organic conjugated polymer based on indendithiophene-co-benzothiadiazole (IDTBT), but is not limited thereto. This material exhibits excellent solution processability and photoelectric response properties.

[0052] In some embodiments, the thickness of the source electrode and the drain electrode is 40~60 nm (e.g., 40 nm, 45 nm, 50 nm, 55 nm, 60 nm), and is 50 nm.

[0053] This invention provides a method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor as described in any of the foregoing embodiments, comprising:

[0054] Step S1: Provide gallium source material and IDTBT polymer. Dissolve gallium source material in solvent to obtain Ga2O3 precursor solution, and dissolve IDTBT polymer in organic solvent to obtain IDTBT semiconductor solution.

[0055] Step S2: Provide a heavily doped silicon wafer (p ++ Using Si as a substrate and performing surface hydrophilization treatment, the precursor solution of Ga2O3 is spin-coated onto the substrate and annealed to form a Ga2O3 dielectric thin film layer that retains the intrinsic hydroxyl (-OH) defect state on the substrate.

[0056] Step S3: Spin-coat the IDTBT semiconductor solution onto the Ga2O3 dielectric thin film layer and perform low-temperature annealing to form the IDTBT semiconductor thin film layer;

[0057] Step S4: Deposit and form spaced source and drain electrodes on the IDTBT semiconductor thin film layer using a thermal evaporation process to obtain the Ga2O3 / IDTBT single-gate reconfigurable transistor.

[0058] The fabrication method provided in this invention is simple and low-cost. Employing a full solution method (aqueous solution combined with organic solution), it successfully fabricates a phototransistor with multimodal reconfiguration capabilities under an extremely low thermal budget of no more than 300°C. In particular, this method avoids expensive high-temperature vacuum deposition processes and, by controlling low-temperature annealing conditions, cleverly preserves the defect states that play a role in charge trapping within the Ga2O3 dielectric layer. The overall process is characterized by low temperature, environmental friendliness, and high compatibility with flexible roll-to-roll large-area manufacturing.

[0059] In step S1, in some embodiments, the gallium salt is gallium nitrate hydrate (Ga(NO3)3·xH2O), and the corresponding solvent is deionized water. The organic solvent corresponding to the IDTBT polymer is chloroform.

[0060] In some embodiments, the concentration of metal ions in the Ga2O3 precursor solution is 1.5~2.5 M; when preparing the precursor solution, it is continuously stirred at 50~70°C for 3~5 hours.

[0061] In some embodiments, the concentration of the IDTBT semiconductor solution is 3-7 mg / mL; the solution is prepared by continuous stirring at 60-80°C for 6-10 hours.

[0062] In step S2, in some embodiments, the substrate is a heavily doped silicon wafer (p... ++ The Ga2O3 precursor solution is treated with plasma before spin coating to enhance its surface hydrophilicity. The spin coating speed of the Ga2O3 precursor solution is 4000~5000 rpm, and the spin coating time is 20~40 s.

[0063] In some embodiments, the Ga2O3 precursor solution is spin-coated onto the substrate and then annealed to form a Ga2O3 dielectric thin film layer retaining intrinsic hydroxyl (-OH) defect states. An optimized spin-coating process yields a Ga2O3 dielectric layer with a thickness of 25–40 nm, which ensures extremely low leakage current while allowing effective penetration of the gate electric field, supporting efficient device operation at low voltages. If necessary, multiple spin-coating steps can further reduce leakage current caused by pinholes inherent in large-area fabrication.

[0064] In some embodiments, step S3 specifically includes:

[0065] An IDT semiconductor thin film precursor solution is provided, and the IDT semiconductor thin film precursor solution is spin-coated onto the Ga2O3 dielectric thin film layer. The solution is then annealed at a temperature of 110~130℃ for 5~15 min to form an IDT semiconductor thin film layer on the Ga2O3 dielectric thin film layer.

[0066] In some embodiments, the material of the semiconductor thin film layer is IDTBT (indobisthiophene-co-benzothiadiazole), that is, the semiconductor thin film layer is an IDTBT organic semiconductor thin film layer, and step S3 specifically includes:

[0067] IDT polymer is dissolved in an organic solvent to obtain an IDT semiconductor solution. The IDT semiconductor solution is then spin-coated onto the Ga2O3 dielectric thin film layer and annealed at 110~130℃ for 5~15 min to form an IDT semiconductor thin film layer on the Ga2O3 dielectric thin film layer.

[0068] In some embodiments, the material of the IDTBT semiconductor thin film layer is an IDTBT (indobisthiophene-co-benzothiadiazole) organic conjugated polymer. The concentration of the IDTBT semiconductor solution is 3~7 mg / mL. This ultrathin organic semiconductor layer design not only endows the device with broadband light absorption capability from the ultraviolet to the visible spectrum, but also greatly enhances the modulation capability of the channel carrier concentration by the -OH defect state charge trapping effect on the Ga2O3 dielectric layer surface by reducing the channel thickness, thereby significantly improving the multimodal reconstruction behavior and the sensitivity of synaptic response.

[0069] In step S4, in some embodiments, source and drain electrodes are formed spaced apart on the IDTBT semiconductor thin film layer. The source and drain electrodes are preferably gold (Au) electrodes. The fabrication method can employ a mask combined with thermal evaporation or electron beam evaporation process to deposit a gold layer with a thickness of 40-60 nm in a vacuum environment, which will not be elaborated further here.

[0070] This invention provides an application of the Ga2O3 / IDTBT single-gate reconfigurable transistor described in any of the foregoing embodiments in multimodal neuromorphic optoelectronics, specifically including its use in constructing neuromorphic pattern recognition networks, performing high-precision broadband photodetection, and performing reconfigurable optoelectronic logic gate (such as AND / OR) operations.

[0071] The present invention will be further illustrated below through specific embodiments:

[0072] Example 1

[0073] This invention provides a method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor, as detailed below:

[0074] Step 1: Dissolve gallium nitrate hydrate (Ga(NO3)3·xH2O) in deionized water and stir continuously at 60°C for 4 hours to obtain a Ga2O3 precursor solution with a metal ion concentration of 2M. Dissolve IDTBT polymer in chloroform and stir continuously at 70°C for 8 hours to obtain an IDTBT polymer solution with a concentration of 5 mg / mL.

[0075] Step 2: Place the heavily doped silicon wafer (p... ++Si) was used as the substrate and also served as the global gate electrode. It was first ultrasonically cleaned in acetone and isopropanol for 5 minutes each, followed by plasma treatment to enhance surface hydrophilicity. Subsequently, a Ga2O3 precursor solution was spin-coated onto (p) ++ - Si) heavily doped silicon substrate (4500 rpm, 30 s) and annealed at 300 °C for 1 h to form Ga2O3 dielectric thin film layer. The final Ga2O3 dielectric thin film layer has a thickness of about 30.6 nm and retains about 62% of intrinsic hydroxyl (-OH) defect states for subsequent charge trapping and release.

[0076] Step 3: Spin-coat the IDTBT polymer solution obtained in Step 1 onto the Ga2O3 dielectric thin film layer (1000 rpm, 60 s), and anneal at 120°C for 10 min to form an IDTBT semiconductor thin film layer on the Ga2O3 dielectric thin film layer.

[0077] Step 4: Using a photomask and a thermal evaporation process, Au source and drain electrodes with a thickness of 50 nm are deposited on the IDTBT semiconductor thin film layer, forming a device channel with a length of 100 μm and a width of 1500 μm, ultimately obtaining a Ga2O3 / IDTBT single-gate reconfigurable transistor.

[0078] like Figure 1 As shown, the Ga2O3 / IDTBT single-gate reconfigurable transistor prepared in Example 1 of this invention exhibits its comprehensive morphology, interface characteristics, and multimodal reconfiguration electrical behavior.

[0079] These include:

[0080] Figure 1 The diagram shows a 3D structural schematic of the device. The device abandons the complexity of traditional reconfigurable devices that rely on multi-gate or floating gate structures and adopts the most streamlined single-gate topology. The substrate (p++-Si also serves as the global gate), Ga2O3 dielectric thin film layer, and IDTBT semiconductor thin film layer are stacked sequentially from bottom to top, and Au source / drain electrodes are deposited at intervals on the channel surface.

[0081] Figure 1 Cross-sectional scanning electron microscope (SEM) images further precisely confirmed the physical thickness of this compact and uniform bilayer heterogeneous structure. The thickness of the bottom Ga2O3 dielectric layer prepared by the low-temperature aqueous solution method is approximately 30.6 nm, while the thickness of the upper spin-coated IDTBT channel layer is approximately 84.6 nm. The interface is clear and there is no solvent mutual dissolution or swelling phenomenon, which fully demonstrates the feasibility of high-quality film formation by step-by-step processing using the all-solution method.

[0082] Figure 1Atomic force microscopy (AFM) surface morphology images show that the Ga2O3 dielectric layer prepared by the optimized process has an extremely smooth surface with a root mean square (RMS) roughness of only 0.128 nm. This atomically smooth surface provides an ideal template for the subsequent deposition of organic semiconductors, so that the IDTBT conjugated polymer film spin-coated on it also maintains extremely high uniformity with an RMS roughness as low as 0.328 nm.

[0083] Figure 1 X-ray photoelectron spectroscopy (XPS) qualitatively and quantitatively revealed the underlying material science roots of synaptic memory function. By fitting the O 1s core spectrum with Gaussian peaks, in addition to the intrinsic lattice oxygen (Ga–O) peak at 531.08 eV, a significant hydroxyl (Ga–OH) defect peak was clearly observed at 532.18 eV. This confirmed that a high concentration (approximately 62%) of intrinsic hydroxyl (-OH) defect states were intentionally retained inside and on the surface of the dielectric layer through low-temperature annealing at 300 °C, serving as deep-level charge trapping centers for subsequent multi-state switching.

[0084] Figure 1 The figure and its inlay illustrate the dielectric properties of the metal-insulator-metal (MIM) capacitor structure. This Ga₂O₃ film exhibits a breakdown field strength as high as 5.02 MV / cm, and at 10... 2 Up to 10 6 The capacitance density is maintained between 143 and 170 nF / cm over a wide frequency band, balancing breakdown insulation with low-voltage (≤ 3 V) gate control efficiency.

[0085] Figure 1 The transfer characteristic curves confirm that the device exhibits standard p-type field-effect transistor (FET) logic switching behavior when a negative drain-source bias is applied, with a turn-on voltage of approximately -0.5 V and an on / off ratio of 3.12 × 10⁻⁶. 3 It exhibits excellent static electrical gate control modulation capability.

[0086] Figure 1 At zero gate voltage (V GS It exhibits strong asymmetric output rectification characteristics at 0 V, with a rectification ratio as high as 8.3 × 10⁻⁶. 3 The ideal factor n = 5.86 (much greater than 2) obtained by fitting the Shockley equation irrefutably proves from a physical perspective that the diode rectification behavior at both ends is driven by a trap-assisted recombination mechanism mediated by the high density of -OH defect states at the interface.

[0087] Figure 1 This indicates that when the transistor is under a strong depletion bias (V0),GS In the operating mode of 3 V, the high built-in electric field in the vertical direction drives photogenerated carriers to be rapidly extracted from the channel before being captured, thus exhibiting stable broadband photodetector behavior with agile response speed and no persistent photoconductivity (PPC) effect.

[0088] Figure 1 This demonstrates when the controlled gate voltage returns to the bias-insensitive region (V GS When the light stimulation is 0 V, the photogenerated electrons are persistently trapped by the deep-level -OH defect through the trap-assisted tunneling (TAT) effect. After the light stimulation ends, they produce a strong persistent grating control effect, exhibiting the photoelectric artificial synaptic behavior of step conductance accumulation, which successfully simulates the non-volatile memory behavior required by brain-like hardware.

[0089] Example and Comparative Examples: Comparative Testing and Physical Mechanism Analysis

[0090] Comparative Example 1

[0091] Comparative Example 1 was prepared in the same way as Example 1, except that the low-temperature annealing temperature of the Ga2O3 dielectric thin film layer in step 2 was increased from 300 °C to 500 °C. The aim was to verify, through comparative experiments, the effect of intrinsic hydroxyl (-OH) defect states on the multimodal reconstruction and synaptic memory performance of the device after high-temperature decomposition.

[0092] Comparative Example 2

[0093] Comparative Example 2 uses a standard thermally oxidized SiO2 thin film (approximately 100 nm thick) as the dielectric layer to replace the solution-processed Ga2O3 dielectric thin film layer in Example 1. The rest of the device fabrication process is exactly the same as in Example 1. This comparative example is used to verify that a pure insulating layer without internal defects cannot achieve the trap-mediated synaptic memory and grating control functions described in this invention.

[0094] The devices and dielectric films prepared in Example 1, Comparative Examples 1 and 2 were subjected to detailed physicochemical characterization and photoelectric physical mechanism testing and analysis:

[0095] (1) Physical and chemical characterization: verification of thickness and defect engineering

[0096] To verify the microstructure and stacked architecture of the Ga2O3 / IDTBT single-gate reconfigurable transistor in Example 1, cross-sectional scanning electron microscopy (SEM) images precisely confirmed the physical thickness of this compact and uniform bilayer heterogeneous structure. The thickness of the bottom Ga2O3 dielectric layer, prepared using a low-temperature aqueous solution method, was approximately 30.6 nm, while the thickness of the upper spin-coated IDTBT channel layer was approximately 84.6 nm. The interface was clear and showed no solvent mixing or swelling. Meanwhile, as... Figure 6The X-ray reflectance (XRR) test curves of the Ga2O3 dielectric thin film layer shown further confirm that the surface of the film prepared by the aqueous solution method is extremely dense, which provides an excellent interface basis for subsequent effective blocking of leakage current and electric field modulation of ultrathin organic channels.

[0097] To further explore the underlying materials science roots of synaptic memory function, such as Figure 7 The figure shows the O 1s X-ray photoelectron spectroscopy (XPS) spectrum of the Ga2O3 dielectric thin film layer in Example 1. A specific peak of the Ga–OH bond at 532.18 eV can be clearly observed in the figure. Quantitative analysis using Gaussian fitting confirms that, under an extremely low thermal budget of 300 °C, a large amount of intrinsic hydroxyl (-OH) components (accounting for approximately 62%) are intentionally retained inside and on the surface of the thin film lattice. These -OH defect states that are not removed at high temperatures serve as deep-level charge trapping centers, forming the core physical basis for the subsequent induction of non-uniform interface charge distribution and trap-assisted tunneling effects.

[0098] like Figure 5 The image shows a comparison of optical microscopic images of Ga2O3 films prepared under annealing at 300 °C (Example 1), pure IDTBT films, and annealing at 500 °C (Comparative Example 1). The results show that both exhibit excellent and similar film uniformity, which eliminates the influence of macroscopic morphology or film roughness differences on device performance, thus strictly limiting subsequent electrical performance differences to the single variable of "concentration variation of internal intrinsic defect states." Furthermore, atomic force microscopy (AFM) surface morphology images show that the Ga2O3 dielectric layer prepared by the optimized process has an extremely smooth surface with a root mean square (RMS) roughness of only 0.128 nm. The IDT conjugated polymer film spin-coated on it also maintains extremely high uniformity, with an RMS roughness as low as 0.328 nm.

[0099] (2) Band engineering: Exploring the underlying physical mechanisms of four-state reconfiguration in devices

[0100] like Figure 2 The diagram shown is a schematic of the asymmetric barrier modulation energy band of the transistor in Example 1 under different operating modes. When no gate voltage (V) is applied... GS When the voltage is 0 V, the -OH defect states at the dielectric layer interface trap charges unevenly during the scan, causing a change in the local electrostatic potential near the drain and inducing an asymmetric Schottky barrier. This is the physical reason why the device can be reconstructed into a rectifier diode and exhibit extremely high rectification characteristics without bias.

[0101] like Figure 2The diagram shows a band structure comparison of the trap-assisted tunneling (TAT) mechanism and the rapid extraction mechanism of photogenerated carriers in the transistor of Example 1 under illumination. In the "artificial synapse mode," photogenerated electrons gain sufficient energy to enter through the TAT mechanism and are persistently trapped by deep-level -OH defects. Due to the extremely high release barrier, the device exhibits a persistent photogating memory effect after the light stimulation ends; conversely, in the "broadband photodetector mode" (e.g., when V is applied...), the photogenerated electrons... GS At a depletion bias of 3 V, the high built-in electric field in the vertical direction drives photogenerated carriers to quickly extract from the channel before being trapped, suppressing the process of tunneling to the defect state for trapping, thus exhibiting a fast transient switching response without sustained photoconductivity (PPC).

[0102] (3) Comparative testing: Verifying the irreplaceable role of intrinsic defects in synaptic memory

[0103] The effects of different dielectric layers on photoelectric memory capability were compared using a Keysight semiconductor parameter analyzer (model B2912B). Figure 10 The diagram shows a comparison of the continuous photocurrent response of transistors using Ga2O3 annealed at 300℃ (Example 1), Ga2O3 annealed at 500℃ (Comparative Example 1), and pure SiO2 (Comparative Example 2) as dielectric layers under multi-wavelength transient illumination. The core conclusion is that only the device in Example 1 exhibits a significant and gradually accumulating photosynaptic memory effect. In contrast, annealing at 500℃ leads to the significant decomposition and loss of -OH defects in the thin film, almost completely eliminating the device's synaptic memory capability; while the defect-free pure SiO2 dielectric layer device exhibits a mediocre photoresponse and no synaptic memory behavior whatsoever. This comparative experiment irrefutably demonstrates that the intrinsic -OH defect states preserved by the 300℃ low-temperature aqueous solution method are an irreplaceable technical feature for realizing the neuromorphic synaptic behavior of the multimodal single-gate transistor of this invention. Meanwhile, as... Figure 8 The diagram demonstrates the extremely high insulation properties of the Ga2O3 dielectric layer, with a breakdown field strength of 5.02 MV / cm, and its inlay plot shows its excellent capacitance-frequency characteristics over a wide frequency range. After verifying the underlying physical mechanism, the fundamental electrical performance of the device under four-state reconfiguration was further characterized. Figure 1 The figure shows the monochromatic transfer characteristic curve of the transistor in Example 1 in field-effect transistor (FET) mode, with a turn-on voltage of approximately -0.5 V and an on / off ratio of 3.12 × 10⁻⁶. 3 This demonstrates excellent gate control capability. For example... Figure 1 The image shows the device in diode mode (V0). GS The output characteristic curve at 0 V shows that, due to the asymmetric barrier induced by interface defects, the device exhibits excellent rectification characteristics, with a rectification ratio as high as 8.3 × 10⁻⁶. 3The ideal factor n = 5.86 was obtained by fitting the equation using the Shockley equation. Figure 14 The figure shows the transfer characteristic curves under 405 nm light intensity modulation. The transfer characteristic curves and threshold voltage (V) of the device change with increasing optical power density. th Significant drift occurred, confirming the strong grating control effect.

[0104] like Figure 3 The photoelectric response test results shown demonstrate that the device of this invention achieves broadband photodetector mode characterization across the full wavelength spectrum of 254 nm, 405 nm, 520 nm, and 635 nm. Optical absorption spectroscopy confirms the complementary advantages of the deep ultraviolet absorption of Ga2O3 and the visible light absorption of IDTBT; it also demonstrates the ability to operate under strong vertical electric fields (V0). GS At 3 V, all four wavelengths exhibit a rapid transient photocurrent response without persistent photoconductivity; further, the evolution of photoresponsivity and specific detectivity at each wavelength with optical power density is presented. Additionally, as... Figure 15 The diagram shows in detail the fine evolution trend of the device's photodetector ratio and detectivity under 520 nm and 635 nm illumination intensity modulation.

[0105] (4) Behavioral performance of four-wavelength multimodal artificial synapses

[0106] like Figure 4 As shown, the device of this invention is fully upgraded to multi-wavelength (254-635 nm) behavioral characterization in the artificial synapse mode. In V GS At a bias voltage of 0 V, the peak values ​​of excitatory postsynaptic currents (EPSCs) induced by light pulses of different wavelengths and power densities (pulse width 0.1 s) all significantly increased with increasing light power density. The physical mechanism is attributed to the fact that higher-energy light pulses induce the generation of more photogenerated electrons, which are then trapped by the deep-level -OH defect states at the Ga2O3 interface through trap-assisted tunneling (TAT). Simultaneously, as... Figure 12 The diagram further confirms the sensitive modulation of the synaptic response to the operating voltage; the peak EPSC varies with the drain read bias (V). DS The absolute value of ) increases linearly, providing extremely high circuit compatibility for flexible control of synaptic weights.

[0107] like Figure 4 The figure illustrates the dependence of the EPSC on the optical pulse width. As the optical pulse width gradually increases from 0.1 s, the peak current of the EPSC continuously increases and the recovery time prolongs. This phenomenon indicates that increasing the stimulation time can promote the entry of more electrons into the deep-level trapping centers within the Ga2O3 lattice, enhance the grating control effect, and lead to a more persistent change in the device conductivity.

[0108] Paired pulse promotion (PPF) is a typical form of short-term plasticity (STP) in biological systems and is crucial for simulating real-time information processing in the human brain. Using a 254 nm dual-pulse sequence to stimulate the device of this invention, the peak EPSC (A2) induced by the second pulse was observed to be significantly greater than the peak (A1) induced by the first pulse, successfully simulating biological PPF behavior. The PPF index can be quantified using the following formula:

[0109]

[0110] In the device of this invention, the PPF behavior can be attributed to a charge dynamics mechanism mediated by interface defects: when the current synaptic light pulse interval (Δt) is less than the relaxation time of the trapped charge, the photogenerated electrons trapped by the deep-level -OH defect state of the Ga2O3 dielectric layer have not yet been fully released; therefore, the application of subsequent light pulses leads to further accumulation of trapped electrons, thereby continuously enhancing the channel conductivity through the photogating effect. Figure 4 The figure shows the relationship between the PPF exponent and the pulse interval (Δt) at four wavelengths. The relationship between the PPF exponent and the presynaptic pulse interval can be effectively fitted using the double exponential decay function:

[0111]

[0112] Where C0 is a constant representing baseline facilitation, C1 and C2 are the initial facilitation amplitudes, and τ1 and τ2 are relaxation times. The τ1 and τ2 obtained by fitting the experimental data perfectly confirm the fast and slow biphasic decay time characteristics of PPF in biological synapses. Furthermore, by changing the input stimulus source (such as introducing specific electrical pulse modulation or opposite bias control), such as... Figure 13 As shown, the device exhibits excellent cyclic stability of dynamic bidirectional adjustment of synaptic weights under 40 consecutive positive / negative pulse stimulations, demonstrating the full-function characteristics of bidirectional adjustment of synaptic weights.

[0113] In the Ga2O3 / IDTBT single-gate reconfigurable transistor of this invention, the transition from short-term memory (STM) to long-term memory (LTM) is demonstrated by changing the number of input optical pulses. Figure 4 The diagram illustrates the excitatory postsynaptic current (EPSC) response and peak value variation with the number of consecutive light pulses (pulse width 0.1 s). As the number of pulses increases from 5 to 40, the EPSC not only accumulates in a stepwise manner to reach a higher peak value, but also exhibits a significantly prolonged time required for the current to decay and return to its initial state after the light stimulation ends, perfectly demonstrating the dynamic transformation from STM to LTM. Meanwhile, as... Figure 9The comparison shown illustrates the current gain factor of the device with the number of light pulses in detector mode (fast recovery) and synaptic memory mode (persistent photocurrent accumulation), highlighting the excellent non-volatile grating-controlled modulation capability of the device of the present invention.

[0114] (5) System-level neuromorphic computation neural network simulation and reconfigurable optoelectronic logic gates

[0115] Long-term enhancement (LTP) and long-term inhibition (LTD) properties are fundamental to building artificial neural networks (ANNs) and performing hardware-level neuromorphic computation. For example... Figure 5 As shown, the independent non-volatile photosynaptic weight update (LTP / LTD) curves extracted from the Ga2O3 / IDTBT single-gate reconfigurable transistor of this invention at four wavelengths of 254 nm, 405 nm, 520 nm, and 635 nm are presented. Experiments show that the device exhibits highly linear and symmetrical conductance modulation characteristics under continuous pulse stimulation.

[0116] Furthermore, based on the extracted multi-wavelength LTP / LTD experimental data, a three-layer perceptron artificial neural network (ANN) for image recognition was constructed on a system-level simulation platform, with the following topology: Figure 5 As shown, the network is interconnected via synaptic weight matrices, and the weight updates during training strictly correspond to the actual conductance changes of the device in this invention. This network was used to train pattern recognition on the standard MNIST handwritten digit dataset. Figure 5 The figure shows the change in recognition accuracy of the neural network under four different excitation wavelengths over training cycles. The results show that, using a supervised learning method based on backpropagation, after 50 training cycles (Epochs), the recognition accuracy based on the four wavelength simulations successfully exceeded 90.8%, demonstrating excellent full-spectrum multimodal sensing and pattern recognition capabilities. Meanwhile, as... Figure 11 The results show that the two-dimensional electrostatic potential and electric field distribution of the device in the vertical and horizontal directions were simulated using finite element software, providing strong support for the above experimental results from the perspective of microscopic device physics.

[0117] In addition to neuromorphic computing, the Ga2O3 / IDTBT transistor of this invention also possesses the ability to perform reconfigurable optoelectronic logic operations. For example... Figure 5The diagram defines the input-output truth relationships of optoelectronic logic gates based on dual-wavelength optical signal inputs (e.g., 254 nm ultraviolet light and 635 nm red light). Furthermore, the transient photocurrent waveform response diagrams for optical AND and OR logic operations implemented by the device of this invention are shown. Due to the selective absorption and defect trapping efficiency differences of the IDTBT semiconductor layer and the Ga2O3 dielectric layer for photons of different wavelengths, the device can perform different threshold logic responses to dual-wavelength optical signals through simple bias modulation, thereby successfully executing the dynamic switching of AND and OR logic gates within a single physical device.

[0118] Compared to existing technologies, this invention offers significant structural and process advantages. The Ga2O3 / IDTBT transistor of this invention, with its extremely low thermal budget (300 °C for oxides, 120 °C for organics) and all-solution spin-coating process, uniquely and perfectly integrates four core functions—FET, diode, photosynapse, and photodetector—in a highly streamlined single-gate architecture. By simply adjusting the single-gate bias and illumination conditions, dynamic decoupling and seamless switching of four optoelectronic operating modes can be achieved within a single physical space. Its underlying mechanism innovatively utilizes the large number of intrinsic hydroxyl (-OH) defect states retained in the Ga2O3 dielectric layer through a low-temperature aqueous solution method for dynamic charge capture. Based on this mechanism, this invention successfully simulates synaptic memory conversion and high-pass filtering characteristics, and demonstrates superior system-level computing capabilities in pattern recognition and reconfigurable optoelectronic logic gates of artificial neural networks. Furthermore, the fabrication method of this invention is extremely simple, low-cost, and compatible with large-area flexible manufacturing, providing a revolutionary physical support and hardware solution for future high-efficiency, highly integrated multimodal neuromorphic optoelectronic chips and edge artificial intelligence hardware.

[0119] In summary, the Ga2O3 / IDTBT single-gate reconfigurable transistor provided by this invention abandons the complex physical structure of traditional multi-terminal or multi-gate architectures, breaking down the physical barriers between different computing modes. Only by adjusting the single-gate bias and illumination conditions, dynamic decoupling and seamless switching of four optoelectronic operating modes can be achieved within a single physical space. Its underlying mechanism innovatively utilizes the large number of intrinsic hydroxyl (-OH) defect states retained in the Ga2O3 dielectric layer through a low-temperature aqueous solution method for dynamic charge trapping. Based on this mechanism, this invention successfully simulates the synaptic memory transition from short-term to long-term plasticity (STP-to-LTM) and exhibits excellent system-level computing capabilities in pattern recognition and reconfigurable optoelectronic logic gates (AND / OR) in artificial neural networks. Furthermore, the fabrication method of this invention is extremely simple, low-cost, and compatible with large-area flexible manufacturing, providing a revolutionary physical support and hardware solution for future high-efficiency, highly integrated multimodal neuromorphic optoelectronic chips and edge artificial intelligence hardware.

[0120] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A Ga2O3 / IDTBT single-gate reconfigurable transistor for multimodal neuromorphic optoelectronics, characterized in that, include: A substrate, a Ga2O3 dielectric thin film layer, an IDTBT semiconductor thin film layer are stacked sequentially, and a source electrode and a drain electrode are spaced apart on the side of the IDTBT semiconductor thin film layer away from the Ga2O3 dielectric thin film layer.

2. The Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 1, characterized in that, The Ga2O3 dielectric thin film layer retains hydroxyl defect states (-OH) inside and on its surface. These hydroxyl defect states serve as charge trapping centers to achieve the trapping and release of photogenerated charge carriers.

3. The Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 1, characterized in that, The transistor is a single-gate reconfigurable structure that can dynamically switch between field-effect transistor mode, rectifier diode mode, broadband photodetector mode, and artificial synapse mode based on the bias voltage applied to the gate and drain.

4. The Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 1, characterized in that, The Ga2O3 dielectric thin film layer has a thickness of 25~40 nm, and the substrate is a heavily doped silicon wafer (p... ++ -Si); the source electrode and drain electrode are gold electrodes.

5. The Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 1, characterized in that, The IDTBT semiconductor thin film layer is formed by spin-coating an organic conjugated polymer solution based on indobisthiophene-co-benzothiadiazole (IDTBT).

6. A method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor according to any one of claims 1 to 5, characterized in that, include: Step S1: Provide gallium salt and IDTBT polymer. Dissolve gallium salt in water to obtain a Ga2O3 precursor solution. Dissolve IDTBT polymer in chloroform to obtain an IDTBT polymer solution. Step S2: Provide a heavily doped silicon wafer (p ++ Using Si as a substrate and performing surface hydrophilization treatment, the precursor solution of Ga2O3 is spin-coated onto the substrate and annealed to form a Ga2O3 dielectric thin film layer retaining hydroxyl defect states on the substrate. Step S3: Spin-coat the IDTBT polymer solution onto the Ga2O3 dielectric thin film layer and anneal it to form an IDTBT semiconductor thin film layer. Step S4: Form source and drain electrodes spaced apart on the IDTBT semiconductor thin film layer to obtain the Ga2O3 / IDTBT single-gate reconfigurable transistor.

7. The method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 6, characterized in that, In step S1, the Ga2O3 precursor solution is prepared by dissolving gallium nitrate hydrate in deionized water, wherein the metal ion concentration is 1.5 ~ 2.5 M; the IDTBT polymer solution is prepared by dissolving IDTBT in chloroform, wherein the concentration is 3 ~ 7 mg / mL.

8. The method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 6, characterized in that, In step S2, the annealing temperature is 280 ~ 320 ℃ and the annealing time is 55 ~ 70 min.

9. The method for fabricating a Ga2O3 / IDTBT single-gate reconfigurable transistor according to claim 6, characterized in that, In step S3, the annealing temperature is 110 ~ 130 ℃ and the time is 5 ~ 15 min.

10. The application of the Ga2O3 / IDTBT single-gate reconfigurable transistor according to any one of claims 1 to 5 in multimodal neuromorphic optoelectronics, characterized in that, The applications include using the transistor to build neuromorphic pattern recognition networks, perform broadband photodetection, or perform reconfigurable optoelectronic logic gate (AND / OR) operations.

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