A 375 nm visual memory resistance transistor of a MAPbI3 doped gate and a preparation method thereof

Abstract

The application discloses a 375nm visual memory resistance transistor with a MAPbI3 doped gate and a preparation method thereof, and belongs to the technical field of transistors. The visual memory resistance transistor comprises a substrate layer, an electrode layer, a semiconductor active layer and an ionic gel electrolyte layer. The electrode layer comprises a source electrode, a drain electrode and a gate electrode, and the semiconductor active layer is located between the source electrode and the drain electrode to form a channel. A PEDOT:PSS capacitance enhancement layer is arranged between the gate electrode and the ionic gel electrolyte layer, a MAPbI3 gate photosensitive memory layer is formed in the gate region, and a PMMA packaging regulation layer is formed on the surface of the MAPbI3 gate photosensitive memory layer to passivate defects and adjust a polarization relaxation time constant. Under the stimulation of a 375nm light pulse, the MAPbI3 gate photosensitive memory layer generates photo-generated carriers, and reversible interface dipoles and slow polarization are formed under the synergistic action of grain boundaries / defects and ion vacancies, so that a maintainable equivalent bias and equivalent capacitance modulation are generated on the gate side. Under the condition of low gate voltage and low drain voltage, the cumulative enhancement / inhibition of the channel conductance can be realized, and multi-level conductance storage with not less than 8 levels can be realized.

Description

Technical Field

[0001] This invention relates to the fields of perovskite photoelectric memristors, neuromorphic vision devices, and three-terminal in-memory transistors, specifically to a visual memristor transistor that achieves programmable conductance memory under 375nm ultraviolet light stimulation by doping / integrating a MAPbI3 polycrystalline thin film in the gate and the same method for fabricating it. Background Technology

[0002] Visual memristors couple optical stimulation, perception, and electrical conductance memory to achieve functions similar to the biological retina, such as perception, adaptation, and memory. They enable preprocessing at the sensing end and reduce the computational and transmission burden at the back end. Existing photosensitive memristors mostly employ a two-terminal structure, achieving conductance plasticity and maintenance through photogenerated carriers and defect trapping, ion migration, and interface barrier changes. However, when integrated in a cross-array, the read / write paths of the two-terminal structure are difficult to decouple, easily leading to crosstalk and write errors. Furthermore, the device's conductance state is more sensitive to electrode interfaces and environmental disturbances, often limiting consistency and repeatability when multi-level fine-grained storage is required.

[0003] Three-terminal transistor structures, by independently modulating the channel conductance through the gate, naturally possess advantages such as suppressing array crosstalk, expanding the read / write window, and low-voltage control, thus becoming an important device platform for constructing synaptic-like devices and in-memory computing front-ends. Halide perovskites (such as MAPbI3) have advantages in strong absorption coefficients, long carrier diffusion lengths, and low-temperature solution fabrication, and have been used in devices such as photodiodes, photodetectors, and phototransistors. Meanwhile, the presence of migratable ions and defect states in perovskite materials makes them prone to hysteresis and threshold drift under the coupling of external electric and optical fields, providing a physical basis for constructing programmable memory. However, under ultraviolet stimulation (e.g., 375nm), defect states are more easily activated, and ion migration and interface reactions may be exacerbated, leading to device drift, insufficient retention, or poor cycle consistency.

[0004] Existing perovskite phototransistors typically use perovskite as the channel material to achieve high photocurrent. However, when the channel is directly exposed to the gate electric field and the operating current channel, it is susceptible to the combined effects of water and oxygen, thermal stress, and ion migration, which is detrimental to stable multi-level memory. In addition, ultraviolet light can easily induce the evolution of surface / interface defects in the channel, further amplifying drift. Therefore, there is an urgent need for a device structure that transfers the perovskite photosensitivity and polarization memory processes from the channel side to the gate side, while retaining the advantages of three-terminal gate control, to achieve stable sensing of 375nm ultraviolet light, programmable memory, and adjustable time constants, in order to meet the requirements of low power consumption and high consistency for event-driven vision, neuromorphic computing, and front-end in-memory computing. Summary of the Invention

[0005] The purpose of this invention is to provide a 375nm visual memristor transistor with a MAPbI3-doped gate and its fabrication method. By using a composite gate structure, the photosensitive memory process is confined to the gate side and capacitance enhancement and packaging control are achieved, thereby obtaining stable and programmable ultraviolet visual memory at low voltage and solving problems such as array crosstalk, ultraviolet drift and insufficient retention.

[0006] The technical solution adopted in this invention is as follows: (1) Device structure: The visual memristor transistor of the present invention includes, from bottom to top, a base layer, an electrode layer, a semiconductor active layer and an ion gel electrolyte layer; the electrode layer includes a source electrode, a drain electrode and a gate electrode, and the semiconductor active layer is located between the source and drain to form a channel; the ion gel electrolyte layer covers the channel and is connected to the gate region to form an ion-electron coupled gate control path.

[0007] (2) Composite gate design: A PEDOT:PSS capacitance enhancement layer is set between the gate electrode and the ion gel electrolyte layer to improve the equivalent gate capacitance, reduce the interface impedance and improve wetting, so that the applied gate voltage can be more effective in the channel ion doping process; a MAPbI3 gate photosensitive memory layer is set on the PEDOT:PSS layer as a programmable gate signal source driven by photostimulation.

[0008] (3) Gate doped with MAPbI3: The MAPbI3 gate photosensitive memory layer is formed in the gate region by the commonly used MAPbI3 in-situ spin-coating polycrystalline preparation method. By controlling the precursor concentration, antisolvent drop time and annealing temperature / time, the grain size and grain boundary density can be adjusted, thereby achieving a designable trade-off between response speed and holding time.

[0009] (4) Working mechanism: Under 375nm illumination, MAPbI3 generates photogenerated carriers and forms traps and slow releases at grain boundaries / defects, accompanied by reversible migration of halide ions / vacancies and interface dipole polarization. The above process forms a maintainable equivalent bias and capacitance modulation on the gate side, and then drives the ion redistribution and electrochemical doping degree change of the channel through ion gel, thereby realizing the cumulative enhancement / suppression of drain current.

[0010] (5) Adjustable plasticity: By changing the number of light pulses, frequency, power density or gate bias, a controllable transition from rapidly decaying short-term plasticity (STM) to long-term plasticity (LTM) can be achieved; and the experience-dependent characteristics of learning-forgetting-relearning can be achieved through training-decaying-retraining, which can be used to simulate visual synapse and retinal adaptation.

[0011] (6) Packaging control and stability: As a preferred option, a PMMA packaging control layer can be spin-coated on the surface of the MAPbI3 gate photosensitive memory layer; PMMA can passivate surface defects, inhibit water and oxygen intrusion and limit ion exchange channels, thereby reducing drift under ultraviolet stimulation and prolonging the retention time; at the same time, the thickness of PMMA can be used as a knob for adjusting the time constant, realizing continuous adjustment between "fast response / fast forgetting" and "slow response / long retention".

[0012] (7) Material and parameter range: The semiconductor active layer can be P3HT or DPP-DTT and its composite system with SEBS; the ion gel is formed by block polymer and ionic liquid, which has both high ionic conductivity and mechanical support; the device can work under the condition that Vd and Vg do not exceed 0.8V, which is suitable for low power integration.

[0013] (8) Overview of preparation method: The present invention adopts the process of “substrate cleaning - electrode preparation - semiconductor spin coating - PEDOT:PSS layer formation - MAPbI3 in-situ spin coating of polycrystalline material - optional PMMA encapsulation - ion gel drop curing”; all steps are compatible with conventional spin coating, drying and low temperature annealing processes, which facilitates arraying and large-area preparation.

[0014] (9) Performance example: Under the conditions of Vd=-0.5V, Vg=-0.6V, and 375nm power density of 0.5mW / cm², after 25 light pulse training, the device Id can be gradually increased from about 1 to 3µA to about 70 to 100µA, forming no less than 8 levels of resolvable conductance states; after light removal, it can be maintained for 1000 to 3000s under PMMA packaging conditions, and exhibits repeatable learning-forgetting-relearning behavior.

[0015] Step 1: Clean the transparent glass substrate, and then dry it with nitrogen or heat it in a constant temperature oven for more than 6 hours. Step 2: Pour SEBS, PDMS or PU onto a glass substrate coated with detergent. After the solution is spread evenly, place it in a vacuum drying oven to dry. After drying, use a blade to peel the flexible substrate off the glass substrate. Step 3: Spray carbon paste electrodes (80~150nm) onto the PU substrate; Step 4: Deposit a PEDOT:PSS electrode modification layer onto the carbon paste grid electrode; Step 5: Clean the microscope slides, and then dry them with nitrogen or in a constant temperature oven for more than 6 hours. Step 6: Spin-coat the prepared PVA solution onto a microscope slide, and then dry the spin-coated slide to obtain the PVA sacrificial layer; Step 7: Spin-coat the prepared P3HT mixed solution or DPP-DTT mixed solution onto the PVA sacrificial layer; Step 8: Place the substrate in a petri dish containing 60°C deionized water to dissolve the PVA sacrificial layer in the deionized water to obtain a semiconductor active layer. Transfer a semiconductor active layer onto a flexible substrate and dry it with nitrogen gas. Step 9: Drop ion gel electrolyte onto the semiconductor channel.

[0016] As a preferred technical solution, in step 2, the drying temperature is 30°C and the time range is 12 hours.

[0017] As a preferred technical solution, in step 4, the drying temperature is 30°C and the time range is 30 minutes.

[0018] As a preferred technical solution, in step 6, the drying temperature is 110℃ and the time range is 2 minutes.

[0019] As a preferred technical solution, the drying method employs one or more of the following: constant temperature hot table heating, oven heating, far-infrared heating, and hot air heating.

[0020] The beneficial effects of this invention are as follows: 1. Three-terminal structure suppresses crosstalk: The three-terminal structure of the transistor achieves decoupling of the read and write paths. Compared with two-terminal memristors, it can significantly reduce the risk of crosstalk and miswrite in the cross array, and improve the accuracy of multi-level storage and the scalability of the array.

[0021] 2. Gate-side memory improves stability: By doping / integrating the MAPbI3 photosensitive memory layer on the gate side, the channel material is not directly subjected to the stress caused by perovskite ion migration and environmental sensitivity, avoiding channel drift accumulation and improving consistency and cycle repeatability under ultraviolet stimulation.

[0022] 3. Capacitor enhancement reduces power consumption: The introduction of the PEDOT:PSS capacitor enhancement layer increases the equivalent gate capacitance and reduces the interface impedance, making the applied gate voltage more effective in driving the channel ion-electron coupling doping. The device can achieve significant plasticity and transconductance amplification at a low voltage of ≤0.8V, thus reducing power consumption.

[0023] 4. Time constant can be designed and multi-level storage: By controlling the MAPbI3 grain / defect and adjusting the PMMA package thickness, the retention time and forgetting rate can be continuously controlled to achieve STM-LTM adjustable conversion; the device can achieve no less than 8 levels of multi-level conductivity storage and support learning-forgetting-relearning, which is suitable for UV vision front-end preprocessing and neuromorphic computing. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below; it should be understood that the component proportions in the accompanying drawings do not represent the actual proportional relationships in the material selection and design, but are only schematic diagrams of the structure or position, wherein: Figure 1 This is a schematic diagram of the 375nm visual memristor transistor structure with a MAPbI3-doped gate according to the present invention. Explanation of reference numerals: 1-Base layer; 2-Source electrode; 3-Drain electrode; 4-Gate electrode; 5-PEDOT:PSS capacitor enhancement layer; 6-Semiconductor active layer; 7-Ion gel electrolyte layer; 8-MAPbI3 gate photosensitive memory layer; 9-PMMA encapsulation control layer. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention; those skilled in the art can make equivalent substitutions or improvements to the material system, layer thickness, and process parameters without departing from the spirit of the invention.

[0026] The following is combined Figure 1 The present invention will be described in detail below.

[0027] Example 1 (Control group: without MAPbI3 gate memory layer) 1) Substrate treatment: Take a glass or PI substrate and ultrasonically clean it in deionized water, acetone and isopropanol for 10-15 minutes each. After drying with nitrogen, treat it with ultraviolet ozone for 10-20 minutes to improve surface cleanliness and wettability.

[0028] 2) Electrode fabrication: Source and drain electrodes (thickness 80-150nm) are formed by mask evaporation or spraying, with channel length L=50µm and channel width W=1000µm; gate electrodes (carbon paste / Au / Ag / ITO) are fabricated in adjacent regions.

[0029] 3) Semiconductor active layer: P3HT and SEBS were dissolved in chloroform at a mass ratio of 2:1 (total concentration 10-20 mg / mL), filtered through a 0.22 µm filter membrane, and a semiconductor thin film was formed by spin coating between the source and drain (5000 rpm, 10 s), and annealed at 80-110 °C for 5-10 min to optimize morphology and improve electrical stability.

[0030] 4) Gate capacitance enhancement layer: PEDOT:PSS (PH1000) is deposited on the gate electrode surface and dried at 40°C for 20 min to form a capacitance enhancement layer (thickness of about 80-200 nm); no MAPbI3 gate photosensitive memory layer is introduced in this control group.

[0031] 5) Ion gel electrolyte layer: PS-PMMA-PS and ionic liquid [EMIM][TFSI] are mixed and dissolved at a mass ratio of 1:9, and then dripped onto the channel and gate regions and cured at room temperature to form an ion gel layer, so that the ion pathway covers both the channel and the gate.

[0032] 6) Electrical / Optical Testing: The transfer characteristics were tested in the dark (Vd=-0.5V, Vg swept from 0.1V to -0.7V), and the transconductance and threshold were recorded; optical pulses (1s on, 2s off, 1 to 25 times) were applied at a power density of 0.5mW / cm² at 375nm, and the change of Id over time was recorded.

[0033] 7) Results: The control group showed a transient increase in Id when the light was turned on, but quickly recovered to the baseline after the light was turned off, and the holding time was usually less than 30-60s; after multiple cycles, the pulse amplitude fluctuated greatly and it was difficult to form a stable multi-level conductance state, indicating that PEDOT:PSS gate modification alone is not enough to achieve ultraviolet programmable memory.

[0034] 8) Drop PS-PEO-PS:[EMIM][TFSI] ionogel onto the semiconductor channel and dry it in a vacuum drying oven at 40℃ after dropping; 9) Under the test conditions: Drain voltage (VD) = -0.5V, gate voltage (VG) scan range is 1V~-1.5V, that is, when VG = 1V, the ions injected into the semiconductor layer of this device can be released from the semiconductor and return to the electrolyte. The on / off ratio (Ion / Ioff) is 8.6×103, the on current (Ion) is 108μA, and the transconductance (gm) is 0.47mS.

[0035] 10) After stretching the device to 120% for 300 cycles, the transconductance (gm) of the device was measured to be 0.40 mS, retaining 85.11% of the transconductance.

[0036] Example 2 (MAPbI3 doped gate: introduction of MAPbI3 gate photosensitive memory layer) 1) Prepare the substrate, source / drain electrodes, semiconductor active layer and PEDOT:PSS capacitor enhancement layer according to steps 1 to 4 of Example 1.

[0037] 2) MAPbI3 precursor solution: Dissolve MAI and PbI2 in a mixed solvent of DMF:DMSO=4:1 at a molar ratio of 1:1 to obtain a concentration of 1.2M; stir at 60℃ until clear and then filter to obtain the precursor solution.

[0038] 3) In-situ spin-coating of MAPbI3 polycrystalline film: The precursor solution was spin-coated in the gate region using a two-stage spin-coating program (1000 rpm for 10 s, 4000 rpm for 30 s). Chlorobenzene (about 200 µL) was added 10 s before the end of the second spin-coating stage as an antisolvent to promote rapid nucleation. Subsequently, the film was annealed at 100 °C for 15 min to obtain a dense MAPbI3 polycrystalline film (thickness about 150-200 nm).

[0039] 4) Ion gel preparation and assembly: The solidified ion gel layer was dripped and deposited according to step 5 of Example 1 to form a continuous ion pathway with the MAPbI3 gate memory layer, PEDOT:PSS layer and channel region.

[0040] 5) Memristor training and multi-level states: Under the conditions of Vd=-0.5V and Vg=-0.6V, 375nm optical pulses are applied for training (power density 0.5mW / cm², 1s pulse, 2s interval, 1 to 25 times); during the training process, Id shows cumulative enhancement. After 25 pulses, Id can be increased from about 2µA to about 70 to 100µA, and at least 8 levels of resolvable conductance states are formed.

[0041] 6) Retention and Forgetting: After light removal, Id exhibits a decay process that is fast at first and then slows down; in this embodiment, the high conductivity state can be maintained for about 300 to 800 seconds, which is a transition from STM to LTM; by reducing the number of pulses (e.g., 1 to 5 times), a faster forgetting STM state can be obtained.

[0042] 7) Repeatability: After more than 10 rounds of repetition under the same training conditions, the conductivity level can still be distinguished and the drift is less than about 10%; indicating that introducing MAPbI3 into the gate side can form a relatively stable programmable threshold / capacitance modulation under ultraviolet stimulation.

[0043] 8) Place the spin-coated glass slide in a petri dish containing deionized water, place the petri dish on a hot stage (60°C) to dissolve the PVA sacrificial layer in the deionized water to obtain a semiconductor active layer, transfer a layer of semiconductor active layer onto a flexible substrate, and dry it with nitrogen gas. 9) Drop PS-PEO-PS:[EMIM][TFSI] ionogel onto the semiconductor channel and dry it in a vacuum drying oven at 40℃ after dropping; 10) Under the test conditions: Drain voltage (VD) = -0.5V, gate voltage (VG) scan range is 0.2V~-0.8V, that is, when VG = 0.2V, the ions injected into the semiconductor layer of this device can be released from the semiconductor and return to the electrolyte, and the on / off ratio (Ion / Ioff) is measured to be 4.9×104, the on current (Ion) is 381μA, and the transconductance (gm) is 0.59mS.

[0044] Example 3 (PMMA Packaging Control: Improving Stability and Adjustable Time Constant) 1) A device containing a MAPbI3 gate photosensitive memory layer was prepared according to Example 2.

[0045] 2) PMMA encapsulation layer: PMMA was dissolved in anethole to prepare an 8 mg / mL solution, filtered, and then spin-coated onto the MAPbI3 surface (4000 rpm, 40 s). The solution was then baked at 80 °C for 5 min to form a PMMA encapsulation control layer (approximately 80 nm thick).

[0046] 3) After the ionogel is deposited and cured, a 375nm pulse training and holding test is performed under the same conditions.

[0047] 4) Results: PMMA encapsulation can reduce water and oxygen intrusion and rapid interface recombination, and suppress drift under ultraviolet stimulation; the retention time after light removal is significantly extended from 300-800s in Example 2 to about 1000-3000s, and the spacing between the multi-level states is more stable.

[0048] 5) Time constant adjustment: The forgetting time constant can be continuously adjusted by changing the PMMA concentration (2-10 mg / mL) or the spin coating speed (3000-5000 rpm), for example, from about 200 s to about 2500 s, to achieve programmable switching between "fast response / fast forgetting" and "slow response / long retention".

[0049] 6) Energy consumption example: Under the conditions of 0.5mW / cm² and 2Hz, the energy of a single write operation can be less than 0.2µJ / pixel based on the typical spot area; the readout disturbance is less than 5% under the dark state readout voltage of 100mV, which is suitable for low-power vision front-ends.

[0050] 7) Spin-coat the prepared PVA solution onto a microscope slide (3000 rpm, 60 s), and dry the spin-coated slide (110 ℃, 2 min) to obtain the PVA sacrificial layer; Example 4 (Learning-Forgetting-Relearning and Structural Parameter Optimization) 1) Learning-forgetting-relearning test was performed using the device in Example 3: First, a set of light pulses (e.g., 20 times) were applied as a learning process, and Id was recorded to gradually rise from the baseline and enter a high conductivity state; after the light was removed, the decay of Id over time was recorded to obtain the forgetting curve.

[0051] 2) When Id decays to 30% to 50% of its peak value, a second set of fewer light pulses (e.g., 5 to 10 times) is applied for relearning, and Id is recorded to quickly recover to a conductivity level close to that after the first learning; this indicates that the device has experience-dependent characteristics and synaptic relearning advantages.

[0052] 3) Frequency and power adjustment: The write rate and retention can be adjusted by changing the pulse frequency (0.5~10Hz) and power density (0.05~5mW / cm²); higher frequency / power is more likely to trigger LTM state, while lower frequency / power is more likely to obtain STM state, which meets the time scale requirements of different visual scenarios.

[0053] 4) Grain size optimization: Different grain sizes (approximately 200-800 nm) can be obtained by adjusting the antisolvent drop time (5-15 s earlier / later) and annealing temperature (90-110 °C). Larger grains result in lower interface defect density and enhanced retention, but may reduce response speed. Smaller grains result in faster response but also faster forgetting.

[0054] 5) Stability example: After being placed in room temperature air for 7 days, the PMMA packaged device still maintains considerable UV training and multi-level holding capability; after 50 consecutive light pulse training, it can still distinguish multi-level conductance states, indicating that the composite gate structure has good environmental robustness.

[0055] 1. Clean the transparent glass substrate with a surface roughness of less than 1 nm, and then dry it in a constant temperature oven for more than 6 hours; 2. Apply a layer of detergent to the glass substrate, pour PU onto the glass substrate coated with detergent, shake it slightly to spread the solution evenly, and then place it in a vacuum drying oven to dry (30℃, 12h). After drying, carefully peel the flexible substrate off the glass substrate with a blade. 3. Spray the carbon paste electrode (80~150nm) onto the PU substrate; 4. A PEDOT:PSS electrode modification layer is deposited onto the gate electrode coated with carbon paste, and the device with the PEDOT:PSS gate electrode modification layer is dried (30°C, 30 min). Step 4 above is repeated twice. 5. Clean microscope slides with a surface roughness of less than 1 nm, and then dry them in a constant temperature oven for more than 6 hours. 6. Spin-coat the prepared PVA solution onto a microscope slide (3000 rpm, 60 s), and then dry the spin-coated slide (110 ℃, 2 min) to obtain the PVA sacrificial layer; 7. Spin coat the prepared P3HT mixed solution (P3HT:SEBS=2:1) ​​onto the PVA sacrificial layer (5000rpm, 10s). 8. Place the spin-coated glass slide in a petri dish containing deionized water, place the petri dish on a hot stage (60°C) to dissolve the PVA sacrificial layer in the deionized water to obtain a semiconductor active layer, transfer a layer of semiconductor active layer onto a flexible substrate, and dry it with nitrogen gas. 9. Drop PS-PEO-PS:[EMIM][TFSI] ionogel onto the semiconductor channel and dry it in a vacuum drying oven at 40℃ after dropping. 10. Under test conditions: Drain voltage (VD) = -0.5V, gate voltage (VG) scan range is 0.1V to -0.7V, that is, when VG = 0.1V, the ions injected into the semiconductor layer of the device can be released from the semiconductor and return to the electrolyte. When VG = -0.7V, the output leakage current (ID) of the device is close to saturation, and the measured on / off ratio (Ion / Ioff) is 1.2×105, the on-state current (Ion) is 501μA, and the transconductance (gm) is 0.73mS.

[0056] 11. After stretching the device to 120% for 300 cycles, the transconductance (gm) of the device was measured to be 0.64 mS, retaining 87.67% of the transconductance.

[0057] As can be seen from the above embodiments, by integrating a MAPbI3 in-situ spin-coated polycrystalline photosensitive memory layer on the gate side and introducing a PEDOT:PSS capacitor enhancement layer and an optional PMMA package control layer, the present invention can achieve cumulative modulation of channel conductance, multi-level conductance storage, and adjustable hold time constant under low voltage; at the same time, the three-terminal structure is beneficial to suppress array crosstalk and improve read accuracy.

[0058] Compared to the control group, the device of this invention exhibits more stable current accumulation under 375nm light pulse stimulation, and its multi-level states are more easily distinguishable. Through encapsulation control, the retention time can be significantly extended and drift reduced, demonstrating repeatable learning-forgetting-relearning behavior. These features make this invention suitable for applications such as ultraviolet visual perception, event-driven front-end preprocessing, and neuromorphic computing.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 375nm visual memristor transistor with a MAPbI3-doped gate, characterized in that, From bottom to top, it includes a base layer (1), an electrode layer, a semiconductor active layer (6), and an ion gel electrolyte layer (7); the electrode layer includes a source electrode (2), a drain electrode (3), and a gate electrode (4), and the semiconductor active layer (6) forms a channel between the source electrode (2) and the drain electrode (3); A PEDOT:PSS capacitor enhancement layer (5) and a MAPbI3 gate photosensitive memory layer (8) are sequentially disposed between the gate electrode (4) and the ion gel electrolyte layer (7). The MAPbI3 gate photosensitive memory layer (8) is a polycrystalline thin film formed by the MAPbI3 in-situ spin-coating polycrystalline preparation method and doped / integrated in the gate region. It is used to generate a maintainable equivalent gate polarization state under the combined action of 375nm light illumination and gate electric field. Under a fixed drain bias, the equivalent gate polarization state modulates the channel ion-electron coupling doping degree through the ion gel electrolyte layer (7), thereby realizing the cumulative control of channel conductivity, multi-level conductivity storage, and retention / forgetting after light removal; the adjustable conversion between short-term memory and long-term memory can be realized by the number of light pulses, frequency, or gate packaging parameters.

2. The 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The substrate layer (1) is one or more of glass, PI, PET, PU, ​​SEBS and PDMS; when the substrate layer is made of a flexible material to form a flexible substrate, the visual memristor transistor can be bent to work and the gate memory layer improves environmental stability through the encapsulation layer.

3. The 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The source electrode (2), drain electrode (3) and gate electrode (4) are made of one or more of carbon paste, Au, Ag, ITO and their stacked structures, with an electrode thickness of 80-150 nm; the channel length L is 20-200 µm and the channel width W is 200-2000 µm.

4. A 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The semiconductor active layer (6) is a composite film of P3HT, DPP-DTT or the elastomer SEBS, with a film thickness of 150-350 nm; the composite film is used to simultaneously ensure carrier transport and flexible mechanical stability.

5. A 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The ion gel electrolyte layer (7) is formed by mixing a polymer with an ionic liquid; the polymer is one or more of PS-PMMA-PS, PS-PEO-PS, P(VDF-TrFE), P(VDF-HFP) and P(VDF-TrFE-CTFE), and the ionic liquid is one or more of [EMIM][TFSI], [EMIM][FSI], [EMIM][DCA], [BMIM][PF6] and [EMIM][BF4].

6. A 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The PEDOT:PSS capacitance enhancement layer (5) is PH1000 or its modified system, with a thickness of 30-300 nm, used to improve the interface wetting and ion implantation efficiency between the gate electrode and the ion gel, increase the equivalent gate capacitance and reduce the interface impedance.

7. A 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 1, characterized in that, The thickness of the MAPbI3 gate photosensitive memory layer (8) is 80-400 nm; the surface of the MAPbI3 gate photosensitive memory layer (8) may be further covered with a PMMA encapsulation control layer (9), the thickness of which is 30-150 nm, for passivating defects, isolating water and oxygen and adjusting the polarization relaxation time constant, thereby controlling the retention time and forgetting rate.

8. A method for fabricating a 375nm visual memristor transistor with a MAPbI3-doped gate, characterized in that, The method for fabricating a 375nm visual memristor transistor with a MAPbI3-doped gate as described in any one of claims 1 to 7 comprises the following steps: Step 1: The substrate layer (1) is cleaned and dried, and then surface activation is performed using ultraviolet ozone or plasma; Step 2: Fabricate source electrode (2), drain electrode (3) and gate electrode (4) on substrate layer (1), and define channel geometry using a mask; Step 3: Prepare a semiconductor solution by mixing P3HT or DPP-DTT with SEBS in a certain proportion and dissolving it in chloroform or chlorobenzene. After filtration, spin-coating is performed to form a semiconductor active layer and annealing is carried out to optimize the morphology. Step 4: PEDOT:PSS is drop-coated or spin-coated onto the surface of the gate electrode (4) to form a capacitance enhancement layer (5), and dried at 30-60°C for 10-30 min; Step 5: Prepare a MAPbI3 gate photosensitive memory layer in the gate electrode region using the MAPbI3 in-situ spin-coating polycrystalline preparation method (8): Dissolve MAI and PbI2 in a mixed solvent of DMF and DMSO to prepare a precursor solution, spin-coat the film, and add antisolvent at the end of the spin coating to promote rapid nucleation and crystallization. Then, anneal at a low temperature of 90-110℃ for 10-20 min to obtain a MAPbI3 polycrystalline thin film; Step 6: Spin-coat PMMA solution onto the surface of the MAPbI3 polycrystalline thin film to form an encapsulation control layer, in order to further improve stability and adjust the retention time constant; Step 7: Prepare ion gel electrolyte by mixing and dissolving the polymer and ionic liquid, dripping it onto the channel and gate regions and solidifying it to form an ion gel electrolyte layer (7). Step 8: Apply 375nm optical pulse stimulation under fixed drain and gate bias conditions to train the device to obtain multi-level conductance states and record the learning-forgetting-relearning behavior; Step 9: As needed, encapsulate the edges of the device to further block water and oxygen and improve long-term environmental stability.

9. The method for fabricating a 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 8, characterized in that, In step 5, the concentration of the MAPbI3 precursor solution is 0.8–1.5 M, the DMF:DMSO volume ratio is (3:1)–(6:1), and the spin coating program is 1000 rpm for 10 s and 4000 rpm for 20–40 s. The antisolvent is chlorobenzene, toluene, or ethyl acetate, and the amount added is 100–300 µL. The addition time is 5–15 s before the end of the second spin coating stage.

10. The method for fabricating a 375nm visual memristor transistor with a MAPbI3-doped gate according to claim 8, characterized in that, In step 8, the drain voltage Vd is -0.1 to -0.8V, the gate voltage Vg is 0.1 to -0.8V, the 375nm optical power density is 0.05 to 5mW / cm², the pulse frequency is 0.5 to 10Hz, and the number of pulses is 1 to 50, so as to achieve multi-level conductivity storage of no less than 8 levels and adjustable conversion from STM to LTM.

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