Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes a semiconductor circuit substrate including a pixel circuit, a reflective conductive pattern on the semiconductor circuit substrate, an emission element including a first electrode, an emission unit, and a second electrode, a pixel-defining layer on the semiconductor circuit substrate and having an emission opening exposing the first electrode, and a peripheral emission unit on the pixel-defining layer. The pixel-defining layer includes a silicon nitride layer directly on the first electrode, and a silicon oxide layer directly on the silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes more inward from the emission opening than the silicon nitride layer. The peripheral emission unit is directly on the silicon oxide layer and is electrically separated from the emission unit by the tip structure.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to display devices and electronic devices including display devices, and for example to display devices including semiconductor circuit substrates and electronic devices including display devices. Background Technology

[0002] Display devices for displaying images are included in electronic devices (such as smartphones, laptops, navigation systems, smart TVs, etc.) used to provide images to users. Display devices may include high-resolution image display devices, such as virtual reality (VR) devices, augmented reality (AR) devices, and smartwatches. High-resolution image display devices may include light-emitting diodes on silicon (LEDoS) and / or organic light-emitting diodes on silicon (OLEDoS), both of which include a silicon substrate and an emitting element on the silicon substrate.

[0003] High-resolution image display devices may have narrower pixel gaps due to the reduced size of each individual pixel. Therefore, lateral leakage current between adjacent pixels may lead to a decrease in image quality.

[0004] The information disclosed in this Background section is intended to enhance the understanding of the background techniques of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] Aspects of one or more embodiments of this disclosure are directed to a display device having enhanced (e.g., improved) image quality and increased reliability.

[0006] One or more embodiments of this disclosure are directed to electronic devices including display devices.

[0007] Other aspects of the implementation will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] According to one or more embodiments of this disclosure, a display device may include: a semiconductor circuit substrate including pixel circuitry; a reflective conductive pattern on the semiconductor circuit substrate; an emitting element including a first electrode in contact with the reflective conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; a pixel defining layer on the semiconductor circuit substrate and having an emitting opening exposing the first electrode; and a peripheral emitting unit on the pixel defining layer. The pixel defining layer may include: a silicon nitride layer directly on the first electrode; and a silicon oxide layer directly on the silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes further inward from the emitting opening than the silicon nitride layer. The peripheral emitting unit may be directly on the silicon oxide layer and electrically isolated from the emitting unit by the tip structure.

[0009] In one or more embodiments, the display device may further include an interlayer dielectric layer between the reflective conductive pattern and the first electrode. The first electrode may be in contact with a side surface of the reflective conductive pattern.

[0010] In one or more embodiments, a silicon nitride layer may be present around (e.g., surrounding) a first electrode. The first electrode may be in contact with a side surface of a reflective conductive pattern. The pixel defining layer may also include a lower silicon oxide layer between a silicon oxide layer and a semiconductor circuit substrate. The lower silicon oxide layer may be present around (e.g., surrounding) a silicon nitride layer.

[0011] In one or more embodiments, the thickness of the silicon nitride layer can be in the range of about 50 Å to about 100 Å.

[0012] In one or more embodiments, the tip structure may have a bottom surface and an inclined surface. The inclined surface of the tip structure may form an acute angle relative to the bottom surface of the tip structure.

[0013] In one or more embodiments, the acute angle can be in the range of about 30° to about 60°.

[0014] In one or more embodiments, each of the transmitting unit and the peripheral transmitting unit may include: a hole injection layer; a hole transport layer on the hole injection layer; an emission layer on the hole transport layer; an electron transport layer on the emission layer; and an electron injection layer on the electron transport layer. The hole injection layer of the transmitting unit and the hole injection layer of the peripheral transmitting unit may be spaced apart and / or separated from each other (e.g., spaced apart or separated) by a tip structure.

[0015] In one or more embodiments, the second electrode may extend further to the peripheral transmitting unit.

[0016] In one or more embodiments, the pixel defining layer may further include: a lower silicon nitride layer in contact with a side surface of the reflective conductive pattern; and a lower silicon oxide layer between the silicon nitride layer and the semiconductor circuit substrate. The lower silicon oxide layer may surround the lower silicon nitride layer (e.g., around the lower silicon nitride layer).

[0017] In one or more embodiments, the reflective conductive pattern may include: a first reflective layer; and a second reflective layer on the first reflective layer and in contact with the first electrode.

[0018] In one or more embodiments, the first electrode may include: a first-1 electrode, directly on the second reflective layer and comprising a transparent conductive oxide; and a first-2 electrode, on the first-1 electrode and comprising titanium nitride.

[0019] In one or more embodiments, the thickness of the first and second electrodes can be in the range of about 10 Å to about 20 Å.

[0020] According to one or more embodiments of this disclosure, a display device may include: a semiconductor circuit substrate including pixel circuitry; a reflective electrically conductive pattern (e.g., a reflective electrically conductive pattern) on the semiconductor circuit substrate; an emitting element including a first electrode in contact with the reflective electrically conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; a pixel defining layer on the semiconductor circuit substrate and having an emitting opening exposing the first electrode; and a peripheral emitting unit on the pixel defining layer. The pixel defining layer may include: a first-1 silicon nitride layer directly on the first electrode; a first-2 silicon nitride layer on the first-1 silicon nitride layer; and a silicon oxide layer directly on the first-2 silicon nitride layer. The first-2 silicon nitride layer includes a protrusion that protrudes further inward from the emitting opening than the first-1 silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes further inward from the emitting opening than the protrusion of the first-1 silicon nitride layer. The peripheral emitter unit can be directly on the silicon oxide layer and electrically separated from the emitter unit through a tip structure.

[0021] In one or more embodiments, the pixel defining layer may further include a lower silicon oxide layer between the first-1 silicon nitride layer and the first-2 silicon nitride layer.

[0022] In one or more embodiments, the tip structure may have a bottom surface and a sloping surface. The sloping surface of the tip structure may form an acute angle relative to the bottom surface of the tip structure. The angle between the inner surface of the protrusion of the first-1 silicon nitride layer and the top surface of the first electrode may be greater than this acute angle.

[0023] In one or more embodiments, the protrusions of the first-1 silicon nitride layer can provide a step difference. A portion of the silicon oxide layer can be on the step difference.

[0024] In one or more embodiments, each of the transmitting unit and the peripheral transmitting unit may include: a hole injection layer; a hole transport layer on the hole injection layer; an emission layer on the hole transport layer; an electron transport layer on the emission layer; and an electron injection layer on the electron transport layer. The hole injection layer of the transmitting unit and the hole injection layer of the peripheral transmitting unit may be spaced apart and / or separated from each other (e.g., spaced apart or separated) by a tip structure.

[0025] In one or more embodiments, the display device may further include an interlayer dielectric layer between the reflective conductive pattern and the first electrode. The first electrode may be in contact with a side surface of the reflective conductive pattern.

[0026] According to one or more embodiments of the present disclosure, an electronic device may include: a display device; a power module that provides power to the display device; and a processor connected to the display device.

[0027] The display device may include: a semiconductor circuit substrate including pixel circuitry; a reflective conductive pattern (e.g., a reflective conductive pattern) on the semiconductor circuit substrate; an emitting element including a first electrode in contact with the reflective conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; a pixel defining layer on the semiconductor circuit substrate and having an emitting opening exposing the first electrode; and a peripheral emitting unit on the pixel defining layer. The pixel defining layer may include: a silicon nitride layer directly on the first electrode; and a silicon oxide layer directly on the silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes further inward from the emitting opening than the silicon nitride layer. The peripheral emitting unit may be directly on the silicon oxide layer and electrically decoupled from the emitting unit by the tip structure.

[0028] In one or more embodiments, the thickness of the silicon nitride layer can be in the range of about 50 Å to about 100 Å. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the subject matter of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings: Figure 1 A block diagram of an electronic device according to one or more embodiments of the present disclosure is shown.

[0030] Figure 2 A simplified diagram of an electronic device according to one or more suitable embodiments is shown.

[0031] Figure 3 A perspective view of a display device according to one or more embodiments of the present disclosure is shown.

[0032] Figure 4 A simplified cross-sectional view of a display device according to one or more embodiments of the present disclosure is shown.

[0033] Figure 5A A cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0034] Figure 5B An enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0035] Figure 6 A simplified enlarged cross-sectional view of a transmitting element according to one or more embodiments of the present disclosure is shown.

[0036] Figures 7A to 7C A partial cross-sectional view is shown of a method of manufacturing a display panel according to one or more embodiments of the present disclosure.

[0037] Figure 8A A cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0038] Figure 8B and Figure 8C An enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0039] Figure 9A A cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0040] Figure 9B An enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure is shown.

[0041] Figures 10A to 10E A partial cross-sectional view is shown of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. Detailed Implementation

[0042] The subject matter of this disclosure can be modified in various ways and takes various suitable forms, and exemplary embodiments are shown in the accompanying drawings and described in more detail in the context of the drawings. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, but rather is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of this disclosure.

[0043] In this specification, when a component (or area, layer, part, etc.) is referred to as being "on", "connected to", or "linked to" another component (or area, layer, part, etc.), the component (or area, layer, part, etc.) may be directly arranged on the other component (or area, layer, part, etc.), directly connected to / directly linked to the other component (or area, layer, part, etc.), or at least one intermediate component may be arranged between them.

[0044] The same reference numerals indicate the same parts. Furthermore, in the drawings, the thickness, proportions, dimensions, etc., of parts may be exaggerated to effectively interpret the technical content. The term "and / or" includes one or more combinations defined by the relevant parts.

[0045] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe one or more suitable components, these components should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or portion from another element, component, region, layer, or portion. For example, without departing from the scope of this disclosure, a first element, first component, first region, first layer, or first portion may be referred to as a second element, second component, second region, second layer, or second portion; similarly, a second element, second component, second region, second layer, or second portion may also be referred to as a first element, first component, first region, first layer, or first portion. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0046] Furthermore, the terms "below," "under," "above," "upper," etc., may be used herein to describe the relationship between one component and another shown in the accompanying drawings. In addition to the orientations depicted in the drawings, relative terms are intended to also encompass different orientations.

[0047] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” used in this document are intended to also include the plural forms.

[0048] In this disclosure, it should also be understood that the terms “comprising,” “including,” “having,” etc., are used to specify the presence of the stated features, integrals, steps, operations, components, elements, or combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, components, elements, or combinations thereof.

[0049] Unless otherwise specified, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms defined in a common dictionary shall be understood to have the same meaning as in the context defined herein, and not in an ideal or overly formal sense, unless expressly defined herein.

[0050] One or more embodiments of this disclosure are described below with reference to the accompanying drawings.

[0051] The display device according to one or more embodiments can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments may include the display device, and may also include other functional modules or devices besides the display device.

[0052] Figure 1 A block diagram of an electronic device ED according to one or more embodiments of the present disclosure is shown.

[0053] refer to Figure 1 An electronic device ED according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0054] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0055] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. If the processor 12 runs an application stored in the memory 13 (for example, when the processor 12 runs an application stored in the memory 13), the display module 11 can receive one or more of image data signals and input control signals, and can process the received one or more signals to output image information through the display screen.

[0056] The power module 14 may include a power supply module such as a power adapter or battery device, and may also include a power conversion module configured or set to convert the power supplied by the power supply module to generate the power required or desired for the operation of the electronic device ED.

[0057] At least one component selected from the electronic device ED may be included in the display device according to one or more embodiments. Furthermore, one or more individual modules functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, display module 11 may be included in the display device, and processor 12, memory 13, and power module 14 may be provided within the electronic device ED in the form of other devices different from the display device.

[0058] Figure 2 A simplified diagram of an electronic device ED according to one or more embodiments is shown.

[0059] refer to Figure 2 Various suitable electronic devices employing a display device according to one or more embodiments may include: image display electronic devices, such as smartphones 10-1a, tablet computers 10-1b, laptop computers 10-1c, televisions 10-1d and / or desktop monitors 10-1e; wearable electronic devices including display modules, such as smart glasses 10-2a, head-mounted displays 10-2b and / or smartwatches 10-2c; and vehicle electronic devices 10-3 including display modules, such as dashboards, center consoles, central information displays (CIDs) arranged on vehicle dashboards, and interior mirror displays.

[0060] Figure 2 The smartphone 10-1a depicted may include a communication module and an input module such as a touch sensor, in addition to a display module. The smartphone 10-1a can process information received via its communication module or other input modules and can display the received information via the display module of a display device. Like the smartphone 10-1a, each of the tablet PC 10-1b, laptop computer 10-1c, television set 10-1d, and desktop monitor 10-1e may include a display module and an input module, and optionally may also include a communication module.

[0061] Figure 2 The smart glasses 10-2a and head-mounted display 10-2b depicted may include a display module for outputting displayed images and a reflector for reflecting the output display image to the user's eyes, through which virtual reality or augmented reality images can be provided to the user. The smartwatch 10-2c may include a biosensor as an input sensor and can provide the user with biometric information identified by the biosensor via the display module.

[0062] Figure 3 A perspective view of a display device DD according to one or more embodiments of the present disclosure is shown. Figure 4A simplified cross-sectional view of a display device DD according to one or more embodiments of the present disclosure is shown.

[0063] refer to Figure 3 The display device DD according to one or more embodiments of the present disclosure may have a rectangular shape in a plan view having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto, and the display device DD may have a circular shape, a polygonal shape, or any other suitable shape. In the following description, the third direction DR3 may be defined as a direction that intersects substantially perpendicularly to the plane defined by the first direction DR1 and the second direction DR2. In this specification, the phrase "when viewed in a plane" may define the meaning of "when viewed in the third direction DR3".

[0064] The top surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. The display surface DS can provide the user with an image generated by the display device DD.

[0065] The display surface DS may include a display area DA and a non-display area NDA surrounding (e.g., around) the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. Although the non-display area NDA may be surrounding (e.g., around) the display area DA, this disclosure is not limited thereto, and the non-display area NDA may also not be on one side of the display area DA.

[0066] Multiple pixels (PX) can be arranged in a display area (DA). Pixels (PX) can be arranged in a matrix. Each of the pixels (PX) can include pixel circuitry and an emitting element. Pixels (PX) can all produce light of the same color. In one or more embodiments of this disclosure, pixels (PX) can include multiple groups that produce light of different colors from each other.

[0067] refer to Figure 4 The display device DD may include a semiconductor circuit substrate 100, an emitting element layer 200, an encapsulation layer 300, and an optical layer 400. The display device DD may include a display area DA and a non-display area NDA surrounding (e.g., around) the display area DA, and the emitting element layer 200 may be within the display area DA. The display device DD may also include a display panel, a window on the display panel, and / or a housing below the display panel.

[0068] Figure 5A A cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. Figure 5BAn enlarged cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. Figure 6 A simplified enlarged cross-sectional view of a transmitting element 100ED according to one or more embodiments of the present disclosure is shown.

[0069] The semiconductor circuit substrate 100 may include a complementary metal-oxide-semiconductor (CMOS) wafer. The CMOS wafer may include complementary nMOSFETs (NMOS) and pMOSFETs (PMOS). Multiple pixel regions may be regularly arranged on the CMOS wafer, and pixel circuits 100PC may be located in each pixel region.

[0070] The semiconductor circuit substrate 100 may include a base substrate 110 and pixel circuitry 100PC on the base substrate 110. The base substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-on-insulator (SOI) substrate. For example, the base substrate 110 may be a monocrystalline silicon substrate, but this disclosure is not particularly limited thereto.

[0071] The pixel circuit 100PC can control the operation of the emission element included in the emission element layer 200. The pixel circuit 100PC may include at least one transistor. The pixel circuit 100PC may include a gate electrode E1 on the base substrate 110, a gate dielectric pattern GIL between the gate electrode E1 and the base substrate 110, and source / drain regions E2 and E3 on opposite sides of the gate electrode E1. The source / drain regions E2 and E3 may be impurity-doped regions formed in the base substrate 110 on opposite sides of the gate electrode E1.

[0072] The gate electrode E1 may comprise a doped semiconductor material, a conductive metal nitride (e.g., a conductive metal nitride such as titanium nitride and / or tantalum nitride), a metal (e.g., aluminum and / or tungsten), or a combination thereof. The gate dielectric pattern GIL may comprise silicon oxide. The source / drain regions E2 and E3 may each have a different conductivity than the base substrate 110. The source / drain regions E2 and E3 may each comprise an n-type impurity (e.g., phosphorus (P) and / or arsenic (As)) or a p-type impurity (e.g., boron (B)).

[0073] The base substrate 110 may have an interlayer dielectric layer 120 covering the pixel circuitry 100PC thereon. The interlayer dielectric layer 120 may include an oxide layer, a nitride layer, and / or an oxide-oxygen nitride layer. The interlayer dielectric layer 120 may have lower conductive contacts 130 (e.g., lower conductive contacts 130) correspondingly connected to the source / drain regions E2 and E3. The lower conductive contacts 130 may include a conductive material (e.g., a conductive material).

[0074] Line pattern 140 may be disposed on the underlying interlayer dielectric layer 120. Each of the lower conductive contacts 130 may be connected to a corresponding one of the line patterns 140. Line pattern 140 may include, for example, metal. Additional line patterns may be disposed between the underlying interlayer dielectric layer 120 and the line pattern 140. In one or more embodiments, each of the lower conductive contacts 130 may be electrically connected to a corresponding one of the line patterns 140 via one or more corresponding additional line patterns. Additional line patterns may include, for example, metal.

[0075] The lower interlayer dielectric layer 120 may have an upper interlayer dielectric layer 150 on which a cover line pattern 140 is disposed. The upper interlayer dielectric layer 150 may include an oxide layer, a nitride layer and / or an oxide oxynitride layer.

[0076] The emitting element layer 200 may include an emitting element 100ED electrically connected to the pixel circuit 100PC. The emitting element layer 200 may be on the semiconductor circuit substrate 100. Figure 5A A representative emitting element 100ED is depicted. In one or more embodiments, the emitting element 100ED may include an organic light-emitting element, but this disclosure is not limited thereto. The emitting element 100ED may generate a first color light, a second color light, and a third color light. The first color light, the second color light, and the third color light may be mixed to generate white light. However, this disclosure is not limited thereto, and the emitting element 100ED may generate only the first color light. The emitting region PXA may be defined to correspond to the emitting element 100ED. The emitting region PXA may be defined by an emitting aperture PDL-OP disposed in the pixel defining layer PDL.

[0077] The emitting element 100ED may include a first electrode AE, an emitting unit EL, and a second electrode CE. The first electrode AE ​​may be referred to as a pixel electrode or anode, and the second electrode CE may be referred to as a common electrode or cathode. The emitting unit EL may include a functional layer commonly disposed in the emitting region PXA and a patterned (e.g., selectively patterned) emitting layer corresponding to each of the emitting regions PXA.

[0078] The first electrode AE ​​can be on the semiconductor circuit substrate 100. The first electrode AE ​​can be connected to one of the line patterns 140 via an upper conductive contact 160 (e.g., an upper conductive contact 160) penetrating the upper interlayer dielectric layer 150. The first electrode AE ​​can be a transmissive electrode, a semi-transmissive / semi-reflective electrode, or a reflective electrode. In one or more embodiments, the first electrode AE ​​can include a reflective layer formed of magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or combinations thereof, and also includes a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, aluminum-doped zinc oxide, or combinations thereof. For example, the first electrode AE ​​can have a multilayer structure in which indium tin oxide, silver, and indium tin oxide are stacked sequentially.

[0079] A reflective conductive pattern RP (e.g., a reflective conductive pattern RP) may be on a semiconductor circuit substrate 100. The reflective conductive pattern RP may be placed on an upper interlayer dielectric layer 150 and electrically connected to a pixel circuit 100PC via an upper conductive contact 160. The reflective conductive pattern RP may have a multilayer structure in which multiple reflective layers are stacked sequentially. For example, the reflective conductive pattern RP may include a first reflective layer RP1, a second reflective layer RP2 on the first reflective layer RP1, and a third reflective layer RP3 on the second reflective layer RP2. The first reflective layer RP1 may be on the semiconductor circuit substrate 100 and connected to a corresponding line pattern 140 via an upper conductive contact 160.

[0080] The first reflective layer RP1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys including combinations thereof. For example, the first reflective layer RP1 may include titanium (Ti) and / or titanium nitride (TiN).

[0081] The second reflective layer RP2 may be formed of alloys comprising copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or combinations thereof. For example, the second reflective layer RP2 may comprise aluminum (Al).

[0082] The third reflective layer RP3 can be formed of alloys comprising copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or combinations thereof. For example, the third reflective layer RP3 may comprise titanium nitride (TiN).

[0083] The second reflective layer RP2 can substantially reflect light from the emitting element 100ED. The thickness of the second reflective layer RP2 can be greater than the thickness of each of the first reflective layer RP1 and the third reflective layer RP3. For example, the thickness of the second reflective layer RP2 can be in the range of about 500 Å to about 1000 Å, and the thickness of each of the first reflective layer RP1 and the third reflective layer RP3 can be in the range of about 80 Å to about 150 Å.

[0084] In one or more embodiments of this disclosure, the interlayer dielectric layer IML may be located on the third reflective layer RP3 positioned on top of the reflective conductive pattern RP. The interlayer dielectric layer IML may be located between the reflective conductive pattern RP and the first electrode AE. Therefore, the first electrode AE ​​may not be in direct contact with the top surface of the reflective conductive pattern RP, but may be in contact with the side surface of the reflective conductive pattern RP.

[0085] The pixel defining layer (PDL) may be on the semiconductor circuit substrate 100. The PDL may have an emission opening (PDL-OP) that exposes a portion of the first electrode AE. For example, the PDL may cover the edge of the first electrode AE. The PDL may define an emission region (PXA). The PDL may be a single-layer or multi-layer structure.

[0086] The emitter unit EL can be located on the first electrode AE. The peripheral emitter unit EL-A can be located on the pixel definition layer PDL. The second electrode CE can be placed on the emitter unit EL or on the peripheral emitter unit EL-A.

[0087] The emitting element layer 200 may further include a capping layer CPL on the second electrode CE. The capping layer CPL can be used to improve emission efficiency by utilizing the principle of constructive interference. For example, the capping layer CPL may include a material with a refractive index equal to or greater than about 1.6 relative to light having a wavelength of about 589 nm. The capping layer CPL may be an organic capping layer including organic materials, an inorganic capping layer including inorganic materials, or a composite capping layer (e.g., a composite capping layer including organic and inorganic materials). For example, the capping layer CPL may include carbocyclic compounds, heterocyclic compounds, amino-containing compounds, porphyrin derivatives, phthalocyanine derivatives, naphtholine derivatives, alkali metal complexes, alkaline earth metal complexes, or any combination thereof. The carbocyclic compounds, heterocyclic compounds, and amino-containing compounds may optionally be substituted with substituents including oxygen (O), nitrogen (N), sulfur (S), selenium (Se), silicon (Si), fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or any combination thereof.

[0088] The encapsulation layer 300 may be on the emitting element layer 200. The encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 stacked sequentially. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can protect the emitting element layer 200 from moisture and oxygen, and the organic encapsulation layer 320 can protect the emitting element layer 200 from foreign matter such as dust particles.

[0089] Optical layer 400 may be on encapsulation layer 300. Optical layer 400 may include separation layer 410, multiple color filters 420, cover layer 430 and lens pattern 440.

[0090] The materials included in the separator layer 410 are not particularly limited, as long as the material absorbs light. The separator layer 410 may be a black layer, and in one or more embodiments, the separator layer 410 may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals such as chromium, and / or oxides thereof.

[0091] Color filter 420 may correspond to an opening defined in the separating layer 410. Color filter 420 is transparent to light supplied from the emitting unit EL that overlaps with color filter 420. Color filter 420 may increase the color reproducibility of light supplied from emitting unit EL.

[0092] The overlay layer 430 may cover the color filter 420. The overlay layer 430 may include organic materials, but this disclosure is not particularly limited thereto. The lens pattern 440 may be arranged in an area that partially overlaps with the emission opening PDL-OP of the pixel defining layer PDL. However, the shape of the lens pattern 440 is not particularly limited thereto. The overlay layer 430 and the lens pattern 440 may include the same material and may have a single integral shape.

[0093] In this specification, the phrase "a component is directly on another component" means that there is no third component between the component and the other component, and that the component and the other component are in contact with each other. Furthermore, the expression "direct contact" indicates that the various surfaces of the components are in direct contact with each other.

[0094] refer to Figure 5B The pixel definition layer PDL may include a silicon nitride layer SNL directly on the first electrode AE ​​and a silicon oxide layer SOL1 directly on the silicon nitride layer SNL.

[0095] Reference Figure 5A and Figure 5BThe emitting element layer 200 may further include an interlayer dielectric layer IML between the reflective conductive pattern RP and the first electrode AE. The interlayer dielectric layer IML may comprise the same material as the silicon oxide layer SOL1. For example, the interlayer dielectric layer IML may comprise silicon oxide (e.g., SiO2). The thickness of the interlayer dielectric layer IML can be adjusted to improve light reflection efficiency. For example, the refractive index of the interlayer dielectric layer IML can be adjusted to reduce light interference, and thus the display device can improve its emission characteristics.

[0096] The first electrode AE ​​may be located around the interlayer dielectric layer IML and the reflective conductive pattern RP (e.g., around the interlayer dielectric layer IML and the reflective conductive pattern RP). The first electrode AE ​​may contact the side surface RP-SS of the reflective conductive pattern RP and is thus electrically connected to the semiconductor circuit substrate 100. The distal end of the first electrode AE ​​may be on the semiconductor circuit substrate 100.

[0097] The silicon nitride layer SNL may be present around a portion of the first electrode AE ​​(e.g., surrounding a portion of the first electrode AE). The silicon nitride layer SNL may also be present around a side surface of the first electrode AE ​​(e.g., surrounding a side surface of the first electrode AE). The silicon nitride layer SNL can be formed by the following... Figures 7A to 7C The silicon nitride layer SNL is patterned using a process (e.g., selectively patterned). The silicon nitride layer SNL may include silicon nitride (e.g., Si3N4 or SiN). x Its composition varies depending on the processing conditions.

[0098] In one or more embodiments, the thickness of the silicon nitride layer SNL can be in the range of about 50 Å to about 100 Å. The thickness of the silicon nitride layer SNL can be less than the thickness of the silicon oxide layer SOL1. Reducing the thickness of the silicon nitride layer SNL can facilitate etching in an isotropic wet etching process. Therefore, the tip structure SOL1-TP of the silicon oxide layer SOL1 can be easily formed.

[0099] In one or more embodiments, the pixel defining layer PDL may further include a lower silicon oxide layer SOL2 between the silicon oxide layer SOL1 and the semiconductor circuit substrate 100. On the semiconductor circuit substrate 100, the lower silicon oxide layer SOL2 may surround (e.g., around) the silicon nitride layer SNL. Figure 5A and Figure 5BIn this context, the silicon oxide layer SOL1 can refer to the upper silicon oxide layer SOL1. The lower silicon oxide layer SOL2 can include the same material as the upper silicon oxide layer SOL1. For example, each of the lower silicon oxide layer SOL2 and the upper silicon oxide layer SOL1 can include silicon oxide (e.g., SiO2). The upper silicon oxide layer SOL1 can be deposited after a planarization process of the lower silicon oxide layer SOL2. The maximum thickness of the lower silicon oxide layer SOL2 can be greater than the maximum thickness of the upper silicon oxide layer SOL1.

[0100] When viewed in a plane (e.g., in a planar view), the upper silicon oxide layer SOL1 defines a tip structure SOL1-TP that protrudes further inward from the emission opening PDL-OP than the silicon nitride layer SNL. For example, the tip structure SOL1-TP of the upper silicon oxide layer SOL1 can indicate a pointed portion protruding from the silicon nitride layer SNL toward the emission opening PDL-OP. The tip structure SOL1-TP can be defined as a portion that is spaced apart from and / or separated (e.g., spaced apart or separated) from the top surface of the first electrode AE ​​and does not overlap with the silicon nitride layer SNL.

[0101] In one or more embodiments, the tip structure SOL1-TP may have a bottom surface TP-DS facing the first electrode AE ​​and an inclined surface TP-IS corresponding to the side surface of the tip structure SOL1-TP. The inclined surface TP-IS of the tip structure SOL1-TP may form an inclined angle relative to the bottom surface TP-DS. The inclined angle of the inclined surface TP-IS of the tip structure SOL1-TP may form an acute angle θ1 relative to the bottom surface TP-DS. The acute angle θ1 of the tip structure SOL1-TP is in the range of about 30° to about 60°.

[0102] According to one or more embodiments of this disclosure, the peripheral emitter unit EL-A can be directly on the upper silicon oxide layer SOL1. For example, the peripheral emitter unit EL-A can be directly on the tip structure SOL1-TP of the upper silicon oxide layer SOL1. The peripheral emitter unit EL-A and the emitter unit EL can be electrically isolated from each other through the tip structure SOL1-TP. Since the peripheral emitter unit EL-A and the emitter unit EL are electrically isolated from each other, the lateral current path of the emitter element 100ED can be interrupted. Therefore, lateral leakage current can be reduced, and emission efficiency and emission uniformity can be improved.

[0103] refer to Figure 6 The emitting element 100ED may include a first electrode AE, and may also include an emitting unit EL on the first electrode AE ​​and a second electrode CE. Peripheral emitting unit (see...) Figure 5B The EL-A can have the same stacking structure as the transmitter EL.

[0104] The emitter unit EL may include a hole injection layer HIL on the first electrode AE, a hole transport layer HTL on the hole injection layer HIL, an emitter layer EML on the hole transport layer HTL, an electron transport layer ETL on the emitter layer EML, and an electron injection layer EIL on the electron transport layer ETL.

[0105] The hole injection layer HIL may include a hole injection material doped with p-type impurities. The hole injection layer HIL facilitates the injection of holes from the first electrode AE ​​into the emitter layer EML. The hole transport layer HTL may include a hole transport material doped with p-type impurities. The hole transport layer HTL can transport holes injected from the hole injection layer HIL to the emitter layer EML. The electron transport layer ETL may include an electron transport material containing metal, and the electron injection layer EIL may include an electron injection material containing metal. The electron injection layer EIL can facilitate the injection of electrons from the second electrode CE into the emitter layer EML. Similarly, the electron transport layer ETL can transport electrons injected from the electron injection layer EIL to the emitter layer EML. The emitter layer EML can generate a first color light, a second color light, and a third color light. The first color light may be red light, the second color light may be green light, and the third color light may be blue light.

[0106] refer to Figure 5B and Figure 6 The hole injection layer HIL can have a higher conductivity than other layers included in the emitter unit EL. The tip structure SOL1-TP can electrically disconnect the hole injection layer HIL on the first electrode AE ​​of the emitter unit EL from the hole injection layer HIL on the upper silicon oxide layer SOL1 of the peripheral emitter unit EL-A. Therefore, unwanted lateral leakage current between adjacent emitter elements 100ED can be reduced.

[0107] The second electrode CE on the transmitting unit EL can further extend to the peripheral transmitting unit EL-A. The second electrode CE on both the transmitting unit EL and the peripheral transmitting unit EL-A can have a single, integral shape. For example... Figure 5B As shown, when the upper silicon oxide layer SOL1 with the tip structure SOL1-TP is on the silicon nitride layer SNL, the pixel limiting layer PDL can reduce its total thickness. Therefore, the second electrode CE on the peripheral emitter unit EL-A and emitter unit EL can suppress or reduce the occurrence of disconnections caused by the thickness of the pixel limiting layer PDL.

[0108] Figures 7A to 7C A partial cross-sectional view is shown of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. In the following description, the same reference numerals are assigned to the same parts as those discussed above, and no explanation will be provided for them.

[0109] refer to Figure 7A The image shows a semiconductor circuit substrate 100 and a first electrode AE ​​around the reflective conductive pattern RP (e.g., reflective conductive pattern RP) and the interlayer dielectric layer IML on the semiconductor circuit substrate 100 (e.g., around the reflective conductive pattern RP (e.g., reflective conductive pattern RP) and the interlayer dielectric layer IML on the semiconductor circuit substrate 100). Figure 7A The diagram depicts a structure in which an initial silicon nitride layer SNL-P is disposed on a first electrode AE ​​(e.g., surrounding the first electrode AE) and a lower silicon oxide layer SOL2 is disposed on the semiconductor circuit substrate 100. Figure 7A The initial silicon nitride layer SNL-P and the lower silicon oxide layer SOL2 depicted can be planarized using processes such as chemical mechanical polishing (CMP) to form a planarization layer.

[0110] refer to Figure 7B An initial upper silicon oxide layer SOL1-P can be deposited on a planarization layer formed by each of the initial silicon nitride layer SNL-P and the lower silicon oxide layer SOL2.

[0111] refer to Figure 7C Photolithography can be used to make... Figure 7B The initial silicon nitride layer SNL-P and the initial upper silicon oxide layer SOL1-P can be patterned (e.g., selectively patterned) to form the silicon nitride layer SNL and the upper silicon oxide layer SOL1, respectively. The silicon nitride layer SNL, the upper silicon oxide layer SOL1, and the lower silicon oxide layer SOL2 can constitute the pixel definition layer PDL (see [link to documentation]). Figure 5B When patterning is performed using an isotropic wet etching process, more side etching can be formed in the silicon nitride layer SNL than in the upper silicon oxide layer SOL1. In the etching processes of the initial silicon nitride layer SNL-P and the initial upper silicon oxide layer SOL1-P, the first electrode AE ​​is not etched because the first electrode AE ​​and the pixel defining layer PDL have different etching selectivity. The etching gas for silicon oxide and silicon nitride is a fluorine-based gas, while the etching gas for the first electrode AE, which includes indium oxide, is a chlorine-based gas, and therefore the first electrode AE ​​and the pixel defining layer PDL can have different etching selectivity.

[0112] Figure 8A A cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. Figure 8B and Figure 8C An enlarged cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. In the following description, the same reference numerals are assigned to... Figure 5A and Figure 5B The components discussed herein are the same components, and no further explanation of them will be provided.

[0113] and Figure 5A compared to, Figure 8A Interlayer dielectric layers may not be required (see [link]). Figure 5A (IML). Therefore, the first electrode AE ​​can contact the top surface of the third reflective layer RP3. Furthermore, the third reflective layer RP3 can be patterned (e.g., selectively patterned) to have a cavity or groove recessed inward in its central portion.

[0114] refer to Figure 8B The pixel-defining layer PDL may also include a silicon nitride layer SNL2 in contact with the side surface RP-SS of the reflective conductive pattern RP. Figure 8B In this design, the silicon nitride layer below the first electrode AE ​​can be referred to as the lower silicon nitride layer SNL2, and the silicon nitride layer above the first electrode AE ​​can be referred to as the upper silicon nitride layer SNL1. The upper silicon nitride layer SNL1 and the lower silicon nitride layer SNL2 may comprise the same material. The first electrode AE ​​may extend inward toward the upper silicon nitride layer SNL1, and a portion of the upper silicon nitride layer SNL1 may overlap with a portion of the first electrode AE.

[0115] In one or more embodiments, the pixel defining layer PDL may further include a lower silicon oxide layer SOL2 between the upper silicon nitride layer SNL1 and the semiconductor circuit substrate 100 and around the lower silicon nitride layer SNL2 (e.g., surrounding the lower silicon nitride layer SNL2). The silicon oxide layer on the top surface of the upper silicon nitride layer SNL1 may be referred to as the upper silicon oxide layer SOL1, and the silicon oxide layer on the bottom surface of the upper silicon nitride layer SNL1 may be referred to as the lower silicon oxide layer SOL2. The upper silicon oxide layer SOL1 and the lower silicon oxide layer SOL2 may comprise the same material.

[0116] refer to Figure 8C The first electrode AE ​​may include a first electrode AE-1 directly on the reflective conductive pattern RP and a first electrode AE-2 on the first electrode AE-1. The first electrode AE-1 may include a transparent or translucent electrode layer. For example, the first electrode AE-1 may include a transparent conductive oxide selected from indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, aluminum-doped zinc oxide, or combinations thereof. The first electrode AE-2 may include a conductive metal nitride (e.g., a conductive metal nitride). For example, the first electrode AE-2 may include titanium nitride. The thickness of the first electrode AE-2 may be in the range of about 10 Å to about 20 Å.

[0117] Since electrode AE-2 is located on electrode AE-1, the top surface of electrode AE-1 and the upper silicon nitride layer SNL1 can be in non-direct contact with each other. Because electrode AE-2 protects the top surface of electrode AE-1, indium (In) deposition in electrode AE-1 due to hydrogen reduction during photolithography can be prevented or reduced. Indium (In) deposition can be suppressed to reduce indium protrusions at the interface of electrode AE-1, and thus resistance (e.g., electrical resistance) can be reduced to achieve uniform conductivity. Despite including electrode AE-2, the light reflectivity can be maintained relative to that excluding electrode AE-2. Figure 8B The same level.

[0118] Figure 9A A cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. Figure 9B An enlarged cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure is shown. Figure 9A and Figure 9B In the figures, the same reference numerals are assigned to the same figures. Figure 5A and Figure 5B The components discussed herein are the same components, and no further explanation of them will be provided.

[0119] refer to Figure 9A and Figure 9B The pixel defining layer (PDL) may include a first-1 silicon nitride layer SNL10-1 directly on the first electrode AE, a first-2 silicon nitride layer SNL10-2 on the first-1 silicon nitride layer SNL10-1, and a silicon oxide layer SOL10 directly on the first-2 silicon nitride layer SNL10-2. When viewed in a plane (e.g., in a planar view), the first-2 silicon nitride layer SNL10-2 may include a protrusion SNL-ET that protrudes more inward from the emission opening PDL-OP than the first-1 silicon nitride layer SNL10-1.

[0120] When viewed in a plane (e.g., in a planar view), the silicon oxide layer SOL10 defines a tip structure SOL10-TP that protrudes further inward from the emission opening PDL-OP compared to the protrusion SNL-ET of the first-first silicon nitride layer SNL10-1.

[0121] In this specification, the protrusion SNL-ET of the first silicon nitride layer SNL10-1 can indicate the portion that contacts the first electrode AE, while the tip structure SOL10-TP of the silicon oxide layer SOL10 can represent the portion that is spaced apart from and / or separated from the first electrode AE ​​(e.g., spaced apart or separated), does not overlap with the protrusion SNL-ET, and protrudes inward from the emission opening PDL-OP.

[0122] In one or more embodiments, the pixel defining layer PDL may further include a silicon oxide layer SOL20 between the first-first silicon nitride layer SNL10-1 and the first-second silicon nitride layer SNL10-2. The silicon oxide layer SOL20 may be located between the semiconductor circuit substrate 100 and the first-second silicon nitride layer SNL10-2. (Reference) Figure 9B The silicon oxide layer SOL10 on the first-second silicon nitride layer SNL10-2 can be referred to as the upper silicon oxide layer SOL10, and the silicon oxide layer SOL20 between the first-first silicon nitride layer SNL10-1 and the first-second silicon nitride layer SNL10-2 can be referred to as the lower silicon oxide layer SOL20. The lower silicon oxide layer SOL20 may comprise the same material as the upper silicon oxide layer SOL10.

[0123] In one or more embodiments, the protrusion SNL-ET of the first-1 silicon nitride layer SNL10-1 can provide a step difference. A portion of the protrusion SNL-ET can be bent at a right angle and can form an upward step difference. A portion of the upper silicon oxide layer SOL10 can be on the step difference and can have a shape that compensates for or fills the step difference. The peripheral emitter EL-A on the tip structure SOL10-TP of the upper silicon oxide layer SOL10 can overlap with the step difference, thereby also forming a step difference.

[0124] In one or more embodiments, the tip structure SOL10-TP may have a bottom surface TP-DS and a tilted surface TP-IS. The tilted surface TP-IS of the tip structure SOL10-TP may form an acute angle θ2 relative to the bottom surface TP-DS of the tip structure SOL10-TP, and the angle θ3 between the inner surface of the protrusion SNL-ET formed in the first-1 silicon nitride layer SNL10-1 and the top surface of the first electrode AE ​​may be greater than the acute angle θ2. For example, the angle θ3 between the inner surface of the protrusion SNL-ET formed in the first-1 silicon nitride layer SNL10-1 and the top surface of the first electrode AE ​​may be a right angle.

[0125] Figures 10A to 10E A partial cross-sectional view is shown of a method of manufacturing a display panel according to one or more embodiments of the present disclosure.

[0126] refer to Figure 10AThe image shows a semiconductor circuit substrate 100 and a first electrode AE ​​around the reflective conductive pattern RP (e.g., reflective conductive pattern RP) and the interlayer dielectric layer IML on the semiconductor circuit substrate 100 (e.g., around the reflective conductive pattern RP (e.g., reflective conductive pattern RP) and the interlayer dielectric layer IML on the semiconductor circuit substrate 100). Figure 10A The diagram depicts a structure in which an initial first-1 silicon nitride layer SNL10-1P is disposed on a first electrode AE ​​(e.g., surrounding the first electrode AE) and a lower silicon oxide layer SOL20 is disposed thereon covering the semiconductor circuit substrate 100. Figure 10A The initial first silicon nitride layer SNL10-1P and the lower silicon oxide layer SOL20 depicted in the figure can be planarized using processes such as chemical mechanical polishing (CMP) to form a planarization layer.

[0127] refer to Figure 10B , Figure 10A The initial first-1 silicon nitride layer SNL10-1P can be patterned (e.g., selectively patterned) by a photolithography process. Since one of the first electrode AE ​​and the initial first-1 silicon nitride layer SNL10-1P has a different etch selectivity than the other, only the initial first-1 silicon nitride layer SNL10-1P is etched to form the first-1 silicon nitride layer SNL10-1 through which the top surface of the first electrode is partially exposed.

[0128] refer to Figure 10C An initial 1-2 silicon nitride layer SNL10-2P can be deposited on the first-1 silicon nitride layer SNL10-1 and the lower silicon oxide layer SOL20. The thickness of the initial 1-2 silicon nitride layer SNL10-2P can range from about 50 Å to about 100 Å. The initial 1-2 silicon nitride layer SNL10-2P can have [missing information - likely referring to a specific feature or characteristic]. Figure 10B The step difference is formed by the patterning of the first-1 silicon nitride layer SNL10-1 as depicted in the figure.

[0129] refer to Figure 10D An initial silicon oxide layer SOL10-P can be deposited on top of the initial 1-2 silicon nitride layers SNL10-2P. The thickness of the initial silicon oxide layer SOL10-P can be greater than the thickness of the initial 1-2 silicon nitride layers SNL10-2P. Similarly, Figure 10C The initial 1-2 silicon nitride layers SNL10-2P can be patterned (e.g., selectively patterned) to form step differences.

[0130] refer to Figure 10E Photolithography can be used to make... Figure 10DThe initial silicon oxide layer SOL10-P and the initial 1-2 silicon nitride layer SNL10-2P can be patterned (e.g., selectively patterned) to form the silicon oxide layer SOL10 and the 1-2 silicon nitride layer SNL10-2, respectively. In an isotropic wet etching process, reducing the thickness of the 1-2 silicon nitride layer SNL10-2 can promote etching. Therefore, the tip structure SOL10-TP of the silicon oxide layer SOL10 can be easily formed.

[0131] According to embodiments of this disclosure, the pixel defining layer may include a silicon nitride layer directly on the first electrode and a silicon oxide layer directly on the silicon nitride layer. The silicon oxide layer may include a tip structure, and the peripheral emitter unit directly on the pixel defining layer may be electrically decoupled from the emitter unit on the first electrode, which can reduce lateral leakage current.

[0132] Furthermore, the total thickness of the pixel-defining layer can be reduced to allow the second electrode to have a shape extending over the peripheral emitter unit and the emitter unit. Therefore, electrical disconnection of the second electrode can be suppressed.

[0133] Although embodiments have been described with reference to several illustrative examples of this disclosure, those skilled in the art will understand that various suitable changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the following claims and their equivalents.

[0134] Therefore, the scope of this disclosure is not limited to the embodiments and examples described in more detail above, but is limited by the following claims and their equivalents.

Claims

1. A display device, comprising: Semiconductor circuit substrates, including pixel circuits; A reflective conductive pattern is present on the semiconductor circuit substrate; The emitting element includes a first electrode in contact with the reflective conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; A pixel defining layer is provided on the semiconductor circuit substrate and has an emission opening that exposes the first electrode. as well as Peripheral emission units, on the pixel defining layer, The pixel definition layer includes: A silicon nitride layer is directly on the first electrode; and A silicon oxide layer is placed directly on the silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes more inward from the emission opening compared to the silicon nitride layer. The peripheral emission unit is directly on the silicon oxide layer and is electrically separated from the emission unit through the tip structure.

2. The display device according to claim 1, further comprising: An interlayer dielectric layer is located between the reflective conductive pattern and the first electrode. The first electrode is in contact with the side surface of the reflective conductive pattern.

3. The display device according to claim 1, wherein, The silicon nitride layer surrounds the side surface of the first electrode. The first electrode is in contact with the side surface of the reflective conductive pattern, and The pixel defining layer further includes a lower silicon oxide layer between the silicon oxide layer and the semiconductor circuit substrate, the lower silicon oxide layer surrounding the side surface of the silicon nitride layer.

4. The display device according to claim 1, wherein, The thickness of the silicon nitride layer is in the range of 50 Å to 100 Å.

5. The display device according to claim 1, wherein, The tip structure has a bottom surface and an inclined surface. The inclined surface of the tip structure forms an acute angle with respect to the bottom surface of the tip structure.

6. The display device according to claim 5, wherein, The acute angle is in the range of 30° to 60°.

7. The display device according to claim 1, wherein, Each of the transmitting unit and the peripheral transmitting unit includes: Hole injection layer; Hole transport layer, on the hole injection layer; The emission layer is located on the hole transport layer; An electron transport layer, on the emitting layer; and Electron injection layer, on the electron transport layer, The hole injection layer of the transmitting unit and the hole injection layer of the peripheral transmitting unit are separated from each other by the tip structure.

8. The display device according to claim 7, wherein, The second electrode extends further onto the peripheral transmitting unit.

9. The display device according to claim 1, wherein, The pixel definition layer further includes: The lower silicon nitride layer is in contact with the side surface of the reflective conductive pattern; and A lower silicon oxide layer is located between the silicon nitride layer and the semiconductor circuit substrate, and the lower silicon oxide layer surrounds the side surface of the lower silicon nitride layer.

10. The display device according to claim 9, wherein, The reflective conductive pattern includes: First reflective layer; and A second reflective layer is placed on top of the first reflective layer and is in contact with the first electrode.

11. The display device according to claim 10, wherein, The first electrode includes: The first electrode, located directly on the second reflective layer, comprises a transparent conductive oxide; and The first-second electrode is on the first-first electrode and includes titanium nitride.

12. The display device according to claim 11, wherein, The thickness of the first and second electrodes is in the range of 10 Å to 20 Å.

13. A display device, comprising: Semiconductor circuit substrates, including pixel circuits; A reflective conductive pattern is present on the semiconductor circuit substrate; The emitting element includes a first electrode in contact with the reflective conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; A pixel defining layer is provided on the semiconductor circuit substrate and has an emission opening that exposes the first electrode. as well as Peripheral emission units, on the pixel defining layer, The pixel definition layer includes: The first-1 silicon nitride layer is directly on the first electrode; A first-second silicon nitride layer, on the first-first silicon nitride layer; and The silicon oxide layer is directly on the first and second silicon nitride layers. The first-second silicon nitride layer includes protrusions that protrude more inward from the emission opening compared to the first-first silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes further inward from the emission opening than the protrusion of the first-first silicon nitride layer. The peripheral emission unit is directly on the silicon oxide layer and is electrically separated from the emission unit through the tip structure.

14. The display device according to claim 13, wherein, The pixel defining layer also includes a lower silicon oxide layer between the first-1 silicon nitride layer and the first-2 silicon nitride layer.

15. The display device according to claim 13, wherein, The tip structure has a bottom surface and an inclined surface. The inclined surface of the tip structure forms an acute angle with respect to the bottom surface of the tip structure, and The angle between the inner surface of the protrusion of the first silicon nitride layer and the top surface of the first electrode is greater than the acute angle.

16. The display device according to claim 13, wherein, The protrusions in the first-1 silicon nitride layer provide a step difference, and A portion of the silicon oxide layer is located on the step difference.

17. The display device according to claim 13, wherein, Each of the transmitting unit and the peripheral transmitting unit includes: Hole injection layer; Hole transport layer, on the hole injection layer; The emission layer is located on the hole transport layer; An electron transport layer, on the emitting layer; and Electron injection layer, on the electron transport layer, The hole injection layer of the transmitting unit and the hole injection layer of the peripheral transmitting unit are separated from each other by the tip structure.

18. The display device according to claim 13, further comprising: An interlayer dielectric layer is located between the reflective conductive pattern and the first electrode. The first electrode is in contact with the side surface of the reflective conductive pattern.

19. Electronic devices, including: Display device; A power module that provides power to the display device; as well as The processor is connected to the display device. The display device includes: Semiconductor circuit substrates, including pixel circuits; A reflective conductive pattern is present on the semiconductor circuit substrate; The emitting element includes a first electrode in contact with the reflective conductive pattern, an emitting unit on the first electrode, and a second electrode on the emitting unit, the emitting element being on the semiconductor circuit substrate; A pixel defining layer is provided on the semiconductor circuit substrate and has an emission opening exposing the first electrode; and Peripheral emission units, on the pixel defining layer, The pixel definition layer includes: A silicon nitride layer is directly on the first electrode; and A silicon oxide layer is placed directly on the silicon nitride layer. The silicon oxide layer defines a tip structure that protrudes more inward from the emission opening compared to the silicon nitride layer. The peripheral emission unit is directly on the silicon oxide layer and is electrically separated from the emission unit through the tip structure.

20. The electronic device according to claim 19, wherein, The thickness of the silicon nitride layer is in the range of 50 Å to 100 Å.

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