Display panel and preparation method thereof

Abstract

The application provides a display panel and a preparation method thereof. The display panel comprises a substrate, a wiring layer, a planarization layer, a conductive layer and a first electrode layer. The wiring layer is located on one side of the substrate. The planarization layer is located on the side of the wiring layer away from the substrate, and the planarization layer is provided with a first via hole, and the first via hole exposes part of the wiring layer. The conductive layer comprises a first part and a second part. The first part fills the first via hole, and the second part is located on the side of the planarization layer away from the substrate. The first electrode layer is located on the side of the second part away from the substrate, and the orthographic projection of the second part on the substrate is located within the orthographic projection range of the first electrode layer on the substrate. The application improves the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are the latest generation of display technology, boasting advantages such as fast response times, thinness, and flexibility. Full-color OLED displays utilize a method of juxtaposing red, green, and blue subpixels, where red, green, and blue light-emitting materials are patterned onto a substrate using fine masking technology. However, as market demands for screen resolution increase, traditional fine masking techniques, due to process limitations, can no longer meet high-resolution requirements. This is especially true in recent years with the rise of miniature head-mounted displays for AR (Augmented Display) and VR (Virtual Reality), which place even higher demands on screen resolution. To address this trend, WOLED, coupled with a color filter layer, has emerged. Summary of the Invention

[0003] The purpose of this application is to provide a display panel and a method for manufacturing the same, so as to improve the display effect of the display panel.

[0004] To achieve the above objectives, this application provides a display panel, the display panel comprising:

[0005] substrate; The wiring layer is located on one side of the substrate; A planarization layer is located on the side of the wiring layer opposite to the substrate; the planarization layer is provided with a first via, the first via exposing a portion of the wiring layer; A conductive layer comprising a first portion and a second portion, wherein the first portion fills the first via and the second portion is located on the side of the planarization layer opposite to the substrate; The first electrode layer is located on the side of the second portion away from the substrate, and the orthographic projection of the second portion on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

[0006] In one embodiment, the display panel further includes a barrier layer located on the side of the planarization layer opposite to the substrate; the barrier layer has a second via penetrating the barrier layer in a direction perpendicular to the substrate, and the orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0007] In one embodiment, the second via is formed together with the first via.

[0008] In one embodiment, the material of the barrier layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0009] In one embodiment, the material of the wiring layer includes at least one of titanium and aluminum.

[0010] In one embodiment, the first portion fills the first via and the second via, the second portion is located on the side of the barrier layer away from the substrate, and the orthographic projection of the first portion on the substrate is within the orthographic projection range of the second portion on the substrate.

[0011] In one embodiment, the material of the conductive layer includes a conductive organic adhesive; the conductive organic adhesive includes an intrinsically conductive polymer organic adhesive.

[0012] In one embodiment, the edge of the second portion is recessed relative to the edge of the first electrode layer.

[0013] In one embodiment, the material of the first electrode layer includes at least one of titanium, aluminum, titanium nitride, and indium tin oxide.

[0014] In one embodiment, the display panel further includes a pixel definition layer that at least covers the sidewalls of the second portion and the sidewalls of the first electrode layer, and the pixel definition layer covers a portion of the surface of the first electrode layer facing away from the substrate.

[0015] In one embodiment, the material of the pixel definition layer includes an inorganic material.

[0016] In one embodiment, the material of the pixel definition layer includes at least one of silicon oxide and silicon nitride.

[0017] In one embodiment, the display panel further includes: The light-emitting layer is at least partially located on the side of the first electrode layer opposite to the substrate, and the pixel definition layer at least partially surrounds the light-emitting layer; The second electrode layer is located on the side of the light-emitting layer that is away from the substrate.

[0018] In one embodiment, the display panel further includes an auxiliary electrode layer located on the side of the second electrode layer opposite to the substrate.

[0019] In one embodiment, the light-emitting layer includes a white light-emitting layer.

[0020] In one embodiment, the auxiliary electrode layer is made of indium zinc oxide.

[0021] Secondly, this application also provides a method for manufacturing a display panel, the method comprising: Provide a substrate; A wiring layer is fabricated on one side of the substrate; A planarization layer is prepared on the side of the wiring layer opposite to the substrate; A first via is formed on the surface of the planarization layer opposite to the substrate, so that the first via exposes a portion of the wiring layer; A conductive layer is prepared such that a first portion of the conductive layer fills the first via, and a second portion of the conductive layer is located on the side of the planarization layer opposite to the substrate. A first electrode layer is prepared on the side of the second portion away from the substrate, such that the orthographic projection of the second portion on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

[0022] In one embodiment, before forming the first via on the surface of the planarization layer opposite to the substrate, the method further includes: A barrier layer is prepared on the side of the planarization layer opposite to the substrate, such that the barrier layer covers the surface of the planarization layer opposite to the substrate.

[0023] In one embodiment, the step of forming a first via on the surface of the planarization layer opposite to the substrate includes: Photoresist is coated on the side of the barrier layer away from the substrate, and the photoresist is patterned to form a photoresist pattern layer. The photoresist pattern layer is used to etch the barrier layer and the planarization layer, thereby forming a second via and a first via. The second via penetrates the barrier layer in a direction perpendicular to the substrate. Remove the photoresist pattern layer.

[0024] In one embodiment, the first portion fills the first via and the second via, and the second portion is located on the side of the barrier layer opposite to the substrate.

[0025] In one embodiment, fabricating the first electrode layer on the side of the second portion opposite to the substrate includes: A first electrode material is coated on the side of the second part that is away from the substrate; The first electrode material is patterned to form the first electrode layer, and the second part is patterned so that the orthographic projection of the second part on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

[0026] In one embodiment, after fabricating the first electrode layer on the side of the second portion opposite to the substrate, the method further includes: A pixel definition layer is prepared such that the pixel definition layer at least covers the sidewall of the second portion and the sidewall of the first electrode layer, and the pixel definition layer covers a portion of the surface of the first electrode layer facing away from the substrate; An emissive layer is prepared such that at least a portion of the emissive layer is located on the side of the first electrode layer opposite to the substrate, and the pixel definition layer at least partially surrounds the emissive layer; A second electrode layer is prepared on the side of the light-emitting layer opposite to the substrate.

[0027] In one embodiment, after fabricating the second electrode layer on the side of the light-emitting layer opposite to the substrate, the method further includes: An auxiliary electrode layer is prepared on the side of the second electrode layer that is away from the substrate.

[0028] This application proposes a display panel that exposes a wiring layer by creating a first via on a planarization layer above the wiring layer, eliminating the need to extend the wiring layer below the anode. A conductive layer then fills the first via, allowing a first portion of the conductive layer to directly contact the wiring layer for electrical signal connection, while a second portion extends above the planarization layer and electrically connects to the first electrode layer. This conductive layer, while providing electrical connection, also fills the via on the planarization layer, preventing poor overlap caused by residual organic adhesive on the wiring layer surface and improving dark spot issues. Furthermore, the conductive layer avoids insufficient filling due to overexposure when filling the via, ensuring surface smoothness and consistent light emission angle. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of the structure of a display panel provided in the prior art; Figure 2 for Figure 1 The illustrated embodiment shows a structural diagram of the display panel. Figure 3 for Figure 1 An analytical diagram of the display panel in the illustrated embodiment; Figure 4 for Figure 1 The illustrated embodiment shows a structural diagram of the display panel. Figure 5 A schematic diagram of the structure of a display panel provided in this application; Figure 6This is a schematic diagram of the structure of the display panel in one embodiment of this application; Figure 7 This is a schematic diagram of the display panel structure in another embodiment of this application; Figure 8 A flowchart illustrating a method for fabricating a display panel provided in this application; Figure 9 for Figure 8 The illustrated embodiment shows a flowchart of the manufacturing process of the display panel. Figure 10 This is a process flow diagram of the manufacturing process of the display panel in one embodiment of this application; Figure 11 This is a process flow diagram of the manufacturing process of the display panel in another embodiment of this application; Figure 12 This is a schematic diagram of the structure of a display device provided in this application.

[0031] Reference numerals: 10-substrate, 20'-transfer line layer, 20-trace layer, 30'-filler, 30-conductive layer, 31-first portion, 32-second portion, 40-planarization layer, 41-first via, 50-first electrode layer, 60-barrier layer, 61-second via, 70'-first pixel definition layer, 70-pixel definition layer, 80-light-emitting layer, 90-second electrode layer, 100-auxiliary electrode layer, 110-photoresist pattern layer, 200-display panel, 300-display device. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0033] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in the embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0034] It should be understood that in the description of the embodiments of this application, the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the scheme of the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0035] Furthermore, when an element or layer is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, the element or layer may be directly on the other element or layer, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers.

[0036] The terms First, Second, etc., are used to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or part from another element, component, region, layer, and / or part.

[0037] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] OLED (Organic Light-Emitting Diode) displays have become the mainstream next-generation display technology due to their advantages such as fast response time, thinness, and flexibility. Currently, the main full-color solutions for OLED displays include the red, green, and blue primary color juxtaposition method, which involves patterning the three light-emitting materials onto a substrate using a fine metal mask (FMM). However, with the continuous increase in market demands for screen resolution, especially the rise of miniature head-mounted displays such as AR (Augmented Reality) and VR (Virtual Reality) in recent years, traditional FMM processes are limited by issues such as thermal expansion, alignment accuracy, and aperture ratio, making it difficult to meet the requirements of ultra-high resolution (PPI). To overcome these process bottlenecks, the WOLED (White Organic Light-Emitting Diode) technology combined with a color filter layer (CF) has emerged. Because it does not require high-precision mask evaporation, it is considered an important way to achieve high-resolution displays.

[0039] Conventional glass-based WOLED displays typically employ a planar anode structure paired with a pixel definition layer (PDL). Since the anode area covered by the PDL cannot emit light, and the exposure resolution in the glass substrate manufacturing process is usually only at the micrometer level, it cannot meet the requirements for finer patterning. This directly limits the improvement of aperture ratio and results in poor overall light extraction efficiency (luminous efficacy), making it difficult to meet the stringent brightness and lifespan requirements of applications such as AR / VR.

[0040] To improve the aperture ratio, an improved display panel structure has been proposed in the prior art. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of a display panel structure provided by the prior art. After completing the via process of the planarization layer 40, this solution adds a transition layer (e.g., an ITO layer) to lead electrical signals from the metal layer at the bottom of the vias in the planarization layer 40 to the surface of the planarization layer 40. Subsequently, filler adhesive 30' is used to fill and smooth the vias in the planarization layer 40. The first electrode layer 50 (i.e., the anode layer) formed on this basis can partially extend and occupy the area above the original vias in the planarization layer 40, thereby effectively increasing the effective light-emitting area of ​​the anode within a limited pixel area and improving the aperture ratio.

[0041] However, while the aforementioned existing technologies have improved the aperture ratio to some extent, problems still exist in actual manufacturing processes and device performance. Specifically: Please continue to refer to this. Figure 1In the prior art, the filler adhesive 30' used to fill vias is typically an insulating organic adhesive (such as PSPI, photosensitive polyimide). During the filling process, this organic adhesive is prone to overflow, resulting in residue on the surface of the adapter layer 20'. This residue can lead to poor electrical signal bonding between the first electrode layer 50 (anode) and the adapter layer 20', thereby causing pixel dark spots and affecting the display effect.

[0042] To avoid surface residue, the filler adhesive 30' can be exposed and etched after filling. However, excessive exposure, causing overexposure of the organic adhesive, will result in insufficient via filling. Figure 2 As shown, overexposure causes obvious surface depressions (pits) to form in the via area, which makes the first electrode layer 50 (anode) deposited on it uneven. This unevenness can cause the dominant emission wavelength to drift and the emission angle to deviate, thus affecting the display effect of the final product.

[0043] Furthermore, in ultra-high PPI applications such as AR / VR, a Ti / Al / TiN / ITO structures are typically used for the anode to improve aperture ratio and conductivity. During the etching process to form the anode pattern, the process gas often contains chlorine (Cl2). Because organic adhesives have strong water absorption, they release trace amounts of water vapor in the high-temperature / vacuum environment of the etching chamber. This water vapor reacts with chlorine to produce corrosive substances such as hydrochloric acid, causing corrosion to the anode metal layer (especially the Al layer). Figure 3 As shown, this aluminum corrosion phenomenon causes oxidation and blackening at the edge of the anode, resulting in the anode pattern changing from a regular shape (such as a hexagon) to an irregular shape, reducing pixel size accuracy and affecting luminous efficiency.

[0044] Furthermore, during anode etching, the organic film layer beneath the anode (e.g., filler 30' and planarization layer 40) is highly susceptible to over-etching, resulting in etching loss. For example, as... Figure 4 As shown, over-etching of the organic adhesive can lead to a noticeable discontinuity on its surface. Consequently, the subsequently deposited cathode layer faces a climbing coverage problem when crossing this discontinuity. The cathode layer is typically thin and has poor step coverage, making it highly susceptible to fracture at the discontinuity edge due to stress concentration. Cathode fracture disrupts the current transmission path in that pixel area, preventing the corresponding sub-pixel from emitting light properly, resulting in dark spots and reducing the reliability and yield of the display panel.

[0045] To address the aforementioned problems, a first aspect of this application provides a display panel. Please refer to... Figure 5 , Figure 5This is a schematic diagram of the structure of a display panel according to an embodiment of this application. Specifically, the display panel 200 includes a substrate 10, a wiring layer 20, a planarization layer 40, a conductive layer 30, and a first electrode layer 50. The wiring layer 20 is located on one side of the substrate 10; the planarization layer 40 is located on the side of the wiring layer 20 away from the substrate 10, and a first via 41 is provided on the planarization layer 40, exposing a portion of the wiring layer 20; the conductive layer 30 includes a first portion 31 and a second portion 32, the first portion 31 filling the first via 41, and the second portion 32 located on the side of the planarization layer 40 away from the substrate 10; the first electrode layer 50 is located on the side of the second portion 32 away from the substrate 10, and the orthographic projection of the second portion 32 onto the substrate 10 is within the orthographic projection range of the first electrode layer 50 onto the substrate 10.

[0046] In this embodiment, the substrate 10 includes a substrate and a driving circuit layer disposed on the substrate. The substrate can be a rigid substrate made of glass, or a flexible substrate made of materials such as polyethylene terephthalate (PET) or polyimide (PI). The driving circuit layer contains a driving circuit for controlling the light emission of the light-emitting layer 80. The driving circuit layer is generally composed of inorganic film layers such as metal layers, semiconductor layers (active layers), and insulating layers. By patterning these inorganic film layers, a driving circuit for controlling the light emission of the light-emitting layer 80 can be formed. There are various ways to implement the specific circuit structure, which will not be described in detail here.

[0047] The wiring layer 20 is located above the substrate 10 and is used to transmit electrical signals to control and drive each sub-pixel light-emitting unit. In some embodiments, the wiring layer 20 may include a plurality of spaced wiring portions, each wiring portion corresponding to a corresponding sub-pixel light-emitting unit to achieve independent driving. For example, the wiring layer 20 includes three spaced wiring portions, each corresponding to three sub-pixels.

[0048] A planarization layer 40 (PLN) is located above the wiring layer 20. It covers the wiring layer 20 and provides a flat upper surface, providing a good process foundation for the fabrication of subsequent film layers. A first via 41 is provided on the surface of the planarization layer 40 facing away from the substrate 10 (i.e., the upper surface). The first via 41 exposes a portion of the wiring layer 20, thereby providing a channel for electrical connection between the wiring layer 20 and the upper conductive structure. In some embodiments, the upper surface of the planarization layer 40 may have multiple first vias 41, each exposing a corresponding wiring portion. For example, the planarization layer 40 has three first vias 41, exposing three corresponding wiring portions.

[0049] The conductive layer 30 fills the first via 41 to achieve electrical connection between the conductive layer 30 and the wiring layer 20 through direct contact. Specifically, the conductive layer 30 includes a first portion 31 and a second portion 32 connected together; wherein, the first portion 31 fills the first via 41, and its bottom is in direct contact with the wiring layer 20 to realize the transmission of electrical signals from the wiring layer 20 to the conductive layer 30; the second portion 32 is located on the side of the planarization layer 40 away from the substrate 10 (i.e., above the planarization layer 40), and its stack is disposed above the first portion 31 and electrically connected to it. From a process perspective, the second portion 32 can be the portion that overflows from the first via 41 and extends to the upper surface of the planarization layer 40 when the first portion 31 fills the first via 41, and the two are integrally formed and electrically connected. In some embodiments, the conductive layer 30 may include three first portions 31, each first portion 31 filling a corresponding first via 41; correspondingly, the conductive layer 30 also includes three second portions 32, each second portion 32 being electrically connected to a corresponding first portion 31.

[0050] The first electrode layer 50 is disposed above the second portion 32 and electrically connected to the second portion 32. The first electrode layer 50 can serve as the anode of the display panel 200 for injecting holes into the organic light-emitting layer 80. In this embodiment, the orthographic projection of the second portion 32 on the substrate 10 is within the orthographic projection range of the first electrode layer 50 on the substrate 10, that is, the edge contour of the second portion 32 falls within the edge contour of the first electrode layer 50, so that the second portion 32 forms an undercut structure relative to the first electrode layer 50. In some embodiments, the first electrode layer 50, which serves as the anode, can be spaced apart in the regions corresponding to different light-emitting units, that is, between each light-emitting unit, the first electrode layer 50 and the second portion 32 are both discontinuous structures spaced apart to avoid electrical signal crosstalk and optical crosstalk between adjacent sub-pixels.

[0051] This embodiment of the application sets up a wiring layer 20 and exposes the wiring layer 20 by creating a first via 41 in the planarization layer 40 above the wiring layer 20, eliminating the need to extend the wiring layer 20 further below the anode. Then, a conductive layer 30 fills the first via 41, allowing the first portion 31 of the conductive layer 30 to directly contact the wiring layer 20 for electrical signal connection, while the second portion 32 extends above the planarization layer 40 and is electrically connected to the first electrode layer 50. The conductive layer 30 in this application simultaneously performs the dual functions of "via filling" and "electrical signal connection," enabling the filling of vias on the planarization layer 40 while achieving electrical connection. This avoids poor overlap caused by residual organic adhesive on the surface of the transition layer, improving the dark spot problem. Furthermore, the conductive layer 30 does not suffer from insufficient filling due to overexposure when filling vias, thus ensuring surface flatness and consistent light emission angle.

[0052] Furthermore, in this application, the orthographic projection of the second portion 32 of the conductive layer 30 onto the substrate 10 lies within the orthographic projection range of the first electrode layer 50 onto the substrate 10, meaning that the second portion 32 forms a side-etched structure relative to the first electrode layer 50. This side-etched structure can serve as an isolation structure to prevent crosstalk between adjacent sub-pixels, thereby improving the display effect of the display panel.

[0053] In the above embodiments, the material of the wiring layer 20 may include at least one of titanium and aluminum. For example, the wiring layer 20 may adopt a Ti / Al / Ti stacked structure, and the thicknesses of each layer are 500 angstroms (Å), 3000 angstroms, and 750 angstroms, respectively. The material of the conductive layer 30 includes a conductive organic adhesive. Specifically, the conductive organic adhesive may include an intrinsically conductive polymer organic adhesive, such as a conductive adhesive system formed by directly dissolving or dispersing intrinsically conductive polymers such as polyaniline and polypyrrole in an aqueous resin; the conductive organic adhesive may also be a doped conductive organic adhesive, such as a conductive organic adhesive formed by dissolving a conductive material (e.g., at least one of graphite, graphene, carbon nanotubes, or metal powder) in an organic adhesive. The above-mentioned conductive organic adhesive has good flowability and can fully fill the first via 41, ensuring dense filling and reliable interface contact.

[0054] Please refer to Figure 6 In one embodiment of this application, the display panel 200 further includes a barrier layer 60. The barrier layer 60 is located on the side of the planarization layer 40 away from the substrate 10; the barrier layer 60 is provided with a second via 61, the second via 61 penetrates the barrier layer 60 in a direction perpendicular to the substrate 10, and the orthographic projection of the second via 61 on the substrate 10 at least partially overlaps with the orthographic projection of the first via 41 on the substrate 10.

[0055] In this embodiment, a barrier layer 60 is provided above the planarization layer 40, and the barrier layer 60 covers the upper surface of the planarization layer 40. The barrier layer 60 is provided with a second via 61 corresponding to the position of the first via 41, that is, the second via 61 penetrates the barrier layer 60, and its orthographic projection on the substrate 10 overlaps with the orthographic projection of the first via 41, thereby realizing the communication between the second via 61 and the first via 41.

[0056] Based on this, the first portion 31 of the conductive layer 30 is filled in the first via 41 and the second via 61, and the second portion 32 is located on the side of the barrier layer 60 away from the substrate 10. The orthographic projection of the first portion 31 on the substrate 10 is within the orthographic projection range of the second portion 32 on the substrate 10. That is, the conductive layer 30 is filled in the first via 41 and the second via 61 and extends above the barrier layer 60 to achieve electrical connection.

[0057] In some embodiments, the second via 61 can be formed together with the first via 41 using the same photolithography process. Specifically, a planarization layer 40 and a barrier layer 60 are sequentially coated over the wiring layer 20, and then the barrier layer 60 and the planarization layer 40 are etched together using a single photolithography process to form the second via 61 and the first via 41, respectively. This simultaneous fabrication method simplifies the process steps and reduces manufacturing costs.

[0058] In some embodiments, the barrier layer 60 is made of an inorganic material. Inorganic materials have high density and good resistance to etching and moisture barrier properties. For example, the material of the barrier layer 60 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0059] This embodiment of the application, by providing an inorganic barrier layer 60 above the planarization layer 40, can prevent the underlying organic film layer from being over-etched during the etching of the first electrode layer 50, thus ensuring the reliability of subsequent cathode ramping. Specifically, during the etching process to form the pattern of the first electrode layer 50 (anode), the etching gas or etching solution may cause over-etching of the underlying organic film layer (e.g., the planarization layer 40), resulting in a discontinuity on the film surface. This discontinuity makes it difficult for the subsequently deposited cathode layer to ramp and cover across this area, and it is prone to fracture due to stress concentration, causing dark spot problems. In this application, the barrier layer 60 covers the planarization layer 40. During the etching of the first electrode layer 50, the barrier layer 60 can act as an etching stop layer, preventing the etching material from eroding the planarization layer 40, thereby avoiding the formation of discontinuities caused by over-etching and ensuring the continuous coverage and electrical integrity of the subsequent cathode layer.

[0060] In addition, the inorganic barrier layer 60 in this embodiment has excellent density and water vapor barrier ability. It covers the planar layer 40 and can effectively block the water vapor in the organic film layer from being released outward, thereby preventing water vapor from reacting with chlorine to generate corrosive substances, avoiding aluminum corrosion at the anode edge, and ensuring the regularity of the anode pattern and luminous efficiency.

[0061] It should be noted that, as described in the foregoing embodiments, the conductive layer 30 can be made of a conductive organic adhesive material. Those skilled in the art may worry that since the conductive layer 30 is an organic material, it might also experience aluminum corrosion due to moisture release. This application avoids this problem by forming a side-etched structure of the second portion 32 of the conductive layer 30 relative to the first electrode layer 50. Specifically, the orthographic projection of the second portion 32 onto the substrate 10 lies within the orthographic projection range of the first electrode layer 50 onto the substrate 10. Therefore, when etching the first electrode layer 50, the conductive layer 30 (second portion 32), being an organic material, is not exposed within the etching area of ​​the first electrode layer 50. In other words, even if the edge of the conductive layer 30 (second portion 32) is over-etched to a certain extent when etching the first electrode layer 50, this actually helps to form a side-etched structure, making its edge contour more pronounced, which is beneficial for subsequent use as an isolation structure to prevent crosstalk between adjacent pixels. Therefore, the introduction of the barrier layer 60 in this application is compatible and synergistic with the use of conductive organic adhesive in the conductive layer 30. The barrier layer 60 protects the planarization layer 40 from over-etching, while the side-etching structure protects the conductive organic adhesive from exposure to the aluminum corrosion environment. The two complement each other.

[0062] In some embodiments, to achieve the side-etched structure of the conductive layer 30, the edge of the second portion 32 of the conductive layer 30 may be recessed relative to the edge of the first electrode layer 50. Furthermore, the material of the first electrode layer 50 may include at least one of titanium, aluminum, titanium nitride, and indium tin oxide. For example, the first electrode layer 50 may be a multilayer metal stack structure such as Ti / Al / TiN / ITO, with each layer having a thickness of 100 angstroms, 700 angstroms, 10 angstroms, and 150 angstroms, respectively.

[0063] Please refer to Figure 7 In one embodiment of this application, the display panel 200 further includes a pixel definition layer 70. The pixel definition layer 70 covers at least the sidewalls of the second portion 32 and the sidewalls of the first electrode layer 50, and the pixel definition layer 70 covers a portion of the surface of the first electrode layer 50 facing away from the substrate 10.

[0064] The pixel definition layer 70 (PDL) is used to define the light-emitting area of ​​each sub-pixel and to provide electrical and optical isolation between adjacent sub-pixels to prevent crosstalk between them. In this embodiment, the pixel definition layer 70 covers the sidewall surface of the first electrode layer 50 (anode) and the exposed sidewall surface of the second portion 32 in the conductive layer 30, while exposing the surface of the central region of the first electrode layer 50 to serve as the effective light-emitting area for the subsequent light-emitting layer 80 and cathode layer.

[0065] In this embodiment, the pixel definition layer 70 is made of an inorganic material. For example, the material of the pixel definition layer 70 can be at least one of silicon oxide and silicon nitride.

[0066] Please refer to Figure 1 In existing technologies, the PDL (i.e., the first pixel definition layer 7070') typically uses organic materials (such as polyimide, photosensitive resin, etc.). Because organic materials have good flowability and coating spreadability, during the PDL formation process, they easily flow into and fill the side-etched gaps between adjacent second portions 32, essentially backfilling the side-etched structure and preventing it from achieving its isolation and crosstalk prevention effect. In this application, however, the pixel definition layer 70 uses inorganic materials. Inorganic materials do not have liquid flowability during film formation, therefore they cannot flow into and fill the recessed gaps of the side-etched structure, allowing the side-etched structure to remain intact and perform its isolation function.

[0067] In the WOLED (white OLED) display panel involved in this application, the organic light-emitting layer 80 is typically formed by continuous vapor deposition across the entire surface, rather than by separately patterning red, green, and blue light-emitting layers 80 using a fine metal mask (FMM). Under this architecture, if adjacent sub-pixels are only isolated by gaps, the entire light-emitting layer 80 will extend continuously between adjacent pixel areas, causing light or electrical signals to permeate between adjacent sub-pixels, thereby generating crosstalk and degrading the display quality.

[0068] In existing technologies using organic PDL, the high fluidity of organic materials causes backfilling of the gaps between adjacent second portions 32. After depositing the light-emitting layer 80 across the entire surface of this backfilled structure, the light-emitting layer 80 becomes continuous between adjacent pixels, resulting in severe signal crosstalk. In this application, however, the inorganic PDL does not backfill the side-etched structure, which forms a physical barrier between adjacent sub-pixels. When depositing the light-emitting layer 80 across the entire surface, the material of the light-emitting layer 80 cannot cross the steep cross-section formed by the side-etched structure, thus creating a discontinuity between adjacent sub-pixels. This blocks the lateral diffusion of charge carriers between adjacent pixels, suppresses crosstalk, and improves the display effect of the display panel.

[0069] In this embodiment, the thickness of the pixel definition layer 70 can be from 3000 Å to 4000 Å. For example, the thickness of the pixel definition layer 70 can be 3000 Å, 3500 Å, or 4000 Å.

[0070] Please continue to refer to this. Figure 7 In one embodiment of this application, the display panel 200 further includes a light-emitting layer 80 and a second electrode layer 90. The light-emitting layer 80 is at least partially located on the side of the first electrode layer 50 away from the substrate 10, and the pixel definition layer 70 at least partially surrounds the light-emitting layer 80; the second electrode layer 90 is located on the side of the light-emitting layer 80 away from the substrate 10.

[0071] In this embodiment, the display panel 200 is a WOLED (white OLED) display panel 200, and the light-emitting layer 80 is formed by vapor deposition over its entire surface. Specifically, the light-emitting layer 80 is deposited over the first electrode layer 50 and the pixel definition layer 70 by vapor deposition. That is, the light-emitting layer 80 is not only located in the opening area enclosed by the pixel definition layer 70 (i.e., above the exposed first electrode layer 50), but also continuously extends to cover the upper surface of the pixel definition layer 70. In this application, the light-emitting layer 80 is a white light-emitting layer 80, and the white light emitted by it passes through the subsequent color filter layer (CF) and is filtered to produce red, green, and blue primary colors, thereby achieving full-color display.

[0072] The second electrode layer 90 is located on the side of the light-emitting layer 80 facing away from the substrate 10. The second electrode layer 90 serves as the cathode of the display panel 200, used to inject electrons into the light-emitting layer 80. In this embodiment, the material of the second electrode layer 90 may include at least one of magnesium (Mg) and silver (Ag), for example, a Mg / Ag alloy system. The second electrode layer 90 is formed above the light-emitting layer 80 by a vapor deposition process. Due to the strong directionality of the deposited particles in the vapor deposition process and the generally thin thickness of the second electrode layer 90, its step coverage capability is limited. When the second electrode layer 90 crosses the sidewall of the pixel definition layer 70, thinning, discontinuity, or even breakage of the film layer can easily occur at that location. Breakage of the second electrode layer 90 will interrupt the current transmission path in the corresponding sub-pixel area, causing the pixel to fail to emit light normally, resulting in dark spot defects.

[0073] To address the aforementioned problems, in one embodiment of this application, the display panel 200 further includes an auxiliary electrode layer 100. Please refer to [link / reference needed]. Figure 7 The auxiliary electrode layer 100 is located on the side of the second electrode layer 90 facing away from the substrate 10. In this embodiment, considering that the second electrode layer 90 (cathode) may experience breakage or local thinning at the sidewall of the pixel definition layer 70 due to limited step coverage during the evaporation process, this application further provides an auxiliary electrode layer 100 above the second electrode layer 90. The auxiliary electrode layer 100 is formed above the second electrode layer 90 by sputtering. The deposited particles of the sputtering process have higher energy and better incident direction uniformity, and its step coverage is significantly better than that of the thermal evaporation process. Therefore, the auxiliary electrode layer 100 can form a continuous cover layer on the basis of the second electrode layer 90, especially in areas where the second electrode layer 90 is broken or thinned, thereby compensating for the electrical defects caused by insufficient step coverage of the second electrode layer 90.

[0074] In this embodiment, the auxiliary electrode layer 100 is made of indium zinc oxide (IZO). IZO, as a transparent conductive oxide, has good conductivity and excellent step coverage. Furthermore, the material of the auxiliary electrode layer 100 is not limited to IZO; other conductive oxides such as indium tin oxide (ITO) can also be used, and this application does not specifically limit this.

[0075] A second aspect of this application provides a method for manufacturing a display panel. Please refer to... Figure 8 , Figure 8 This is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention. The method includes the following steps: S010, Provide a substrate; S020. Fabricate a wiring layer on one side of the substrate; S030. Prepare a planarization layer on the side of the wiring layer that is away from the substrate; S040. A first via is formed on the surface of the planarization layer facing away from the substrate, so that the first via exposes part of the wiring layer. S050. Prepare a conductive layer, such that a first portion of the conductive layer fills a first via, and a second portion of the conductive layer is located on the side of the planarization layer away from the substrate. S060. A first electrode layer is prepared on the side of the second part away from the substrate, such that the orthographic projection of the second part on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

[0076] Please refer to Figure 8 and Figure 9 In this embodiment, the substrate 10 includes a substrate and a driving circuit layer disposed on the substrate. The substrate can be a rigid substrate made of glass, or a flexible substrate made of materials such as polyethylene terephthalate (PET) or polyimide (PI). The driving circuit layer contains a driving circuit for controlling the light emission of the light-emitting layer 80. The driving circuit layer is generally composed of inorganic film layers such as metal layers, semiconductor layers (active layers), and insulating layers. By patterning these inorganic film layers, a driving circuit for controlling the light emission of the light-emitting layer 80 can be formed. There are various ways to implement the specific circuit structure, which will not be described in detail here.

[0077] A wiring layer 20 is fabricated above the substrate 10. The wiring layer 20 is used to transmit electrical signals to control and drive each sub-pixel light-emitting unit. In some embodiments, the fabricated wiring layer 20 may include a plurality of spaced wiring portions, each wiring portion corresponding to a corresponding sub-pixel light-emitting unit to achieve independent driving. For example, the fabricated wiring layer 20 includes three spaced wiring portions.

[0078] Then, a planarization layer 40 is coated across the entire surface, covering the wiring layer 20 and providing a flat upper surface for subsequent applications. A first via 41 is formed on the upper surface of the planarization layer 40 using photolithography, exposing a portion of the wiring layer 20 and providing a channel for electrical connection between the wiring layer 20 and the upper conductive structure. In some embodiments, multiple first vias 41 can be formed on the upper surface of the planarization layer 40, each exposing a corresponding wiring portion. For example, three first vias 41 are formed on the planarization layer 40, exposing three corresponding wiring portions.

[0079] Next, a conductive layer 30 is prepared on the first via 41, such that the conductive layer 30 fills the first via 41 and extends above the planarization layer 40 to achieve electrical connection. Specifically, the conductive layer 30 material is deposited over the entire surface of the first via 41 to fill the first via 41 to form the first portion 31. Deposition continues so that the conductive material extends to the upper surface of the planarization layer 40 to form the second portion 32. In this way, the first portion 31 and the second portion 32 are connected as a single structure, and the conductive layer 30 is in contact with the wiring layer 20 through the first via 41.

[0080] A first electrode layer 50 (anode) is prepared on the surface of the second portion 32 of the conductive layer 30. Specifically, the first electrode layer 50 material is deposited over the entire surface of the second portion 32, and then patterned using photolithography to form the first electrode layer 50. Simultaneously, while etching to form the first electrode layer 50, the second portion 32 of the conductive layer 30 is simultaneously patterned, causing the edge of the second portion 32 to be recessed relative to the edge of the first electrode layer 50, thereby forming a side-etched structure, i.e., the orthogonal projection of the second portion 32 on the substrate 10 is located within the orthogonal projection range of the first electrode layer 50 on the substrate 10.

[0081] This application embodiment prepares a wiring layer 20 and exposes the wiring layer 20 by forming a first via 41 in the planarization layer 40 above the wiring layer 20, eliminating the need to extend the wiring layer 20 below the anode. Then, a conductive layer 30 is prepared to fill the first via 41 while simultaneously establishing an electrical signal connection with the wiring layer 20. The conductive layer 30 in this application simultaneously performs the dual functions of "via filling" and "electrical signal connection," enabling the filling of vias on the planarization layer 40 while achieving electrical connection. This avoids poor overlap caused by residual organic adhesive on the surface of the transition layer, improving dark spot issues. Furthermore, the conductive layer 30 avoids insufficient filling due to overexposure when filling vias, ensuring surface flatness and consistent light emission angle. Simultaneously, when etching the first electrode layer 50, the second portion 32 is also simultaneously patterned, forming an inwardly recessed side-etched structure relative to the first electrode layer 50. This side-etched structure serves as an isolation structure to prevent crosstalk between adjacent sub-pixels, improving the display effect of the display panel.

[0082] Please refer to Figure 10 In one embodiment of this application, before forming the first via on the surface of the planarization layer facing away from the substrate (i.e., step S040), the method further includes: S035. A barrier layer is prepared on the side of the planarization layer away from the substrate, such that the barrier layer covers the surface of the planarization layer away from the substrate.

[0083] In this embodiment, after the planarization layer 40 is prepared, a barrier layer 60 is formed on the entire upper surface of the planarization layer 40 by a deposition process. The barrier layer 60 covers the upper surface of the planarization layer 40 to protect the underlying planarization layer 40 as an etching stop layer in subsequent etching processes and to isolate moisture. In some embodiments, the material of the barrier layer 60 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] Based on this, step S040 specifically includes: S041. Photoresist is applied to the side of the barrier layer away from the substrate, and the photoresist is patterned to form a photoresist pattern layer. S042. Using a photoresist pattern layer, the barrier layer and the planarization layer are etched to form a second via and a first via. The second via penetrates the barrier layer along the direction perpendicular to the substrate. S043, Remove the photoresist pattern layer.

[0085] In this embodiment, a layer of photoresist is coated on the upper surface of the barrier layer 60, and then the photoresist is exposed and developed to form a photoresist pattern layer 110 with an opening pattern. The position of the opening pattern corresponds to the position of the first via 41 and the second via 61 to be formed. Using the photoresist pattern layer 110 as an etching mask, the barrier layer 60 and the planarization layer 40 are etched in one step until the underlying wiring layer 20 is exposed. Through the same etching process, the second via 61 is formed in the barrier layer 60 and the first via 41 is formed in the planarization layer 40, simplifying the process and improving the via position accuracy. After completing the above etching steps, the photoresist pattern layer 110 is removed by an ashing or wet stripping process, exposing the upper surface of the barrier layer 60 and the inner wall of the second via 61 / first via 41.

[0086] Please continue to refer to this. Figure 10 After completing the above steps, proceed to step S050. That is, deposit conductive layer 30 material above the second via 61, so that the conductive layer 30 material fills the first via 41 and the second via 61 to form the first portion 31, and continue to deposit conductive layer 30 material to extend to the upper surface of the barrier layer 60 to form the second portion 32, so as to realize the electrical connection between the conductive layer 30 and the wiring layer 20.

[0087] In this embodiment, an inorganic barrier layer 60 is prepared above the planarization layer 40. This layer prevents the underlying organic film layer from being over-etched during the etching process to form the first electrode layer 50, ensuring the reliability of subsequent cathode ramping. Specifically, during the etching process to form the pattern of the first electrode layer 50 (anode), the etching gas or etching solution may cause over-etching of the underlying organic film layer (e.g., the planarization layer 40), resulting in a discontinuity on the film surface. This discontinuity makes it difficult for the subsequently deposited cathode layer to ramp and cover across this area, and it is prone to fracture due to stress concentration, causing dark spot problems. In this application, the barrier layer 60 covers the planarization layer 40. During the etching of the first electrode layer 50, the barrier layer 60 can act as an etching stop layer, preventing the etching material from eroding the planarization layer 40, thereby avoiding the formation of discontinuities caused by over-etching and ensuring continuous coverage and electrical integrity of the subsequent cathode layer.

[0088] In addition, in this embodiment, the inorganic barrier can prevent water vapor in the organic film layer from being released outward, thereby preventing water vapor from reacting with chlorine to generate corrosive substances, avoiding aluminum corrosion at the anode edge, and ensuring luminous efficiency.

[0089] In the subsequent step S060, when the second portion 32 of the first electrode layer 50 and the conductive layer 30 is simultaneously patterned and etched, the presence of the barrier layer 60 will not affect the formation of the side-etched structure. On the contrary, since the barrier layer 60 is an inorganic material, its etching rate during the etching process has a good etching selectivity ratio with that of the conductive layer 30 and the first electrode layer 50, which facilitates precise control of the etching endpoint and is more conducive to obtaining the side-etched structure.

[0090] In one embodiment of this application, the fabrication of the first electrode layer on the side of the second portion away from the substrate (step S060) specifically includes: S061. Coat the first electrode material on the side of the second part away from the substrate. S062. Pattern the first electrode material to form a first electrode layer, and simultaneously pattern the second part so that the orthographic projection of the second part on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

[0091] In this embodiment, a first electrode layer 50 material is first deposited over the entire surface of the second portion 32. Then, the first electrode layer 50 material is patterned using photolithography to form the first electrode layer 50. Simultaneously, while etching to form the first electrode layer 50, the second portion 32 of the conductive layer 30 is also patterned, causing the edge of the second portion 32 to be recessed relative to the edge of the first electrode layer 50, thereby forming a side-etched structure. That is, the orthogonal projection of the second portion 32 onto the substrate 10 lies within the orthogonal projection range of the first electrode layer 50 onto the substrate 10. This side-etched structure can serve as an isolation structure to prevent crosstalk between adjacent sub-pixels, improving the display effect of the display panel.

[0092] Please refer to Figure 11 In one embodiment of this application, after the first electrode layer is formed on the side of the second portion facing away from the substrate (step S060), the method further includes: S070. Prepare a pixel definition layer such that the pixel definition layer at least covers the sidewall of the second part and the sidewall of the first electrode layer, and the pixel definition layer covers a portion of the surface of the first electrode layer facing away from the substrate. S080. Prepare a light-emitting layer such that the light-emitting layer is at least partially located on the side of the first electrode layer away from the substrate, and the pixel definition layer at least partially surrounds the light-emitting layer. S090. A second electrode layer is prepared on the side of the light-emitting layer that is away from the substrate.

[0093] In this embodiment, the pixel definition layer 70 is formed on the first electrode layer 50, which covers the sidewall surface of the first electrode layer 50 and the exposed sidewall surface of the second part 32 in the conductive layer 30, while exposing the surface of the central region of the first electrode layer 50, so as to serve as the effective light-emitting area of ​​the subsequent light-emitting layer 80 and cathode layer.

[0094] In this application, the pixel definition layer 70 is made of inorganic material. Inorganic materials do not have liquid flow during film formation, so they cannot flow into and fill the recessed gaps of the side-etched structure, thus the side-etched structure is completely preserved.

[0095] In the WOLED display panel involved in this application, the organic light-emitting layer 80 is typically formed by continuous vapor deposition across the entire surface, rather than by separately patterning red, green, and blue light-emitting layers 80 using a fine metal mask. Under this architecture, if adjacent sub-pixels are only isolated by gaps, the entire light-emitting layer 80 would extend continuously between adjacent pixel areas, causing light or electrical signals to permeate between adjacent sub-pixels, resulting in crosstalk and degrading display quality. This application uses an inorganic PDL to prevent backfilling of the side-etched structure, thereby creating a physical barrier between adjacent sub-pixels. When the light-emitting layer 80 is deposited across the entire surface, the material of the light-emitting layer 80 cannot cross the steep cross-section formed by the side-etched structure, thus creating a discontinuity between adjacent sub-pixels, blocking the lateral diffusion of charge carriers between adjacent pixels, suppressing crosstalk, and improving the display effect of the display panel. The thickness and other parameters of the inorganic PDL are set as described above and will not be repeated here.

[0096] In this embodiment, the light-emitting layer 80 is formed by vapor deposition over its entire surface. Specifically, the light-emitting layer 80 is deposited over the first electrode layer 50 and the pixel definition layer 70 using a vapor deposition process. That is, the light-emitting layer 80 is not only located within the opening area enclosed by the pixel definition layer 70 (i.e., above the exposed first electrode layer 50), but also continuously extends to cover the upper surface of the pixel definition layer 70. In this application, the light-emitting layer 80 is a white light-emitting layer 80. The white light emitted by it passes through the subsequently disposed color filter layer (CF) and is filtered to produce red, green, and blue primary colors, thereby achieving full-color display.

[0097] Next, a second electrode layer 90 (cathode) is formed above the light-emitting layer 80 by vapor deposition of a metal material. Due to the strong directionality of the deposited particles in the vapor deposition process and the typically thin thickness of the second electrode layer 90, its step coverage capability is limited. When the second electrode layer 90 crosses the sidewall of the pixel definition layer 70, thinning, discontinuity, or even breakage of the film layer can easily occur at that point. Breakage of the second electrode layer 90 will interrupt the current transmission path in the corresponding sub-pixel area, causing the pixel to fail to emit light normally and forming a dark spot defect.

[0098] To address the aforementioned issues, after fabricating a second electrode layer on the side of the light-emitting layer facing away from the substrate, the process further includes the following steps: S100: An auxiliary electrode layer is prepared on the side of the second electrode layer away from the substrate.

[0099] Please continue to refer to this. Figure 11 Considering that the second electrode layer 90 may experience breakage or localized thinning at the sidewalls of the pixel definition layer 70 during the evaporation process due to limited step coverage, this application further prepares an auxiliary electrode layer 100 above the second electrode layer 90. The auxiliary electrode layer 100 can be formed by sputtering. The deposited particles from the sputtering process have higher energy and better incident direction uniformity, and its step coverage is significantly better than that of the thermal evaporation process. Therefore, the auxiliary electrode layer 100 can form a continuous cover layer on top of the cathode, thereby compensating for the electrical defects caused by insufficient step coverage of the cathode. The material selection for the auxiliary electrode layer 100 in this embodiment is the same as described above and will not be repeated here.

[0100] A third aspect of this application provides a display device. Please refer to... Figure 12The display device 300 includes the display panel 200 as described above. The display device can be any device with display function, such as a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a non-mobile device such as a personal computer (PC), television (TV), ATM, or self-service machine.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; The wiring layer is located on one side of the substrate; A planarization layer is located on the side of the wiring layer opposite to the substrate; The planarization layer is provided with a first via, which exposes a portion of the wiring layer; A conductive layer comprising a first portion and a second portion, wherein the first portion fills the first via and the second portion is located on the side of the planarization layer opposite to the substrate; The first electrode layer is located on the side of the second portion away from the substrate, and the orthographic projection of the second portion on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

2. The display panel according to claim 1, characterized in that: The display panel further includes a barrier layer located on the side of the planarization layer opposite to the substrate; the barrier layer is provided with a second via, the second via penetrating the barrier layer in a direction perpendicular to the substrate, and the orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate; Preferably, the second via is formed together with the first via; Preferably, the material of the barrier layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; Preferably, the material of the wiring layer includes at least one of titanium and aluminum.

3. The display panel according to claim 2, characterized in that: The first portion fills the first via and the second via, the second portion is located on the side of the barrier layer away from the substrate, and the orthographic projection of the first portion on the substrate is within the orthographic projection range of the second portion on the substrate; Preferably, the conductive layer is made of a conductive organic adhesive; the conductive organic adhesive includes an intrinsically conductive polymer organic adhesive.

4. The display panel according to claim 2, characterized in that: The edge of the second portion is recessed relative to the edge of the first electrode layer; Preferably, the material of the first electrode layer includes at least one of titanium, aluminum, titanium nitride, and indium tin oxide.

5. The display panel according to claim 1, characterized in that: The display panel further includes a pixel definition layer, which at least covers the sidewall of the second portion and the sidewall of the first electrode layer, and the pixel definition layer covers a portion of the surface of the first electrode layer facing away from the substrate; Preferably, the material of the pixel definition layer includes inorganic materials; Preferably, the material of the pixel definition layer includes at least one of silicon oxide and silicon nitride.

6. The display panel according to claim 5, characterized in that, The display panel also includes: The light-emitting layer is at least partially located on the side of the first electrode layer opposite to the substrate, and the pixel definition layer at least partially surrounds the light-emitting layer; The second electrode layer is located on the side of the light-emitting layer that is away from the substrate; Preferably, the display panel further includes an auxiliary electrode layer, which is located on the side of the second electrode layer opposite to the substrate; Preferably, the light-emitting layer includes a white light-emitting layer; Preferably, the material of the auxiliary electrode layer includes indium zinc oxide.

7. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; A wiring layer is fabricated on one side of the substrate; A planarization layer is prepared on the side of the wiring layer opposite to the substrate; A first via is formed on the surface of the planarization layer opposite to the substrate, so that the first via exposes a portion of the wiring layer; A conductive layer is prepared such that a first portion of the conductive layer fills the first via, and a second portion of the conductive layer is located on the side of the planarization layer opposite to the substrate. A first electrode layer is prepared on the side of the second portion away from the substrate, such that the orthographic projection of the second portion on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

8. The method for manufacturing a display panel according to claim 7, characterized in that: Before opening the first via on the surface of the planarization layer opposite to the substrate, the method further includes: A barrier layer is prepared on the side of the planarization layer opposite to the substrate, such that the barrier layer covers the surface of the planarization layer opposite to the substrate. Preferably, the step of forming a first via on the surface of the planarization layer opposite to the substrate includes: Photoresist is coated on the side of the barrier layer away from the substrate, and the photoresist is patterned to form a photoresist pattern layer. The photoresist pattern layer is used to etch the barrier layer and the planarization layer, thereby forming a second via and a first via. The second via penetrates the barrier layer in a direction perpendicular to the substrate. Remove the photoresist pattern layer; Preferably, the first portion fills the first via and the second via, and the second portion is located on the side of the barrier layer opposite to the substrate.

9. The method for manufacturing a display panel according to claim 8, characterized in that: The step of fabricating a first electrode layer on the side of the second portion opposite to the substrate includes: A first electrode material is coated on the side of the second part that is away from the substrate; The first electrode material is patterned to form the first electrode layer, and the second part is patterned so that the orthographic projection of the second part on the substrate is within the orthographic projection range of the first electrode layer on the substrate.

10. The method for manufacturing a display panel according to claim 9, characterized in that: After fabricating the first electrode layer on the side of the second portion opposite to the substrate, the method further includes: A pixel definition layer is prepared such that the pixel definition layer at least covers the sidewall of the second portion and the sidewall of the first electrode layer, and the pixel definition layer covers a portion of the surface of the first electrode layer facing away from the substrate; An emissive layer is prepared such that at least a portion of the emissive layer is located on the side of the first electrode layer opposite to the substrate, and the pixel definition layer at least partially surrounds the emissive layer; A second electrode layer is prepared on the side of the light-emitting layer opposite to the substrate; Preferably, after fabricating the second electrode layer on the side of the light-emitting layer opposite to the substrate, the method further includes: An auxiliary electrode layer is prepared on the side of the second electrode layer that is away from the substrate.

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