Display device and electronic device having the same

Abstract

A display device and an electronic device including the display device are disclosed. The display device includes a first transistor. The first transistor includes a first oxide semiconductor pattern including a first input region, a first output region, and a first channel region provided between the first input region and the first output region; a first gate electrode provided over the first channel region and overlapping with the first channel region in a plan view; a 1-1 gate electrode provided below the first channel region, overlapping with the first channel region in the plan view, and electrically connected to the first output region; and a 1-2 gate electrode provided below the first channel region, overlapping with the first channel region in the plan view, and electrically connected to the first output region. The 1-1 gate electrode and the 1-2 gate electrode are provided at different layers.

Description

Technical Field

[0001] The present invention relates herein to display devices and electronic devices including display devices, and to display devices having oxide transistors and electronic devices including display devices. Background Technology

[0002] The display device may include a plurality of pixels and driving circuitry (e.g., scan driving circuitry and data driving circuitry) for controlling the plurality of pixels. Each of the plurality of pixels may include a display element and pixel circuitry for controlling the display element. The pixel circuitry may include a plurality of organically connected transistors.

[0003] Multiple transistors may include silicon semiconductor or metal oxide transistors. Summary of the Invention

[0004] Some exemplary embodiments of the present invention provide display devices with improved driving characteristics.

[0005] Some exemplary embodiments of the present invention provide electronic devices including a display device.

[0006] A display device according to some exemplary embodiments of the present invention may include: a base layer; a plurality of insulating layers on the base layer; a first transistor on the base layer; and a light-emitting element electrically connected to the first transistor. The first transistor may include: a first oxide semiconductor pattern including a first input region, a first output region, and a first channel region between the first input region and the first output region; a first gate electrode above the first channel region and at least partially overlapping the first channel region in a vertical direction extending perpendicular to the top surface of the base layer; a first-1 gate electrode disposed below the first channel region and at least partially overlapping the first channel region in a vertical direction and electrically connected to the first output region; and a first-2 gate electrode below the first channel region and at least partially overlapping the first channel region in a vertical direction and electrically connected to the first output region. The first-1 gate electrode and the first-2 gate electrode may be located in different layers, such that one of the first-1 gate electrode and the first-2 gate electrode is closer to the top surface of the base layer in a vertical direction than the other of the first-1 gate electrode and the first-2 gate electrode.

[0007] The display device according to some exemplary embodiments of the present invention may further include a connection electrode on the base layer and configured to electrically connect the first output area, the first-1 gate electrode and the first-2 gate electrode.

[0008] The plurality of insulating layers may include: a first insulating layer on the first-1 gate electrode; a second insulating layer on the first insulating layer and the first-2 gate electrode, such that the first insulating layer is located vertically between the first-1 gate electrode and the second insulating layer and between the first-1 gate electrode and the first-2 gate electrode; and a third insulating layer on the second insulating layer and the first oxide semiconductor pattern.

[0009] The connection electrode can be connected to the first-1 gate electrode through a first contact hole passing through the first, second, and third insulating layers. The connection electrode can be connected to the first-2 gate electrode through a second contact hole passing through the second and third insulating layers. The connection electrode can be connected to the first output region through a third contact hole passing through the third insulating layer.

[0010] The first contact hole and the second contact hole may be spaced apart from the first gate electrode and the first oxide semiconductor pattern in one or more horizontal directions extending parallel to the top surface of the base layer.

[0011] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. A first portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first input region, and a second portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first channel region. Similarly, a first portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first output region, and a second portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first channel region.

[0012] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. A first portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first output region, and a second portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first channel region. Similarly, a first portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first input region, and a second portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first channel region.

[0013] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. The first-1 gate electrode may include a first portion that is at least partially overlapped by the first input region in the vertical direction, a second portion that is at least partially overlapped by the first channel region in the vertical direction, and a third portion that is at least partially overlapped by the first output region in the vertical direction. The first-2 gate electrode may include a first portion that is at least partially overlapped by the first input region or the first output region in the vertical direction, and a second portion that is at least partially overlapped by the first channel region in the vertical direction.

[0014] A portion of the 1-1 gate electrode and a portion of the 1-2 gate electrode may at least partially overlap each other in the vertical direction.

[0015] The first-1 gate electrode and the first-2 gate electrode may be spaced apart from each other in one or more horizontal directions extending parallel to the top surface of the base layer.

[0016] The display device according to some exemplary embodiments of the present invention may further include a second transistor on a base layer. The second transistor may include: a second oxide semiconductor pattern including a second input region, a second output region, and a second channel region between the second input region and the second output region; a second gate electrode above the second channel region and overlapping the second channel region in a vertical direction; and a second-first gate electrode below the second channel region and at least partially overlapping the second channel region in a vertical direction and electrically connected to the second gate electrode. A first vertical separation distance between the first channel region and the first-second gate electrode may be less than a second vertical separation distance between the second channel region and the second-first gate electrode.

[0017] The second-first gate electrode may be located in the same layer as the first-first gate electrode and may comprise the same material as the first-first gate electrode.

[0018] The display device according to some exemplary embodiments of the present invention may further include a connection electrode that connects the second gate electrode and the second-1st gate electrode. A plurality of insulating layers may include: a first insulating layer and a second insulating layer on the second-1st gate electrode; and a third insulating layer on the second oxide semiconductor pattern and the second gate electrode. A portion of the connection electrode may be on the third insulating layer.

[0019] The display device according to some exemplary embodiments of the present invention may further include a capacitor electrically connected between a first lower gate electrode and a first channel region defined by the first-1 gate electrode and the first-2 gate electrode.

[0020] An electronic device according to some exemplary embodiments of the present invention may include a display device and a processor for controlling the display device. The display device may include: a base layer; a plurality of insulating layers on the base layer; a first transistor on the base layer; and a light-emitting element electrically connected to the first transistor. The first transistor may include: a first oxide semiconductor pattern, which may include a first input region, a first output region, and a first channel region between the first input region and the first output region; a first gate electrode above the first channel region and at least partially overlapping the first channel region in a vertical direction extending perpendicular to the top surface of the base layer; a first-1 gate electrode below the first channel region and at least partially overlapping the first channel region in a vertical direction and electrically connected to the first output region; and a first-2 gate electrode below the first channel region and at least partially overlapping the first channel region in a vertical direction and electrically connected to the first output region. The first-1 gate electrode and the first-2 gate electrode may be located in different layers, such that one of the first-1 gate electrode and the first-2 gate electrode is closer to the top surface of the base layer in a vertical direction than the other of the first-1 gate electrode and the first-2 gate electrode.

[0021] The display device according to some exemplary embodiments of the present invention may further include a connection electrode on the base layer and configured to electrically connect the first channel region, the first-1 gate electrode and the first-2 gate electrode.

[0022] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. A first portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first input region, and a second portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first channel region. Similarly, a first portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first output region, and a second portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first channel region.

[0023] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. A first portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first output region, and a second portion of the first-1 gate electrode may be at least partially overlapped in the vertical direction by the first channel region. Similarly, a first portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first input region, and a second portion of the first-2 gate electrode may be at least partially overlapped in the vertical direction by the first channel region.

[0024] The first-1 gate electrode may be closer to the base layer in the vertical direction than the first-2 gate electrode. The first-1 gate electrode may include a first portion that is at least partially overlapped by the first input region in the vertical direction, a second portion that is at least partially overlapped by the first channel region in the vertical direction, and a third portion that is at least partially overlapped by the first output region in the vertical direction. The first-2 gate electrode may include a first portion that is at least partially overlapped by the first input region or the first output region in the vertical direction, and a second portion that is at least partially overlapped by the first channel region in the vertical direction.

[0025] The display device according to some exemplary embodiments of the present invention may further include a second transistor on a base layer. The second transistor may include: a second oxide semiconductor pattern including a second input region, a second output region, and a second channel region between the second input region and the second output region; a second gate electrode above the second channel region and overlapping the second channel region in a vertical direction; and a second-first gate electrode below the second channel region, the second-first gate electrode being at least partially overlapped by the second channel region in a vertical direction and electrically connected to the second gate electrode. A first vertical separation distance between the first channel region and the first-second gate electrode is less than a second vertical separation distance between the second channel region and the second-first gate electrode. Attached Figure Description

[0026] Figure 1A This is a block diagram of an electronic device according to some exemplary embodiments of the present invention.

[0027] Figure 1B These are schematic diagrams of electronic devices according to some exemplary embodiments of the present invention.

[0028] Figure 2 This is a block diagram of a display device according to some exemplary embodiments of the present invention.

[0029] Figure 3A This is an equivalent circuit diagram of a pixel according to some exemplary embodiments of the present invention.

[0030] Figure 3B These are some exemplary embodiments of the concept of the present invention for driving Figure 3A The waveform diagram of the driving signal of the pixel is shown.

[0031] Figure 4A This is a cross-sectional view of a display panel according to some exemplary embodiments of the present invention.

[0032] Figure 4B This is a voltage-current diagram of a first transistor according to some exemplary embodiments of the present invention.

[0033] Figure 4C This is a cross-sectional view of a display panel according to some exemplary embodiments of the present invention.

[0034] Figure 5A This is a plan view of a first transistor according to some exemplary embodiments of the present invention.

[0035] Figure 5B This is a cross-sectional view of a first transistor according to some exemplary embodiments of the present invention.

[0036] Figure 5C This is a cross-sectional view of a second transistor according to some exemplary embodiments of the present invention.

[0037] Figure 6A and Figure 6B Each of these is a cross-sectional view of a display panel according to some exemplary embodiments of the present invention.

[0038] Figure 7A This is a plan view of a first transistor according to some exemplary embodiments of the present invention.

[0039] Figure 7B This is a first cross-sectional view of a first transistor according to some exemplary embodiments of the present invention.

[0040] Figure 7C This is a second cross-sectional view of a first transistor according to some exemplary embodiments of the present invention. Detailed Implementation

[0041] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being “on”, “connected to”, or “attached to” another element, it may be directly disposed on, directly connected to, or directly attached to the other element, or may be disposed between other elements.

[0042] The same reference numerals or symbols always denote the same elements. In the drawings, the thickness, scale, and dimensions of the elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, the first element below may be referred to as the second element without departing from the scope of the inventive concept. Similarly, the second element may be referred to as the first element. Unless the context clearly indicates otherwise, the singular expressions are intended to include the plural forms as well.

[0044] Furthermore, the terms "below," "on the lower side," "above," "on the upper side," etc., may be used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0045] It will also be understood that terms such as “comprising” or “having”, when used in this specification, indicate the presence of the stated features, quantities, steps, operations, elements, components or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components or combinations thereof.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] It will be understood that elements and / or their properties (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular" or "parallel" with respect to other elements and / or their properties (e.g., structure, surface, orientation, etc.) can be "perpendicular" or "parallel" with respect to other elements and / or their properties, or can be "substantially perpendicular" or "substantially parallel" with respect to other elements and / or their properties.

[0048] Components and / or their properties that are “substantially perpendicular” or “substantially parallel” with respect to other components and / or their properties (e.g., structure, surface, orientation, etc.) will be understood as being “perpendicular” or “parallel” with respect to other components and / or their properties respectively within manufacturing tolerances and / or material tolerances, and / or having magnitude and / or angular deviations from being “perpendicular” or “parallel” with respect to other components and / or their properties respectively by an amount equal to or less than 10% (e.g., ±10% tolerance).

[0049] It will be understood that a component and / or its properties may be listed herein as “identical” to other components and / or its properties, and it will also be understood that a component and / or its properties listed herein as “identical” to other components and / or its properties may be “identical” or “substantially identical” to other components and / or its properties. A component and / or its properties that are “substantially identical” to other components and / or its properties will be understood to include components and / or its properties that are identical to other components and / or its properties within manufacturing tolerances and / or material tolerances. Components and / or its properties that are identical or substantially identical to other components and / or its properties may be structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical.

[0050] While the term “identical” may be used to describe some exemplary implementations, it should be understood that some inaccuracies may exist. Therefore, when one element or feature is described as identical to another element or feature, it should be understood that the element or feature is identical to the other element or feature within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0051] It will be understood that elements and / or characteristics described herein that are “substantially” identical to one or more other elements and / or characteristics encompass elements and / or characteristics that have a relative amplitude difference equal to or less than 10% with one or more other elements and / or characteristics. Furthermore, regardless of whether an element and / or characteristic is modified to “substantially,” it will be understood that such elements and / or characteristics should be interpreted as including said elements and / or characteristics within manufacturing or operational tolerances (e.g., ±10%).

[0052] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical value includes the value within manufacturing or operational tolerances (e.g., ±10%). Furthermore, when the terms “about” and “substantially” are used in conjunction with geometry, it means that precision of the geometry is not required, but rather that the degree of freedom of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it will be understood that such numerical value and shape should be interpreted as including the value or shape within manufacturing or operational tolerances (e.g., ±10%). When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0053] As described herein, when an operation is described as being performed "by" or "through" an additional operation, or an effect such as a structure is described as being produced "by" or "through" an additional operation, it will be understood that the operation may be performed "based on" the additional operation, and / or an effect / structure may be produced "based on" the additional operation, which may include performing the additional operation alone or in combination with other additional operations.

[0054] As described herein, elements described as generally “spaced apart” from another element, and / or “spaced apart” in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as “separated” from another element can be understood as generally isolated from another element without direct contact, and / or isolated in a particular direction without direct contact (e.g., isolated vertically without direct contact, isolated laterally or horizontally without direct contact, etc.). Similarly, elements described as generally “spaced apart” from each other, and / or “spaced apart” from each other in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as “separated” from each other can be understood as generally isolated from each other without direct contact, and / or isolated from each other without direct contact in a particular direction (e.g., isolated vertically without direct contact, isolated laterally or horizontally without direct contact, etc.). Similarly, a structure described in this paper as separating two other structures from each other can be understood as being configured to isolate the two other structures from each other without direct contact.

[0055] In the following description, some exemplary embodiments of the inventive concept are described with reference to the accompanying drawings.

[0056] Figure 1A This is a block diagram of an electronic device ED according to some exemplary embodiments of the present invention. Figure 1B This is a schematic diagram of an electronic device ED according to some exemplary embodiments of the present invention.

[0057] refer to Figure 1A An electronic device ED according to some example embodiments may include a display device 11, a processor 12, a memory 13, and a power module 14.

[0058] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0059] The memory 13 can store data information (such as a program including instructions) required for the operation of the processor 12 or the display device 11. The processor 12 can execute the application program (e.g., a program of instructions) stored in the memory 13 to cause image data signals and / or input control signals to be transmitted to the display device 11, and the display device 11 can process the received signals and output (transmit) image information through the display screen. In other words, the processor 12 can control the operation of the display device 11.

[0060] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device ED.

[0061] The processor 12, power module 14, and memory 13 described above can be included in the display device 11, or can be separated from the display device 11 as separate modules. The processor 12, power module 14, and memory 13 can be provided separately from the display device 11 within the housing that constitutes the exterior of the electronic device ED.

[0062] refer to Figure 1B Electronic devices ED according to some exemplary embodiments of the present invention may include not only typical electronic devices for information purposes (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and displays for desktop computers 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices 10_3 (such as vehicle instrument panels, central dashboards, central information displays (CIDs) mounted on the dashboard, and interior mirror displays).

[0063] Figure 2 This is a block diagram of a display device DD according to some exemplary embodiments of the present invention. In the following, reference is made to... Figure 1A The described display device 11 is described as display device DD. Furthermore, the controller 112-1, which will be described later, is part of the processor 12 described above.

[0064] The display device DD may include a controller 112-1, a display panel 141, a scan driver 142, and a data driver 143. Figure 2 In some exemplary embodiments of the illustrated embodiments, the display panel 141 is described as an emitting display panel. The emitting display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0065] The controller 112-1 converts the image signal data format to match the interface specification of the scan driver 142 and generates image data D-RGB. The controller 112-1 outputs the image data D-RGB and various control signals DCS and SCS.

[0066] Scan driver 142 receives scan control signal SCS from controller 112-1. Scan control signal SCS may include a vertical start signal to initiate operation of scan driver 142, a clock signal to determine the output timing of signals, etc. Scan driver 142 generates multiple scan signals and sequentially outputs them to corresponding scan lines SL11 to SL1n. Furthermore, scan driver 142 generates multiple transmit control signals in response to scan control signal SCS and outputs these transmit control signals to corresponding transmit signal lines EL1 to ELn.

[0067] Multiple scan signals and multiple transmit control signals in Figure 2 The signal is shown as output from a scan driver 142, but the inventive concept is not limited thereto. In some exemplary embodiments of the inventive concept, the display device DD may also include multiple scan drive circuits. Furthermore, in some exemplary embodiments of the inventive concept, the drive circuit for generating and outputting multiple scan signals may be separately configured from the drive circuit for generating and outputting multiple transmit control signals.

[0068] Data driver 143 receives data control signal DCS and image data D-RGB from controller 112-1. Data driver 143 converts the image data D-RGB into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, described later. The data signal is an analog voltage corresponding to the grayscale level of the image data D-RGB. Here, each of n and m is an integer greater than or equal to 1.

[0069] Display panel 141 may include multiple sets of scan lines. As an example, Figure 2 The first group of scan lines SL11 to SL1n is shown. The display panel 141 also includes transmit signal lines EL1 to ELn, data lines DL1 to DLm, a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, a fourth voltage line VL4, and a plurality of pixels PX.

[0070] The scan lines SL11 to SL1n of the first group can extend in the first direction DR1 and be aligned in the second direction DR2. The data lines DL1 to DLm can intersect with the scan lines SL11 to SL1n of the first group.

[0071] The first voltage line VL1 receives a first power voltage ELVSS. The second voltage line VL2 receives a second power voltage ELVDD. The second power voltage ELVDD has a higher level than the first power voltage ELVSS (e.g., a larger voltage amplitude). The third voltage line VL3 receives a reference voltage Vref (hereinafter referred to as the first voltage). The fourth voltage line VL4 receives an initialization voltage Vint (hereinafter referred to as the second voltage). The first voltage Vref has a lower level than the second power voltage ELVDD. The second voltage Vint has a lower level than the second power voltage ELVDD. In this embodiment, the second voltage Vint may have a lower level than both the first voltage Vref and the first power voltage ELVSS.

[0072] At least one of the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the fourth voltage line VL4 may include at least one of a line extending in the first direction DR1 and a line extending in the second direction DR2. The lines extending in the first direction DR1 and the lines extending in the second direction DR2 of the voltage lines can be electrically connected to each other, even if they are set as follows: Figure 5B and Figure 5C At different layers of the plurality of insulating layers 10 to 40 shown (e.g., directly on different layers).

[0073] Although reference Figure 2 A display device DD according to some exemplary embodiments has been described, but the display device DD conceived according to the present invention is not limited thereto. Depending on the configuration of the pixel circuitry, signal lines may be further added or omitted. Furthermore, the electrical connection relationship between a pixel PX and the signal lines may also be changed.

[0074] Multiple pixels (PX) can include multiple groups that generate light of different colors. For example, a pixel can include a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light-emitting elements of the red pixel, the green pixel, and the blue pixel can include emitting layers made of different materials.

[0075] The pixel circuit may include multiple transistors and at least one capacitor. At least one of the scan driver 142 and the data driver 143 may include multiple transistors formed using the same process as the pixel circuit.

[0076] Figure 3A This is an equivalent circuit diagram of pixel PXij according to some exemplary embodiments of the present invention. Figure 3B These are some exemplary embodiments of the concept of the present invention for driving Figure 3A The waveform diagram of the driving signal for pixel PXij is shown.

[0077] Figure 3A Representatively shown are scan lines SL11 to SL1n connected to the first group (see...) Figure 2 The i-th scan line SL1i is connected to multiple data lines DL1 to DLm (see...). Figure 2 Pixel PXij is the pixel of the j-th data line DLj in the second group of scan lines. Pixel PXij is connected to the i-th scan line SL2i in the second group of scan lines and to the i-th scan line SL3i in the third group of scan lines.

[0078] Including Figure 3A In some exemplary embodiments of the illustrated implementation, the pixel circuit may include first transistors T1 to fifth transistors T5, first capacitors C1 to third capacitors C3, and a light-emitting element OLED. In the inclusion of... Figure 3A In some exemplary embodiments of the illustrated exemplary implementation, the first transistor T1 through the fifth transistor T5 can be described as an n-type transistor. The first transistor T1 through the fifth transistor T5 may include a semiconductor pattern made of the same material. For example, the first transistor T1 through the fifth transistor T5 may include a metal-oxide-semiconductor.

[0079] However, the first transistor T1 through the fifth transistor T5 are not limited thereto, and at least one of them may be p-type. For example, the fifth transistor T5 may be a p-type transistor. The fifth transistor T5 may include a semiconductor pattern made of a material different from that of the first transistor T1 through the fourth transistor T4. In some exemplary embodiments of the inventive concept, the third capacitor C3 may be omitted.

[0080] Including Figure 3A In some exemplary embodiments of the illustrated exemplary implementation, each of the first transistor T1 and the second transistor T2 includes two gates, and each of the third transistor T3 to the fifth transistor T5 includes one gate, but the exemplary implementation is not limited thereto. Similar to the second transistor T2, at least one of the third transistor T3 to the fifth transistor T5 may include two gates.

[0081] Including Figure 3A In some exemplary embodiments of the illustrated exemplary implementation, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. A node connected to the gate G1-1 (hereinafter referred to as the first upper gate) of the first transistor T1 may be defined as a first node ND1, and a node connected to the source S1 of the first transistor T1 may be defined as a second node ND2. A first capacitor C1 is electrically connected between the first node ND1 and the second node ND2, and the light-emitting element OLED is electrically connected to the second node ND2.

[0082] The light-emitting element OLED includes a first electrode electrically connected to a second node ND2, a second electrode electrically connected to a first voltage line VL1 receiving a first power voltage ELVSS, and an emitting layer disposed between the first electrode and the second electrode. The light-emitting element OLED will be described in detail later.

[0083] The first transistor T1 is electrically connected between the second node ND2 and the second voltage line VL2, which receives the second power voltage ELVDD. The first transistor T1 may include a source S1 (hereinafter referred to as the first source), a drain D1 (hereinafter referred to as the first drain), a channel region (or active region), and a first upper gate G1-1 connected to the second node ND2. The first transistor T1 may also include a gate G1-2 (hereinafter referred to as the first lower gate) connected to the second node ND2. The first transistor T1 controls the driving current of the light-emitting element OLED based on the charging capacitance of the first capacitor C1.

[0084] Here, the first source S1 may include a source region of a semiconductor pattern, or a source region of a semiconductor pattern and a source electrode connected thereto. Furthermore, the first drain D1 may include a drain region of a semiconductor pattern, or a drain region of a semiconductor pattern and a drain electrode connected thereto. The source and drain regions of the first transistor T1 are located on opposite sides of the channel region of the first transistor T1. In an n-type transistor, the source region may be defined as the output region, and the drain region may be defined as the input region. The definitions of the source S1 and drain D1 described with reference to the first transistor T1 can be applied to the second transistor T2 through the fifth transistor T5. The second transistor T2 is electrically connected between the j-th data line DLj and the first node ND1. The second transistor T2 may include a second source S2 connected to the first node ND1, a second drain D2 connected to the j-th data line DLj, a channel region, and a second upper gate G2-1 connected to the i-th scan line SL1i of the first group. The second transistor T2 may also include a gate G2-2 (hereinafter referred to as the second lower gate) connected to the second upper gate G2-1. The second transistor T2 outputs a data voltage. The first capacitor C1 receives the data voltage.

[0085] The third transistor T3 is electrically connected between the first node ND1 and the third voltage line VL3 that receives the first voltage Vref. The third transistor T3 may include a third drain D3 connected to the first node ND1, a third source S3 connected to the third voltage line VL3, a channel region, and a third gate G3-1 connected to the i-th scan line SL2i of the second group.

[0086] The fourth transistor T4 is electrically connected between the second node ND2 and the fourth voltage line VL4 that receives the second voltage Vint. The fourth transistor T4 may include a fourth drain D4 connected to the second node ND2, a fourth source S4 connected to the fourth voltage line VL4, a channel region, and a fourth gate G4 connected to the i-th scan line SL3i of the third group.

[0087] The fifth transistor T5 is electrically connected between the second voltage line VL2 and the first drain D1 or the first source S1. (Including...) Figure 3A In some exemplary embodiments of the exemplary implementation shown, the fifth transistor T5 may include a fifth drain D5 connected to the second voltage line VL2, a fifth source S5 connected to the first drain D1, a channel region, and a fifth gate G5 connected to the i-th transmit signal line ELi.

[0088] The first capacitor C1 includes a first electrode E1-1 connected to the first node ND1 and a second electrode E1-2 connected to the second node ND2. The second capacitor C2 is electrically connected between the second voltage line VL2 and the second node ND2. The second capacitor C2 includes a first electrode E2-1 connected to the second voltage line VL2 and a second electrode E2-2 connected to the second node ND2. The third capacitor C3 is electrically connected between the first electrode and the second electrode of the light-emitting element OLED. The third capacitor C3 may include a first electrode E3-1 connected to the first electrode of the light-emitting element OLED and a second electrode E3-2 connected to the second electrode of the light-emitting element OLED.

[0089] Reference Figure 3A and Figure 3B A more detailed description of the operation of pixel PXij. Display device DD (see...) Figure 2 The image is displayed in each frame period. The scan lines of the first group, the second group, the third group, and the corresponding signal lines in the transmit signal line are scanned sequentially for each frame period. Figure 3B This shows a portion of the frame period.

[0090] refer to Figure 3B Each of the signals Ei, GRi, GWi, and GIi can have a high level V-HIGH for some cycles and a low level V-LOW for some cycles. When the corresponding control signal has a high level V-HIGH, each of the n-type transistors T1 to T5 described above is turned on.

[0091] During the initialization cycle IP, the third transistor T3 and the fourth transistor T4 are turned on. The first node ND1 is initialized to the first voltage Vref. The second node ND2 is initialized to the second voltage Vint. The first capacitor C1 is initialized to the difference between the first voltage Vref and the second voltage Vint. The second capacitor C2 is initialized to the difference between the second power voltage ELVDD and the second voltage Vint. The third capacitor C3 is initialized to the difference between the first power voltage ELVSS and the second voltage Vint.

[0092] During the compensation cycle CPP, the third transistor T3 and the fifth transistor T5 are turned on. A first voltage Vref can be provided to the first node ND1, and a second power voltage ELVDD can be provided to the first drain D1 of the first transistor T1, causing the first transistor T1 to turn on. When the voltage at the first source S1 of the first transistor T1 reaches the difference between the first voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. The voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1, and the first capacitor C1 can compensate for the threshold voltage (Vth) of the first transistor T1.

[0093] During the write cycle WP, the second transistor T2 is turned on. The second transistor T2 outputs a voltage (or data voltage) corresponding to the data signal DS. As a result, the voltage level corresponding to the data signal DS is charged into the first capacitor C1. The threshold voltage of the first transistor T1 is compensated for by the data signal DS being charged into the first capacitor C1. For each pixel PX (see...), Figure 2 The threshold voltage of the driving transistor can be different, and Figure 2 and Figure 3A The pixel PXij shown can supply the OLED with a current having an amplitude proportional to the data signal DS, regardless of the deviation between the threshold voltages of the driving transistors.

[0094] Subsequently, during the emission cycle, the fifth transistor T5 is turned on. The first transistor T1 provides the light-emitting element OLED with a current corresponding to the charging capacitance stored in the first capacitor C1. The light-emitting element OLED can then emit light with a brightness corresponding to the data signal DS.

[0095] Figure 4A This is a cross-sectional view of a display panel 141 according to some exemplary embodiments of the present invention. Figure 4B This is a voltage-current diagram of the first transistor T1 according to some exemplary embodiments of the present invention. Figure 4C This is a cross-sectional view of a display panel 141 according to some exemplary embodiments of the present invention.

[0096] refer to Figure 4A The display panel 141 may include a base layer BS, a circuit element layer 141-CL, a display element layer 141-OLED, and a thin film encapsulation layer TFE disposed on the base layer BS. Although not shown, the display panel 141 may also include functional layers disposed on the thin film encapsulation layer TFE, such as an anti-reflective layer or a refractive index control layer.

[0097] The circuit element layer 141-CL may include pixel circuitry. Pixel circuitry may be set in... Figure 2 In each of the plurality of pixels PX shown, the pixel circuitry may include a first transistor T1 and a second transistor T2. The first transistor T1 may be... Figure 3A The first transistor T1 in the process, and the second transistor T2 can be Figure 3A One of the second transistor T2 to the fifth transistor T5 in the process.

[0098] The first transistor T1 includes a first oxide semiconductor pattern OS1, a first upper gate G1-1, and a first lower gate G1-2, and the second transistor T2 includes a second oxide semiconductor pattern OS2, a second upper gate G2-1, and a second lower gate G2-2. Figure 4A In some exemplary embodiments of the exemplary implementation shown, the first lower gate G1-2 includes two gate electrodes disposed at different layers (e.g., the two gate electrodes are directly disposed on different layers, at different distances from the top surface BSu of the base layer BS in a third direction DR3 perpendicular to the top surface BSu such that the corresponding bottom surfaces of the two gate electrodes are at different distances from the top surface BSu in the third direction DR3, do not overlap or expose each other in one or more horizontal directions extending parallel to the top surface BSu (e.g., a first direction DR1 and a second direction DR2), any combination thereof, etc.), and the second lower gate G2-2 includes a gate electrode. The gate electrodes disposed at different layers can be directly disposed on different layers. The gate electrodes disposed at different layers can be at different distances from the top surface BSu of the base layer BS in a third direction DR3 perpendicular to the top surface BSu. The gate electrode at a different distance from the top surface BSu in the third direction DR3 can have a corresponding surface closest to the top surface BSu at a different distance from the top surface BSu. Gate electrodes disposed in different layers may have corresponding bottom surfaces at different distances from the top surface BSu of the base layer BS on a third direction DR3 perpendicular to the top surface BSu. Gate electrodes disposed in different layers may not overlap with each other and / or may be exposed to each other in one or more horizontal directions (such as the first direction DR1 and the second direction DR2) extending parallel to the top surface BSu.

[0099] The first oxide semiconductor pattern OS1 includes a first input region DA1, a first output region SA1, and a first channel region CA1 disposed between the first input region DA1 and the first output region SA1. The second oxide semiconductor pattern OS2 may be disposed on the same layer as the first oxide semiconductor pattern OS1 (e.g., directly disposed on the same layer). The second oxide semiconductor pattern OS2 includes a second input region DA2, a second output region SA2, and a second channel region CA2 disposed between the second input region DA2 and the second output region SA2.

[0100] A portion of a first oxide semiconductor pattern OS1 and a second oxide semiconductor pattern OS2 disposed on the same layer (e.g., directly disposed on the same layer) can be formed using the same photolithography process and can include the same semiconductor material. For example, the first oxide semiconductor pattern OS1 and the second oxide semiconductor pattern OS2 can include indium gallium oxide (IGO) semiconductor, indium gallium zinc oxide (IGZO) semiconductor, or indium tin gallium zinc oxide (ITGZO) semiconductor. The constituent materials of the first oxide semiconductor pattern OS1 and the second oxide semiconductor pattern OS2 are not limited to these. The crystallization state of the first oxide semiconductor pattern OS1 and the second oxide semiconductor pattern OS2 can be the same, but is not necessarily limited to this. Only one of the first oxide semiconductor pattern OS1 and the second oxide semiconductor pattern OS2 can be crystallized through partial crystallization.

[0101] The first input region DA1 and the second input region DA2, as well as the first output region SA1 and the second output region SA2, are each reduced regions of a metal-oxide-semiconductor (MOS) semiconductor and substantially correspond to conductive regions. The first channel region CA1 and the second channel region CA2 are each non-reduced regions of the MOS semiconductor and substantially correspond to the channels of a transistor.

[0102] The base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic acid-based resins, methacrylic acid-based resins, polyisoprene-based resins, ethylene-based resins, epoxy-based resins, urethane-based resins, cellulose-based resins, siloxane-based resins, polyamide-based resins, and perylene-based resins. Furthermore, the base layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. The base layer BS may include a first polyimide layer, a second polyimide layer, and an inorganic layer interposed therebetween.

[0103] Multiple insulating layers 10, 20, 30, 40, and 50 are disposed on the top surface BSu of the base layer BS. Each of the multiple insulating layers 10, 20, 30, 40, and 50 may include an inorganic layer or an organic layer. The multiple insulating layers 10, 20, 30, 40, and 50 may overlap the entire top surface BSu of the base layer BS (e.g., overlap it on a third direction DR3 extending perpendicular to the top surface BSu of the base layer BS), or may only be partially disposed on a portion of the top surface BSu of the base layer BS. A portion of the multiple insulating layers 10, 20, 30, 40, and 50 may include multiple insulating patterns patterned by etching.

[0104] The first lower gate G1-2 and the second lower gate G2-2 may be disposed on the base layer BS. Each of the first lower gate G1-2 and the second lower gate G2-2 may include a conductive pattern. For example, each of the first lower gate G1-2 and the second lower gate G2-2 may include a metal pattern. Hereinafter, the first lower gate G1-2 and the second lower gate G2-2, each including a conductive pattern, may be defined as a first lower gate electrode G1-2 and a second lower gate electrode G2-2, respectively.

[0105] The first lower gate electrode G1-2 may include multiple portions disposed at different layers (e.g., directly disposed on different layers), and thus the respective bottom surfaces of the multiple portions may be located at different distances from the top surface BSu of the base layer BS in a third direction DR3 perpendicular to the top surface BSu, exposed to each other in one or more horizontal directions parallel to the top surface BSu, or any combination thereof. As an example, Figure 4A The first lower gate electrode G1-2, comprising two parts, is shown. Figure 4A In some exemplary embodiments of the illustrated exemplary implementation, the first lower gate electrode G1-2 may include a first-1 gate electrode G1-21 and a first-2 gate electrode G1-22. Hereinafter, the second lower gate electrode G2-2 may be defined as a second-1 gate electrode G2-2.

[0106] The first-1 gate electrode G1-21 and the second-1 gate electrode G2-2 are disposed in the same layer (e.g., directly disposed on the same layer), that is, disposed on the top surface BSu of the base layer BS (e.g., directly disposed on the top surface BSu of the base layer BS). The first-1 gate electrode G1-21 and the second-1 gate electrode G2-2 can be formed by the same photolithography process. Therefore, the first-1 gate electrode G1-21 and the second-1 gate electrode G2-2 can include the same material and have the same stacked structure. In some exemplary embodiments of the present invention, at least one insulating layer may be further disposed between the top surface BSu of the base layer BS and the first-1 gate electrode G1-21, and between the top surface BSu of the base layer BS and the second lower gate electrode G2-2.

[0107] The first-1 gate electrode G1-21 may at least partially overlap with the first channel region CA1 in a plane (e.g., it may at least partially overlap with the first channel region CA1 in a third direction DR3). In the plane, the first-1 gate electrode G1-21 may include a first portion P1 that overlaps with the first input region DA1 (e.g., it may at least partially overlap with the first input region DA1 in a third direction DR3) and a second portion P2 that overlaps with the first channel region CA1 (e.g., it may at least partially overlap with the first channel region CA1 in a third direction DR3). The first portion P1 and the second portion P2 may be defined by separate portions of a single solid material defining (e.g., constituting) the first-1 gate electrode G1-21. As described herein, when an element is described as overlapping with another element, the element may be at least partially overlapped by the other element. As described herein, when an element is described as overlapping with another element "in a plane," "plane" may be understood as a plane extending parallel to the top surface BSu of the base layer BS (e.g., in the first direction DR1 and the second direction DR2). As described herein, when an element is described as overlapping another element "in a plane," the element can be understood as overlapping or being overlapped by another element in or on a plane extending parallel to the top surface BSu of the base layer BS. "Plane" can be a plane extending parallel to the top surface BSu, and in some exemplary embodiments, it can be a plane at least partially defined by the top surface BSu. In the cases where separate relative arrangements, overlaps, etc., associated with multiple elements are described individually "in a plane" herein, the separate relative arrangements, overlaps, etc., can be generally understood to be occurring on the same plane.

[0108] The second-first gate electrode G2-2 may at least partially overlap with the second channel region CA2 in a plane (e.g., it may at least partially overlap with the second channel region CA2 in a third-direction DR3). In the plane, the second-first gate electrode G2-2 may include a first portion P100 that overlaps with the second input region DA2 (e.g., it may at least partially overlap with the second input region DA2 in a third-direction DR3), a second portion P200 that overlaps with the second channel region CA2 (e.g., it may at least partially overlap with the second channel region CA2 in a third-direction DR3), and a third portion P300 that overlaps with the second output region SA2 (e.g., it may at least partially overlap with the second output region SA2 in a third-direction DR3). The first portion P100, the second portion P200, and the third portion P300 may be defined by separate portions of a single monolithic material that defines (e.g., constitutes) the second-first gate electrode G2-2.

[0109] Although not shown, a buffer layer comprising at least one inorganic layer may be disposed on the top surface BSu of the base layer BS (e.g., directly thereon). Here, the first lower gate G1-2 and the second lower gate G2-2 may be disposed on the buffer layer. The buffer layer may comprise at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The buffer layer may comprise an inorganic layer having a multilayer structure.

[0110] A first insulating layer 10 covering the first-1 gate electrode G1-21 and the second-1 gate electrode G2-2 is disposed (e.g., directly disposed on) the top surface BSu of the base layer BS. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 10 may include an inorganic layer having a multilayer structure.

[0111] The first-second gate electrode G1-22 is disposed on (e.g., directly disposed on) the first insulating layer 10 (e.g., directly disposed on the top surface 10u of the first insulating layer 10). The first-second gate electrode G1-22 can be formed by a different photolithography process than the first-first gate electrode G1-21. However, the first-second gate electrode G1-22 may include the same material as the first-first gate electrode G1-21. The first-second gate electrode G1-22 may at least partially overlap with the first channel region CA1 in a plane (e.g., may at least partially overlap with the first channel region CA1 in a third-direction DR3). In a plane, the first-second gate electrode G1-22 may include a first portion P10 that overlaps with the first output region SA1 (e.g., at least partially overlap with the first output region SA1 in a third-direction DR3), and a second portion P20 that overlaps with the first channel region CA1 (e.g., at least partially overlap with the first channel region CA1 in a third-direction DR3). Therefore, it will be understood that the first upper gate G1-1 may be above the first channel region CA1, while the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 may each be below the first channel region CA1 and at least partially overlapped by the first channel region CA1 on the third-direction DR3, such that the first channel region CA1 can be understood as being between the first upper gate G1-1 and the first lower gate G1-2 (including both the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22) on the third-direction DR3. The first portion P10 and the second portion P20 may be defined by separate portions of a single monolithic material defining (e.g., constituting) the first-2 gate electrode G1-22.

[0112] As shown, gate electrode 1-1 G1-21 and gate electrode 1-22 can be located in different layers. For example, gate electrode 1-1 G1-21 and gate electrode 1-22 can be located at different distances from the top surface BSu of the base layer BS on a third direction DR3 perpendicular to the top surface BSu. For example, gate electrode 1-1 G1-21 and gate electrode 1-22 can be located in different layers such that one of gate electrode 1-1 G1-21 and gate electrode 1-22 is closer to the top surface BSu on the third direction DR3 (which extends perpendicular to the top surface BSu) than the other of gate electrode 1-1 G1-21 and gate electrode 1-22 is on the third direction DR3. For example, the first-1 gate electrode G1-21 may have a proximal surface G1-21s (e.g., a bottom surface), which is the surface of the first-1 gate electrode G1-21 closest to the top surface BSu in the third direction DR3, and may be on or directly on the top surface BSu. The first-2 gate electrode G1-22 may have a proximal surface G1-22s (e.g., a bottom surface), which is the surface of the first-2 gate electrode G1-22 closest to the top surface BSu in the third direction DR3, and the proximal surface G1-21s of the first-1 gate electrode G1-21 may be closer to the top surface BSu in the third direction DR3 than the proximal surface G1-22s of the first-2 gate electrode G1-22. For example, the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 may not overlap each other or may expose each other in one or more horizontal directions extending parallel to the top surface BSu, said one or more horizontal directions including a first direction DR1 and a second direction DR2. It will be understood that the third direction DR3 is interchangeably referred to herein as the vertical direction extending perpendicular to the top surface BSu, and the first direction DR1 and the second direction DR2 are each interchangeably referred to herein as the horizontal direction extending parallel to the top surface BSu, wherein the first direction DR1 and the second direction DR2 may intersect each other (e.g., may extend perpendicular to each other).

[0113] A second insulating layer 20 covering the first-second gate electrodes G1-22 is disposed on the top surface 10u of the first insulating layer 10, for example, such that the first insulating layer 10 is positioned between the first-first gate electrode G1-21 and the second insulating layer 20 on the third-direction DR3, and in some exemplary embodiments, the first insulating layer 10 is positioned between the first-first gate electrode G1-21 and the first-second gate electrode G1-22 on the third-direction DR3. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The second insulating layer 20 may include an inorganic layer having a multilayer structure.

[0114] A first oxide semiconductor pattern OS1 and a second oxide semiconductor pattern OS2 are disposed on the second insulating layer 20. A third-first insulating pattern 31 is disposed on the first channel region CA1, and a third-second insulating pattern 32 is disposed on the second channel region CA2. The third-first insulating pattern 31 and the third-second insulating pattern 32 may be different portions of the third insulating layer 30. A third insulating layer 30 covering the first oxide semiconductor pattern OS1 and the second oxide semiconductor pattern OS2 may be disposed on the second insulating layer 20, and the third insulating layer 30 may then be patterned by a photolithography process. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. Each of the third-first insulating pattern 31 and the third-second insulating pattern 32 may include an inorganic layer having a multilayer structure.

[0115] A first upper gate G1-1 is disposed on the 3-1 insulating pattern 31 (e.g., directly disposed on the 3-1 insulating pattern 31), and a second upper gate G2-1 is disposed on the 3-2 insulating pattern 32 (e.g., directly disposed on the 3-2 insulating pattern 32). Each of the first upper gate G1-1 and the second upper gate G2-1 may include a conductive pattern. For example, each of the first upper gate G1-1 and the second upper gate G2-1 may include a metal pattern. Hereinafter, the first upper gate G1-1 and the second upper gate G2-1, each including a conductive pattern, may be defined as a first upper gate electrode G1-1 and a second upper gate electrode G2-1, respectively. Hereinafter, the first upper gate electrode G1-1 may be defined as a first gate electrode G1-1, and the second upper gate electrode G2-1 may be defined as a second gate electrode G2-1. The first gate electrode G1-1 may be understood to be at least partially overlapping the first channel region CA1 above the first channel region CA1 and on the third-direction DR3. The second gate electrode G2-1 can be understood as being above the second channel region CA2 and at least partially overlapping the second channel region CA2 on the third-direction DR3.

[0116] A fourth insulating layer 40 covering the first gate electrode G1-1 and the second gate electrode G2-1 is disposed on the second insulating layer 20. The fourth insulating layer 40 may include an organic or inorganic layer having a single-layer or multi-layer structure. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include an organic layer having a single-layer or multi-layer structure.

[0117] The light-emitting element OLED is disposed on the fifth insulating layer 50. The first electrode AE ​​of the light-emitting element OLED is disposed on the fifth insulating layer 50. The first electrode AE ​​can be an anode. The first electrode AE ​​is electrically connected to the first output region SA1. The first electrode AE ​​can be directly connected to the first output region SA1 through a contact hole passing through the fourth insulating layer 40 and the fifth insulating layer 50, or it can be connected to the first output region SA1 through a connecting electrode disposed between the fourth insulating layer 40 and the fifth insulating layer 50.

[0118] A pixel-defining film PDL is disposed on a fifth insulating layer 50. An opening portion OP of the pixel-defining film PDL exposes at least a portion of the first electrode AE. The opening portion OP of the pixel-defining film PDL may define an emission region LA. For example, multiple pixels PX (see...) Figure 2 The display panel 141 may be configured according to specific rules on a plane (e.g., on or in a plane extending along the first direction DR1 and the second direction DR2 and parallel to the top surface BSu of the base layer BS). An area where multiple pixels PX are disposed (e.g., an area where multiple pixels PX are disposed on or in a plane extending along the first direction DR1 and the second direction DR2 and parallel to the top surface BSu of the base layer BS) may be defined as a display area, and the display area may include multiple emitting areas LA and non-emitting areas NLA adjacent to the emitting areas LA. The non-emitting areas NLA may surround the emitting areas LA (e.g., on or in a plane extending along the first direction DR1 and the second direction DR2 and parallel to the top surface BSu of the base layer BS).

[0119] A hole control layer (HCL) can be commonly disposed in the emission region (LA) and the non-emission region (NLA), for example, such that a separate portion of a single monolithic material including the hole control layer HCL is located in the emission region LA and the non-emission region NLA. A common layer such as the hole control layer HCL can be commonly disposed in multiple pixels (PX), for example, such that a separate portion of a single monolithic material including the hole control layer HCL is located in separate corresponding pixels of the multiple pixels PX. The hole control layer HCL can include a hole transport layer and a hole injection layer.

[0120] The emitter layer EML is disposed on the hole control layer HCL. The emitter layer EML may not be disposed on a portion of the pixel-defining film PDL, and therefore a portion of the pixel-defining film PDL can be exposed on the third-party DR3. The emitter layer EML may be disposed only in the region corresponding to the opening portion OP. The emitter layer EML may be divided to be disposed on... Figure 2 Each of the multiple pixels PX shown.

[0121] Including Figure 4AIn some exemplary embodiments shown, a patterned emission layer EML is illustrated as an example; however, the emission layer EML can be commonly disposed across multiple pixels PX. The commonly disposed emission layer EML can generate white or blue light. Furthermore, the emission layer EML can have a multi-layered structure.

[0122] An electronic control layer (ECL) is disposed on the emitter layer (EML). The ECL may include an electron transport layer and an electron injection layer. A second electrode (CE) is disposed on the ECL. The ECL and the second electrode (CE) are commonly disposed within multiple pixels (PX).

[0123] A thin-film encapsulation layer (TFE) is disposed on the second electrode (CE). The thin-film encapsulation layer (TFE) is commonly disposed on... Figure 2 Among the multiple pixels PX shown. Including Figure 4A In some exemplary embodiments of the exemplary implementations shown, the thin-film encapsulation layer TFE directly covers the second electrode CE (e.g., is in direct contact with the second electrode CE). In some exemplary embodiments of the present invention, a capping layer that directly covers the second electrode CE may be further provided. In some exemplary embodiments of the present invention, the stacked structure of the light-emitting element OLED may include... Figure 4A The structure shown is an inverted structure.

[0124] The thin-film encapsulation layer (TFE) comprises at least an inorganic layer or an organic layer. In some exemplary embodiments of the present invention, the TFE may comprise two inorganic layers and an organic layer interposed therebetween. In some exemplary embodiments of the present invention, the TFE may comprise a plurality of alternately stacked inorganic layers and a plurality of organic layers.

[0125] The first lower gate electrode G1-2 (also referred to herein as the first lower gate G1-2) may define a first parasitic capacitor C-S1 together with the first channel region CA1. In some exemplary embodiments, the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 may each be electrically connected to the first output region SA1. The first parasitic capacitor C-S1 is defined as the sum of the first-1 parasitic capacitor CD1 defined by the first-1 gate electrode G1-21 and the first channel region CA1 and the first-2 parasitic capacitor CD2 defined by the first-2 gate electrode G1-22 and the first channel region CA1. Therefore, the first parasitic capacitor C-S1 may define a capacitor electrically connected between the first lower gate electrode G1-2 and the first channel region CA1.

[0126] The capacitance of the first-1 parasitic capacitor CD1 can be determined by the overlapping region between the second portion P2 of the first-1 gate electrode G1-21 and the first channel region CA1 (e.g., the overlapping region between corresponding portions of them overlapping each other on a third direction DR3 extending perpendicular to the top surface BSu, wherein the overlapping region may be a region in or on a plane extending parallel to the top surface BSu). The capacitance of the first-2 parasitic capacitor CD2 can be determined by the overlapping region between the second portion P20 of the first-2 gate electrode G1-22 and the first channel region CA1 (e.g., the overlapping region between corresponding portions of them overlapping each other on a third direction DR3 extending perpendicular to the top surface BSu, wherein the overlapping region may be a region in or on a plane extending parallel to the top surface BSu). For example, as Figure 4A As shown, the capacitance of the first-1 parasitic capacitor CD1 can be determined by an overlapping region: the overlapping region is the area on the third direction DR3 between the corresponding portions of the first-1 gate electrode G1-21 and the first channel region CA1 in a plane extending parallel to the top surface BSu, and the capacitance of the first-2 parasitic capacitor CD2 can be determined by an overlapping region: the overlapping region is the area on the third direction DR3 between the corresponding portions of the first-2 gate electrode G1-22 and the first channel region CA1 in a plane extending parallel to the top surface BSu.

[0127] When the overlap between the second portion P2 of the first-1 gate electrode G1-21 and the first channel region CA1 increases, the capacitance of the first-1 parasitic capacitor CD1 increases, and when the overlap between the second portion P20 of the first-2 gate electrode G1-22 and the first channel region CA1 decreases, the capacitance of the first-2 parasitic capacitor CD2 decreases. Here, the capacitance of the first parasitic capacitor C-S1 decreases. The overlap between the second portion P20 of the first-2 gate electrode G1-22 and the first channel region CA1 has a more significant effect on the increase and decrease of the capacitance of the first parasitic capacitor C-S1 than the overlap between the second portion P2 of the first-1 gate electrode G1-21 and the first channel region CA1. This is because the first-2 gate electrode G1-22 is closer to the first channel region CA1 than the first-1 gate electrode G1-21 (e.g., closer to the first channel region CA1 on the third-direction DR3 than the first-1 gate electrode G1-21).

[0128] As the overlap between the second portions P2 and P20 and the first channel region CA1 increases, the capacitance of the first parasitic capacitor C-S1 increases. The overlap between the second portion P2 of the first-1 gate electrode G1-21 and the first channel region CA1 is the same as the overlap between the second portion P20 of the first-2 gate electrode G1-22 and the first channel region CA1, and the capacitance of the first-2 parasitic capacitor CD2 is greater than the capacitance of the first-1 parasitic capacitor CD1. This is because the first-2 gate electrode G1-22 is closer to the first channel region CA1 than the first-1 gate electrode G1-21 (e.g., closer to the first channel region CA1 on the third-direction DR3 than the first-1 gate electrode G1-21).

[0129] The second-first gate electrode G2-2 may define a second parasitic capacitor C-S2 together with the second channel region CA2. The capacitance of the second parasitic capacitor C-S2 is smaller than the capacitance of the first parasitic capacitor C-S1. The second-first gate electrode G2-2 is disposed on the underside of the first insulating layer 10 (e.g., between the top surface BSu of the first insulating layer 10 and the base layer BS) and defines a second parasitic capacitor C-S2 with relatively low capacitance. For example, the second upper gate electrode G2-1 may overlap the second channel region CA2 above and on the third-direction DR3, and the second-first gate electrode G2-2 may be at least partially overlapped by the second channel region CA2 below and on the third-direction DR3. In some exemplary embodiments, the first separation distance SD1 between the first channel region CA1 and the first-second gate electrode G1-22 on the third-direction DR3 may be smaller than the second separation distance SD2 between the second channel region CA2 and the second-first gate electrode G2-2 on the third-direction DR3. If the second-first gate electrode G2-2 is disposed on the upper side of the first insulating layer 10 and is disposed on the same layer as the first-second gate electrode G1-22 (e.g., directly disposed on the same layer), the capacitance of the second parasitic capacitor C-S2 increases. However, when the capacitance of the second parasitic capacitor C-S2 increases, a very large load is applied to the second transistor T2 with the dual-gate structure, which adversely affects the operation of the switching transistor.

[0130] Figure 4B The diagram shows a first curve G1, a second curve G2, and a third curve G3. Curves G1, G2, and G3 are voltage (Vgs)-current (Ids) curves of the driving transistor. The threshold voltage (Vth) of the voltage (Vgs)-current (Ids) curve can be approximately 0.64V.

[0131] The third curve G3 is... Figure 4AThe voltage (Vgs)-current (Ids) curve of the first transistor T1 is shown. Conversely, the driving transistor with the voltage (Vgs)-current (Ids) curves in the first curve G1 and the second curve G2 has the same voltage (Vgs)-current (Ids) curves as shown in the second curve G2. Figure 4A The first transistor T1 in the diagram has a slightly different structure. In the following text, compared to... Figure 4A The first transistor T1 is used to describe the driving transistor having voltage (Vgs)-current (Ids) curves in the first graph G1 and the second graph G2.

[0132] In the driving transistor of the first curve G1, with Figure 4A Unlike the first transistor T1, the first lower gate G1-2 only includes the first-1 gate electrode G1-21, excluding the first-2 gate electrode G1-22. However, the first-1 gate electrode G1-21 completely overlaps with the first channel region CA1 (e.g., it is completely overlapped by the first channel region CA1 on the third-direction DR3). This is the same as or substantially the same as the case where the second-1 gate electrode G2-2 completely overlaps with the second channel region CA2 (e.g., it is completely overlapped by the second channel region CA2 on the third-direction DR3). The first-1 gate electrode G1-21 can include three parts like the second-1 gate electrode G2-2.

[0133] In the driving transistor of the second curve G2, with Figure 4A Unlike the first transistor T1, the first lower gate G1-2 only includes the first-2 gate electrode G1-22, excluding the first-1 gate electrode G1-21. Here, the first-2 gate electrode G1-22 completely overlaps with the first channel region CA1 (e.g., it is overlapped by the entire first channel region CA1 on the third-direction DR3). The first-2 gate electrode G1-22 may consist of three parts, just like the second-1 gate electrode G2-2.

[0134] According to the first curve G1, the slope of this curve is large in the subthreshold region. That is, the low grayscale driving voltage range of the transistor is relatively narrow. However, the driving current Ion (conduction current) is relatively high in the saturation region.

[0135] According to the second curve G2, the slope of this curve is small in the subthreshold region. That is, the low grayscale driving voltage range of the transistor is relatively wide. However, the driving current Ion (conduction current) is relatively low in the saturation region.

[0136] According to the third curve G3, its slope in the subthreshold region is similar to that of the second curve G2 in the subthreshold region. That is, the low-grayscale driving voltage range of the transistor is relatively wide. The subthreshold swing (SS) can be increased to increase the low-grayscale driving voltage range of the first transistor T1, and consequently, the low-grayscale display quality can be improved. Therefore, as... Figure 4B As shown in the third curve G3, the display device (e.g., display device 11) can exhibit improved low grayscale display quality, for example, based on the first transistor T1 exhibiting increased subthreshold swing, low grayscale driving voltage range, etc. The first transistor T1 includes a first upper gate electrode G1-1 above the first channel region CA1 and a first lower gate electrode G1-2 below the first channel region CA1, wherein the first lower gate electrode G1-2 includes both a first-1 gate electrode G1-21 and a first-2 gate electrode G1-22, wherein the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 are below the first channel region CA1 and at different layers such that one of the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 is closer to the top surface BSu of the base layer BS than the other of the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 on the third direction DR3.

[0137] Furthermore, according to the third curve G3, the drive current Ion (conduction current) in the saturation region is lower than the drive current Ion in the saturation region of the first curve G1, but higher than the drive current Ion in the saturation region of the second curve G2. Compared to the second curve G2, the third curve G3 shows that the drive current Ion (conduction current) of the first transistor T1 increases at the same voltage Vgs. Compared to the second curve G2, the third curve G3 shows that the drive voltage range (or data swing range (DSR)) decreases in the saturation region, and as a result, power consumption can be reduced. As a result, for the driving transistor with the characteristics of the third curve G3, based on the first transistor T1, it has a wide low-grayscale driving voltage range and a relatively high driving current Ion. The first transistor T1 includes a first upper gate electrode G1-1 above the first channel region CA1 and a first lower gate electrode G1-2 below the first channel region CA1. The first lower gate electrode G1-2 includes both a first-1 gate electrode G1-21 and a first-2 gate electrode G1-22. The first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 are located below the first channel region CA1 and in different layers, such that one of the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 is closer to the top surface BSu of the base layer BS on the third-direction DR3 than the other of the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22. It can also be seen that the third curve G3 shows a wider driving voltage range and a higher driving current Ion than the second curve G2.

[0138] Figure 4C It shows the relationship with Figure 4A The cross-sectional view of the different display panels 141. Figure 4C Regarding the stacking relationship between the insulating layer and the pattern, and Figure 4A Different, and with Figure 4A compared to, Figure 4C The sixth transistor T6 is further shown.

[0139] and Figure 3A Compared to the pixel PXij shown, according to some exemplary embodiments (including...) Figure 4C The pixels of the display panel 141 (in the exemplary embodiment shown) may further include a sixth transistor T6. Based on Figure 3A In the equivalent circuit, the sixth transistor T6 can be positioned between the second node ND2 and the light-emitting element OLED. Here, Figure 3A The fourth drain D4 of the fourth transistor T4 is connected to the output terminal of the sixth transistor T6 and the anode of the light-emitting element OLED, but not to the second node ND2.

[0140] The sixth transistor T6 may include components composed of... Figure 3AThe semiconductor pattern is made of a material different from that used for at least a portion of the first transistors T1 to T5. The sixth transistor T6 may be made of a material different from that used for the first transistor T1 to the fifth transistor T5. Figure 3A At least a portion of transistors of different types, from the first transistor T1 to the fifth transistor T5. Including... Figure 4C In some exemplary embodiments of the exemplary implementation shown, the sixth transistor T6 may be a p-type transistor.

[0141] The following text mainly describes Figure 4A The display panel 141 and Figure 4C The differences between the display panels 141 in the middle. Although Figure 4A The display panel 141 and Figure 4C The display panels 141 in the reference are different, but Figure 4A and Figure 4B The characteristics of the first transistor T1 described can be applied to Figure 4C The exemplary implementation shown.

[0142] refer to Figure 4C The silicon semiconductor pattern PS is disposed on the buffer layer BFL. The silicon semiconductor in the silicon semiconductor pattern PS can include amorphous silicon, polycrystalline silicon, etc. For example, the silicon semiconductor pattern PS can include polycrystalline silicon that crystallizes at low temperatures (also known as crystalline polycrystalline silicon).

[0143] Depending on whether the silicon semiconductor pattern PS is doped, the silicon semiconductor pattern PS can have different electrical characteristics. The silicon semiconductor pattern PS includes an input region SA6 (hereinafter referred to as the sixth input region), an output region DA6 (hereinafter referred to as the sixth output region), and a channel region CA6 (hereinafter referred to as the sixth channel region) disposed between the sixth input region SA6 and the sixth output region DA6. The sixth input region SA6 and the sixth output region DA6 correspond to the source and drain of the sixth transistor T6, respectively. Although not shown separately, reference is made to... Figure 3A The fifth transistor T5 described may also include a semiconductor pattern formed by the same process, and include the same material as the silicon semiconductor pattern PS of the sixth transistor T6.

[0144] Gate electrode G6 (hereinafter referred to as the sixth gate electrode) is disposed on the sixth channel region CA6. The sixth gate electrode G6 can be formed by the same process as the first-1 gate electrode G1-21 and the second-1 gate electrode G2-2 and includes the same metal.

[0145] Figure 4C The first transistor T1 and the second transistor T2 disposed on the first insulating layer 10 can be connected with Figure 4AThe first transistor T1 and the second transistor T2 disposed on the base layer BS are the same or substantially the same. The fourth insulating layer 40 may include a fourth-1 insulating pattern 41 disposed on the first channel region CA1 and a fourth-2 insulating pattern 42 disposed on the second channel region CA2. A fifth insulating layer 50 covering the first transistor T1 and the second transistor T2 is disposed on the third insulating layer 30. The fifth insulating layer 50 may include an organic layer having a single-layer or multi-layer structure. Functionally, Figure 4C The fourth insulating layer 40 and the fifth insulating layer 50 in the middle correspond to Figure 4A The third insulating layer 30 and the fourth insulating layer 40 in the middle.

[0146] At least one first connection electrode CNE1 may be provided on the fifth insulating layer 50. Four first connection electrodes CNE1 are shown as an example. The four first connection electrodes CNE1 are respectively connected to the sixth input area SA6, the sixth output area DA6, the second input area DA2, and the second output area SA2 through first contact holes CH1, the first contact holes CH1 passing through the respective insulating layers (e.g., defined at least partially by the respective inner surfaces of the respective insulating layers).

[0147] A sixth insulating layer 60 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may include an organic layer. At least one second connection electrode CNE2 may be disposed on the sixth insulating layer 60. The second connection electrode CNE2 can be connected to the sixth output area DA6 through a second contact hole CH2 passing through the sixth insulating layer 60. The j-th data line DLj may be disposed on the sixth insulating layer 60. The j-th data line DLj can be connected to the second input area DA2 through a second contact hole CH2 passing through the sixth insulating layer 60.

[0148] A seventh insulating layer 70 is disposed on the sixth insulating layer 60. The seventh insulating layer 70 may include an organic layer. Functionally, the seventh insulating layer 70 corresponds to... Figure 4A The fifth insulating layer 50. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the third contact hole CH3 passing through the seventh insulating layer 70.

[0149] Figure 5A This is a plan view of the first transistor T1 according to some exemplary embodiments of the present invention. Figure 5B This is along some exemplary embodiments of the concept of the present invention. Figure 5A A cross-sectional view of the first transistor T1 in line II-II'. Figure 5C This is a cross-sectional view of a second transistor T2 according to some exemplary embodiments of the present invention.

[0150] In the following text, see also reference Figure 4A To describe the first transistor T1 and the second transistor T2. (And...) Figure 5A The cross-section of the first transistor T1 corresponding to line I-I' in the diagram is... Figure 4A The cross-section shown is the same.

[0151] like Figure 4A , Figure 5A and Figure 5B As shown, gate electrode 1-1 G1-21 and gate electrode 1-22 are arranged below the first oxide semiconductor pattern OS1 in the first direction DR1. In the plane, gate electrode 1-1 G1-21 is positioned adjacent to the first input region DA1 relative to the first output region SA1, and gate electrode 1-22 is positioned adjacent to the first output region SA1 relative to the first input region DA1. For example, gate electrode 1-1 G1-21 may be closer to the first input region DA1 in a horizontal direction (e.g., at least one of the first direction DR1 and the second direction DR2) parallel to the top surface BSu of the base layer BS, and gate electrode 1-22 may be closer to the first output region SA1 in the horizontal direction relative to the first input region DA1. As shown, the first gate electrode G1-21 can be positioned closer to the base layer BS than the first gate electrode G1-22, such that the first gate electrode G1-21 can be closer to the base layer BS on the third-direction DR3 than the first gate electrode G1-22.

[0152] The first-1 gate electrode G1-21 may include a first portion P1, a second portion P2, and a third portion P3 separated along a first direction DR1. The first portion P1 overlaps at least in a plane with the first input region DA1 (e.g., at least partially overlapped by the first input region DA1 along the third direction DR3), and the second portion P2 overlaps at least in a plane with the first channel region CA1 (e.g., at least partially overlapped by the first channel region CA1 along the third direction DR3). The second portion P2 is positioned closer to the first output region SA1 than the first portion P1. For example, the second portion P2 may be closer to the first output region SA1 than the first portion P1 in a horizontal direction extending parallel to the top surface BSu of the base layer BS (e.g., at least one of the first direction DR1 and the second direction DR2). In another example, the second portion P2 may be at least partially located between the first output region SA1 and the first portion P1 in a horizontal direction. The third portion P3 extends from the second portion P2 and overlaps with the first connection electrode CNE1, which will be described later. The third portion P3 does not overlap with the first oxide semiconductor pattern OS1 (e.g., it is exposed from the first oxide semiconductor pattern OS1 on the third-direction DR3). The first portion P1, the second portion P2, and the third portion P3 may be defined by separate portions of a single monolithic material that defines (e.g., constitutes) the first-1 gate electrode G1-21.

[0153] The first and second gate electrodes G1-22 may include a first portion P10, a second portion P20, and a third portion P30 separated in a first direction DR1. The first portion P10 overlaps at least with the first output region SA1 in a plane (e.g., it is at least partially overlapped by the first output region SA1 in a third direction DR3), and the second portion P20 overlaps at least with the first channel region CA1 in a plane (e.g., it is at least partially overlapped by the first channel region CA1 in a third direction DR3). The second portion P20 is positioned closer to the first input region DA1 than the first portion P10. For example, the second portion P20 may be closer to the first input region DA1 than the first portion P10 in a horizontal direction extending parallel to the top surface BSu of the base layer BS (e.g., at least one of the first direction DR1 and the second direction DR2). The third portion P30 extends from the first portion P10 and overlaps with the first connection electrode CNE1, which will be described later. The third portion P30 does not overlap with the first oxide semiconductor pattern OS1 (e.g., it is exposed from the first oxide semiconductor pattern OS1 in a third direction DR3). The first part P10, the second part P20 and the third part P30 can be defined by separate portions of a single monolithic material that defines (e.g., constitutes) the first-second gate electrodes G1-22.

[0154] like Figure 5A As shown, the first oxide semiconductor pattern OS1 can be disposed on the second direction DR2 (which can extend parallel to the top surface BSu of the base layer BS) between the third portion P3 of the first-1 gate electrode G1-21 and the third portion P30 of the first-2 gate electrode G1-22.

[0155] like Figure 5A and Figure 5B As shown, the first connecting electrode CNE1 can be arranged to overlap with the first output region SA1 (e.g., overlap with the first output region SA1 on the third-direction DR3). There are no particular limitations on the planar shape of the first connecting electrode CNE1.

[0156] The first connecting electrode CNE1 is electrically connected to the first output region SA1, the first-1 gate electrode G1-21, and the first-2 gate electrode G1-22. The first connecting electrode CNE1 is connected to the first-1 gate electrode G1-21 through a first contact hole CH1. The first contact hole CH1 can pass through... Figure 5B The first insulating layer 10, the second insulating layer 20, and the fourth insulating layer 40 are shown (e.g., they may be at least partially defined by the respective inner surfaces of the first insulating layer 10, the second insulating layer 20, and the fourth insulating layer 40). The first connection electrode CNE1 is connected to the first-second gate electrode G1-22 through the second contact hole CH2. The second contact hole CH2 can pass through... Figure 5BThe second insulating layer 20 and the fourth insulating layer 40 are shown (e.g., they may be at least partially defined by the respective inner surfaces of the second insulating layer 20 and the fourth insulating layer 40). The first connection electrode CNE1 is connected to the first output region SA1 through a third contact hole CH3. The third contact hole CH3 can pass through... Figure 5B The fourth insulating layer 40 shown may be at least partially defined by one or more inner surfaces of the fourth insulating layer 40. A portion of the first connection electrode CNE1 is disposed on the fourth insulating layer 40. The first contact hole CH1 and the second contact hole CH2 are arranged to be spaced apart from the first gate electrode G1-1 (also referred to as the first upper gate) and the first oxide semiconductor pattern OS1 (e.g., spaced apart from them in one or more horizontal directions extending parallel to the top surface BSu of the base layer BS).

[0157] Figure 5C It shows the basis with Figure 4A The cross-section of the second transistor T2 with different cut lines is shown in the reference. Figure 5C The second gate electrode G2-1 and the second-first gate electrode G2-2 can be electrically connected via the second connecting electrode CNE2. The second connecting electrode CNE2 can be connected to the second-first gate electrode G2-2 via a fourth contact hole CH4 passing through the first insulating layer 10, the second insulating layer 20, and the fourth insulating layer 40, and connected to the second gate electrode G2-1 via a fifth contact hole CH5 passing through the fourth insulating layer 40. The second connecting electrode CNE2 can be electrically connected via... Figure 5B The first connecting electrode CNE1 in the process is formed using the same photolithography process.

[0158] Figure 6A and Figure 6B Each of these is a cross-sectional view of a display panel 141 according to some exemplary embodiments of the present invention. Hereinafter, with reference to... Figures 4A to 5C Detailed reference for the same parts as the described parts Figures 4A to 5C .

[0159] refer to Figure 6AIn a plane (e.g., in or on a plane extending parallel to the top surface BSu of the base layer BS), the first-1 gate electrode G1-21 may include a first portion P1 overlapping with the first input region DA1 (e.g., at least partially overlapping with the first input region DA1 on the third-direction DR3), a second portion P2 overlapping with the first channel region CA1 (e.g., at least partially overlapping with the first channel region CA1 on the third-direction DR3), and a third portion P3 overlapping with the first output region SA1 (e.g., at least partially overlapping with the first output region SA1 on the third-direction DR3). The second portion P2 and the third portion P3 of the first-1 gate electrode G1-21 may overlap with the first-2 gate electrode G1-22 (e.g., may be at least partially overlapping with the first-2 gate electrode G1-22 on the third-direction DR3). Figure 4A In contrast, the capacitance of the first-second parasitic capacitor CD2 can be the same, but the capacitance of the first-first parasitic capacitor CD1 can be increased to increase the capacitance of the first parasitic capacitor C-S1. The first-second gate electrodes G1-22 may include at least a first portion P10 and a second portion P20 divided in the first direction DR1, wherein the first portion P10 overlaps at least in the plane with the first output region SA1 or the first input region DA1 (e.g., at least partially overlapped by the first output region SA1 or the first input region DA1 in the third direction DR3), and the second portion P20 overlaps at least in the plane with the first channel region CA1 (e.g., at least partially overlapped by the first channel region CA1 in the third direction DR3). For example, Figure 6A The exemplary embodiment shown depicts a first portion P10 that at least overlaps with the first output region SA1 (e.g., is at least partially overlapped by the first output region SA1 on the third-direction DR3). However, in some exemplary embodiments, the first portion P10 at least overlaps with the first input region DA1 (e.g., such as...). Figure 7B As shown, it is at least partially overlapped by the first input region DA1 on the third-direction DR3.

[0160] The second portion P2 of the first-1 gate electrode G1-21, which overlaps with the first-2 gate electrode G1-22 (e.g., at least partially overlapped by the first-2 gate electrode G1-22 on the third-direction DR3), has a low effect on the increase in capacitance of the first parasitic capacitor C-S1. Figure 6A As shown, the surface area of ​​the first-1 gate electrode G1-21 (the surface area in the plane extending parallel to the top surface BSu) has a low influence on the increase in capacitance of the first parasitic capacitor C-S1, and therefore the design of the first-1 gate electrode G1-21 can be freely carried out.

[0161] refer to Figure 6BThe first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 can be spaced apart from each other in the first direction DR1, for example, such that the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 are exposed to each other in the third direction DR3. Figure 6B Some exemplary embodiments are shown, in which the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 are spaced apart by a specific distance (or optionally, a predetermined distance) DT. As the specific distance (or optionally, a predetermined distance) DT increases, the capacitance of at least one of the first-1 parasitic capacitor CD1 and the first-2 parasitic capacitor CD2 can decrease, and therefore the capacitance of the first parasitic capacitor C-S1 can decrease.

[0162] Figure 7A This is a plan view of the first transistor T1 according to some exemplary embodiments of the present invention. Figure 7B This is a first cross-sectional view of a first transistor T1 according to some exemplary embodiments of the present invention. Figure 7C It is along some exemplary embodiments of the first transistor T1 according to the present invention. Figure 7A The second sectional view along line II-II'. In the following text, with reference to... Figures 4A to 6B Detailed reference for the same parts as the described parts Figures 4A to 6B .

[0163] refer to Figures 7A to 7C Compared to the first input region DA1 in the first oxide semiconductor pattern OS1, the first gate electrode G1-21, which is disposed on the same layer as the second-first gate electrode G2-2 (e.g., directly disposed on the same layer), is positioned adjacent to the first output region SA1. For example, in a horizontal direction extending parallel to the top surface BSu of the base layer BS (e.g., at least one of the first direction DR1 and the second direction DR2), the first gate electrode G1-21 may be closer to the first output region SA1 than to the first input region DA1. In the plane, the first-second gate electrode G1-22 (which is positioned adjacent to the first channel region CA1 in the third direction DR3 than the first gate electrode G1-21) is positioned adjacent to the first input region DA1 than to the first output region SA1. For example, the first-second gate electrode G1-22 may be closer to the first channel region CA1 on the third direction DR3 than the first-first gate electrode G1-21, and the first-second gate electrode G1-22 may be closer to the first input region DA1 in the horizontal direction than to the first output region SA1.

[0164] The first-1 gate electrode G1-21 may include a first portion P1, a second portion P2, and a third portion P3 separated along a first direction DR1. The first portion P1 overlaps at least with the first output region SA1 in a plane (e.g., at least partially overlapped by the first output region SA1 in the third direction DR3), and the second portion P2 overlaps at least with the first channel region CA1 in a plane (e.g., at least partially overlapped by the first channel region CA1 in the third direction DR3). The second portion P2 is positioned closer to the first input region DA1 than the first portion P1. For example, the second portion P2 may be closer to the first input region DA1 than the first portion P1 in a horizontal direction extending parallel to the top surface BSu of the base layer BS (e.g., at least one of the first direction DR1 and the second direction DR2). The third portion P3 extends from the first portion P1 and overlaps with the first connection electrode CNE1 (e.g., at least partially overlapped by the first connection electrode CNE1 in the third direction DR3). The third portion P3 does not overlap with the first oxide semiconductor pattern OS1 (e.g., exposed from the first oxide semiconductor pattern OS1 in the third direction DR3).

[0165] The first and second gate electrodes G1-22 may include a first portion P10, a second portion P20, and a third portion P30 separated in a first direction DR1. The first portion P10 overlaps at least with the first input region DA1 in a plane (e.g., at least partially overlapped by the first input region DA1 in a third direction DR3), and the second portion P20 overlaps at least with the first channel region CA1 in a plane (e.g., at least partially overlapped by the first channel region CA1 in a third direction DR3). The second portion P20 is positioned closer to the first output region SA1 than the first portion P10. For example, the second portion P20 may be closer to the first output region SA1 than the first portion P10 in a horizontal direction extending parallel to the top surface BSu of the base layer BS (e.g., at least one of the first direction DR1 and the second direction DR2). The third portion P30 extends from the second portion P20 and overlaps with the first connection electrode CNE1 (e.g., at least partially overlapped by the first connection electrode CNE1 in a third direction DR3). The third part P30 does not overlap with the first oxide semiconductor pattern OS1 (e.g., it is exposed from the first oxide semiconductor pattern OS1 on the third-direction DR3).

[0166] Compared to parasitic capacitor CD1, parasitic capacitor CD2 has a more significant effect on the increase and decrease of capacitance of the first parasitic capacitor C-S1. This is because gate electrode G1-22 is closer to the first channel region CA1 than gate electrode G1-21 (e.g., because gate electrode G1-22 is closer to the first channel region CA1 on the third-direction DR3 than gate electrode G1-21).

[0167] The first-1 gate electrode G1-21 can be like Figure 6A Thus, it extends further from the top surface BSu of the base layer BS toward the first input region DA1, and the first-1 gate electrode G1-21 and the first-2 gate electrode G1-22 can be like Figure 6B They are spaced apart from each other in the first direction DR1.

[0168] As described above, the subthreshold swing (SS) can be increased to increase the low grayscale driving voltage range of the first transistor T1, and as a result, the low grayscale display quality can be improved (e.g., the low grayscale display quality of the display device 11).

[0169] In addition, the drive current Ion (conduction current) of the first transistor T1 can be increased to reduce the drive voltage range (or data swing range (DSR)) in the saturation region, and as a result, power consumption can be reduced (e.g., power consumption of the display device 11).

[0170] The foregoing has described some exemplary embodiments of the inventive concept with reference to the present invention. However, it will be understood by those skilled in the art or those with common knowledge in the art that various modifications and changes can be made to the inventive concept, as long as such modifications and changes do not depart from the spirit and technical scope of the inventive concept set forth in the appended claims.

[0171] Therefore, the technical scope of this invention is not limited to the content described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: base layer; Multiple insulating layers are present on the base layer; The first transistor is located on the base layer; as well as The light-emitting element is electrically connected to the first transistor. The first transistor includes: A first oxide semiconductor pattern, the first oxide semiconductor pattern including a first input region, a first output region, and a first channel region between the first input region and the first output region. A first gate electrode is located above the first channel region and at least partially overlaps the first channel region in a vertical direction, the vertical direction extending perpendicular to the top surface of the base layer. The first-1 gate electrode, located below the first channel region, is at least partially overlapped by the first channel region in the vertical direction and electrically connected to the first output region. The first and second gate electrodes are located below the first channel region, and are at least partially overlapped by the first channel region in the vertical direction and electrically connected to the first output region. The first-1 gate electrode and the first-2 gate electrode are located in different layers, such that one of the first-1 gate electrode and the first-2 gate electrode is closer to the top surface of the base layer in the vertical direction than the other of the first-1 gate electrode and the first-2 gate electrode.

2. The display device according to claim 1, further comprising a connection electrode, the connection electrode being on the base layer and configured to electrically connect the first output area, the first-1 gate electrode, and the first-2 gate electrode.

3. The display device according to claim 2, wherein, The plurality of insulating layers include: A first insulating layer is formed on the first-1 gate electrode; A second insulating layer is formed on the first insulating layer and the first-2 gate electrodes, such that the first insulating layer is positioned vertically between the first-1 gate electrode and the second insulating layer, and between the first-1 gate electrode and the first-2 gate electrode; and A third insulating layer is formed on the second insulating layer and the first oxide semiconductor pattern.

4. The display device according to claim 3, wherein, The connection electrode is connected to the first-1 gate electrode through a first contact hole passing through the first insulating layer, the second insulating layer, and the third insulating layer. The connection electrode is connected to the first-2 gate electrode through a second contact hole passing through the second insulating layer and the third insulating layer, and The connection electrode is connected to the first output area through a third contact hole passing through the third insulating layer.

5. The display device according to claim 4, wherein, The first contact hole and the second contact hole are spaced apart from the first gate electrode and the first oxide semiconductor pattern in one or more horizontal directions extending parallel to the top surface of the base layer.

6. The display device according to claim 1, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first portion of the first-1 gate electrode is at least partially overlapped by the first input region in the vertical direction, and the second portion of the first-1 gate electrode is at least partially overlapped by the first channel region in the vertical direction. The first portion of the first-second gate electrode is at least partially overlapped by the first output region in the vertical direction, and the second portion of the first-second gate electrode is at least partially overlapped by the first channel region in the vertical direction.

7. The display device according to claim 1, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first portion of the first-1 gate electrode is at least partially overlapped by the first output region in the vertical direction, and the second portion of the first-1 gate electrode is at least partially overlapped by the first channel region in the vertical direction. The first portion of the first-second gate electrode is at least partially overlapped by the first input region in the vertical direction, and the second portion of the first-second gate electrode is at least partially overlapped by the first channel region in the vertical direction.

8. The display device according to claim 1, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first-1 gate electrode includes a first portion that is at least partially overlapped by the first input region in the vertical direction, a second portion that is at least partially overlapped by the first channel region in the vertical direction, and a third portion that is at least partially overlapped by the first output region in the vertical direction. The first-second gate electrode includes a first portion that is at least partially overlapped in the vertical direction by the first input region or the first output region, and a second portion that is at least partially overlapped in the vertical direction by the first channel region.

9. The display device according to claim 1, wherein, A portion of the first-1 gate electrode and a portion of the first-2 gate electrode at least partially overlap each other in the vertical direction.

10. The display device according to claim 1, wherein, The first-1 gate electrode and the first-2 gate electrode are spaced apart from each other in one or more horizontal directions extending parallel to the top surface of the base layer.

11. The display device of claim 1, further comprising a second transistor on the base layer, in, The second transistor includes: The second oxide semiconductor pattern includes a second input region, a second output region, and a second channel region, wherein the second channel region is located between the second input region and the second output region; A second gate electrode is located above the second channel region and overlaps with the second channel region in the vertical direction; and The second-1 gate electrode is located below the second channel region, and is at least partially overlapped by the second channel region in the vertical direction and electrically connected to the second gate electrode. Wherein, the first separation distance between the first channel region and the first-2 gate electrode in the vertical direction is less than the second separation distance between the second channel region and the second-1 gate electrode in the vertical direction.

12. The display device according to claim 11, wherein, The second-first gate electrode is located in the same layer as the first-first gate electrode and comprises the same material as the first-first gate electrode.

13. The display device of claim 12, further comprising a connection electrode configured to electrically connect the second gate electrode and the second-1st gate electrode. in, The plurality of insulating layers include: A first insulating layer and a second insulating layer are disposed on the second-1st gate electrode; and A third insulating layer is formed on the second oxide semiconductor pattern and the second gate electrode. A portion of the connecting electrode is located on the third insulating layer.

14. The display device according to claim 1, wherein, The first-1 gate electrode and the first-2 gate electrode together define the lower gate electrode, and the display device further includes a capacitor electrically connected between the lower gate electrode and the first channel region.

15. Electronic devices, including: Display device; as well as The processor is configured to control the display device. The display device includes: base layer Multiple insulating layers, on the base layer, The first transistor, on the base layer, and The light-emitting element is electrically connected to the first transistor. The first transistor includes: A first oxide semiconductor pattern includes a first input region, a first output region, and a first channel region between the first input region and the first output region; A first gate electrode is located above the first channel region and at least partially overlaps the first channel region in a vertical direction, the vertical direction extending perpendicular to the top surface of the base layer. A first-1 gate electrode, located below the first channel region, is at least partially overlapped by the first channel region in the vertical direction and electrically connected to the first output region; and The first and second gate electrodes are located below the first channel region, and are at least partially overlapped by the first channel region in the vertical direction and electrically connected to the first output region. The first-1 gate electrode and the first-2 gate electrode are located in different layers, such that one of the first-1 gate electrode and the first-2 gate electrode is closer to the top surface of the base layer in the vertical direction than the other of the first-1 gate electrode and the first-2 gate electrode.

16. The electronic device according to claim 15, wherein, The display device further includes a connection electrode on the base layer and configured to electrically connect the first channel region, the first-1 gate electrode, and the first-2 gate electrode.

17. The electronic device according to claim 15, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first portion of the first-1 gate electrode is at least partially overlapped by the first input region in the vertical direction, and the second portion of the first-1 gate electrode is at least partially overlapped by the first channel region in the vertical direction. The first portion of the first-second gate electrode is at least partially overlapped by the first output region in the vertical direction, and the second portion of the first-second gate electrode is at least partially overlapped by the first channel region in the vertical direction.

18. The electronic device according to claim 15, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first portion of the first-1 gate electrode is at least partially overlapped by the first output region in the vertical direction, and the second portion of the first-1 gate electrode is at least partially overlapped by the first channel region in the vertical direction. The first portion of the first-second gate electrode is at least partially overlapped by the first input region in the vertical direction, and the second portion of the first-second gate electrode is at least partially overlapped by the first channel region in the vertical direction.

19. The electronic device according to claim 15, wherein, The first-1 gate electrode is closer to the base layer in the vertical direction than the first-2 gate electrode. The first-1 gate electrode includes a first portion that is at least partially overlapped by the first input region in the vertical direction, a second portion that is at least partially overlapped by the first channel region in the vertical direction, and a third portion that is at least partially overlapped by the first output region in the vertical direction. The first-second gate electrode includes a first portion that is at least partially overlapped in the vertical direction by the first input region or the first output region, and a second portion that is at least partially overlapped in the vertical direction by the first channel region.

20. The electronic device according to claim 15, wherein, The display device also includes a second transistor on the base layer. The second transistor includes: The second oxide semiconductor pattern includes a second input region, a second output region, and a second channel region, wherein the second channel region is located between the second input region and the second output region; A second gate electrode is located above the second channel region and overlaps with the second channel region in the vertical direction; and The second-1 gate electrode is located below the second channel region, and is at least partially overlapped by the second channel region in the vertical direction and electrically connected to the second gate electrode. Wherein, the first separation distance between the first channel region and the first-2 gate electrode in the vertical direction is less than the second separation distance between the second channel region and the second-1 gate electrode in the vertical direction.

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