Display panel, method for manufacturing display panel, and display device

Abstract

Embodiments of the present application provide a display panel, a preparation method of the display panel and a display device. The display panel comprises, in sequence along its thickness direction, a substrate, a driving backplate layer, a planarization layer, a first electrode layer, a pixel definition layer and a common layer. The first electrode layer comprises a plurality of first electrodes arranged at intervals. The pixel definition layer is located on a side of the planarization layer away from the substrate. The pixel definition layer comprises a plurality of pixel opening regions and a plurality of barrier regions located between adjacent two pixel opening regions. The barrier region has a through hole penetratingly arranged. The planarization layer is provided with a groove corresponding to the region of the through hole. The through hole and the groove are in communication to form a recess structure between the barrier region and the planarization layer. The common layer covers the surface of the first electrode, the pixel definition layer and the recess structure. According to the embodiments of the present application, the length of the common layer is increased, and thus the impedance of the common layer is increased, so that the crosstalk between adjacent light-emitting pixels is reduced or eliminated.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are self-emissive display devices. Compared to traditional liquid crystal displays (LCDs), OLED technology does not require a backlight and is self-emissive. OLEDs use a thin layer of organic material and a glass substrate; when current flows through, the organic material emits light. Therefore, OLED display panels can significantly save energy, be made lighter and thinner, withstand a wider range of temperature variations than LCD panels, and have a wider viewing angle. OLED display panels are expected to become the next-generation flat panel display technology after LCDs and are currently one of the most watched technologies in the flat panel display field. However, the manufacturing process performance of current OLED display products still needs improvement. Summary of the Invention

[0003] This application provides a display panel, a method for manufacturing the display panel, and a display device, aiming to improve the process performance of the display panel.

[0004] An embodiment of the first aspect of this application provides a display panel, including:

[0005] Substrate;

[0006] A driving backplane layer, the driving backplane layer being located on one side of the substrate;

[0007] A planarization layer, the planarization layer covering the side of the drive backplane layer opposite to the substrate;

[0008] A first electrode layer is disposed on the side of the planarization layer opposite to the drive backplane layer, and the first electrode layer includes a plurality of spaced first electrodes.

[0009] A pixel definition layer is located on the side of the planarization layer opposite to the substrate. The pixel definition layer includes a plurality of pixel opening regions and a plurality of barrier regions located between two adjacent pixel opening regions. The pixel opening regions have pixel openings, and at least a portion of the first electrode is exposed from the pixel openings.

[0010] The barrier region has a through hole, and the planarization layer has a groove in the area corresponding to the through hole. The through hole and the groove are connected to form a recessed structure in the barrier region and the planarization layer.

[0011] A common layer covers the surfaces of the first electrode, the pixel definition layer, and the recessed structure.

[0012] According to an embodiment of the first aspect of this application, the surface of the recessed structure is provided with a plurality of spaced protrusions.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the plurality of protrusions are located at the bottom of the groove.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the plurality of protrusions are spaced apart and distributed over all areas of the surface of the recessed structure.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the surface of the recessed structure is provided with a plurality of wavy regions corresponding to the protrusions.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the surface of the recessed structure is further provided with a plurality of notches, and the plurality of protrusions and the plurality of notches are arranged alternately.

[0017] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the hole wall of the through hole and / or the opposite sidewall of the groove is recessed along a first direction, the first direction intersecting the thickness direction of the display panel.

[0018] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the wall of the through hole and / or the opposite sidewall of the groove have different curvatures of concavity along the first direction.

[0019] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the bottom of the groove is recessed in the direction toward the substrate.

[0020] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the wall of the through hole and / or the wall of the groove is deposited with a plurality of insulating particles of different particle sizes, and the common layer is capable of expanding at the insulating particles.

[0021] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the hole wall of the through hole and / or the groove wall of the groove is recessed along a first direction to form a recessed portion; a plurality of insulating particles of different particle sizes are deposited on the surface of the recessed portion; the first direction intersects the thickness direction of the display panel.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the orthogonal projection range of the through hole on the substrate is located within the orthogonal projection range of the groove on the substrate;

[0023] Alternatively, the orthographic projection range of the via on the substrate coincides with the orthographic projection range of the groove on the substrate, and the aperture of the via at one end along the thickness direction of the display panel and near the common layer is smaller than the aperture of the via at one end along the thickness direction of the display panel and near the planarization layer, and the via at one end along the thickness direction of the display panel and near the planarization layer is aligned and connected to the groove opening.

[0024] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection shape of the recessed structure on the substrate is any one of a rectangle, a circle, or a rhombus.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the same blocking region has a plurality of recessed structures, and the plurality of recessed structures are arranged sequentially at intervals along the vertical direction of two adjacent pixel opening regions.

[0026] The second aspect of this application also provides a method for manufacturing a display panel, wherein the display panel is a display device as described in any embodiment of the first aspect of this application, and the method for manufacturing the display panel includes:

[0027] The driving backplate layer is prepared on one side of the substrate;

[0028] The planarization layer is prepared on the side of the drive backplane layer opposite to the substrate;

[0029] The first electrode layer is prepared on the side of the planarization layer opposite to the substrate, wherein the first electrode includes a plurality of spaced-apart first electrodes;

[0030] The pixel definition layer is prepared on the side of the planarization layer opposite to the substrate. The pixel definition layer includes a plurality of pixel opening regions and a plurality of barrier regions located between two adjacent pixel opening regions. The pixel opening regions have pixel openings, and at least a portion of the first electrode is exposed from the pixel openings.

[0031] The through-hole is formed in the barrier area, and a groove is formed in the planarization layer corresponding to the through-hole to prepare the recessed structure;

[0032] The common layer is prepared on the side of the pixel definition layer opposite to the substrate, and the common layer covers the surface of the first electrode, the pixel definition layer and the recessed structure.

[0033] An embodiment of the third aspect of this application also provides a display device, including a display panel as described in any embodiment of the first aspect above, or including a display panel prepared by a method for preparing a display panel as described in any embodiment of the second aspect above.

[0034] In this application, in the embodiments thereof, a driving backplate is disposed on one side of the substrate, and a planarization layer is disposed on the side of the driving backplate away from the substrate for planarization; the pixel definition layer includes multiple pixel opening regions and multiple blocking regions located between two adjacent pixel opening regions. The pixel opening region has a pixel opening, at least a portion of the first electrode is exposed from the pixel opening and in contact with at least a portion of the common layer. The first electrode layer and the common layer drive the light-emitting pixel to emit light. The barrier region is used to isolate the light-emitting pixel. The barrier region is provided with a through hole. The planarization layer is provided with a groove in the area corresponding to the through hole. The through hole and the groove are connected, thereby forming a recessed structure on the barrier region and the planarization layer. The common layer covers the surface defined by the first electrode and the pixel, so that the first electrode can be exposed from the pixel opening and in contact with the common layer. The common layer covers the surface of the recessed structure and is attached to the surface of the recessed structure, so that the common layer forms a recess at the recessed structure, thereby increasing the length of the common layer and increasing the impedance of the common layer. The amount of charge transferred between adjacent light-emitting pixels is reduced, improving the crosstalk problem of the display device. Moreover, when a single pixel is lit, the charge is not easy to move laterally, ensuring the light output brightness and light output uniformity of the display panel. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0036] Figure 1 This is a schematic diagram of the structure of a display panel provided in the first aspect embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure of a display panel provided in another embodiment of the first aspect of this application;

[0038] Figure 3 This is a schematic diagram of the structure of a display panel provided in another embodiment of the first aspect of this application;

[0039] Figure 4 This is a schematic flowchart of a method for manufacturing a display panel according to a second aspect embodiment of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. Substrate; 2. Driving backplane layer; 3. Planarization layer; 31. Groove; 4. First electrode layer; 41. First electrode; 5. Pixel definition layer; 51. Pixel opening area; 511. Pixel opening; 52. Barrier area; 521. Through hole; 6. Recessed structure; 61. Protrusion; 62. Concave portion; 7. Common layer; 71. Second electrode; 8. Light-emitting pixel;

[0042] Z represents the thickness direction of the display panel; X represents the first direction. Detailed Implementation

[0043] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0044] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0046] Organic light-emitting diodes (OLEDs) are self-emissive display devices. Compared to traditional liquid crystal displays (LCDs), OLED technology does not require a backlight and is self-emissive. OLEDs use a thin layer of organic material and a glass substrate; when current flows through, the organic material emits light. Therefore, OLED display panels can significantly save energy, be made lighter and thinner, withstand a wider range of temperature variations than LCD panels, and have a wider viewing angle. OLED display panels are expected to become the next-generation flat panel display technology after LCDs and are currently one of the most watched technologies in the flat panel display field. However, the manufacturing process performance of current OLED display products still needs improvement.

[0047] In related technologies, when a certain light-emitting pixel is lit, some of the charge is transferred through the common layer to the adjacent unlit light-emitting pixel area, which causes the light emitted by that pixel to be dim or not lit at all. This is especially true in the case of low brightness and low grayscale, where the amount of charge itself is small, and the dimness of the light emitted by the display panel is more obvious in this case.

[0048] To solve the above-mentioned technical problems, this application forms a recessed structure on the blocking area and planarization layer of the pixel definition layer, and sets the common layer to fit the surface of the recessed structure, thereby increasing the length of the common layer and increasing the impedance of the common layer. This reduces the amount of charge transferred between adjacent light-emitting pixels, improves the crosstalk problem of the display device, and makes it less likely for the charge to move laterally when a single pixel is lit, thus ensuring the brightness and uniformity of light output when a single pixel is lit.

[0049] To better understand this application, the following will be combined with... Figures 1 to 4 The display panel, the method for manufacturing the display panel, and the display device according to the embodiments of this application will be described in detail.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0051] like Figure 1 As shown, this application provides a display panel, comprising:

[0052] Substrate 1.

[0053] Drive backplane layer 2, which is located on one side of substrate 1.

[0054] Planarization layer 3 covers the side of the drive backplane layer 2 that is away from the substrate 1.

[0055] The first electrode layer 4 is disposed on the side of the planarization layer 3 opposite to the drive backplane layer 2. The first electrode layer 4 includes a plurality of first electrodes 41 arranged at intervals.

[0056] A pixel definition layer 5 is located on the side of the planarization layer 3 facing away from the substrate 1. The pixel definition layer 5 includes a plurality of pixel opening regions 51 and a plurality of barrier regions 52 located between two adjacent pixel opening regions 51. The pixel opening regions 51 have pixel openings 511. At least a portion of the first electrode 41 is exposed from the pixel opening 511.

[0057] The barrier region 52 has a through hole 521. The planarization layer 3 has a groove 31 in the area corresponding to the through hole 521. The through hole 521 and the groove 31 are connected to form a recessed structure 6 in the barrier region 52 and the planarization layer 3.

[0058] The common layer 7 covers the surface of the first electrode 41, the pixel definition layer 5, and the recessed structure 6.

[0059] In this embodiment, a driving backplate is disposed on one side of the substrate 1, and a planarization layer 3 is disposed on the side of the driving backplate away from the substrate 1 for planarization. The pixel definition layer 5 includes a plurality of pixel opening regions 51 and a plurality of blocking regions 52 located between two adjacent pixel opening regions 51. The pixel opening region 51 has a pixel opening 511, and at least a portion of the first electrode 41 is exposed from the pixel opening 511 and in contact with at least a portion of the common layer 7. The first electrode layer 4 and the common layer 7 drive the light-emitting pixel 8 to emit light. The blocking region 52 is used to isolate the light-emitting pixel 8. The blocking region 52 is provided with a through hole 521. The planarization layer 3 is provided with a groove 31 in the area corresponding to the through hole 521. The through hole 521 and the groove 31 are connected, thereby forming a recessed structure 6 on the blocking region 52 and the planarization layer 3. The common layer 7 covers the first electrode 4. The common layer 7 is defined by the pixel and the surface of the common layer 8, so that the first electrode 41 can be exposed from the pixel opening 511 and contact the common layer 7. The common layer 7 covers the surface of the recessed structure 6 and is attached to the surface of the recessed structure 6, so that the common layer 7 forms a recess at the recessed structure 6, thereby increasing the length of the common layer 7 and increasing the impedance of the common layer 7. The amount of charge transferred between adjacent light-emitting pixels 8 is reduced, the crosstalk problem of the display device is improved, and the charge is not easy to move laterally when a single pixel is lit, thus ensuring the light output brightness and light output uniformity of the display panel.

[0060] Specifically, such as Figure 1As shown, substrate 1 is disposed on the side of the driving backplane layer 2 opposite to the light-emitting side of the display panel. Substrate 1 mainly serves to provide stable foundation support for the various functional layers thereon, ensure the integrity and reliability of the display panel, and also prevent damage to the display device from external mechanical shocks or moisture. Optionally, substrate 1 is a glass substrate. Glass substrates are transparent and have high strength, which can protect the display device from the influence of the external environment while allowing light to pass through.

[0061] The driving backplane is used to control and drive each luminescent pixel 8 in the display panel. In AMOLED products, each luminescent pixel 8 consists of red, green, and blue sub-pixels, and each sub-pixel requires individual current driving to produce the correct color and brightness. The driving backplane precisely controls the on / off state and color changes of each luminescent pixel 8 through integrated circuits and logic control. Optionally, the driving backplane is an LTPS backplane or a TFT driving backplane.

[0062] like Figure 1 As shown, the planarization layer 3 is disposed on the side of the driving backplane facing away from the substrate 1. Thin-film transistors and other circuit structures on the driving backplane may have minute surface irregularities during manufacturing, which can affect the performance and quality of the OLED light-emitting layer. The planarization layer 3 is used to fill these minute surface irregularities, making the entire surface smooth.

[0063] The planarization layer 3 eliminates surface irregularities in the driving backplane, ensuring uniform coating and growth of the OLED material. As an insulating layer, the planarization layer 3 provides protection, preventing direct contact between the OLED material and the circuitry of the driving backplane, thus avoiding electrical short circuits. Optionally, the material of the planarization layer 3 includes one or more of polyimide, polyester, polydimethylsiloxane, epoxy resin, polyfluorinated polyethylene, polymethyl methacrylate, or incubation polymers.

[0064] like Figure 1 As shown, the pixel definition layer 5 includes a plurality of pixel opening regions 51 spaced apart along the planar direction of the display panel. A plurality of light-emitting pixels 8 are respectively located in the plurality of pixel opening regions 51. Each pixel opening region 51 is provided with a pixel opening 511. Optionally, the pixel opening 511 is provided through the pixel opening region 51, and at least a portion of the first electrode layer 4 is exposed through the pixel opening 511, directly contacting at least a portion of the common layer 7.

[0065] like Figure 1 As shown, the first electrode layer 4 is located on the side of the planarization layer 3 facing away from the substrate 1. Optionally, the first electrode layer 4 may be, for example, an anode layer. Optionally, in the first electrode layer 4, the pixel electrode is disposed that at least partially overlaps with the pixel opening 511 along the thickness direction Z of the display panel.

[0066] The common layer 7 includes, for example, a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, an electron injection layer, and a second electrode layer. The second electrode layer includes a second electrode 71. When the first electrode layer 4 and the second electrode layer are used to drive the light-emitting pixel 8 in the pixel opening 511 to emit light, the first electrode 41 in the first electrode layer 4 serves as the anode, and the second electrode 71 in the second electrode layer serves as the cathode.

[0067] A common layer 7 covers the first electrode 41 and the pixel definition layer 5. The common layer 7 makes at least partial contact with the first electrode 41 through the pixel opening 511 in the pixel opening region 51, thereby driving the light-emitting pixels 8 within the pixel opening 511 to emit light through the first electrode layer 4 and the common layer 7. The common layer 7 covers the entire surface of the pixel definition layer 5 to ensure that each first electrode 41 can contact the common layer 7, enabling the emission of multiple light-emitting pixels 8.

[0068] The pixel definition layer 5 is an insulating layer, primarily used to isolate the light-emitting pixels 8 and allow electrical contact between the first electrode layer 4 and the common layer 7. The portion of the pixel definition layer 5 between two adjacent pixel opening regions 51 is a barrier region 52. The barrier region 52 is used to isolate the light-emitting pixels 8, preventing crosstalk between them. Optionally, the pixel definition layer 5 can be bonded to the side of the planarization layer 3 facing away from the substrate 1 using optically transparent adhesive.

[0069] Among them, such as Figure 1 As shown, along the thickness direction Z of the display panel, the barrier area 52 is provided with a through hole 521 extending through the thickness direction Z of the display panel. Correspondingly, the planarization layer 3 is provided with a groove 31 in the area corresponding to the through hole 521. The depth direction of the groove 31 is consistent with the thickness direction Z of the display panel. The through hole 521 and the groove 31 are connected to form a recessed structure 6 between the pixel definition layer 5 and the planarization layer 3. The common layer 7 covers the surface of the recessed structure 6 in the area corresponding to the recessed structure 6, that is, the common layer 7 forms a recess in this area to fit the recessed structure 6, thereby increasing the length of the common layer 7, thereby increasing the impedance of the common layer 7, extending the charge transfer path, and when a single pixel is lit, the charge is less likely to flow to adjacent light-emitting pixels 8, improving crosstalk between display devices, reducing the risk of lateral leakage, ensuring the light output brightness and light output stability of the display panel, and especially ensuring the display effect of the display panel under low brightness and low grayscale conditions.

[0070] In some alternative embodiments, such as Figure 2 As shown, the surface of the recessed structure 6 is provided with a plurality of spaced protrusions 61.

[0071] In these optional embodiments, the pixel definition layer 5 forms a barrier region 52 with a barrier function between two adjacent pixel opening regions 51 using a patterning process. The barrier region 52 is fabricated with a through-hole 521 that penetrates its thickness using a photolithography process. Correspondingly, the planarization layer 3 is etched with a dry etching process to form a groove 31 in the region corresponding to the location of the through-hole 521. The groove 31 and the through-hole 521 are interconnected through a sidewall ramp structure, thereby jointly forming a recessed structure 6 at the junction of the barrier region 52 and the planarization layer 3.

[0072] Optionally, the depth of the groove 31 is 1μm to 3μm. Alternatively, the depth of the recessed structure 6 is 5μm to 8μm. Optionally, the surface of the recessed structure 6 is formed with an array of multiple spaced protrusions 61 using nanoimprint lithography. Optionally, the protrusions 61 are hemispherical. Optionally, the height of the protrusions 61 is 0.5μm to 1.2μm, and the spacing between adjacent protrusions 61 is 2μm to 4μm, arranged in an alternating pattern. The common layer 7 can cover the surfaces of the recessed structure 6 and the protrusions 61 using chemical vapor deposition, allowing the common layer 7 to form a continuous bending path in the barrier region 52, extending the effective conductive path of the common layer 7, increasing the impedance value of the common layer 7. This makes it less likely for charge to crosstalk along the common layer 7 to other light-emitting pixel 8 areas when a certain light-emitting pixel 8 is lit, reducing crosstalk between adjacent light-emitting pixels 8, and preventing lateral movement of charge, thus ensuring the brightness and uniformity of the light emitted by the display panel.

[0073] In some optional embodiments, multiple protrusions 61 are located at the bottom of the groove 31 to ensure that the planarization layer 3 has sufficient thickness in this area, thereby preventing electrical short circuits between the common layer 7 and the drive backplane layer 2 and ensuring the light emission stability of the display panel.

[0074] In some alternative embodiments, multiple protrusions 61 are spaced apart across all areas of the surface of the recessed structure 6, which can more effectively prevent charge from lateral crosstalk along the common layer 7 to other light-emitting pixel 8 areas, thereby ensuring crosstalk between adjacent light-emitting pixels 8.

[0075] In some alternative embodiments, such as Figure 2 As shown, the surface of the recessed structure 6 has a wavy area with multiple protrusions 61 distributed accordingly. This wavy distribution of the protrusions 61 increases the resistance to current flow in the common layer 7 in this area, enhancing the impedance characteristics of the common layer 7 and further reducing mutual interference between the light-emitting pixels 8. The recessed structure 6 not only improves the electrical performance of the display panel but also significantly enhances the isolation between the light-emitting pixels 8. Especially under low brightness and low grayscale conditions, it effectively reduces crosstalk effects, thereby improving the image quality and stability of the display panel.

[0076] In some alternative embodiments, the surface of the recessed structure 6 is further provided with a plurality of notches. The plurality of protrusions 61 and the plurality of notches are arranged alternately.

[0077] In these optional embodiments, the surface of the recessed structure 6 is further provided with multiple notches. The notches and protrusions 61 are arranged alternately. The multiple protrusions 61 and multiple notches are staggered, and the common layer 7 extends along the surface of the protrusions 61 and the walls of the notches, further optimizing the impedance characteristics of the common layer 7. The common layer 7 covers the surface of the recessed structure 6, forming a stable electrical connection layer, effectively reducing crosstalk problems of the light-emitting pixels 8 caused by lateral charge flow, and further enhancing the isolation between the light-emitting pixels 8.

[0078] In some alternative embodiments, such as Figure 3 As shown, at least a portion of the opposite sidewalls of the through-hole 521 and / or the groove 31 are recessed along the first direction X. The first direction X intersects the thickness direction Z of the display panel.

[0079] In these optional embodiments, at least a portion of the hole wall of the through-hole 521 and / or the opposite sidewall of the groove 31 is recessed along the first direction X, and the common layer 7 covers along the recessed area, which can significantly increase the length of the common layer 7, thereby improving its impedance characteristics, suppressing lateral leakage of charge, greatly reducing the degree of crosstalk between adjacent light-emitting pixels 8, and thus ensuring that the display panel still has better brightness and better light emission stability under low brightness and low grayscale conditions.

[0080] In some alternative embodiments, at least a portion of the opposite sidewalls of the through hole 521 and / or the groove 31 have different curvatures of concavity along the first direction X.

[0081] In these optional embodiments, at least a portion of the concave curvature of the hole wall of the through-hole 521 and / or the opposite sidewall of the groove 31 along the first direction X is different, forming an uneven curved structure between the hole wall of the through-hole 521 and the sidewall of the groove 31. This results in the geometry of the through-hole 521 and the groove 31 having different curvatures in the first direction X. Due to the asymmetry of the shapes of the through-hole 521 and the groove 31, the length of the common layer 7 is further increased, and the impedance of the common layer 7 during current flow is increased. Because of the increased impedance of the common layer 7, the current is more impeded during transmission, thereby reducing electrical signal interference between adjacent light-emitting pixels 8 and greatly reducing crosstalk.

[0082] In some alternative embodiments, at least a portion of the bottom of the groove 31 is recessed in the direction toward the substrate 1.

[0083] In these alternative embodiments, at least a portion of the wall of the via 521 and / or the opposing sidewalls of the groove 31 are bent along a first direction X, which intersects the thickness direction Z of the display panel. The geometry of the via 521 and the groove 31 exhibits an asymmetrical bending shape in the first direction X, thereby further increasing the impedance of the common layer 7 during current flow and further enhancing the electrical characteristics and physical stability of the common layer 7.

[0084] In some alternative embodiments, at least a portion of the walls of the through-hole 521 and / or the walls of the groove 31 are deposited with a plurality of insulating particles of different particle sizes. The common layer 7 is capable of expanding at the insulating particles.

[0085] In these alternative embodiments, at least a portion of the wall of the via 521 and / or the wall of the groove 31 is deposited with a plurality of insulating particles of different particle sizes. The common layer 7 is adhered to the surface of the plurality of insulating particles to expand the common layer 7 through the insulating particles, thereby more effectively increasing the length and impedance of the common layer 7 and further improving the problem of crosstalk between adjacent light-emitting pixels 8.

[0086] Optionally, several insulating particles of different particle sizes may be deposited only on the wall of the through-hole 521.

[0087] Optionally, several insulating particles of different particle sizes are deposited on the wall of the through hole 521 and the side and bottom walls of the groove 31.

[0088] Optionally, the insulating particles can be made of the same material as either the pixel definition layer 5 or the planarization layer 3 to ensure adhesion of the insulating particles. The pixel definition layer 5 and the planarization layer 3 can be made of the same material to simplify the display panel manufacturing process. For example, both the pixel definition layer 5 and the planarization layer 3 can be made of organic adhesive.

[0089] In some alternative embodiments, at least a portion of the wall of the through-hole 521 and / or the groove wall of the recess 31 is recessed along the first direction X to form a recess 62. A plurality of insulating particles of different particle sizes are deposited on the surface of the recess 62. The first direction X intersects the thickness direction Z of the display panel.

[0090] In these optional embodiments, to further increase the impedance of the common layer 7, at least a portion of the hole wall of the via 521 and the groove wall of the groove 31 are recessed along the first direction X to form a recess 62. The first direction X intersects the thickness direction Z of the display panel, ensuring that the design of the recess 62 can precisely adjust and optimize the geometry of the common layer 7; due to the increased impedance, the electrical crosstalk problem between adjacent light-emitting pixels 8 is effectively mitigated. At the same time, several insulating particles of different particle sizes are deposited on the surface of the recess 62, so that while extending the length of the common layer 7 through the recess 62, the insulating particles further expand the film of the common layer 7 located on the surface of the insulating ions, thereby more effectively increasing the length and impedance of the common layer 7, and further improving the crosstalk problem between adjacent light-emitting pixels 8.

[0091] In some alternative embodiments, the orthographic projection range of the via 521 onto the substrate 1 is located within the orthographic projection range of the groove 31 onto the substrate 1.

[0092] In these optional embodiments, in order to further enhance the isolation effect of the light-emitting pixels 8 of the display panel, the orthographic projection range of the via 521 on the substrate 1 is located within the orthographic projection range of the groove 31 on the substrate 1, that is, the aperture of the via 521 is smaller than the circumferential dimension of the groove 31, thereby forming a stepped surface between the hole wall of the via 521 and the sidewall of the groove 31, so that the common layer 7 can extend along the hole wall of the via 521, the stepped surface and the sidewall of the groove 31, further increasing the length of the common layer 7, so that the common layer 7 has a greater impedance in structure, effectively reducing the electrical crosstalk between adjacent light-emitting pixels 8.

[0093] In some optional embodiments, the orthographic projection range of the via 521 on the substrate 1 coincides with the orthographic projection range of the groove 31 on the substrate 1, and the aperture of the via 521 at the end along the thickness direction of the display panel and near the common layer 7 is smaller than the aperture of the via 521 at the end along the thickness direction of the display panel and near the planarization layer 3. The via 521 at the end along the thickness direction of the display panel and near the planarization layer 3 is aligned and connected to the groove opening of the groove 31.

[0094] In these optional embodiments, the orthographic projection range of the via 521 onto the substrate 1 coincides with the orthographic projection range of the recess 31 onto the substrate 1, ensuring precise spatial alignment of the via 521 and the recess 31. To optimize the charge blocking characteristics of the common layer 7, the aperture of the via 521 at the end near the common layer 7 along the thickness direction of the display panel is smaller than the aperture of the via 521 at the end near the planarization layer 3 along the thickness direction of the display panel. This design helps improve the electrical impedance of the common layer 7 and reduce crosstalk. Simultaneously, the precise alignment of the via 521 at the end near the planarization layer 3 with the groove opening of the recess 31 further enhances the electrical isolation performance of the recessed structure 6.

[0095] In some alternative embodiments, the orthographic shape of the recessed structure 6 on the substrate 1 is any one of a rectangle, a circle, or a rhombus.

[0096] In these optional embodiments, the shape of the recessed structure 6 can be any one of rectangle, circle, or rhombus. The specific shape can be determined by the process requirements and design needs of the display panel, and this embodiment does not impose a specific limitation on it. Optionally, the orthographic projection shape of the recessed structure 6 onto the substrate 1 is rectangular to simplify the fabrication process.

[0097] In some alternative embodiments, the same blocking region 52 has multiple recessed structures 6. The multiple recessed structures 6 are arranged sequentially at intervals along the vertical direction of two adjacent pixel opening regions 51.

[0098] In these optional embodiments, multiple recessed structures 6 are provided within the same barrier region 52. These recessed structures 6 are arranged sequentially at intervals along the vertical direction of adjacent pixel opening regions 51 to further increase the length of the common layer 7, thereby significantly increasing the impedance of the common layer 7. The increased impedance of the common layer 7 effectively reduces crosstalk between adjacent light-emitting pixels 8, thereby improving the display performance of the display panel and mitigating the degree of crosstalk between the light-emitting pixels 8. By optimizing the arrangement of the recessed structures 6 within the barrier region 52, both the electrical isolation effect and the overall performance of the display device are improved.

[0099] Optionally, the number of recessed structures 6 within the same barrier region 52 can be two, three, four, five, or seven, etc., and this embodiment does not specifically limit this. The specific structures of the multiple recessed structures 6 within the same barrier region 52 can be the same or different, as long as they can effectively extend the length of the common layer 7.

[0100] Please refer to the following: Figures 1 to 4 The second aspect of this application also provides a method for manufacturing a display panel, used to manufacture the display panel, wherein the display device is the display device described in any embodiment of the first aspect of this application. Figure 4 As shown, the method for manufacturing the display device includes:

[0101] Step S01: Prepare a driving backplate layer 2 on one side of substrate 1.

[0102] Step S02: Prepare a planarization layer 3 on the side of the driving backplate layer 2 that is away from the substrate 1.

[0103] Step S03: Prepare a first electrode layer 4 on the side of the planarization layer 3 away from the substrate 1, wherein the first electrode 41 includes a plurality of spaced first electrodes 41.

[0104] Step S04: A pixel definition layer 5 is prepared on the side of the planarization layer 3 away from the substrate 1. The pixel definition layer 5 includes a plurality of pixel opening regions 51 and a plurality of barrier regions 52 located between two adjacent pixel opening regions 51. The pixel opening region 51 has a pixel opening 511, and at least part of the first electrode 41 is exposed from the pixel opening 511.

[0105] Step S05: Open a through hole 521 in the barrier area 52, and set a groove 31 in the area of ​​the planarization layer 3 corresponding to the through hole 521 to prepare a recessed structure 6.

[0106] Step S06: Prepare a common layer 7 on the side of the pixel definition layer 5 away from the substrate 1, and make the common layer 7 cover the surface of the first electrode 41, the pixel definition layer 5 and the recessed structure 6.

[0107] In the second aspect embodiment of this application, firstly, a driving backplane layer 2 is prepared on one side of the substrate 1 in step S01, and then a planarization layer 3 is prepared on the side of the driving backplane layer 2 away from the substrate 1 in step S02; nextly, a first electrode layer 4 is prepared on the side of the planarization layer 3 away from the substrate 1 in step S03, wherein the first electrode 41 includes a plurality of spaced first electrodes 41; then, a pixel definition layer 5 is prepared on the side of the planarization layer 3 away from the substrate 1 in step S04, wherein the pixel definition layer 5 includes a plurality of pixel opening regions 51 and a pixel opening region located between two adjacent pixels. Multiple barrier regions 52 are formed between the opening regions 51. The pixel opening region 51 has a pixel opening 511 so that at least part of the first electrode 41 is exposed from the pixel opening 511. Further, in step S05, through holes 521 are formed in the barrier regions 52, and grooves 31 are formed in the planarization layer 3 in the area corresponding to the through holes 521 to prepare the recessed structure 6. Finally, in step S06, a common layer 7 is prepared on the side of the pixel definition layer 5 away from the substrate 1, and the common layer 7 covers the surface of the first electrode 41, the pixel definition layer 5 and the recessed structure 6, thereby completing the preparation of the display panel. The display panel obtained by this preparation method has a recess in the common layer 7 at the recessed structure 6, which increases the length of the common layer 7 and thus increases the impedance of the common layer 7. The amount of charge transferred between adjacent light-emitting pixels 8 is reduced, the crosstalk problem of the display device is improved, and the charge is not easy to move laterally when a single pixel is lit, thus ensuring the light output brightness and light output uniformity of the display panel.

[0108] Optionally, in step S05, a plasma etching process can be used to etch through-hole 521 and groove 31 in the barrier region 52 and the planarization layer 3, respectively.

[0109] A third aspect of this application also provides a display device, including a display panel as described in any of the embodiments of the first aspect of this application, or including a display panel prepared using the preparation method of a display panel as described in any of the embodiments of the second aspect of this application.

[0110] Since the display panel of the display device of the embodiment of the third aspect of this application includes the display panel provided in any of the first aspect embodiments, or includes a display panel prepared by the preparation method of the display panel provided in any of the second aspect embodiments, the display device of the embodiment of the third aspect of this application has the beneficial effects of the display panel provided in any of the first aspect embodiments, or the display device of the embodiment of the third aspect of this application has the beneficial effects of the preparation method of the display panel provided in any of the second aspect embodiments, which will not be repeated here.

[0111] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0112] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; A driving backplane layer, the driving backplane layer being located on one side of the substrate; A planarization layer, the planarization layer covering the side of the drive backplane layer opposite to the substrate; A first electrode layer is disposed on the side of the planarization layer opposite to the drive backplane layer, and the first electrode layer includes a plurality of spaced first electrodes. A pixel definition layer is located on the side of the planarization layer opposite to the substrate. The pixel definition layer includes a plurality of pixel opening regions and a plurality of barrier regions located between two adjacent pixel opening regions. The pixel opening regions have pixel openings, and at least a portion of the first electrode is exposed from the pixel openings. The barrier region has a through hole, and the planarization layer has a groove in the area corresponding to the through hole. The through hole and the groove are connected to form a recessed structure in the barrier region and the planarization layer. A common layer covers the surfaces of the first electrode, the pixel definition layer, and the recessed structure.

2. The display panel according to claim 1, characterized in that, The surface of the recessed structure is provided with a plurality of spaced protrusions; Preferably, the plurality of protrusions are located at the bottom of the groove; Preferably, the plurality of protrusions are spaced apart across all areas of the surface of the recessed structure; Preferably, the surface of the recessed structure has a plurality of wavy areas corresponding to the protrusions; Preferably, the surface of the recessed structure is further provided with multiple notches, and the multiple protrusions and multiple notches are arranged alternately.

3. The display panel according to claim 1, characterized in that, At least a portion of the hole wall of the through hole and / or the opposite side wall of the groove is recessed along a first direction, which intersects the thickness direction of the display panel. Preferably, at least a portion of the opposite sidewalls of the through hole and / or the groove have different curvatures of concavity along the first direction; Preferably, at least a portion of the bottom of the groove is recessed in the direction toward the substrate.

4. The display panel according to claim 1, characterized in that, At least a portion of the wall of the through hole and / or the wall of the groove is deposited with a plurality of insulating particles of different particle sizes, and the common layer is capable of expanding at the insulating particles.

5. The display panel according to claim 4, characterized in that, At least a portion of the wall of the through hole and / or the groove wall of the groove is recessed inward along a first direction to form a recessed portion; a plurality of insulating particles of different particle sizes are deposited on the surface of the recessed portion; the first direction intersects the thickness direction of the display panel.

6. The display panel according to claim 1, characterized in that, The orthographic projection range of the through hole on the substrate is located within the orthographic projection range of the groove on the substrate; Alternatively, the orthographic projection range of the via on the substrate coincides with the orthographic projection range of the groove on the substrate, and the aperture of the via at one end along the thickness direction of the display panel and near the common layer is smaller than the aperture of the via at one end along the thickness direction of the display panel and near the planarization layer, and the via at one end along the thickness direction of the display panel and near the planarization layer is aligned and connected to the groove opening.

7. The display panel according to any one of claims 1-6, characterized in that, The recessed structure has a rectangular, circular, or rhomboid shape when projected onto the substrate.

8. The display panel according to any one of claims 1-6, characterized in that, The same blocking region has multiple recessed structures, and the multiple recessed structures are arranged sequentially at intervals along the vertical direction of two adjacent pixel opening regions.

9. A method for manufacturing a display panel, characterized in that, The display device is the display panel according to any one of claims 1-8, and the method for manufacturing the display panel includes: The driving backplate layer is prepared on one side of the substrate; The planarization layer is prepared on the side of the drive backplane layer opposite to the substrate; The first electrode layer is prepared on the side of the planarization layer opposite to the substrate, wherein the first electrode includes a plurality of spaced-apart first electrodes; The pixel definition layer is prepared on the side of the planarization layer opposite to the substrate. The pixel definition layer includes a plurality of pixel opening regions and a plurality of barrier regions located between two adjacent pixel opening regions. The pixel opening regions have pixel openings, and at least a portion of the first electrode is exposed from the pixel openings. The through-hole is formed in the barrier area, and a groove is formed in the planarization layer corresponding to the through-hole to prepare the recessed structure; The common layer is prepared on the side of the pixel definition layer opposite to the substrate, and the common layer covers the surface of the first electrode, the pixel definition layer and the recessed structure.

10. A display device, characterized in that, It includes the display panel as described in any one of claims 1-8, or the display panel prepared by the method for preparing a display panel as described in claim 9.

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