Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, comprising a plurality of pixel circuits, a plurality of first signal lines and a first shielding electrode; the pixel circuit comprises a first transistor, a second transistor and a first node, the first transistor and the second transistor are electrically connected with the first node; the first signal line extends along a first direction; the plurality of pixel circuits comprise a first type of pixel circuit, in the same first type of pixel circuit, the first transistor and the second transistor are respectively located on both sides of the first signal line in a second direction, and the first node and the first signal line overlap in a direction perpendicular to the plane where the display panel is located, and the second direction intersects the first direction; the first shielding electrode covers the first node in the first type of pixel circuit in a direction perpendicular to the plane where the display panel is located. The first shielding electrode can alleviate the signal interference problem between the first node and the first signal line, thereby improving the accurate presentation of the display panel on the brightness of the display picture.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] When a display panel includes self-emissive light-emitting devices, it typically also includes pixel circuitry to drive the light-emitting devices to emit light. However, the signals received by the pixel circuitry can become inaccurate due to interference, which in turn affects the display panel's ability to accurately reproduce the brightness, color, and other aspects of the image. Summary of the Invention

[0003] Based on this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0004] In a first aspect, embodiments of this application provide a display panel, including multiple pixel circuits, multiple first signal lines, and a first shielding electrode; the pixel circuits include a first transistor, a second transistor, and a first node, both the first transistor and the second transistor being electrically connected to the first node; the first signal lines extend along a first direction; the multiple pixel circuits include a first type of pixel circuit, in the same first type of pixel circuit, the first transistor and the second transistor are respectively located on both sides of the first signal line in a second direction, and the first node and the first signal line overlap in a direction perpendicular to the plane of the display panel, the second direction intersecting the first direction; the first shielding electrode covers the first node in the first type of pixel circuit in a direction perpendicular to the plane of the display panel.

[0005] In one implementation of the first aspect, the display panel further includes a light-emitting device electrically connected to a first node; the pixel circuit further includes a driving transistor, the first electrode of a second transistor is connected to the driving transistor and the second electrode is connected to the light-emitting device; the gates of a plurality of second transistors arranged along a first direction are connected to the same scan line; the first signal line overlaps with the first node in a plurality of first-type pixel circuits arranged along the first direction.

[0006] In one implementation of the first aspect, the display panel further includes multiple data lines arranged along a first direction and extending along a second direction, the data lines being electrically connected to the pixel circuit; and the first signal line being electrically connected to the data lines.

[0007] In one implementation of the first aspect, the display panel includes a first region and a second region, and a first signal line is located in the first region; both the first region and the second region include a first shielding electrode.

[0008] In one implementation of the first aspect, the display panel includes a first region and a second region, with the first signal line and the first shielding electrode both located in the first region.

[0009] In one implementation of the first aspect, the pixel circuit further includes a third transistor; the plurality of first-type pixel circuits include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit are arranged adjacent to each other along a second direction; wherein the first transistor in the first pixel circuit and the third transistor in the second pixel circuit are located on the same side of the first signal line in the second direction, and the gate of the first transistor in the first pixel circuit and the gate of the third transistor in the second pixel circuit are connected to the same scan line.

[0010] In one implementation of the first aspect, the display panel further includes a light-emitting device electrically connected to a first node; a first electrode of a first transistor is connected to a first reset signal line, and a second electrode is connected to the first node; the pixel circuit further includes a driving transistor, a first electrode of a third transistor is connected to a second reset signal line, and a second electrode is connected to the gate of the driving transistor.

[0011] In one implementation of the first aspect, the first shielding electrode is connected to the second reset signal line.

[0012] In one implementation of the first aspect, the first shielding electrode and the second reset signal line are disposed on the same layer.

[0013] In one implementation of the first aspect, the second reset signal line includes a first trace segment connected to two first shielding electrodes; the first trace segment partially overlaps with the first signal line along a direction perpendicular to the plane of the display panel.

[0014] In one implementation of the first aspect, the second reset signal line includes a first trace segment connected to two first shielding electrodes; the second reset signal line also includes a second trace segment not connected to the first shielding electrodes, and the distance between the first trace segment and the first signal line is less than the distance between the second trace segment and the first signal line.

[0015] In one implementation of the first aspect, the second reset signal line includes a first trace segment, the first signal line includes a third trace segment, and both the third trace segment and the first trace segment overlap with two first nodes in a direction perpendicular to the plane of the display panel; along the direction perpendicular to the plane of the display panel, the orthographic projection of the first trace segment covers the orthographic projection of the third trace segment; the portion where the first trace segment intersects with the first node is multiplexed as a first shielding electrode.

[0016] In one implementation of the first aspect, first-type pixel circuits arranged adjacent to each other along a first direction are arranged symmetrically about a symmetry axis extending along a second direction; the plurality of first-type pixel circuits arranged adjacent to each other along the first direction include a first pixel circuit, a third pixel circuit, and a fourth pixel circuit; the first pixel circuit and the third pixel circuit are arranged adjacent to each other along the first direction, and the third pixel circuit and the fourth pixel circuit are arranged adjacent to each other along the first direction; the distance between the first node of the first pixel circuit and the first node of the third pixel circuit is less than the distance between the first node of the third pixel circuit and the first node of the fourth pixel circuit.

[0017] In one implementation of the first aspect, the first shielding electrode overlapping with the first pixel circuit and the first pixel circuit arranged adjacent to each other along the first direction are integral structures.

[0018] In one implementation of the first aspect, the pixel circuit further includes a second node connected to a third transistor; the display panel further includes a second shielding electrode that covers the second node in the first type of pixel circuit along a direction perpendicular to the plane of the display panel.

[0019] In one implementation of the first aspect, the first shielding electrode and the second shielding electrode are connected to the same signal line, and the second shielding electrode is located on the side of the signal line away from the first signal line.

[0020] In one implementation of the first aspect, first-type pixel circuits arranged adjacent to each other along a first direction are symmetrically arranged about a symmetry axis extending along a second direction; the plurality of first-type pixel circuits arranged adjacent to each other along the first direction include a fifth pixel circuit, a sixth pixel circuit, and a seventh pixel circuit; the fifth pixel circuit and the sixth pixel circuit are arranged adjacent to each other along the first direction, and the sixth pixel circuit and the seventh pixel circuit are arranged adjacent to each other along the first direction; the distance between the second node of the fifth pixel circuit and the second node of the sixth pixel circuit is greater than the distance between the second node of the sixth pixel circuit and the second node of the seventh pixel circuit; in the sixth pixel circuit and the seventh pixel circuit arranged adjacent to each other along the first direction, the second shielding electrode overlapping with the sixth pixel circuit and the second shielding electrode overlapping with the seventh pixel circuit are integral structures.

[0021] Secondly, embodiments of this application provide a display device, including the display panel provided in the first aspect.

[0022] The shielding effect of the first shielding electrode can alleviate the signal interference problem between the first node and the first signal line, improve the problem of large fluctuations in the signal transmitted on the first signal line when the potential of the first node changes continuously, and thus improve the display panel's accurate representation of the brightness of the displayed image. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This is an equivalent schematic diagram of a pixel circuit related to an embodiment of this application; Figure 3 A partial schematic diagram of a display panel provided in an embodiment of this application; Figure 4 A schematic diagram of a display panel provided in an embodiment of this application; Figure 5 A schematic diagram of a display panel provided in an embodiment of this application; Figure 6 A partial schematic diagram of a display panel provided in an embodiment of this application; Figure 7 A partial schematic diagram of a display panel provided in an embodiment of this application; Figure 8 for Figure 3 and Figure 7 A partially enlarged schematic diagram; Figure 9 for Figure 3 and Figure 7 Another enlarged partial schematic diagram; Figure 10 A partial schematic diagram of a display panel provided in an embodiment of this application; Figure 11 A partial schematic diagram of a display panel provided in an embodiment of this application; Figure 12 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0025] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0027] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms "a" and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0028] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "roughly", "generally" and "generally" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0030] It should be understood that although terms such as "first," "second," etc., may be used to describe transistors and the like in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish transistors and the like from one another. For example, without departing from the scope of the embodiments of this application, a first transistor may also be referred to as a second transistor, and similarly, a second signal line may also be referred to as a first transistor. Through meticulous and in-depth research, the applicant of this application has provided a solution to the problems existing in the prior art.

[0031] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application, such as... Figure 1 As shown, the display panel 01 includes multiple pixel circuits 10, which drive the pixels in the display panel 01 to emit light. The display panel 01 may also include multiple light-emitting devices 20, with the pixel circuits 10 electrically connected to and driving the light-emitting devices 20 to emit light. The light-emitting devices 20 may be at least one of organic light-emitting diodes (OLEDs), micro-LEDs, or mini-LEDs.

[0032] The function of the pixel circuit 10 directly affects the light emission effect of the display panel 01. The pixel circuit 10 should stably and accurately drive the light-emitting device 20 to emit light of a preset brightness. In order to achieve this purpose, the pixel circuit 10 includes not only one transistor, but multiple transistors working together. Figure 2 This is an equivalent schematic diagram of a pixel circuit related to an embodiment of this application, such as... Figure 2As shown, the pixel circuit 10 includes a first transistor M1, a second transistor M2, and a first node N1. Both the first transistor M1 and the second transistor M2 are electrically connected to the first node N1. Therefore, the first transistor M1 and the second transistor M2 are electrically connected through the first node N1, and both the first transistor M1 and the second transistor M2 will change the potential of the first node N1 when they are turned on.

[0033] In addition, such as Figure 1 As shown, the display panel 01 also includes multiple first signal lines L1, which extend along a first direction X. The multiple pixel circuits 10 include a first type of pixel circuit 10a. Within the same first type of pixel circuit 10a, such as... Figure 3 As shown, Figure 3 This is a partial schematic diagram of a display panel provided in an embodiment of this application. A first transistor M1 and a second transistor M2 are located on opposite sides of a first signal line L1 in a second direction Y. The second direction Y intersects with the first direction X, and the structure used to connect the first transistor M1 and the second transistor M2 intersects with the first signal line L1. Specifically, a first node N1 overlaps with the first signal line L1 in a direction perpendicular to the plane of the display panel 01. That is, the portion of the structure used to connect the first transistor M1 and the second transistor M2 that intersects with the first signal line L1 is the first node N1. When the potential of the first node N1 changes when the first transistor M1 is turned on and / or the second transistor M2 is turned on, it affects the potential of the first signal line L1 through coupling, thereby affecting the display effect of the display panel 01. The first transistor M1 and the second transistor M2 can be connected through a semiconductor structure.

[0034] like Figure 3 As shown, the display panel 01 provided in this embodiment further includes a first shielding electrode 11, which covers the first node N1 in the first type of pixel circuit 10a along a direction perpendicular to the plane where the display panel 01 is located. The shielding effect of the first shielding electrode 11 can alleviate the signal interference problem between the first node N1 and the first signal line L1, improve the problem of large fluctuations in the signal transmitted on the first signal line L1 when the potential of the first node N1 changes continuously, and thus improve the accuracy of the display panel 01 in displaying the brightness and color of the image.

[0035] Wherein, along the thickness direction perpendicular to the plane where the display panel 01 is located, the first shielding electrode 11 may be located between the first node N1 and the first signal line L1, and / or the first shielding electrode 11 may also be located on the side of the first signal line L1 away from the first node N1.

[0036] Figure 4 This is a schematic diagram of a display panel provided in an embodiment of this application, such as... Figure 4As shown, the display panel 01 also includes multiple data lines DL arranged along the first direction X and extending along the second direction Y. The data lines DL are electrically connected to the pixel circuit 10; a first signal line L1 is electrically connected to the data lines DL. The first signal line L1 can be a portion of the FIAA trace extending along the first direction X. The FIAA trace mainly extends within the display area AA of the display panel 01, with one end electrically connected to the data lines DL and the other end electrically connected to the fan-shaped trace within the bonding area NA. Figure 4 As shown, the first signal line L1 includes a portion extending along the first direction X and a portion extending along the second direction Y. The first signal line L1 is the portion extending along the first direction in the FIAA trace. Then, the first nodes N1 of the multiple first-type pixel circuits 10a arranged along the first direction X can overlap with the first signal line L1 in a direction perpendicular to the plane where the display panel 01 is located.

[0037] The first signal line L1 is part of the signal line connecting the pins in the data line DL and the bonding area NA, used to transmit the data voltage received by the pins to the data line DL. When multiple first nodes N1 in the first type of pixel circuits 10a arranged along the first direction X overlap with the first signal line L1 that transmits the data voltage, the voltage on the first signal line L1 is greatly affected by the potential changes of the multiple first nodes N1, resulting in severe distortion of the data voltage transmitted from the first signal line L1 to the data line DL. However, by adopting the inventive concept of this application and setting a shielding electrode covering the first nodes N1 in the first type of pixel circuit 10a, significant distortion of the data voltage transmitted from the first signal line L1 to the data line DL can be avoided, thereby ensuring that the pixel circuit 10 drives the light-emitting device 20 to emit a more ideal brightness.

[0038] like Figure 4 As shown, the display panel 01 includes a first region R1 and a second region R2, wherein a first signal line L1 is located in the first region R1. The first region R1 and the second region R2 are located in different regions of the display panel 01. The region can be determined as the first region R1 and the second region R2 according to whether the first signal line L1 is included in the region. The first region R1 includes the first signal line L1 and the second region R2 includes the first signal line L1.

[0039] Furthermore, the display panel may also include a second type of pixel circuit, wherein the first pixel circuit 101 is located in the first region R1, and at least a portion of the second type of pixel circuit is located in the second region, wherein the second pixel circuit may not include the first shielding electrode 11. In one implementation, all pixel circuits 10 in the first region R1 are first type pixel circuits 10a and all pixel circuits 10 in the second region R2 are second type pixel circuits; in another implementation, the pixel circuits 10 in the first region R1 include both first type pixel circuits 10a and second type pixel circuits, and all pixel circuits 10 in the second region R2 are second type pixel circuits.

[0040] In one embodiment of this application, such as Figure 4 As shown, both the first region R1 and the second region R2 include a first shielding electrode 11. That is, the first shielding electrode 11 is provided in both the region of the display panel 01 that includes the first signal line L1 and the region that does not include the first signal line L1. The first shielding electrode 11 in the first region R1 is used to mitigate the influence of the potential of the first node N1 on the voltage transmitted by the first signal line L1. The first shielding electrode 11 in the second region R2 ensures that the first shielding electrodes 11 are uniformly distributed within the display panel 01, increasing the visual uniformity of the display panel 01 and the uniformity of signal variations caused by the first shielding electrode 11 within the display panel 01.

[0041] In one embodiment of this application, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a display panel provided in an embodiment of this application. The first signal line L1 and the first shielding electrode 11 are both located in the first region R1. That is, the first shielding electrode 11 is only disposed in the region where the first signal line L1 is located, in order to reduce the influence of the potential change of the first node N1 in the first type of pixel circuit 10a on the signal transmitted by the first signal line L1, and to avoid the influence on the lines in other regions.

[0042] like Figure 1 and Figure 2 As shown, the display panel 01 also includes a light-emitting device 20, which is also electrically connected to the first node N1. For example, the anode of the light-emitting device 20 is electrically connected to the first node N1. When the light-emitting device 20 switches from a non-light-emitting state to a light-emitting state or from a light-emitting state to a non-light-emitting state, the potential of the first node N1, which is electrically connected to it, will change.

[0043] refer to Figure 2The pixel circuit 10 in the display panel 01 provided in this application embodiment further includes a driving transistor M0, wherein the first terminal of the second transistor M2 is connected to the driving transistor M0 and the second terminal is connected to the light-emitting device 20. The second transistor M2 is electrically connected between the driving transistor M0 and the light-emitting device 20 and is used to control the conduction state between the driving transistor M0 and the light-emitting device 20. When the second transistor M2 is turned on, the driving transistor M0 can be electrically connected to the light-emitting device 20 and transmit driving current to the light-emitting device 20. Figure 6 This is a partial schematic diagram of a display panel provided in an embodiment of this application, such as... Figure 6 As shown, the gates of a plurality of second transistors M2 arranged along the first direction X are connected to the same scan line. The same scan line can control the plurality of second transistors M2 arranged along the first direction X to be turned on or off simultaneously. In other words, it can control the light-emitting devices 20 that are electrically connected to the plurality of first-type pixel circuits 10a arranged along the first direction X to switch from a non-light-emitting state to a light-emitting state or from a light-emitting state to a non-light-emitting state.

[0044] In addition, such as Figure 6 As shown, the first signal line L1 overlaps with the first node N1 of a plurality of first-type pixel circuits 10a arranged along the first direction X. When the plurality of first-type pixel circuits 10a arranged along the first direction X simultaneously control the light-emitting device 20 electrically connected to them to start or stop emitting light, the potential of the first node N1 in the plurality of first-type pixel circuits 10a will change, and the potential on the first signal line L1 that overlaps with the plurality of first nodes N1 in the direction perpendicular to the plane where the display panel 01 is located will show obvious fluctuations. However, the embodiments of this application can significantly improve the problem of the potential on the first signal line L1 being interfered with by the first-type pixel circuits 10a by setting the first shielding electrode 11.

[0045] like Figure 2 As shown, the pixel circuit 10 also includes a third transistor M3; Figure 7 This is a partial schematic diagram of a display panel provided in an embodiment of this application, such as... Figure 7As shown, the plurality of first-type pixel circuits 10a include a first pixel circuit 101 and a second pixel circuit 102, and the first pixel circuit 101 and the second pixel circuit 102 are arranged adjacently along the second direction Y. For example, the first pixel circuit 101 and the second pixel circuit 102 are arranged adjacently along the column direction. It should be noted that the pixel circuit 10 has a certain width in the second direction Y. Here, most of the first pixel circuit 101 and most of the second pixel circuit 102 are arranged along the column direction. The first transistor M1 in the first pixel circuit 101 and the third transistor M3 in the second pixel circuit 102 are located on the same side of the first signal line L1 in the second direction Y. The first signal line L1 can be located substantially between the first pixel circuit 101 and the second pixel circuit 102. The first pixel circuit 101 and the second pixel circuit 102, which are arranged substantially adjacently along the second direction Y, are each substantially located on both sides of the first signal line L1. The first transistor M1 in the first pixel circuit 101 can be positioned across the first signal line L1 and can be located at a position that slightly overlaps with the second pixel circuit 102 in the first direction X. The gate of the first transistor M1 in the first pixel circuit 101 and the gate of the third transistor M3 in the second pixel circuit 102 are connected to the same scan line S2. When the first transistor M1 in the first pixel circuit 101 and the third transistor M3 in the second pixel circuit 102 are located on the same side of the first signal line L1 in the second direction Y, it is beneficial to realize that the gates of the first transistor M1 in the first pixel circuit 101 and the third transistor M3 in the second pixel circuit 102 share the scan line S2.

[0046] Please continue to refer to this. Figure 2 The display panel 01 also includes a light-emitting device 20, which is electrically connected to a first node N1. The first terminal of the first transistor M1 is connected to a first reset signal line RL1, and its second terminal is connected to the first node N1. When the first transistor M1 is turned on, it can transmit the reset voltage transmitted by the first reset signal line RL1 to the first node N1, thus resetting the terminal of the light-emitting device 20 that is electrically connected to the pixel circuit 10. The pixel circuit 10 also includes a driving transistor M0. The first terminal of a third transistor M3 is connected to a second reset signal line RL2, and its second terminal is connected to the gate of the driving transistor M0. When the third transistor M3 is turned on, it can transmit the reset voltage transmitted by the second reset signal line RL2 to the gate of the driving transistor M0, thus resetting the gate of the driving transistor M0. Figure 7As shown, when the gate of the first transistor M1 in the first pixel circuit 101 and the gate of the third transistor M3 in the second pixel circuit 102 are connected to the same scan line S2, the reset of the light-emitting device 20 electrically connected to the first pixel circuit 101 and the reset of the driving transistor M0 in the second pixel circuit 102 can be performed simultaneously.

[0047] It should be noted that the first transistor M1 in the first pixel circuit 101 and the third transistor M3 in the second pixel circuit 102, which are arranged adjacently along the second direction Y, may overlap in the second direction Y, share the scan line S2, and share the reset signal line. Therefore, the first reset signal line RL1 electrically connected to the first transistor M1 in the first pixel circuit 101 and the second reset signal line RL2 electrically connected to the third transistor M3 in the second pixel circuit 102 can actually be the same reset signal line. The reason for distinguishing between the first reset signal line RL1 and the second reset signal line RL2 is that the first transistor M1 and the third transistor M3 in the same pixel circuit 10 are electrically connected to different reset signal lines, for example, they are electrically connected to the first reset signal line RL1 and the second reset signal line RL2, respectively.

[0048] In addition, such as Figure 2 As shown, the pixel circuit 10 may further include a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 is electrically connected to the first terminal of the driving transistor M0, and the fifth transistor M5 is electrically connected between the first terminal and the gate of the driving transistor M0. When the fourth transistor M4 and the fifth transistor M5 are turned on, the data voltage on the data line DL can be written to the gate of the driving transistor M0. Furthermore, it may also include a sixth transistor M6, which is electrically connected to either the first or second terminal of the driving transistor M0, for writing the power supply voltage to the driving transistor M0. Additionally, the pixel circuit 10 may also include a storage capacitor Cst, and the storage capacitor Cst is electrically connected to the gate of the driving transistor M0.

[0049] It should be noted that, Figure 2 The illustration shows a pixel circuit 10 related to an embodiment of this application. Furthermore, the inventive concept of this application is also applicable to display panels 01 including other structures.

[0050] In one embodiment of this application, such as Figure 3 and Figure 7As shown, the first shielding electrode 11 is connected to the second reset signal line RL2. The second reset signal line RL2 can provide a stable potential signal to the first shielding electrode 11, so that the first shielding electrode 11 can obtain a better shielding effect. In addition, the second reset signal line RL2 is electrically connected to the third transistor M3. Therefore, the first node N1 of the first transistor M1 in the first pixel circuit 101, which shares a scan line with the third transistor M3 in the second pixel circuit 102, is close to the reset signal line. Thus, the first shielding electrode 11, which overlaps with the first node N1, is close to the second reset signal line RL2, and the two can be easily connected.

[0051] In one technical solution, the first shielding electrode 11 and the second reset signal line RL2 are arranged in the same layer. The first shielding electrode 11 can be regarded as the extension of the second reset signal line RL2 extending to the first node N1. The preparation of the first shielding electrode 11 is simple. It can also avoid the difficulty of laying the line by increasing the space occupied by the connection structure when the two are electrically connected by means of vias or overlaps.

[0052] Figure 8 for Figure 3 and Figure 7 A partially enlarged schematic diagram, Figure 9 for Figure 3 and Figure 7 Another enlarged partial schematic diagram, such as Figure 8 and Figure 9 As shown, the second reset signal line RL2 includes a first trace segment RL21, which is connected to the first shielding electrode 11; in addition, the second reset signal line RL2 may also include a second trace segment RL22, which is not connected to the first shielding electrode 11.

[0053] In one embodiment of this application, such as Figure 8 As shown, along the direction perpendicular to the plane where the display panel 01 is located, the first trace segment RL21 partially overlaps with the first signal line L1, and the first node N1 also overlaps with the first signal line L1. Therefore, the distance between the first trace segment RL21 and the first node N1 in the second direction Y is closer, and the first shielding electrode 11 connected to the first trace segment RL21 is more likely to overlap with the first node N1 in the direction perpendicular to the plane where the display panel 01 is located.

[0054] In one embodiment of this application, as shown in Figure 9, the distance between the first trace segment RL21 and the first signal line L1 is less than the distance between the second trace segment RL22 and the first signal line L1. The first signal line L1 and the first reset signal line RL1 can be arranged substantially parallel. However, compared to the second trace segment RL22 which is not connected to the first shielding electrode 11, the first trace segment RL21 connected to the first shielding electrode 11 is designed to be closer to the first signal line L1. Since the first node N1 overlaps with the first signal line L1, it is easier for the first shielding electrode 11 to overlap with the first node N1 in a direction perpendicular to the plane of the display panel 01. The first shielding electrode 11 can be considered as a protruding structure of the first trace segment RL21 facing the first node N1.

[0055] In addition, such as Figure 8 and Figure 9 As shown, the first trace segment RL21 can be connected to two first shielding electrodes 11 simultaneously, meaning that one of the first trace segments RL21 in the second reset signal line RL2 is simultaneously connected to the first shielding electrodes 11 in the regions where the two pixel circuits 10 are located. By reducing the number of times the first trace segment RL21 and the second trace segment RL22 are alternately set in the second reset signal line RL2, the number of width changes and / or position changes of the second reset signal line RL2 during etching is relatively small. This reduces process defects at the width and position changes of the second reset signal line RL2, thereby increasing the process yield when forming the first trace segment RL21.

[0056] Figure 10 This is a partial schematic diagram of a display panel provided in an embodiment of this application. In one embodiment of this application, as shown... Figure 10 As shown, the second reset signal line RL2 includes a first trace segment RL21, and the first signal line L1 includes a third trace segment L11. Both the third trace segment L11 and the first trace segment RL21 overlap with the first node N1 in a direction perpendicular to the plane of the display panel 01. Along the direction perpendicular to the plane of the display panel 01, the orthographic projection of the first trace segment RL21 covers the orthographic projection of the third trace segment L11. The first node N1 is the portion that overlaps with the third trace segment L11 in the plane perpendicular to the display panel 01. Therefore, the portion of the first trace segment RL21 that overlaps with the first node N1 is multiplexed as the first shielding electrode 11. This can be understood as a widened section of the second reset signal line RL2, with the portion overlapping with the first node N1 being multiplexed as the first shielding electrode 11.

[0057] In addition, such as Figure 10As shown, the third trace segment L11 and the first trace segment RL21 both overlap with the two first nodes N1 in a direction perpendicular to the plane of the display panel 01. That is, one of the third trace segments L11 in the first signal line L1 and one of the first trace segments RL21 in the second reset signal line RL2 are simultaneously connected to the first shielding electrode 11 in the area where the two pixel circuits 10 are located. By reducing the number of times the first trace segment RL21 and the second trace segment RL22 are alternately set in the second reset signal line RL2, the number of width changes and / or position changes of the second reset signal line RL2 are relatively small when etching to form the second reset signal line RL2. This reduces the process defects at the width and position changes of the second reset signal line RL2, thereby increasing the process yield when forming the first trace segment RL2.

[0058] In one embodiment of this application, such as Figure 6 As shown, the first type of pixel circuits 10a, arranged adjacent to each other along the first direction X, are symmetrically arranged about an axis of symmetry extending along the second direction Y. (Reference) Figure 6 The plurality of first-type pixel circuits 10a arranged adjacent to each other along the first direction X include a first pixel circuit 101, a third pixel circuit 103, and a fourth pixel circuit 104. The first pixel circuit 101 and the third pixel circuit 103 are arranged adjacent to each other along the first direction X, and the third pixel circuit 103 and the fourth pixel circuit 104 are arranged adjacent to each other along the first direction X. In this embodiment, the pixel circuits 10a arranged adjacent to each other along the first direction X are symmetrically arranged. Therefore, the first pixel circuit 101 and the third pixel circuit 103 are symmetrically arranged about an axis of symmetry extending along the second direction Y, and the third pixel circuit 103 and the fourth pixel circuit 104 are symmetrically arranged about an axis of symmetry extending along the second direction Y. In this way, the distance between the first node N1 of the first pixel circuit 101 and the first node N1 of the third pixel circuit 103 can be less than the distance between the first node N1 of the third pixel circuit 103 and the first node N1 of the fourth pixel circuit 104. Therefore, in the multiple first-type pixel circuits 10a arranged sequentially along the first direction X, each pair of first-type pixel circuits 10a forms a group, and the distance between the first nodes N1 of the two first-type pixel circuits 10a in the same group is closer. The first shielding electrodes 11 that overlap with the first nodes N1 in the group of first-type pixel circuits 10a are more concentrated, avoiding excessive influence on the setting of other lines and reducing the difficulty of setting the first shielding electrodes 11.

[0059] In one technical solution, in the first pixel circuit 101 and the third pixel circuit 103 arranged adjacent to each other along the first direction X, reference is made to... Figure 10The first shielding electrode 11 overlapping with the first pixel circuit 101 and the first shielding electrode 11 overlapping with the third pixel circuit 103 are integrated into a single structure. Since the first pixel circuit 101 and the third pixel circuit 103 are symmetrically arranged along the first direction X and their first nodes N1 are close to each other, by integrating the first shielding electrode 11 overlapping with the first node N1 of the first pixel circuit 101 and the first shielding electrode 11 overlapping with the first node N1 of the third pixel circuit 103 into a single structure, the area of ​​the first shielding electrode 11 will not be too large, thus avoiding excessive interference with the layout of other lines; the area of ​​the first shielding electrode 11 will also not be too small, thus better shielding the signal interference of the first node N1 to the first signal line L1.

[0060] In one embodiment of this application, the pixel circuit 10 further includes a second node N2, which is connected to a third transistor M3. For example... Figure 7 As shown, the display panel 01 also includes a second shielding electrode 12, which covers the second node N2 in the first type of pixel circuit 10a along a direction perpendicular to the plane where the display panel 01 is located. The second shielding electrode 12 can shield the signal changes of the second node N2 from the influence of signals transmitted on other signal lines, and can also shield the potential changes of the second node N2 from the influence of signal changes on other signal lines.

[0061] In one technical solution, the first shielding electrode 11 and the second shielding electrode 12 are connected to the same signal line, for example, as shown below. Figure 7 As shown, all are electrically connected to the second reset signal line RL2. The second shielding electrode 12 is located on the side of the signal line furthest from the first signal line L1, for example, as... Figure 7 As shown, when the second shielding electrode 12 is electrically connected to the second reset signal line RL2, the second shielding electrode 12 is located on the side of the second reset signal line RL2 away from the first signal line L1. Therefore, the second shielding electrode 12 can shield the mutual influence between the first signal line L1 and the second reset signal line RL2.

[0062] In one embodiment of this application, such as Figure 11 As shown, Figure 11 This is a partial schematic diagram of a display panel provided in an embodiment of this application. The first type of pixel circuits 10a, arranged adjacent to each other along the first direction X, are symmetrically arranged about a symmetry axis extending along the second direction Y. (Reference) Figure 11The plurality of first-type pixel circuits 10a arranged adjacent to each other along the first direction X include a fifth pixel circuit 105, a sixth pixel circuit 106, and a seventh pixel circuit 107; the fifth pixel circuit 105 and the sixth pixel circuit 106 are arranged adjacent to each other along the first direction X, and the sixth pixel circuit 106 and the seventh pixel circuit 107 are arranged adjacent to each other along the first direction X. In this embodiment, the pixel circuits 10 arranged adjacent to each other along the first direction X are symmetrically arranged, so the fifth pixel circuit 105 and the sixth pixel circuit 106 are symmetrically arranged about a symmetry axis extending along the second direction Y, and the sixth pixel circuit 106 and the seventh pixel circuit 107 are symmetrically arranged about a symmetry axis extending along the second direction Y. In this way, the distance between the second node N2 of the sixth pixel circuit 106 and the second node N2 of the seventh pixel circuit 107 can be less than the distance between the second node N2 of the fifth pixel circuit 105 and the second node N2 of the sixth pixel circuit 106. Therefore, in the multiple first-type pixel circuits 10a arranged sequentially along the first direction X, each pair of first-type pixel circuits 10a forms a group, and the distance between the second nodes N2 of the two first-type pixel circuits 10a in the same group is closer. The second shielding electrodes 12 that overlap with the second nodes N2 in the group of first-type pixel circuits 10a are more concentrated, avoiding excessive influence on the setting of other lines and reducing the difficulty of setting the second shielding electrodes 12.

[0063] In the sixth pixel circuit 106 and the seventh pixel circuit 107, which are arranged adjacently along the first direction X, the second shielding electrode 12 overlapping with the sixth pixel circuit 106 and the second shielding electrode 12 overlapping with the seventh pixel circuit 107 are integrated into a single structure. Since the sixth pixel circuit 106 and the seventh pixel circuit 107 are symmetrically arranged along the first direction X and their second nodes N2 are close to each other, by integrating the second shielding electrode 12 overlapping with the second node N2 of the sixth pixel circuit 106 and the second shielding electrode 12 overlapping with the second node N2 of the seventh pixel circuit 107 into a single structure, the area of ​​the second shielding electrode 12 will not be too large, thus avoiding excessive interference with the layout of other lines; the area of ​​the second shielding electrode 12 will also not be too small, thus better shielding the signal interference of the second node N2 to the first signal line L1.

[0064] Figure 12 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 12 As shown, this application embodiment also provides a display device 001, including the display panel 01 provided in any of the above embodiments. Of course, Figure 12 The display device 001 shown is for illustrative purposes only. The display device 001 can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0065] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, or combinations of different embodiments made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits, each pixel circuit including a first transistor, a second transistor, and a first node, wherein the first transistor and the second transistor are both electrically connected to the first node; Multiple first signal lines extend along a first direction; the multiple pixel circuits include a first type of pixel circuit, in which the first transistor and the second transistor are respectively located on both sides of the first signal line in a second direction, and the first node overlaps with the first signal line in a direction perpendicular to the plane of the display panel, and the second direction intersects with the first direction; A first shielding electrode covers the first node in the first type of pixel circuit along a direction perpendicular to the plane where the display panel is located.

2. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting device, which is electrically connected to the first node; the pixel circuit further includes a driving transistor, wherein the first terminal of the second transistor is connected to the driving transistor and the second terminal is connected to the light-emitting device; The gates of a plurality of second transistors arranged along the first direction are connected to the same scan line; The first signal line overlaps with the first node of a plurality of first-type pixel circuits arranged along the first direction.

3. The display panel according to claim 1, characterized in that, The display panel also includes multiple data lines arranged along the first direction and extending along the second direction, the data lines being electrically connected to the pixel circuit; the first signal line being electrically connected to the data lines.

4. The display panel according to claim 3, characterized in that, The display panel includes a first area and a second area, and the first signal line is located in the first area; Both the first region and the second region include the first shielding electrode.

5. The display panel according to claim 3, characterized in that, The display panel includes a first region and a second region, with the first signal line and the first shielding electrode both located in the first region.

6. The display panel according to claim 1, characterized in that, The pixel circuit further includes a third transistor; the plurality of first-type pixel circuits include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit are arranged adjacent to each other along the second direction; In this configuration, the first transistor in the first pixel circuit and the third transistor in the second pixel circuit are located on the same side of the first signal line in the second direction, and the gate of the first transistor in the first pixel circuit and the gate of the third transistor in the second pixel circuit are connected to the same scan line.

7. The display panel according to claim 6, characterized in that, The display panel further includes a light-emitting device, which is electrically connected to the first node; the first electrode of the first transistor is connected to the first reset signal line, and the second electrode is connected to the first node. The pixel circuit also includes a driving transistor, wherein the first terminal of the third transistor is connected to the second reset signal line, and the second terminal is connected to the gate of the driving transistor.

8. The display panel according to claim 7, characterized in that, The first shielding electrode is connected to the second reset signal line.

9. The display panel according to claim 7, characterized in that, The first shielding electrode is disposed on the same layer as the second reset signal line.

10. The display panel according to claim 8, characterized in that, The second reset signal line includes a first trace segment, which is connected to two of the first shielding electrodes; Along a direction perpendicular to the plane where the display panel is located, the first trace segment partially overlaps with the first signal line.

11. The display panel according to claim 8, characterized in that, The second reset signal line includes a first trace segment, which is connected to two of the first shielding electrodes; The second reset signal line also includes a second trace segment, which is not connected to the first shielding electrode, and the distance between the first trace segment and the first signal line is less than the distance between the second trace segment and the first signal line.

12. The display panel according to claim 8, characterized in that, The second reset signal line includes a first trace segment, and the first signal line includes a third trace segment. Both the third trace segment and the first trace segment overlap with the two first nodes in a direction perpendicular to the plane of the display panel. Along a direction perpendicular to the plane where the display panel is located, the orthographic projection of the first trace segment covers the orthographic projection of the third trace segment; the portion where the first trace segment intersects with the first node is reused as the first shielding electrode.

13. The display panel according to any one of claims 10-12, characterized in that, The first type of pixel circuits arranged adjacent to each other along the first direction are symmetrically arranged about the axis of symmetry extending along the second direction; The plurality of first-type pixel circuits arranged adjacent to each other along the first direction include a first pixel circuit, a third pixel circuit, and a fourth pixel circuit; the first pixel circuit and the third pixel circuit are arranged adjacent to each other along the first direction, and the third pixel circuit and the fourth pixel circuit are arranged adjacent to each other along the first direction; the distance between the first node of the first pixel circuit and the first node of the third pixel circuit is less than the distance between the first node of the third pixel circuit and the first node of the fourth pixel circuit.

14. The display panel according to claim 13, characterized in that, In the first pixel circuit and the third pixel circuit arranged adjacent to each other along the first direction, the first shielding electrode overlapping with the first pixel circuit and the first shielding electrode overlapping with the third pixel circuit are integral structures.

15. The display panel according to claim 6, characterized in that, The pixel circuit further includes a second node, which is connected to the third transistor. The display panel further includes a second shielding electrode, which covers the second node in the first type of pixel circuit along a direction perpendicular to the plane of the display panel.

16. The display panel according to claim 15, characterized in that, The first shielding electrode and the second shielding electrode are connected to the same signal line, and the second shielding electrode is located on the side of the signal line away from the first signal line.

17. The display panel according to claim 15, characterized in that, The first type of pixel circuits arranged adjacent to each other along the first direction are symmetrically arranged about the axis of symmetry extending along the second direction; The plurality of first-type pixel circuits arranged adjacent to each other along the first direction include a fifth pixel circuit, a sixth pixel circuit, and a seventh pixel circuit; The fifth pixel circuit and the sixth pixel circuit are arranged adjacent to each other along the first direction, and the sixth pixel circuit and the seventh pixel circuit are arranged adjacent to each other along the first direction; the distance between the second node of the fifth pixel circuit and the second node of the sixth pixel circuit is greater than the distance between the second node of the sixth pixel circuit and the second node of the seventh pixel circuit; In the sixth pixel circuit and the seventh pixel circuit arranged adjacent to each other in the first direction, the second shielding electrode overlapping with the sixth pixel circuit and the second shielding electrode overlapping with the seventh pixel circuit are integral structures.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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