Display device, electronic device, and method for manufacturing display device

Abstract

The present invention relates to a display device, an electronic device, and a method for manufacturing a display device. The display device includes a substrate including a sub-pixel region; a transistor over the substrate; a first insulating layer over the transistor; a connection electrode over the first insulating layer and connected to the transistor; a second insulating layer over the connection electrode; a reflective electrode over the second insulating layer and connected to the connection electrode; a first electrode over the reflective electrode; a light-emitting stack layer over the first electrode; and a second electrode over the light-emitting stack layer. The reflective electrode and the first electrode are in the sub-pixel region, and the reflective electrode includes a first layer over the second insulating layer and connected to the connection electrode; a second layer over the first layer and including silver; and a third layer over the second layer and including a transparent conductive oxide in an amorphous state at a temperature of about 260 degrees Celsius or lower after deposition.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0054547, filed on April 25, 2025, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to display devices, electronic devices, and methods for manufacturing display devices that can resolve the problem of electrical short circuits between reflective electrodes of adjacent sub-pixel regions. Background Technology

[0003] Organic light-emitting display devices may include display elements whose brightness is changed by an electric current, such as organic light-emitting diodes. Summary of the Invention

[0004] This disclosure provides a display device, an electronic device, and a method for manufacturing a display device that can solve the problem of electrical short circuit between reflective electrodes of adjacent sub-pixel regions.

[0005] According to an aspect of this disclosure, a display device is provided, comprising: a substrate including a sub-pixel region and a non-pixel region; a transistor on the substrate; a first insulating layer on the transistor; a connection electrode disposed on the first insulating layer and connected to the transistor; a second insulating layer on the connection electrode; a reflective electrode disposed on the second insulating layer and connected to the connection electrode; a first electrode on the reflective electrode; a light-emitting stacked layer on the first electrode; and a second electrode on the light-emitting stacked layer, wherein the reflective electrode and the first electrode are disposed in the sub-pixel region, the reflective electrode comprising: a first layer disposed between the second insulating layer and the first electrode and connected to the connection electrode; a second layer disposed between the first layer and the first electrode and comprising silver; and a third layer between the second layer and the first electrode, the third layer and the second layer being in direct contact with each other, and the third layer comprising a transparent conductive oxide and being in an amorphous state at a temperature of about 260 degrees Celsius or lower after deposition.

[0006] The third layer can have a thickness of approximately 30 Å to approximately 300 Å.

[0007] The total thickness of the first electrode and the third layer can be from 150 Å to 700 Å.

[0008] The thickness of the third layer can be between 30 Å and 150 Å, and the total thickness of the third and fourth layers can be approximately 300 Å.

[0009] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory connected to the processor; and a display device connected to the processor and the memory, wherein the display device comprises: a substrate including sub-pixel regions and non-pixel regions; a transistor on the substrate; a first insulating layer on the transistor; a connection electrode disposed on the first insulating layer and connected to the transistor; a second insulating layer on the connection electrode; a reflective electrode disposed on the second insulating layer and connected to the connection electrode; a first electrode on the reflective electrode; a light-emitting stacked layer on the first electrode; and a second electrode on the light-emitting stacked layer, wherein the reflective electrode and the first electrode are disposed in the sub-pixel regions, the reflective electrode comprising: a first layer disposed between the second insulating layer and the first electrode and connected to the connection electrode; a second layer disposed between the first layer and the first electrode and comprising silver; and a third layer between the second layer and the first electrode, the third layer and the second layer being in direct contact with each other, and the third layer comprising a transparent conductive oxide and being in an amorphous state at a temperature of about 260 degrees Celsius or lower after deposition.

[0010] According to another aspect of this disclosure, a method for manufacturing a display device is provided, the method comprising: preparing a substrate including a first sub-pixel region, a second sub-pixel region, and a non-pixel region; forming a first transistor and a second transistor on the substrate; forming a first insulating layer on the first transistor and the second transistor; forming a first connection electrode connected to the first transistor and a second connection electrode connected to the second transistor on the first insulating layer; forming a second insulating layer on the first connection electrode and the second connection electrode; forming a first contact hole exposing the first connection electrode and a second contact hole exposing the second connection electrode in the second insulating layer; forming a first preliminary layer on the second insulating layer, the first preliminary layer being connected to the first connection electrode and the second connection electrode respectively through the first contact hole and the second contact hole, and comprising amorphous ITO; forming a second preliminary layer on the first preliminary layer; forming a third preliminary layer comprising amorphous transparent conductive oxide on the second preliminary layer; forming a resonance control layer on the third preliminary layer of the second sub-pixel region; forming a first preliminary electrode on the third preliminary layer and the resonance control layer; forming a photoresist pattern on the first preliminary electrode of the first sub-pixel region and the second sub-pixel region; and patterning the first preliminary layer, the second preliminary layer, the third preliminary layer, and the first preliminary electrode using the photoresist pattern as a mask. Electrodes are formed in a first sub-pixel region, comprising a first first reflective layer connected to a first connecting electrode, a first second reflective layer disposed on the first first reflective layer, a first third reflective layer disposed on the first second reflective layer, and a first first electrode disposed on the first third reflective layer. In a second sub-pixel region, second first reflective layers connected to a second connecting electrode, second second reflective layers disposed on the second second reflective layers, second third reflective layers disposed on the second second reflective layers, and a second first electrode disposed on the second third reflective layer and a resonance control layer are formed. A capping layer is formed on the edge of the first electrode and on the second insulating layer in the non-pixel region; and the capping layer is heat-treated, wherein before the heat treatment of the capping layer, the first first reflective layer, the first first electrode, the second first reflective layer and the second first electrode each comprise amorphous ITO material, and after the heat treatment of the capping layer, the first first reflective layer, the first first electrode, the second first reflective layer and the second first electrode each comprise crystalline ITO material, and before the formation of the first first electrode and the second first electrode, the first third reflective layer and the second third reflective layer each comprise amorphous transparent conductive oxide.

[0011] According to the display device, electronic device, and method for manufacturing the display device according to the embodiments, the problem of electrical short circuit between reflective electrodes of adjacent sub-pixel regions can be solved.

[0012] For example, the reflective electrode of the display device according to the embodiment may comprise a transparent conductive oxide that can remain amorphous at high temperatures, and accordingly, when the first electrode (e.g., the anode electrode) and the reflective electrode are patterned, no residue (e.g., ITO residue) is formed between adjacent sub-pixel regions (e.g., non-pixel regions). Accordingly, the problem of electrical short circuits where the reflective electrodes of adjacent sub-pixel regions are connected to each other can be solved.

[0013] The effects of this disclosure are not limited to those described above, and other effects not described herein will become apparent to those skilled in the art from the following description. Attached Figure Description

[0014] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0015] Figure 1 An exploded perspective view illustrating the display device according to an embodiment;

[0016] Figure 2 A block diagram illustrating a display device according to an embodiment;

[0017] Figure 3 This is a cross-sectional view of the display device according to an embodiment;

[0018] Figure 4 for Figure 3 A magnified view of region A;

[0019] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a process cross-sectional view used to describe a method for manufacturing a display device according to an embodiment;

[0020] Figure 13 This is a cross-sectional view of the display device according to an embodiment;

[0021] Figure 14 for Figure 13 A magnified view of region B;

[0022] Figure 15 This is a cross-sectional view used to describe the configuration of the third layer according to the embodiment;

[0023] Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20, Figure 21 and Figure 22 This is a process cross-sectional view used to describe a method for manufacturing a display device according to an embodiment;

[0024] Figure 23 A photograph of the non-pixel area of ​​the display device according to the embodiment;

[0025] Figure 24 This is a block diagram of an electronic device according to an embodiment; and

[0026] Figure 25 , Figure 26 and Figure 27 This is a schematic diagram of an electronic device according to various embodiments. Detailed Implementation

[0027] The invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0028] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or an intermediary layer may be present. The same reference numerals throughout the specification indicate the same components. In the drawings, the thickness of layers and regions is enlarged for clarity.

[0029] Although the terms “first,” “second,” “first-first,” “first-second,” “second-first,” “second-second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first element discussed below may be referred to as the second element. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different classes or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first class (or first group),” “second class (or second group),” etc.

[0030] Features of various embodiments of this disclosure can be combined partially or completely. As will be clearly understood by those skilled in the art, various technical interactions and operations are possible. Various embodiments can be practiced individually or in combination.

[0031] As used herein, “about” or “substantially equal to” includes the stated value and means within an acceptable range of deviation for a particular value, determined by a person skilled in the art considering the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the stated value, or within ±10%, ±5%, or ±2% of the stated value. Specific exemplary embodiments will be described below with reference to the accompanying drawings.

[0032] Figure 1 An exploded perspective view illustrating the display device 10 according to an embodiment. Figure 2 A block diagram illustrating a display device according to an embodiment.

[0033] refer to Figure 1 and Figure 2 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices (e.g., mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebook computers, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs)). For example, the display device 10 according to the embodiment can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 according to the embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0034] The display device 10 according to the embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0035] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have curvature or may be formed as a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral and may be formed similar to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments described in this specification are not limited thereto.

[0036] The display panel 100 may include multiple pixel areas PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, a light emission driver 620, and a data driver 700. For example... Figure 2 As explained, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images. Multiple pixel areas PX can be disposed within the display area DAA. The multiple pixel areas PX can be arranged in a matrix on a first direction DR1 and a second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend on the first direction DR1 and can be disposed on the second direction DR2. Multiple data lines DL can extend on the second direction DR2 and can be disposed on the first direction DR1.

[0037] Multiple scan lines SL may include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines EBL. Multiple emit control lines EL may include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0038] The multiple pixel region PX may include multiple sub-pixel regions SP1, SP2, and SP3. The multiple sub-pixel regions SP1, SP2, and SP3 may include multiple transistors (e.g., Figure 3 (Pixel transistor TR in the image).

[0039] The pixel circuitry (e.g., pixel circuitry including pixel transistors) of each of the multiple sub-pixel regions SP1, SP2, and SP3 can be connected to any one of the multiple write scan lines GWL, any one of the multiple control scan lines GCL, any one of the multiple bias scan lines EBL, any one of the multiple first emission control lines EL1, any one of the multiple second emission control lines EL2, and any one of the multiple data lines DL. The pixel circuitry of each of the multiple sub-pixel regions SP1, SP2, and SP3 can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element ED according to the data voltage.

[0040] The scan driver 610, the light-emitting driver 620, and the data driver 700 can be located in the non-display area NDA.

[0041] The scan driver 610 may include multiple scan transistors, and the light-emitting driver 620 may include multiple light-emitting transistors.

[0042] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400 and output the write scan signal sequentially to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS and output the control scan signal sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS and output the bias scan signal sequentially to the bias scan line EBL.

[0043] The light-emitting driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal according to the transmit timing control signal ECS and sequentially output the first transmit control signal to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal according to the transmit timing control signal ECS and sequentially output the second transmit control signal to a second transmit control line EL2.

[0044] The data driver 700 may include multiple data transistors.

[0045] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the converted analog data voltage to the data line DL. In this case, the pixel circuits of sub-pixel regions SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage (e.g., analog data voltage) can be supplied to the selected sub-pixel regions SP1, SP2, and SP3.

[0046] On a third direction DR3, which is the thickness direction of the display panel 100, the heat dissipation layer 200 may overlap with the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100 (e.g., the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or metal (e.g., silver (Ag), copper (Cu), or aluminum (Al)) having a high thermal conductivity.

[0047] The circuit board 300 can be electrically connected to multiple pads of the display panel 100 using conductive adhesive components (such as anisotropic conductive films). The circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible materials. Figure 1 The diagram illustrates that circuit board 300 is unfolded, but it can also be bent. In this case, one end of circuit board 300 can be disposed on the rear surface of display panel 100 and / or the rear surface of heat dissipation layer 200. The other end of circuit board 300 can be electrically connected to a plurality of pads of display panel 100 using conductive adhesive components. One end of circuit board 300 can also be the end opposite to the other end of circuit board 300.

[0048] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the light-emitting driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0049] The power supply circuit 500 can generate multiple panel driving voltages based on the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply the generated driving voltages VSS, VDD, and VINT to the display panel 100.

[0050] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300 and pads. Additionally, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300 and pads.

[0051] Optionally, similar to the scan driver 610, the light-emitting driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors.

[0052] Figure 3 This is a cross-sectional view of the display device 10 according to an embodiment. For example, Figure 3 Can be Figure 2 A cross-sectional view of the display panel 100. Specifically, Figure 3 This can be a cross-sectional view of the display area DAA of the display panel 100. Figure 4 for Figure 3 A magnified view of region A.

[0053] like Figure 3 As explained herein, the display device 10 may include a substrate SUB, a buffer layer BF on the substrate SUB, a pixel circuit layer PCL on the buffer layer BF, a light-emitting element layer EML on the pixel circuit layer PCL, an encapsulation layer ENC on the light-emitting element layer EML, an adhesive layer APL on the encapsulation layer ENC, and a color filter layer CFL on the adhesive layer APL. Here, the pixel circuit layer PCL may include the pixel circuits of the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3.

[0054] The pixel circuit layer PCL may include multiple transistors TR (e.g., pixel transistors TR), multiple insulating layers INS1 and INS2, and multiple connection electrodes CNE.

[0055] The light-emitting element layer EML may include multiple reflective electrodes RL, multiple resonant control layers RCL, multiple first electrodes AND (e.g., anode electrodes), capping layer CPL, pixel defining layer PDL, light-emitting stack layer IL, and second electrode CAT (e.g., cathode electrode).

[0056] The substrate SUB may include a first sub-pixel region SP1, a second sub-pixel region SP2, and a third sub-pixel region SP3.

[0057] Transistor TR, reflective electrode RL, first electrode AND, light-emitting stacked layer IL, second electrode CAT, and first color filter CF1 can be disposed in the first sub-pixel region SP1. Transistor TR, reflective electrode RL, resonant control layer RCL, first electrode AND, light-emitting stacked layer IL, second electrode CAT, and second color filter CF2 can be disposed in the second sub-pixel region SP2. Transistor TR, reflective electrode RL, resonant control layer RCL, first electrode AND, light-emitting stacked layer IL, second electrode CAT, and third color filter CF3 can be disposed in the third sub-pixel region SP3.

[0058] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include glass or metal materials. In contrast, the substrate SUB can include a polymer resin (e.g., polyimide (PI)).

[0059] A buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may be a film used to protect the transistor TR of the pixel circuit layer PCL and the light-emitting stack layer IL (or the light-emitting layer of the light-emitting stack layer IL) of the light-emitting element layer EML from the effects of moisture that penetrates through the substrate SUB, which is easily permeable by moisture.

[0060] The transistor TR can be disposed on the buffer layer BF. For example, the transistor TR can be disposed on the buffer layer BF of the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3.

[0061] A first insulating layer INS1 may be disposed on the transistor TR. The first insulating layer INS1 may include multiple sandwich insulating layers stacked on the transistor TR on the third-direction DR3.

[0062] Multiple connection electrodes CNE can be disposed on the first insulating layer INS1. The multiple connection electrodes CNE can be respectively connected to multiple transistors TR. For example, the transistor TR of the first sub-pixel region SP1 can be electrically connected to the connection electrode CNE of the first sub-pixel region SP1, the transistor TR of the second sub-pixel region SP2 can be electrically connected to the connection electrode CNE of the second sub-pixel region SP2, and the transistor TR of the third sub-pixel region SP3 can be electrically connected to the connection electrode CNE of the third sub-pixel region SP3. In this case, the drain electrode of the transistor TR can be connected to the connection electrode CNE through multiple intermediate connection electrodes disposed between the transistor TR and the connection electrode CNE.

[0063] A second insulating layer INS2 may be disposed on multiple connecting electrodes CNE. The second insulating layer INS2 may include multiple contact holes CT penetrating the second insulating layer INS2. The multiple contact holes CT may overlap with the multiple connecting electrodes CNE respectively. For example, multiple connecting electrodes CNE may be exposed through the multiple contact holes CT respectively.

[0064] Multiple reflective electrodes RL can be disposed on the second insulating layer INS2. The multiple reflective electrodes RL can be connected to multiple connecting electrodes CNE through multiple contact holes CT of the second insulating layer INS2, respectively.

[0065] The reflective electrode RL may include multiple reflective layers sequentially stacked on the second insulating layer INS2 along the third direction DR3. For example, the reflective electrode RL may include a first layer L1, a second layer L2, and a third layer L3 disposed between the second insulating layer INS2 and the first electrode AND (or the resonant control layer RCL) along the third direction DR3. As a specific example, the reflective electrode RL of the first sub-pixel region SP1 may include the first layer L1, the second layer L2, and the third layer L3 disposed between the second insulating layer INS2 and the first electrode AND of the first sub-pixel region SP1. Additionally, the reflective electrode RL of the second sub-pixel region SP2 may include the first layer L1, the second layer L2, and the third layer L3 disposed between the second insulating layer INS2 and the resonant control layer RCL of the second sub-pixel region SP2. Furthermore, the reflective electrode RL of the third sub-pixel region SP3 may include the first layer L1, the second layer L2, and the third layer L3 disposed between the second insulating layer INS2 and the resonant control layer RCL of the third sub-pixel region SP3.

[0066] The first layer L1 may be disposed on the second insulating layer INS2. The first layer L1 may be connected to the connecting electrode CNE through the contact hole CT of the second insulating layer INS2. The first layer L1 may be made of a material including indium tin oxide (ITO). For example, the first layer L1 may be made of a material including crystalline indium tin oxide.

[0067] The second layer L2 may be disposed on the first layer L1. For example, the second layer L2 may be disposed between the first layer L1 and the third layer L3. The second layer L2 may be made of a material including silver (Ag).

[0068] The third layer L3 can be disposed on the second layer L2. For example, the third layer L3 of the first sub-pixel region SP1 can be disposed between the second layer L2 of the first sub-pixel region SP1 and the first electrode AND of the first sub-pixel region SP1. Additionally, the third layer L3 of the second sub-pixel region SP2 can be disposed between the second layer L2 of the second sub-pixel region SP2 and the resonant control layer RCL of the second sub-pixel region SP2. Furthermore, the third layer L3 of the third sub-pixel region SP3 can be disposed between the second layer L2 of the third sub-pixel region SP3 and the resonant control layer RCL of the third sub-pixel region SP3.

[0069] The third layer L3 may be made of a material comprising an amorphous transparent conductive oxide (TCO). For example, the third layer L3 may comprise a heat-resistant transparent conductive oxide and remain amorphous at temperatures of about 260 degrees Celsius or lower (e.g., temperatures during heat treatment processes). The third layer L3 may comprise at least one of tin-doped zinc indium oxide (IZO), zinc indium gallium oxide (IZO), zinc indium gallium oxide (IGZO), zinc indium tin oxide (ITZO), indium gallium oxide (IGO), indium tin gallium oxide (ITGO), indium tin oxide (ITO), and zinc indium tin gallium oxide (ITGZO). For this purpose, the third layer L3 according to an embodiment may be made of a material comprising tin-doped zinc indium oxide (IZO). The third layer L3 according to another embodiment may be made of a material comprising any one of zinc indium oxide (IZO), zinc indium gallium oxide (IGZO), zinc indium tin oxide (ITZO), indium gallium oxide (IGO), indium tin gallium oxide (ITGO), and zinc indium tin gallium oxide (ITGZO). The transparent conductive oxides listed above can remain amorphous at temperatures, for example, around 260 degrees Celsius or lower.

[0070] When the third layer L3 comprises a material containing indium zinc oxide (IZO) doped with tin (Sn), the third layer L3 may comprise 12 atomic percentages (at%) to 22 at% of tin relative to the total number of metal atoms in the third layer L3.

[0071] When the third layer L3 includes IGZO, the composition of the third layer L3 may include approximately 44.2 wt% indium oxide (InO). x Gallium oxide (GaO) of approximately 29.6 wt% x ) and approximately 25.9 wt% zinc oxide (ZnO) x ).

[0072] When the third layer L3 includes IZO, its composition may include 10 at% to 25 at% zinc (Zn) and 75 at% to 90 at% indium (In), relative to the total number of metal atoms in the third layer L3. Alternatively, when the third layer L3 includes IZO, its composition may include approximately 90 wt% indium oxide (InO). x ) and approximately 10 wt% zinc oxide (ZnO) x ).

[0073] When the third layer L3 includes ITZO, under the condition that the atomic ratio of indium and zinc is 1:1, the composition of the third layer L3 may include 6 at% to 22 at% tin relative to the total number of metal atoms in the third layer L3.

[0074] When the third layer L3 includes IGO, the composition of the third layer L3 may include more than 95 wt% indium oxide (InO) relative to the total weight of the third layer L3. x ) and less than 5 wt% gallium oxide (GaO) x ).

[0075] Above a certain temperature, the third layer L3 can also transform from an amorphous state to a crystalline state. For example, in the process of forming the third layer L3 (e.g., a thin film deposition process for the third layer L3), the third layer L3 may be amorphous, but it can be transformed into a crystalline state by heat applied in a subsequent heat treatment process, etc. As a specific example, since a heat treatment process can be performed after the thin film deposition process of the third layer L3 in the process of forming the capping layer CPL, the amorphous third layer L3 can be transformed into a crystalline third layer L3 by applying heat to it during the heat treatment process. In other words, the third layer L3 according to another embodiment can be made of a material comprising a crystalline transparent conductive oxide.

[0076] According to one embodiment, the third layer L3 may be deposited on the second layer L2 after the thin film deposition process of the second layer L2. The second layer L2 and the third layer L3 may be in direct contact with each other. In this case, the third layer L3 on the second layer L2 may remain amorphous at a temperature of about 260 degrees Celsius or lower after the thin film deposition process. At temperatures above about 260 degrees Celsius, the third layer L3 may comprise an amorphous transparent conductive oxide or a crystalline transparent conductive oxide. For example, the third layer L3 may remain amorphous or transform from an amorphous state to a crystalline state at temperatures above about 260 degrees Celsius.

[0077] The third layer L3 and the second layer L2 can have different thicknesses. For example, the thickness of the second layer L2 can be greater than the thickness of the third layer L3. Additionally, the thickness of the second layer L2 can be greater than the thickness of the first layer L1. Furthermore, the thickness of the first layer L1 and the thickness of the second layer L2 can be the same. However, the difference between the thicknesses of the first layer L1, the second layer L2, and the third layer L3 is not limited to this and can be varied. Here, the thickness of the corresponding reflective layer can be the dimension of the corresponding reflective layer on the third-direction DR3.

[0078] As described above, because the third layer L3 comprises an amorphous transparent conductive oxide, it remains amorphous until the formation of the first electrode AND. For example, the third layer L3 may remain amorphous until the patterning process of the first electrode AND. Therefore, after the etching process (e.g., patterning process) used to form the first electrode AND and the reflective electrode RL, residues of the first electrode AND (e.g., ITO residues) can be prevented from remaining in the non-pixel region NPA. When residues of the first electrode AND are present in the non-pixel region NPA, a short circuit can occur where the reflective electrodes RL and / or the first electrode AND of adjacent sub-pixel regions are electrically connected to each other.

[0079] A resonant control layer RCL can be disposed on the reflective electrode RL. For example, the resonant control layer RCL can be disposed on the reflective electrodes RL of the second sub-pixel region SP2 and the third sub-pixel region SP3, respectively. In other words, the resonant control layer RCL of the second sub-pixel region SP2 can be disposed between the third layer L3 of the second sub-pixel region SP2 and the first electrode AND of the second sub-pixel region SP2. Additionally, the resonant control layer RCL of the third sub-pixel region SP3 can be disposed between the third layer L3 of the third sub-pixel region SP3 and the first electrode AND of the third sub-pixel region SP3. The resonant control layer RCL is not disposed on the reflective electrode RL of the first sub-pixel region SP1. The resonant distance of light emitted from each sub-pixel region can be changed depending on the presence or absence of the resonant control layer RCL. Accordingly, since the reflectivity of light can be adjusted for each of the sub-pixel regions SP1, SP2, and SP3 that provide light of different wavelength bands, the optical characteristics or image quality characteristics of the desired wavelength band can be improved. One side of the resonant control layer RCL can further extend into the non-pixel region NPA. For example, at least a portion of the resonance control layer RCL can be set in the non-pixel region NPA.

[0080] The first electrode AND can be disposed on the resonant control layer RCL. For example, the first electrode AND can be disposed on the resonant control layer RCL of the second sub-pixel region SP2 and the resonant control layer RCL of the third sub-pixel region SP3, respectively. In other words, the first electrode AND of the second sub-pixel region SP2 can be disposed between the resonant control layer RCL of the second sub-pixel region SP2 and the light-emitting stacked layer IL of the second sub-pixel region SP2. In addition, the first electrode AND of the third sub-pixel region SP3 can be disposed between the resonant control layer RCL of the third sub-pixel region SP3 and the light-emitting stacked layer IL of the third sub-pixel region SP3. The first electrode AND of the first sub-pixel region SP1 can be disposed between the third layer L3 of the first sub-pixel region SP1 and the light-emitting stacked layer IL of the first sub-pixel region SP1.

[0081] The first electrode AND can be connected to the reflective electrode RL. For example, the first electrode AND of the first sub-pixel region SP1 can be connected to the third layer L3 of the first sub-pixel region SP1, the first electrode AND of the second sub-pixel region SP2 can be connected to the third layer L3 of the second sub-pixel region SP2, and the first electrode AND of the third sub-pixel region SP3 can be connected to the third layer L3 of the third sub-pixel region SP3. In this case, because the resonance control layer RCL is not disposed in the first sub-pixel region SP1, the contact area between the first electrode AND and the third layer L3 of the first sub-pixel region SP1 can be larger than the contact area between the first electrode AND and the third layer L3 of the second sub-pixel region SP2, in which the resonance control layer RCL is disposed. Similarly, the contact area between the first electrode AND and the third layer L3 of the first sub-pixel region SP1 can be larger than the contact area between the first electrode AND and the third layer L3 of the third sub-pixel region SP3, in which the resonance control layer RCL is disposed.

[0082] The first electrode AND of the first sub-pixel region SP1 can contact (or directly contact) the entire upper surface of the third layer L3 of the first sub-pixel region SP1, the first electrode AND of the second sub-pixel region SP2 can contact (or directly contact) the edge of the third layer L3 of the second sub-pixel region SP2, and the first electrode AND of the third sub-pixel region SP3 can contact (or directly contact) the edge of the third layer L3 of the third sub-pixel region SP3.

[0083] The thickness of the first electrode AND can be determined based on the thickness of the third layer L3. For example, since the total thickness (hereinafter, the total thickness) obtained by adding the thickness tk2 of the first electrode AND and the thickness tk1 of the third layer L3 can be between 150 Å and 700 Å, the thickness tk2 of the first electrode AND and the thickness tk1 of the third layer L3 can be adjusted separately to satisfy the range of the total thickness.

[0084] When the thickness tk1 of the third layer L3 is less than a preset lower threshold, the third layer L3 can form an island-like structure on the second layer L2, leading to the exposure of the second layer L2. Conversely, when the thickness tk1 of the third layer L3 is greater than a preset upper threshold, reduced light transmittance may occur. Furthermore, when the third layer L3 has an undercut shape due to the etching ratio between the resonant control layer RCL and the third layer L3, if the thickness tk1 of the third layer L3 is greater than a preset upper threshold, poor contact may occur between the first electrode AND and the third layer L3 in the second sub-pixel region SP2 (e.g., poor contact between the first electrode AND and the reflective electrode RL). Similarly, when the third layer L3 has the undercut shape described above, if the thickness tk1 of the third layer L3 is greater than a preset upper threshold, poor contact may occur between the first electrode AND and the third layer L3 in the third sub-pixel region SP3. Therefore, the thickness tk1 of the third layer L3 can be set to be greater than a preset lower threshold and less than a preset upper threshold. In this case, the preset lower threshold can be approximately 30 Å, and the preset upper threshold can be approximately 300 Å. However, the preset lower and upper thresholds for the third layer L3 are not limited to these and can be modified in various ways.

[0085] The capping layer CPL can be disposed on multiple first electrodes AND. The capping layer CPL can also be disposed on the edges of the multiple first electrodes AND. Furthermore, the capping layer CPL can be disposed between adjacent sub-pixel regions. For example, the capping layer CPL can be disposed between first sub-pixel region SP1 and second sub-pixel region SP2, and can also be disposed between second sub-pixel region SP2 and third sub-pixel region SP3.

[0086] Specifically, when the area between sub-pixel regions SP1, SP2, and SP3 of the display area DAA is defined as a non-pixel region NPA, a capping layer CPL can be disposed in the non-pixel region NPA. In this case, the capping layer CPL in the non-pixel region NPA can be disposed between adjacent reflective electrodes RL and adjacent first electrodes AND. Alternatively, the capping layer CPL can also be disposed between the first electrodes AND and the resonant control layer RCL, which are disposed adjacent to each other. For example, the capping layer CPL can be disposed between the resonant control layer RCL of the second sub-pixel region SP2 and the first electrode AND of the third sub-pixel region SP3. Since the non-pixel region NPA between sub-pixel regions SP1, SP2, and SP3 is filled by the capping layer CPL, the step difference between the non-pixel region NPA and the sub-pixel regions SP1, SP2, and SP3 can be minimized.

[0087] A pixel defining layer (PDL) may be disposed on a capping layer (CPL). The PDL may be disposed on each edge of the first electrode AND and on the capping layer CPL. For example, the PDL may have multiple light-emitting regions EA1, EA2, and EA3 penetrating the PDL, and these regions may expose portions of the first electrode AND excluding its edges. The first electrode AND may overlap with the light-emitting regions EA1, EA2, and EA3 of the PDL, respectively. For example, the first light-emitting region EA1 of the PDL may overlap with the central portion of the first electrode AND of the first sub-pixel region SP1, the second light-emitting region EA2 of the PDL may overlap with the central portion of the first electrode AND of the second sub-pixel region SP2, and the third light-emitting region EA3 of the PDL may overlap with the central portion of the first electrode AND of the third sub-pixel region SP3.

[0088] Additionally, the pixel defining layer PDL may include a pointed tip TP protruding toward each of the light-emitting regions EA1, EA2, and EA3. The inner edges of the light-emitting regions EA1, EA2, and EA3 of the pixel defining layer PDL may have an undercut shape due to the pointed tip TP. For this purpose, according to an embodiment, the pixel defining layer PDL may have a structure in which two or more insulating layers with different etch rates are stacked. The pointed tip TP of the pixel defining layer PDL may be a structure for dividing the light-emitting stacked layer IL, which will be described later.

[0089] A light-emitting stacked layer IL can be disposed on the first electrode AND, the capping layer CPL, and the pixel defining layer PDL. In this case, the light-emitting stacked layer IL can be segmented on the pixel defining layer PDL. For example, the light-emitting stacked layer IL can be segmented on the tip TP of the pixel defining layer PDL. In a cross-sectional view, the light-emitting stacked layer IL can be segmented along the pixel defining layer PDL. Therefore, the light-emitting stacked layer IL can be divided into a portion that contacts the first electrode AND in each of the light-emitting regions EA1, EA2, and EA3, and a portion disposed on the region other than each of the light-emitting regions EA1, EA2, and EA3 (e.g., the upper surface of the pixel defining layer PDL). In other words, the light-emitting stacked layer IL can be segmented along the pixel defining layer PDL, and each of the sub-pixel regions SP1, SP2, and SP3 is separate. Accordingly, the lateral leakage current between adjacent sub-pixel regions SP1, SP2, and SP3 can be minimized. Since the lateral leakage current is minimized, color mixing between adjacent sub-pixel regions SP1, SP2, and SP3 can be prevented, thereby improving the image quality of the display device 10.

[0090] The light-emitting stacked layer IL may include multiple stacked layers sequentially stacked along a third direction DR3. For example, the light-emitting stacked layer IL may have a three-in-series structure, which includes a first stacked layer, a second stacked layer on the first stacked layer, and a third stacked layer on the second stacked layer. Here, the second stacked layer may be disposed between the first stacked layer and the third stacked layer. The embodiments described herein are not limited thereto. For example, the light-emitting stacked layer IL may also have a two-in-series structure including two stacked layers.

[0091] In a three-layer tandem structure, the first, second, and third stacked layers of the light-emitting stack IL can provide light of different colors (or wavelength bands). For example, one of the first, second, and third stacked layers can provide light of a first color (e.g., green light), another of the first, second, and third stacked layers can provide light of a second color (e.g., red light), and the remaining one of the first, second, and third stacked layers can provide light of a third color (e.g., blue light).

[0092] The first stacked layer of the light-emitting stacked layer IL may have a structure in which a first hole transport layer, a first organic light-emitting layer, and a first electron transport layer are stacked sequentially. The second stacked layer of the light-emitting stacked layer IL may have a structure in which a second hole transport layer, a second organic light-emitting layer, and a second electron transport layer are stacked sequentially. The third stacked layer of the light-emitting stacked layer IL may have a structure in which a third hole transport layer, a third organic light-emitting layer, and a third electron transport layer are stacked sequentially. Here, the first, second, and third organic light-emitting layers can provide light of different colors (or wavelength bands). For example, one of the first, second, and third organic light-emitting layers can provide light of a first color (e.g., green light), another of the first, second, and third organic light-emitting layers can provide light of a second color (e.g., red light), and the remaining one of the first, second, and third organic light-emitting layers can provide light of a third color (e.g., blue light).

[0093] A first charge generation layer for supplying holes to the second stacked layer and electrons to the first stacked layer may be disposed between the first and second stacked layers. The first charge generation layer may include an n-type charge generation layer supplying electrons to the first stacked layer and a p-type charge generation layer supplying holes to the second stacked layer. The n-type charge generation layer may include a dopant of a metallic material.

[0094] A second charge generation layer for supplying holes to the third stacked layer and electrons to the second stacked layer may be disposed between the second and third stacked layers. The second charge generation layer may include an n-type charge generation layer for supplying electrons to the second stacked layer and a p-type charge generation layer for supplying holes to the third stacked layer.

[0095] A first stacked layer may be disposed on the first electrode AND and the pixel defining layer PDL. Through the pixel defining layer PDL, the first stacked layer of the light-emitting stacked layer IL may be disconnected between adjacent sub-pixel regions SP1, SP2, and SP3. A second stacked layer of the light-emitting stacked layer IL may be disposed on the first stacked layer. Through the pixel defining layer PDL, the second stacked layer of the light-emitting stacked layer IL may be disconnected between adjacent sub-pixel regions SP1, SP2, and SP3. A third stacked layer of the light-emitting stacked layer IL may be disposed on the second stacked layer. The third stacked layer of the light-emitting stacked layer IL may not be disconnected by the pixel defining layer PDL and may be configured to cover the second stacked layer.

[0096] In a three-series structure, the pixel-defining layer (PDL) can be a structure used to disconnect the first and second charge generation layers of the light-emitting stacked layers (IL) between adjacent sub-pixel regions SP1, SP2, and SP3. Alternatively, in a two-series structure, the pixel-defining layer (PDL) can be a structure used to disconnect the charge generation layer disposed between the lower and upper stacked layers.

[0097] The second electrode CAT can be disposed on the light-emitting stacked layer IL. For example, the second electrode CAT can be disposed on the third stacked layer of the light-emitting stacked layer IL. For example, the second electrode CAT may not be disconnected by the pixel defining layer PDL and may be disposed on the third stacked layer of the light-emitting stacked layer IL. The second electrode CAT may include a semi-transmissive conductive material (e.g., magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). In this case, the luminous efficiency can be increased by a microcavity in each of the first to third sub-pixel regions SP1, SP2, and SP3.

[0098] An encapsulation layer ENC may be disposed on the second electrode CAT. The encapsulation layer ENC may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer stacked sequentially along the third direction DR3.

[0099] An adhesive layer (APL) may be disposed on the encapsulation layer (ENC). The adhesive layer (APL) may be a layer used to increase interfacial adhesion between the encapsulation layer (ENC) and the color filter layer (CFL), which will be described later. The adhesive layer (APL) may be an organic layer made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc. The adhesive layer (APL) may be omitted.

[0100] A color filter layer CFL can be disposed on an adhesive layer APL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 can be disposed on the adhesive layer APL in the first sub-pixel region SP1, the second color filter CF2 can be disposed on the adhesive layer APL in the second sub-pixel region SP2, and the third color filter CF3 can be disposed on the adhesive layer APL in the third sub-pixel region SP3. As described above, when the adhesive layer APL is omitted, the color filter layer CFL and the encapsulation layer ENC can be in direct contact with each other.

[0101] The first color filter CF1 may overlap with the first emitting region EA1 of the first sub-pixel region SP1. The first color filter CF1 may transmit first light (e.g., light in the green wavelength band). For example, the first color filter CF1 may transmit first light emitted from the emitting stack layer IL of the first emitting region EA1.

[0102] The second color filter CF2 may overlap with the second emitting region EA2 of the second sub-pixel region SP2. The second color filter CF2 may transmit second light (e.g., light in the blue wavelength band). For example, the second color filter CF2 may transmit second light emitted from the emitting stack layer IL of the second emitting region EA2.

[0103] The third color filter CF3 may overlap with the third emitting region EA3 of the third sub-pixel region SP3. The third color filter CF3 may transmit third light (e.g., light in the red wavelength band). For example, the third color filter CF3 may transmit third light from the emitting stack layer IL of the third emitting region EA3.

[0104] Although not explained, multiple lenses (e.g., microlenses) that overlap with the first color filter CF1, the second color filter CF2 and the third color filter CF3 may be disposed on the color filter layer CFL.

[0105] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a cross-sectional view of a process used to describe a method for manufacturing a display device 10 according to an embodiment. For example, Figures 5 to 12 For the purpose of describing the manufacture of the above Figure 4 A process cross-sectional view of the method for displaying device 10.

[0106] First, such as Figure 3 and Figure 5As explained, a buffer layer BF can be formed on the substrate SUB, and then a plurality of transistors TR can be formed on the buffer layer BF, and then a first insulating layer INS1 can be formed on the plurality of transistors TR, and then a plurality of connection electrodes CNE can be formed on the first insulating layer INS1, and then a second insulating layer INS2 can be formed on the plurality of connection electrodes CNE. Subsequently, a plurality of contact holes CT can be formed that penetrate the second insulating layer INS2 and expose the plurality of connection electrodes CNE.

[0107] Subsequently, as Figure 6 As explained, a preliminary reflective electrode RLa, comprising a first preliminary layer L1a, a second preliminary layer L2a, and a third preliminary layer L3a, can be formed on the second insulating layer INS2. For example, the first preliminary layer L1a can be formed on the second insulating layer INS2, and then the second preliminary layer L2a can be formed on the first preliminary layer L1a, and then the third preliminary layer L3a can be formed on the second preliminary layer L2a. In this case, the first preliminary layer L1a may comprise a material containing ITO (e.g., amorphous ITO), the second preliminary layer L2a may comprise a material containing silver, and the third preliminary layer L3a may comprise a material containing ITO (e.g., amorphous ITO). Alternatively, the third preliminary layer L3a may comprise a material containing a heat-resistant amorphous transparent conductive oxide as described above.

[0108] Next, as Figure 7As explained, a resonance control layer RCL can be formed on the third preliminary layer L3a. For example, the resonance control layer RCL can be formed on the third preliminary layer L3a of the second sub-pixel region SP2 and the third sub-pixel region SP3. Here, the process of forming the resonance control layer RCL may include a process of depositing a layer (e.g., a silicon oxide layer; hereinafter referred to as the preliminary resonance control layer) as a raw material for the resonance control layer RCL on the third preliminary layer L3a, a process of forming a photoresist pattern on the deposited first preliminary electrode ANDa, and a process of etching (e.g., dry etching) the preliminary resonance control layer using the photoresist pattern as a mask. In this case, the heat applied during the process of depositing the preliminary resonance control layer, the heat applied during the pre-baking process of curing the photoresist pattern, and the heat caused by plasma during the etching process can be applied to the third preliminary layer L3a. However, because the third preliminary layer L3a comprises a heat-resistant amorphous transparent conductive oxide as described above, the third preliminary layer L3a can remain amorphous and not crystallize even under the influence of the aforementioned heat. In other words, during the process of forming the resonance control layer RCL, the third preliminary layer L3a can remain amorphous. Because the first preliminary layer L1a is covered by a thick second preliminary layer L2a (e.g., a second preliminary layer L2a comprising silver (Ag) material), the aforementioned heat can be applied relatively less to the first preliminary layer L1a (e.g., a first preliminary layer L1a comprising ITO material). Accordingly, during the process of forming the resonance control layer RCL, the first preliminary layer L1a can remain amorphous.

[0109] Next, as Figure 8 As explained, a first preliminary electrode ANDa (e.g., a first preliminary electrode ANDa comprising ITO material) can be formed on the resonance control layer RCL and the third preliminary layer L3a. The first preliminary electrode ANDa can be made of a material comprising ITO (e.g., amorphous ITO). Because heat can be applied when depositing the first preliminary electrode ANDa, this heat can also be applied to the aforementioned third preliminary layer L3a and first preliminary layer L1a. However, in this case, for the reasons described above, the third preliminary layer L3a and the first preliminary layer L1a can each remain in an amorphous state.

[0110] Subsequently, as Figure 9As explained, a photoresist pattern PR can be formed on the first preliminary electrode ANDa. For example, the photoresist pattern PR can be formed on the first preliminary electrode ANDa to overlap with the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3. Next, the photoresist pattern PR can be used as a mask to simultaneously pattern (e.g., etch) the first preliminary electrode ANDa, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a. For example, the exposed portions of the first preliminary electrode ANDa not covered by the photoresist pattern PR can be removed by an etching process, the exposed portions of the third preliminary layer L3a not covered by the photoresist pattern PR can be removed by an etching process, the exposed portions of the second preliminary layer L2a not covered by the photoresist pattern PR can be removed by an etching process, and the exposed portions of the first preliminary layer L1a not covered by the photoresist pattern PR can be removed by an etching process. In other words, by using the above-mentioned photoresist pattern PR as a mask in the patterning process, the first preliminary electrode ANDa, the third preliminary layer L3a, the second preliminary layer L2a and the first preliminary layer L1a in each of the sub-pixel regions SP1, SP2 and SP3 can be retained, and the first preliminary electrode ANDa, the third preliminary layer L3a, the second preliminary layer L2a and the first preliminary layer L1a in the non-pixel region NPA between adjacent sub-pixel regions can be removed.

[0111] The patterning process using the aforementioned photoresist pattern PR as a mask, such as... Figure 10As explained, a reflective electrode RL and a first electrode AND can be formed on the second insulating layer INS2. For example, a reflective electrode RL comprising a first layer L1, a second layer L2, and a third layer L3 can be formed on the second insulating layer INS2, which overlaps with the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3, and a first electrode AND connected to the third layer L3 can be formed. Because the first preliminary electrode ANDa, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a are removed from the non-pixel region NPA, the second insulating layer INS2 can be exposed in the non-pixel region NPA. In this case, as described above, because the third preliminary layer L3a is made of a material comprising an amorphous transparent conductive oxide, and furthermore, the first preliminary electrode ANDa can remain amorphous due to the amorphous state of the third preliminary layer L3a, and furthermore, the first layer L1 is covered by a thick second layer L2 and remains amorphous, so during the patterning process for the aforementioned first preliminary electrode ANDa, third preliminary layer L3a, second preliminary layer L2a, and first preliminary layer L1a, residues (e.g., ITO residues) of the first preliminary electrode ANDa, third preliminary layer L3a, and first preliminary layer L1a may not be retained in the non-pixel region NPA. For example, during the etching process, no residue may form in the non-pixel region NPA. In particular, compared to the first preliminary electrode ANDa, the third preliminary layer L3a, which is not covered by the second preliminary layer L2a, can be exposed to the heat source multiple times before the patterning process of the reflective electrode RL and the first electrode ANDa, and therefore the third preliminary layer L3a has the highest probability of crystallization. However, as mentioned above, because the third preliminary layer L3a is made of a material comprising a heat-resistant amorphous transparent conductive oxide, no residue of the third preliminary layer L3a is formed in the non-pixel region NPA after the patterning process. Because the first preliminary electrode ANDa is exposed to relatively little heat source from the deposition process to the patterning process, the first preliminary electrode ANDa can remain amorphous at approximately 260 degrees Celsius or lower until it is patterned (or before it is patterned). Therefore, no residue of the first preliminary electrode ANDa (e.g., ITO residue) is formed in the non-pixel region NPA after the first preliminary electrode ANDa is patterned.

[0112] Subsequently, as Figure 11As illustrated, a capping layer CPL can be formed covering the edge of the first electrode AND and filling the gaps between adjacent sub-pixel regions (e.g., non-pixel regions NPA). For example, the capping layer CPL can be formed on the edge of the first electrode AND and the edge of the second insulating layer INS2 of the non-pixel regions NPA. After forming the capping layer CPL, a heat treatment process for curing the capping layer CPL can be performed. Here, the heat applied during the heat treatment process for the capping layer CPL can be higher than the heat applied in processes performed before the heat treatment process for the capping layer CPL (e.g., the heat applied during a pre-baking process). By the heat applied during the heat treatment process for the capping layer CPL, the first layer L1 (e.g., a first layer L1 comprising ITO material) and the first electrode AND (e.g., a first electrode AND comprising ITO material) can be crystallized. For example, before the heat treatment process for the capping layer CPL, the first layer L1 and the first electrode AND may comprise amorphous ITO material, while after the heat treatment process for the capping layer CPL, the first layer L1 and the first electrode AND may comprise crystalline ITO material.

[0113] Before and after the heat treatment process for the capping layer CPL, the third layer L3 may comprise an amorphous transparent conductive oxide. In other words, the third layer L3 may maintain the same amorphous state before and after the heat treatment process for the capping layer CPL. However, the third layer L3 is not limited to this, and depending on the material composition of the third layer L3, the third layer L3 may remain amorphous before the heat treatment process for the capping layer CPL and may transform into a crystalline state after the heat treatment process for the capping layer CPL. According to the embodiment, because the first preliminary layer L1a, the second preliminary layer L2a, the third preliminary layer L3a, and the first preliminary electrode ANDa are patterned into the first layer L1, the second layer L2, the third layer L3, and the first electrode ANDa by the etching process (or until the first preliminary electrode ANDa is patterned), the first preliminary layer L1a, the third preliminary layer L3a, and the first preliminary electrode ANDa remain amorphous at a temperature of about 260 degrees Celsius or lower, thus preventing the formation of residues (e.g., ITO residues) in the non-pixel region NPA after the patterning process. Therefore, the electrical short circuit problem between the reflective electrodes RL of adjacent sub-pixel regions SP1, SP2 and SP3 can be solved.

[0114] Next, as Figure 12 As explained, a pixel defining layer (PDL) can be formed on the edge of the first electrode AND and on the capping layer CPL. In this case, the pixel defining layer (PDL) can be formed on the first electrode AND so that the light-emitting regions EA1, EA2, and EA3 overlap with the first electrode AND.

[0115] Subsequently, as Figure 4As explained, a light-emitting stacked layer IL can be formed on the first electrode AND and the pixel-defining layer PDL. In this case, the light-emitting stacked layer IL can be segmented by the tip TP of the pixel-defining layer PDL. Subsequently, a second electrode CAT can be formed on the light-emitting stacked layer IL, and then an encapsulation layer ENC can be formed on the second electrode CAT. Next, as... Figure 3 As explained, an adhesive layer APL can be formed on the encapsulation layer ENC, and then a color filter layer CFL can be formed on the adhesive layer APL.

[0116] Figure 13 This is a cross-sectional view of the display device 10 according to an embodiment. For example, Figure 13 Can be Figure 2 A cross-sectional view of the display panel 100. Specifically, Figure 13 This can be a cross-sectional view of the display area DAA of the display panel 100. Figure 14 for Figure 13 A magnified view of region B.

[0117] Figure 13 and Figure 14 The display device 10 and Figure 3 and Figure 4 The difference of the display device 10 is that, Figure 13 and Figure 14 The display device 10 further includes a fourth layer L4, and this difference will be mainly described below.

[0118] like Figure 13 and Figure 14 As explained, the reflective electrode RL may include multiple reflective layers sequentially stacked along a third direction DR3 on the second insulating layer INS2. For example, the reflective electrode RL may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 disposed along the third direction DR3 between the second insulating layer INS2 and the first electrode AND (or the resonant control layer RCL). As a specific example, the reflective electrode RL of the first sub-pixel region SP1 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 disposed between the second insulating layer INS2 and the first electrode AND of the first sub-pixel region SP1. Additionally, the reflective electrode RL of the second sub-pixel region SP2 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 disposed between the second insulating layer INS2 and the resonant control layer RCL of the second sub-pixel region SP2. Furthermore, the reflective electrode RL of the third sub-pixel region SP3 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 disposed between the second insulating layer INS2 and the resonant control layer RCL of the third sub-pixel region SP3.

[0119] because Figure 13 and Figure 14The first layer L1, the second layer L2, and the third layer L3 are the same as those mentioned above. Figure 3 and Figure 4 The first layer L1, the second layer L2, and the third layer L3 are basically the same, so Figure 13 and Figure 14 The descriptions of the first layer L1, the second layer L2, and the third layer L3 are as described above. Figure 3 and Figure 4 Related descriptions.

[0120] A fourth layer L4 can be disposed on the third layer L3. For example, the fourth layer L4 of the first sub-pixel region SP1 can be disposed between the third layer L3 of the first sub-pixel region SP1 and the first electrode AND of the first sub-pixel region SP1. Additionally, the fourth layer L4 of the second sub-pixel region SP2 can be disposed between the third layer L3 of the second sub-pixel region SP2 and the resonant control layer RCL of the second sub-pixel region SP2. Furthermore, the fourth layer L4 of the third sub-pixel region SP3 can be disposed between the third layer L3 of the third sub-pixel region SP3 and the resonant control layer RCL of the third sub-pixel region SP3. The fourth layer L4 can be made of a material including indium tin oxide (ITO).

[0121] When the fourth layer L4 and the first electrode AND are made of the same material, there may be no interface between the fourth layer L4 and the first electrode AND. For example, when the fourth layer L4 and the first electrode AND are made of the same material, the fourth layer L4 and the first electrode AND can be integrally formed without an interface.

[0122] A first electrode AND can be set on the fourth layer L4 of the first sub-pixel region SP1, a resonance control layer RCL can be set on the fourth layer L4 of the second sub-pixel region SP2, and a resonance control layer RCL can be set on the fourth layer L4 of the third sub-pixel region SP3.

[0123] According to an embodiment, when the reflective electrode RL comprises first to fourth layers L1, L2, L3, and L4, the thickness tk of the third layer L3 of the reflective electrode RL can be from 30 Å to 150 Å. The thickness tk of the third layer L3 can be the dimension of the third layer L3 in the light-emitting region (e.g., the first light-emitting region EA1) on the third-direction DR3. When the thickness tk of the third layer L3 is less than a preset lower threshold, the third layer L3 can be formed in an island shape on the second layer L2, resulting in the exposure of the second layer L2. And when the thickness tk of the third layer L3 is greater than a preset upper threshold, the light transmission efficiency can be reduced. The thickness tk of the third layer L3 can be from 30 Å to 150 Å. For example, the preset lower threshold for the thickness tk of the third layer L3 can be 30 Å, and the preset upper threshold can be 150 Å. As mentioned above, even if the third layer L3 forms an undercut shape due to the etching ratio between the resonant control layer RCL and the third layer L3, the fourth layer L4 and the first electrode AND can still contact each other, thereby solving the problem of poor contact between the reflective electrode RL and the first electrode AND.

[0124] The total thickness of the third layer L3 (tk) and the fourth layer L4 can be 300 Å. Here, the thickness of the fourth layer L4 can be the dimension of the fourth layer L4 on the third-direction DR3.

[0125] Figure 15 This is a cross-sectional view used to describe the configuration of the third layer L3 according to an embodiment. For example, Figure 15 for Figure 14 A magnified view of region C.

[0126] like Figure 15 As explained in the text, the third layer L3 may include multiple sublayers containing different materials. For example, the third layer L3 may include a first sublayer L31 on the second layer L2, a second sublayer L32 on the first sublayer L31, and a third sublayer L33 on the second sublayer L32.

[0127] The first sublayer L31, the second sublayer L32, and the third sublayer L33 may comprise different amorphous transparent conductive oxides. For example, the first sublayer L31 may comprise an amorphous transparent conductive oxide, including any one of Sn-doped IZO, IZO, IGZO, ITZO, IGO, ITGO, ITO, and ITGZO. Additionally, the second sublayer L32 may comprise an amorphous transparent conductive oxide, including another one of IZO, IGZO, ITZO, IGO, ITGO, ITO, and ITGZO. Furthermore, the third sublayer L33 may comprise an amorphous transparent conductive oxide, including the remaining one of IZO, IGZO, ITZO, IGO, ITGO, ITO, and ITGZO.

[0128] Figure 15 An example is illustrated where the third layer L3 comprises three sublayers L31, L32, and L33 containing different amorphous transparent conductive oxides; however, the number of sublayers L31, L32, and L33 is not limited thereto. For example, the third layer L3 may also comprise two sublayers containing different amorphous transparent conductive oxides. Alternatively, the third layer L3 may also comprise four or more sublayers containing different amorphous transparent conductive oxides.

[0129] Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a cross-sectional view of a process used to describe a method for manufacturing a display device 10 according to an embodiment. For example, Figures 16 to 22 For the purpose of describing the manufacture of the above Figure 14 A process cross-sectional view of the method for displaying device 10.

[0130] First, such as Figure 13 and Figure 16 As explained, a buffer layer BF can be formed on the substrate SUB, and then a plurality of transistors TR can be formed on the buffer layer BF, and then a first insulating layer INS1 can be formed on the plurality of transistors TR, and then a plurality of connection electrodes CNE can be formed on the first insulating layer INS1, and then a second insulating layer INS2 can be formed on the plurality of connection electrodes CNE. Subsequently, a plurality of contact holes CT can be formed that penetrate the second insulating layer INS2 and expose the plurality of connection electrodes CNE.

[0131] Subsequently, a preliminary reflective electrode RLa comprising a first preliminary layer L1a, a second preliminary layer L2a, a third preliminary layer L3a, and a fourth preliminary layer L4a can be formed on the second insulating layer INS2. For example, the first preliminary layer L1a can be formed on the second insulating layer INS2, and then the second preliminary layer L2a can be formed on the first preliminary layer L1a, then the third preliminary layer L3a can be formed on the second preliminary layer L2a, and then the fourth preliminary layer L4a can be formed on the third preliminary layer L3a. In this case, the fourth preliminary layer L4a may comprise a material containing ITO (e.g., amorphous ITO). Additionally, the third preliminary layer L3a may comprise a material containing a heat-resistant amorphous transparent conductive oxide as described above. In this case, because the third preliminary layer L3a comprises a material containing a non-directional amorphous transparent conductive oxide, the formation of seed crystals of the fourth preliminary layer L4a (e.g., the fourth preliminary layer L4a comprising ITO) formed on the third preliminary layer L3a can be suppressed.

[0132] Next, as Figure 17As explained above, a resonance control layer RCL can be formed on the fourth preliminary layer L4a. For example, the resonance control layer RCL can be formed on the fourth preliminary layer L4a of the second sub-pixel region SP2 and the third sub-pixel region SP3. Here, the first preliminary layer L1a, the third preliminary layer L3a, and the fourth preliminary layer L4a can each remain in an amorphous state. For a detailed description of the above basics, please refer to the above... Figure 7 The relevant description.

[0133] Next, as Figure 18 As explained, a first preliminary electrode ANDa (e.g., a first preliminary electrode ANDa comprising ITO material) can be formed on the resonance control layer RCL and the fourth preliminary layer L4a. In this case, for the reasons described above, the fourth preliminary layer L4a, the third preliminary layer L3a, and the first preliminary layer L1a can each remain in an amorphous state.

[0134] Subsequently, as Figure 19 As explained, a photoresist pattern PR can be formed on the first preliminary electrode ANDa. For example, the photoresist pattern PR can be formed on the first preliminary electrode ANDa to overlap with the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3. Next, the photoresist pattern PR can be used as a mask to simultaneously pattern (e.g., etch) the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a. For example, the exposed portion of the first preliminary electrode ANDa that is not covered by the photoresist pattern PR can be removed by etching; the exposed portion of the fourth preliminary layer L4a that is not covered by the photoresist pattern PR can be removed by etching; the exposed portion of the third preliminary layer L3a that is not covered by the photoresist pattern PR can be removed by etching; the exposed portion of the second preliminary layer L2a that is not covered by the photoresist pattern PR can be removed by etching; and the exposed portion of the first preliminary layer L1a that is not covered by the photoresist pattern PR can be removed by etching. In other words, by using the above-mentioned photoresist pattern PR as a mask, the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a in each of the sub-pixel regions SP1, SP2, and SP3 can be retained, while the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a in the non-pixel region NPA between adjacent sub-pixel regions can be removed.

[0135] Patterning processes using the aforementioned photoresist pattern PR as a mask, such as... Figure 20As explained, a reflective electrode RL and a first electrode AND can be formed on the second insulating layer INS2. For example, a reflective electrode RL comprising a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 can be formed on the second insulating layer INS2, which overlaps with the first sub-pixel region SP1, the second sub-pixel region SP2, and the third sub-pixel region SP3, and a first electrode AND connected to the fourth layer L4 can be formed. Because the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a are removed from the non-pixel region NPA, the second insulating layer INS2 can be exposed in the non-pixel region NPA. In this case, as described above, because the third preliminary layer L3a is made of a material comprising an amorphous transparent conductive oxide, and furthermore, the fourth preliminary layer L4a can remain amorphous due to the amorphous state of the third preliminary layer L3a, and furthermore, the first layer L1 is covered by a thick second layer L2 and remains amorphous, so during the patterning process for the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, the second preliminary layer L2a, and the first preliminary layer L1a, residues (e.g., ITO residues) of the first preliminary electrode ANDa, the fourth preliminary layer L4a, the third preliminary layer L3a, and the first preliminary layer L1a may not be retained in the non-pixel region NPA. For example, during the etching process, no residue may form in the non-pixel region NPA. In particular, compared to the first preliminary electrode ANDa, the third preliminary layer L3a, which is not covered by the second preliminary layer L2a, can be exposed to the heat source multiple times before the patterning process of the reflective electrode RL and the first electrode ANDa, and therefore the third preliminary layer L3a has the highest probability of crystallization. However, as mentioned above, because the third preliminary layer L3a is made of a material comprising a heat-resistant amorphous transparent conductive oxide, no residue of the third preliminary layer L3a is formed in the non-pixel region NPA after the patterning process. Because the first preliminary electrode ANDa is exposed to relatively little heat source from the deposition process to the patterning process, the first preliminary electrode ANDa can remain amorphous at approximately 260 degrees Celsius or lower until it is patterned (or before it is patterned). Therefore, no residue of the first preliminary electrode ANDa (e.g., ITO residue) is formed in the non-pixel region NPA after the first preliminary electrode ANDa is patterned.

[0136] Subsequently, as Figure 21As illustrated, a capping layer CPL can be formed to cover the edge of the first electrode AND and fill the gap between adjacent sub-pixel regions (e.g., non-pixel regions NPA). For example, the capping layer CPL can be formed on the edge of the first electrode AND and the edge of the second insulating layer INS2 of the non-pixel regions NPA. After forming the capping layer CPL, a heat treatment process for curing the capping layer CPL can be performed. Here, the heat applied during the heat treatment process for the capping layer CPL can be higher than the heat applied in the heat treatment process performed before the process for the capping layer CPL (e.g., the heat applied during the pre-baking process). By the heat applied during the heat treatment process for the capping layer CPL, the first layer L1 (e.g., a first layer L1 comprising ITO material), the fourth layer L4 (e.g., a fourth layer L4 comprising ITO material), and the first electrode AND (e.g., a first electrode AND comprising ITO material) can crystallize. For example, up to the heat treatment process used for the capping layer CPL, the first layer L1, the fourth layer L4, and the first electrode AND may comprise amorphous ITO material, while after the heat treatment process used for the capping layer CPL, the first layer L1, the fourth layer L4, and the first electrode AND may comprise crystalline ITO material.

[0137] Before and after the heat treatment process used for the capping layer CPL, the third layer L3 may comprise an amorphous transparent conductive oxide. In other words, the third layer L3 may maintain the same amorphous state before and after the heat treatment process used for the capping layer CPL. However, the third layer L3 is not limited to this, and depending on the material composition of the third layer L3, the third layer L3 may remain amorphous before the heat treatment process used for the capping layer CPL and may transform into a crystalline state after the heat treatment process used for the capping layer CPL. According to the implementation, because the first preliminary layer L1a, the second preliminary layer L2a, the third preliminary layer L3a, the fourth preliminary layer L4a, and the first preliminary electrode ANDa remain amorphous at a temperature of approximately 260 degrees Celsius or lower until the first preliminary layer L1a, the second preliminary layer L2a, the third preliminary layer L3a, the fourth preliminary layer L4a, and the first preliminary electrode ANDa are patterned by an etching process (or until the first preliminary electrode ANDa is patterned), the formation of residues (e.g., ITO residues) in the non-pixel region NPA after the patterning process can be prevented. Therefore, the electrical short circuit problem between the reflective electrodes RL of adjacent sub-pixel regions SP1, SP2, and SP3 can be solved.

[0138] Next, as Figure 22 As explained, a pixel defining layer (PDL) can be formed on the edge of the first electrode AND and on the capping layer CPL. In this case, the pixel defining layer (PDL) can be formed on the first electrode AND so that the light-emitting regions EA1, EA2, and EA3 overlap with the first electrode AND.

[0139] Subsequently, as Figure 14 As explained, a light-emitting stacked layer IL can be formed on the first electrode AND and the pixel-defining layer PDL. In this case, the light-emitting stacked layer IL can be segmented by the tip TP of the pixel-defining layer PDL. Subsequently, a second electrode CAT can be formed on the light-emitting stacked layer IL, and then an encapsulation layer ENC can be formed on the second electrode CAT. Next, as... Figure 13 As explained, an adhesive layer APL can be formed on the encapsulation layer ENC, and then a color filter layer CFL can be formed on the adhesive layer APL.

[0140] Figure 23 This is a photograph of the non-pixel area of ​​the display device 10 according to the embodiment.

[0141] like Figure 23 As explained, no ITO residue forms in the non-pixel region NPA. For example, no ITO residue forms on the second insulating layer INS2 in the non-pixel region NPA. Therefore, the reflective electrode RL in adjacent sub-pixel regions can be resolved. Figure 3 and Figure 13 The problem of electrical short circuit between ( ).

[0142] Display device 10 according to the embodiment ( Figure 1 This technology can be applied to various electronic devices. According to the embodiments, the electronic device may include the aforementioned display device 10, and may further include modules or devices with additional functions in addition to the display device 10.

[0143] Figure 24 This is a block diagram of an electronic device 50 according to an embodiment. (See reference...) Figure 24 The electronic device 50 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 may further include an input module 15, a non-image output module 16, and / or a communication module 17.

[0144] Electronic device 50 can output various information in the form of images through display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 11. Power module 14 may include a power supply module (e.g., a power adapter or battery device) and a power conversion module, which converts the power supplied by the power supply module to generate the power required for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Non-image output module 16 can be used to receive information other than images received from processor 12 (e.g., sound, touch, and light) and provide the information to the user. Communication module 17 is a module responsible for transmitting and receiving information between electronic device 50 and external devices, and may include a receiving unit and a transmitting unit.

[0145] At least one of the components of the electronic device 50 described above may be included in the display device according to the above embodiment. Additionally, some modules that are functionally included in a single module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided within the electronic device 50 as other devices besides the display device.

[0146] Figure 25 , Figure 26 and Figure 27 This is a schematic diagram of an electronic device according to various embodiments. Figures 25 to 27 The display device 10 applicable according to the embodiment is explained. Figure 1 Examples of various electronic devices.

[0147] Figure 25 Examples of electronic devices are illustrated, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0148] In addition to the display module 11, the smartphone 10_1a may also include an input module (e.g., a touch sensor) and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0149] Similar to the smartphone 10_1a, the tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e also include a display module and an input module, and in some cases, may further include a communication module.

[0150] Figure 26This section explains the application of electronic devices, including a display module, in wearable electronic devices. Wearable electronic devices can include smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.

[0151] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides the reflected display image to the user's eyes. The display module and the reflector may provide the user with a virtual reality screen or an augmented reality screen.

[0152] The smartwatch 10_2c includes a biometric sensor as an input device and can provide users with biometric information identified by the biometric sensor through a display module.

[0153] Figure 27 An example of applying the electronic device 10_3, which includes a display module, to a vehicle is illustrated. For example, the electronic device 10_3 can be applied to the dashboard, center console, etc. of a car, or it can be applied to a center information display (CID) installed on the dashboard of a car or an interior mirror display that replaces the side mirrors.

[0154] In concluding this detailed description, those skilled in the art will recognize that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments of the invention disclosed herein are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A display device, comprising: The substrate includes sub-pixel regions and non-pixel regions; Transistors, on the substrate; A first insulating layer is present on the transistor; A connecting electrode is disposed on the first insulating layer and connected to the transistor; A second insulating layer is provided on the connecting electrode; A reflective electrode is disposed on the second insulating layer and connected to the connecting electrode; The first electrode is located on the reflecting electrode; A light-emitting stacked layer is disposed on the first electrode; as well as The second electrode is located on the light-emitting stacked layer. The reflective electrode and the first electrode are disposed in the sub-pixel region. The reflective electrode includes: The first layer is disposed between the second insulating layer and the first electrode and is connected to the connecting electrode; A second layer, disposed between the first layer and the first electrode, and comprising silver; and The third layer is located between the second layer and the first electrode. The third layer and the second layer are in direct contact with each other, and The third layer comprises a transparent conductive oxide that is in an amorphous state at a temperature of 260 degrees Celsius or lower after deposition.

2. The display device according to claim 1, wherein the transparent conductive oxide in the third layer is in a crystalline state at a temperature greater than 260 degrees Celsius.

3. The display device according to claim 1, wherein the third layer comprises at least one of tin-doped indium zinc oxide, indium zinc oxide, indium gallium zinc oxide, indium tin zinc oxide, indium gallium oxide, indium tin gallium oxide, indium tin oxide, and indium tin gallium zinc oxide.

4. The display device according to claim 3, wherein when the third layer comprises the tin-doped indium zinc oxide, the third layer comprises 12 at% to 22 at% tin relative to the total number of metal atoms in the third layer.

5. The display device according to claim 3, wherein when the third layer comprises indium gallium zinc oxide, the third layer comprises 44.2 wt% indium oxide, 29.6 wt% gallium oxide and 25.9 wt% zinc oxide.

6. The display device according to claim 3, wherein when the third layer comprises indium zinc oxide, the third layer comprises 10 at% to 25 at% zinc and 75 at% to 90 at% indium relative to the total number of metal atoms in the third layer.

7. The display device according to claim 3, wherein when the third layer comprises indium zinc oxide, the third layer comprises 90 wt% indium oxide and 10 wt% zinc oxide relative to the total weight of the third layer.

8. The display device according to claim 3, wherein when the third layer comprises indium tin zinc oxide, the third layer comprises 6 at% to 22 at% tin relative to the total number of metal atoms in the third layer, provided that the atomic ratio of indium to zinc is 1:

1.

9. The display device of claim 3, wherein when the third layer comprises indium gallium oxide, the third layer comprises more than 95 wt% indium oxide and less than 5 wt% gallium oxide relative to the total weight of the third layer.

10. The display device according to claim 1, wherein the third layer has a thickness of 30 Å to 300 Å.

11. The display device according to claim 1, wherein the total thickness of the first electrode and the third layer is 150 Å to 700 Å.

12. The display device of claim 1, wherein the sub-pixel region is configured to provide green light.

13. The display device according to claim 1, further comprising a resonance control layer between the third layer and the first electrode. The sub-pixel region is configured to provide red or blue light.

14. The display device of claim 1, wherein the first layer and the first electrode each comprise crystalline indium tin oxide, and The second layer includes silver.

15. The display device of claim 1, wherein the reflective electrode further comprises a fourth layer between the third layer and the first electrode, and The fourth layer comprises crystalline indium tin oxide.

16. The display device according to claim 15, wherein the thickness of the third layer is 30 Å to 150 Å, and The total thickness of the third and fourth layers is 300 Å.

17. The display device of claim 1, wherein the third layer comprises a plurality of sublayers comprising different transparent conductive oxides.

18. The display device according to claim 1, further comprising: A capping layer is disposed on the edge of the first electrode and the edge of the second insulating layer in the non-pixel region; as well as A pixel defining layer is disposed on the edge of the first electrode and on the capping layer, and defines a light-emitting area that overlaps with the first electrode.

19. An electronic device comprising: processor; Memory, connected to the processor; as well as A display device is connected to the processor and the memory. The display device includes: The substrate includes sub-pixel regions and non-pixel regions; Transistors, on the substrate; A first insulating layer is present on the transistor; A connecting electrode is disposed on the first insulating layer and connected to the transistor; A second insulating layer is provided on the connecting electrode; A reflective electrode is disposed on the second insulating layer and connected to the connecting electrode; The first electrode is located on the reflecting electrode; A light-emitting stacked layer is formed on the first electrode; and The second electrode is located on the light-emitting stacked layer. The reflective electrode and the first electrode are disposed on the sub-pixel region. The reflective electrode includes: The first layer is disposed between the second insulating layer and the first electrode and is connected to the connecting electrode; A second layer, disposed between the first layer and the first electrode, and comprising silver; and The third layer is located between the second layer and the first electrode. The third layer and the second layer are in direct contact with each other, and The third layer comprises a transparent conductive oxide that is in an amorphous state at a temperature of 260 degrees Celsius or lower after deposition.

20. A method for manufacturing a display device, the method comprising: A substrate comprising a first sub-pixel region, a second sub-pixel region, and a non-pixel region is prepared. A first transistor and a second transistor are formed on the substrate; A first insulating layer is formed on the first transistor and the second transistor; A first connection electrode connected to the first transistor and a second connection electrode connected to the second transistor are formed on the first insulating layer; A second insulating layer is formed on the first connecting electrode and the second connecting electrode; A first contact hole exposing the first connecting electrode and a second contact hole exposing the second connecting electrode are formed in the second insulating layer; A first preliminary layer is formed on the second insulating layer, the first preliminary layer being connected to the first connection electrode and the second connection electrode through the first contact hole and the second contact hole, respectively, and comprising amorphous indium tin oxide; A second preliminary layer is formed on the first preliminary layer; A third preliminary layer comprising an amorphous transparent conductive oxide is formed on the second preliminary layer; A resonance control layer is formed on the third preliminary layer in the second sub-pixel region; A first preliminary electrode is formed on the third preliminary layer and the resonance control layer; A photoresist pattern is formed on the first preliminary electrode in the first sub-pixel region and the second sub-pixel region; By using the photoresist pattern as a mask to pattern the first preliminary layer, the second preliminary layer, the third preliminary layer, and the first preliminary electrode, a first-first reflective layer connected to the first connecting electrode, a first-second reflective layer disposed on the first-first reflective layer, a first-third reflective layer disposed on the first-second reflective layer, and a first-first electrode disposed on the first-third reflective layer are formed in the first sub-pixel region. Similarly, a second-first reflective layer connected to the second connecting electrode, a second-second reflective layer disposed on the second-first reflective layer, a second-third reflective layer disposed on the second-second reflective layer, and a second-first electrode disposed on the second-third reflective layer and the resonance control layer are formed in the second sub-pixel region. A capping layer is formed on the edges of the first and second electrodes and the edge of the second insulating layer in the non-pixel region; as well as The sealing layer is heat-treated. Prior to the heat treatment of the capping layer, the first first reflective layer, the first first electrode, the second first reflective layer, and the second first electrode each comprise amorphous indium tin oxide material, and after the heat treatment of the capping layer, the first first reflective layer, the first first electrode, the second first reflective layer, and the second first electrode each comprise crystalline indium tin oxide material. Before the formation of the first electrode and the second electrode, the first and second reflective layers each comprise an amorphous transparent conductive oxide.

Images