Package structure, package chip and voltage value detection method

Abstract

The embodiment of the present disclosure provides a packaging structure, a packaging chip and a voltage value detection method, and belongs to the technical field of chips. The packaging structure is used for electrically connecting a chip. The chip surface is provided with a positive electrode power supply bump. The packaging structure comprises: a plurality of metal wiring layers and a plurality of dielectric layers which are vertically stacked and spaced apart. A positive electrode power supply pin for electrically connecting with the positive electrode power supply bump is arranged on the top dielectric layer. A positive electrode power supply solder ball is arranged on the bottom dielectric layer. The positive electrode power supply pin and the positive electrode power supply solder ball are electrically connected through the plurality of metal wiring layers. A plurality of positive electrode detection points are arranged on a plurality of target metal wiring layers. The positive electrode detection points are electrically connected with the positive electrode power supply circuit through the target metal wiring layers. A plurality of positive electrode detection solder balls are arranged on the bottom dielectric layer. The positive electrode detection solder balls are electrically connected with the corresponding positive electrode detection points. The positive electrode detection points and the positive electrode detection solder balls are used for determining the voltage value at the positive electrode power supply bump. The present scheme can reduce the design difficulty of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a packaging structure, a packaged chip, and a voltage value detection method. Background Technology

[0002] The chip is powered through a Power Distribution Network (PDN), which includes power and ground planes on the printed circuit board (PCB), cables, connectors, and other power-related capacitors. The PDN distributes low-noise DC voltages to active devices within the chip, provides low-noise loops for signals, and mitigates electromagnetic interference (EMI). Poor noise control in the PDN can lead to chip malfunction. To verify the effectiveness of the PDN's noise control, it is necessary to test the voltage values ​​at the chip's power supply pins to perform power integrity testing.

[0003] Currently, a power detection bump is added to the chip. The detection bump is connected to the power supply bump inside the chip. The detection bump is connected to the solder ball at the bottom of the package through the trace in the package. The voltage value at the power supply bump of the chip is detected by the solder ball at the bottom of the package.

[0004] However, the number of bumps on a chip is limited. Setting up detection bumps on the chip for power integrity testing will occupy limited bump resources, making the chip design more difficult. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a packaging structure, a packaged chip, and a voltage value detection method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a packaging structure is provided for electrically connecting a chip, wherein a positive power supply bump is provided on the surface of the chip, and the packaging structure includes: a plurality of metal wiring layers and a plurality of dielectric layers; the metal wiring layers and the dielectric layers are vertically stacked and spaced apart, and the top and bottom layers of the stacked plurality of metal wiring layers and the plurality of dielectric layers are both dielectric layers; a positive power supply pin for electrically connecting to the positive power supply bump is provided on the top dielectric layer, and a positive power supply solder ball is provided on the bottom dielectric layer, wherein the positive power supply pin and the positive power supply solder ball are electrically connected through the plurality of metal wiring layers; Positive detection points are provided on multiple target metal wiring layers among the multiple metal wiring layers. Each target metal wiring layer has at least one positive detection point. The positive detection point is electrically connected to the positive power supply line between the target metal wiring layer and the positive power supply pin and the positive power supply solder ball. Multiple positive detection solder balls are provided on the bottom dielectric layer. The positive detection solder balls are electrically connected to the corresponding positive detection points. Different positive detection solder balls correspond to different positive detection points. The positive detection points and positive detection solder balls are used to determine the voltage value at the positive power supply bump.

[0007] According to a second aspect of the present disclosure, a packaged chip is provided, comprising: a chip and a package structure as described in the first aspect above, wherein the chip is bonded to the top dielectric layer of the package structure, and the positive power supply bump of the chip is electrically connected to the positive power supply pin included in the package structure.

[0008] According to a third aspect of the present disclosure, a voltage value detection method is provided for detecting the voltage value at the positive power supply bump in a packaged chip as described in the second aspect above. The method includes: after a first voltage is applied to the positive power supply solder ball, measuring a second voltage at the positive detection point electrically connected to the positive detection solder ball through the positive detection solder ball; calculating a first impedance between the positive detection point and the positive power supply solder ball based on the second voltage and the first voltage; determining a second impedance between the positive power supply bump and the positive power supply solder ball based on a plurality of the first impedances and the target metal wiring layer where the positive detection point is located; and determining the voltage value at the positive power supply bump based on the first voltage and the second impedance.

[0009] According to the scheme provided in this embodiment, multiple positive detection points are led out from the positive power supply line. Each positive detection point is electrically connected to a corresponding positive detection solder ball. By detecting the voltage at the positive detection solder ball, the voltage at each positive detection point can be obtained. Based on the voltage at each positive detection point, a mapping relationship can be fitted between the impedance between the connection point on the power supply line and the positive power supply solder ball, and the metal wiring layer where the connection point is located. Since the impedance between the connection point on the top metal wiring layer and the positive power supply bump is approximately zero, the impedance between the positive power supply bump and the positive power supply solder ball can be determined based on this mapping relationship. Furthermore, based on the impedance between the positive power supply bump and the positive power supply solder ball and the test voltage applied to the positive power supply solder ball, the voltage at the positive power supply bump can be determined. Based on the above packaging structure, the voltage value at the positive power supply bump can be detected using positive detection points and positive detection solder balls. This achieves power integrity testing of the chip without occupying a limited number of bumps on the chip, reducing the design complexity of the chip. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0011] Figure 1 This is a schematic diagram of the packaging structure according to an embodiment of the present disclosure;

[0012] Figure 2 This is a schematic diagram of the packaging structure according to another embodiment of the present disclosure;

[0013] Figure 3 This is a schematic diagram of the packaging structure of yet another embodiment of this disclosure;

[0014] Figure 4 This is a schematic diagram of the packaging structure according to another embodiment of the present disclosure;

[0015] Figure 5 This is a schematic diagram of a packaged chip according to an embodiment of the present disclosure;

[0016] Figure 6 This is a flowchart of a voltage value detection method according to an embodiment of the present disclosure;

[0017] Figure 7 This is a schematic diagram of the straight line represented by the impedance formula of one embodiment of this disclosure;

[0018] Figure 8 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0021] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0023] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0024] First, some nouns or terms appearing in the description of the embodiments of this disclosure shall be interpreted as follows:

[0025] Chip: Also known as an integrated circuit (IC), a chip is a miniature electronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) onto a small semiconductor material. Chips can be classified into various types based on their function and application, such as Central Processing Units (CPUs), Application-Specific Integrated Circuits (ASICs), and Field-Programmable Gate Arrays (FPGAs).

[0026] Metal wiring layer: The metal wiring layer is a metal line layer used to connect various components and realize electrical connections during the chip packaging process. The metal wiring layer enables the signals inside the chip to be effectively transmitted to the outside, and also supports power distribution and signal processing.

[0027] Bumps: Bumps are tiny metal protrusions in semiconductor packages used to connect the chip to external circuitry. They are typically made of metals such as gold, copper, or tin and are precisely placed on the chip's pads to provide electrical connections and mechanical support.

[0028] Solder balls: Solder balls are metal balls used to connect chips to a substrate or a substrate to a printed circuit board (PCB). They are typically made of metals such as tin, lead, copper, or gold and are used to achieve electrical connections and physical support.

[0029] Vias: A via is a conductive hole used in multilayer packaging structures or multilayer PCBs to achieve electrical connections between different layers. Vias penetrate the dielectric layer (insulating layer), enabling signal transmission and power distribution in the vertical direction.

[0030] Packaging structure

[0031] Figure 1 and Figure 2 A schematic diagram of a packaging structure according to an embodiment of this disclosure is shown. Figure 1 and Figure 2 As shown, the package structure 10 is used for electrical connection to the chip 20, and the surface of the chip 20 is provided with a positive power supply bump 21. The package structure 10 includes multiple metal wiring layers 11 and multiple dielectric layers 12. Figure 1As an example, 12 metal wiring layers 11 are shown. The metal wiring layers 11 and the dielectric layers 12 are stacked vertically and spaced apart, and after multiple metal wiring layers 11 and multiple dielectric layers 12 are stacked, the top and bottom layers are both dielectric layers 12.

[0032] like Figure 1 and Figure 2 As shown, a positive power supply pin 13 for electrical connection with the positive power supply bump 21 is provided on the top dielectric layer, and a positive power supply solder ball 14 is provided on the bottom dielectric layer. The positive power supply pin 13 and the positive power supply solder ball 14 are electrically connected through each metal wiring layer 11. It should be noted that the chip 20 may include multiple positive power supply bumps 21, and different positive power supply bumps 21 provide different voltages to the chip 20. Correspondingly, multiple positive power supply pins 13 are provided on the top dielectric layer. Since the measurement structure set in the package structure 10 is the same for detecting the voltage value of different positive power supply bumps 21, this embodiment of the disclosure takes the provision of one positive power supply pin 13 on the top dielectric layer as an example for explanation.

[0033] The top dielectric layer is the dielectric layer 12 located at the top of the package structure 10, and the bottom dielectric layer is the dielectric layer 12 located at the bottom of the package structure 10. Figure 2 Taking the encapsulation structure 10 shown as an example, according to the top-to-bottom order shown in the figure, the first dielectric layer 12 is the top dielectric layer, and the thirteenth dielectric layer 12 is the bottom dielectric layer.

[0034] The plurality of metal wiring layers 11 includes a plurality of target metal wiring layers, each target metal wiring layer having a positive electrode detection point 15, and each target metal wiring layer having at least one positive electrode detection point 15. For example... Figure 2 As shown in the diagram, following the top-to-bottom order, the 3rd, 4th, and 9th metal wiring layers 11 are the target metal wiring layers. One positive electrode detection point 15 is provided on each of the 3rd and 9th metal wiring layers 11, and two positive electrode detection points 15 are provided on the 4th metal wiring layer 11. It should be noted that... Figure 2 The target metal wiring layer and positive electrode detection point 15 shown are only one example of this disclosure. In other embodiments, the target metal wiring layer can be any multiple metal wiring layers 11, and one or more positive electrode detection points 15 can be provided on each target metal wiring layer.

[0035] The positive detection point 15 is electrically connected to the positive power supply line between the positive power supply pin 13 and the positive power supply solder ball 14 through the target metal wiring layer it resides in. The positive detection point 15 is electrically connected to the positive power supply line between the positive power supply pin 13 and the positive power supply solder ball 14 through the metal trace or metal plane in its target metal wiring layer. Since the impedance of the metal trace or metal plane on the same metal wiring layer 11 is small, the voltage of the positive detection point 15 is approximately equal to the voltage at the connection point corresponding to the positive detection point 15 when voltage detection is performed. The connection point corresponding to the positive detection point 15 refers to the connection position between the positive detection point 15 and the positive power supply line.

[0036] The positive power supply line is composed of interconnected metal traces or metal planes on each metal wiring layer 11. Metal traces or metal planes on adjacent metal wiring layers 11 are electrically connected through vias penetrating the dielectric layer 12 between these two metal wiring layers 11. Therefore, the positive power supply line includes metal traces / metal planes on the metal wiring layers 11 and multiple vias penetrating each dielectric layer 12. The relative positions of the vias in the positive power supply line on the corresponding dielectric layer 12 can be different; that is, the axis of each via is parallel to the stacking direction of the metal wiring layers 11 and the dielectric layer 12, but the axes of different vias may not coincide. For example... Figure 2 As shown, in the order from top to bottom, among the vias included in the positive power supply line, the axis of the via located in the first dielectric layer 12 does not coincide with the axis of the via located in the second dielectric layer 12, while the axes of the vias located in the first and third to twelfth dielectric layers coincide with each other.

[0037] Multiple positive detection solder balls 16 are arranged on the bottom dielectric layer. The number of positive detection solder balls 16 is equal to the number of positive detection points 15, with each positive detection point 15 corresponding to one positive detection solder ball 16. Different positive detection points 15 correspond to different positive detection solder balls 16. The positive detection solder balls 16 are electrically connected to their corresponding positive detection points 15. Viewed from the positive power supply bump 21 side, the circuit connecting the positive detection point 15 and the positive detection solder ball 16 is a parallel connection of a capacitor, inductor, and resistor. As the frequency changes, the impedance caused by the parasitic inductance gradually increases, while the impedance caused by the decoupling capacitor gradually decreases. To ensure that the resonant point is not located within the operating range, a decoupling capacitor is added to shift the resonance backward, thereby achieving a low-impedance state for the positive power supply line. Compared to the positive power supply line, the circuit connecting the positive detection point 15 and the positive detection solder ball 16 has high-impedance characteristics. Therefore, during voltage detection, the voltage at the positive detection solder ball 16 is equal to the voltage at the connected positive detection point 15.

[0038] Since the voltage at the positive detection solder ball 16 is equal to the voltage at the connected positive detection point 15, and the voltage at the positive detection point 15 is equal to the voltage at its corresponding connection point, and the connection point is located on the positive power supply line, and the connection point corresponding to the positive detection point 15 is located on the same metal wiring layer 11 as the positive detection point 15, after applying a test voltage to the positive power supply solder ball 14, the voltage at each positive detection point 15 can be obtained by detecting the voltage at each positive detection solder ball 16. Based on the voltage at the positive detection point 15, the test voltage, and the current on the positive power supply line, the impedance between the positive detection point 15 and the positive power supply solder ball 14 can be determined. Furthermore, the mapping relationship between the impedance between the connection point on the positive power supply line and the positive power supply solder ball 14, and the metal wiring layer where the connection point is located can be fitted. Since the positive power supply bump 21 is electrically connected to the positive power supply pin 13, the voltage at the positive power supply bump 21 is equal to the voltage at the positive power supply pin 13. Since the positive power supply pin 13 is located at the upper end of the positive power supply line, the voltage at the positive power supply bump 21 can be determined according to the above mapping relationship.

[0039] It should be noted that, unless otherwise stated, the mapping relationship in the following embodiments refers to the mapping relationship between the impedance between the connection point on the positive power supply line and the positive power supply solder ball 14, and the metal wiring layer where the connection point is located.

[0040] In this embodiment of the disclosure, multiple positive detection points 15 are led out from the positive power supply line. The positive detection points 15 are electrically connected to the corresponding positive detection solder balls 16. By detecting the voltage at the positive detection solder balls 16, the voltage at each positive detection point 15 can be obtained. Based on the voltage at each positive detection point 15, the mapping relationship between the impedance between the connection point on the power supply line and the positive power supply solder ball 14 and the metal wiring layer where the connection point is located can be fitted. The impedance between the connection point located in the top metal wiring layer and the positive power supply bump 21 is approximately equal to 0. Therefore, the impedance between the positive power supply bump 21 and the positive power supply solder ball 14 can be determined based on this mapping relationship. Furthermore, based on the impedance between the positive power supply bump 21 and the positive power supply solder ball 14 and the test voltage acting on the positive power supply solder ball 14, the voltage at the positive power supply bump 21 can be determined. Based on the above-mentioned packaging structure 10, the voltage value at the positive power supply bump 21 can be detected by the positive detection point 15 and the positive detection solder ball 16. While performing power integrity testing on the chip 20, it does not occupy the limited number of bumps on the chip 20, thus reducing the design difficulty of the chip 20.

[0041] In one possible implementation, such as Figure 3As shown, the multiple dielectric layers 12 in the package structure 10 include a first dielectric layer 121 and multiple second dielectric layers 122, wherein the thickness of the first dielectric layer 121 is greater than the thickness of the second dielectric layers 122. At least one metal wiring layer 11 exists between the first dielectric layer 121 and the top dielectric layer, and at least one metal wiring layer 11 exists between the first dielectric layer 121 and the bottom dielectric layer. Both the top dielectric layer and the bottom dielectric layer belong to the second dielectric layer 122. Figure 3 As shown, there are six metal wiring layers 11 between the first dielectric layer 121 and the top dielectric layer, and six metal wiring layers 11 between the first dielectric layer 121 and the bottom dielectric layer. The target metal wiring layer with the positive detection point 15 is located between the first dielectric layer 121 and the top dielectric layer.

[0042] The first dielectric layer 121 has a larger thickness than the second dielectric layer 121. The first dielectric layer 121 serves as the foundation of the package structure 10, ensuring sufficient strength. The first dielectric layer 121 and the metal wiring layers 11 on both sides can be implemented using a double-sided copper-clad laminate. The metal wiring layers 11 and dielectric layers 12 are stacked on top and bottom of this double-sided copper-clad laminate to form the package structure 10. The thickness of each second dielectric layer 122 is less than that of the first dielectric layer 121, but the thickness of each second dielectric layer 122 can be different.

[0043] In this embodiment, the thicker first dielectric layer 121 serves as the foundation of the package structure 10, ensuring its structural strength. However, since the parasitic inductance of the vias on the first dielectric layer 121 accounts for a large proportion of the total inductance of the package path, if the target metal wiring layer is located between the first dielectric layer 121 and the bottom dielectric layer, the large parasitic inductance of the vias on the first dielectric layer 121 will cause a significant error in the fitted mapping relationship, resulting in a large error in the voltage detection result at the positive power supply bump 21. By placing the target metal wiring layer between the first dielectric layer 121 and the top dielectric layer, the fitted mapping relationship can eliminate the influence of the parasitic inductance of the vias on the first dielectric layer 121, thereby ensuring the accuracy of the voltage detection at the positive power supply bump 21.

[0044] In one possible implementation, the target metal wiring layer is a metal wiring layer 11 on which the power plane of the chip 20 is disposed.

[0045] The power plane is a metal layer (such as a copper layer) in the package structure 10 specifically used to provide power. It is usually specified as the supply voltage (Volt Current Condenser, VCC) and can provide a stable voltage for the chip 20.

[0046] In this embodiment, since the power plane of the chip 20 has a large area, when the positive detection point 15 is set on the metal wiring layer 11 where the power plane is located, there are many positions where the positive detection point 15 can be set. This makes it easy to determine the positive detection point 15 that avoids the power supply path and signal path of the chip 20, reducing the design difficulty of the package structure 10.

[0047] In one possible implementation, in the direction perpendicular to the metal wiring layer 11 (i.e., the stacking direction of the metal wiring layer 11 and the dielectric layer 12), the distance between the projection of the positive detection point 15 and the positive power supply pin 13 onto the underlying dielectric is less than a distance threshold, and the distance between the projection of the positive power supply pin 13 onto the underlying dielectric layer and the positive detection solder ball 16 is less than a distance threshold.

[0048] A three-dimensional Cartesian coordinate system is constructed with the X and Y axes parallel to the metal wiring layer 11 and the Z axis perpendicular to the metal wiring layer 11. The Z axis is parallel to the stacking direction of the metal wiring layer 11 and the dielectric layer 12. The distance between the projections of the positive detection point 15 and the positive power supply pin 13 on the XY plane is less than a distance threshold, and the distance between the projections of the positive power supply pin 13 and the positive detection solder ball 16 on the XY plane is also less than a distance threshold. That is, the positional offset of the positive detection point 15 and the positive detection solder ball 16 relative to the positive power supply pin 13 in the X and Y axis directions is small.

[0049] In this embodiment, since the positive power supply pin 13 and the positive power supply bump 21 are electrically connected, the X and Y coordinates of the positive power supply pin 13 and the positive power supply bump 21 are the same. This makes the positional offset of the positive detection point 15 and the positive detection solder ball 16 relative to the positive power supply pin 13 in the X and Y axis directions small. As a result, the voltage difference between the positive detection point 15 and the positive power supply bump 21 comes from the difference in resistance and inductance in the Z direction. This ensures the accuracy of the mapping relationship fitted based on the voltage of the positive detection point 15, and thus ensures the accuracy of the voltage at the positive power supply bump 21 determined based on the mapping relationship.

[0050] In one possible implementation, such as Figure 2 and Figure 3 As shown, the positive electrode detection point 15 and the corresponding positive electrode detection solder ball 16 are electrically connected by a metal wire, and the stacking direction of the metal wiring layer 11 and the dielectric layer 12 is parallel to the metal wire.

[0051] It should be noted that, unless otherwise specified, the stacking direction in the following embodiments refers to the stacking direction of the metal wiring layer 11 and the dielectric layer 12.

[0052] The positive detection point 15 and the corresponding positive detection solder ball 16 are electrically connected via a metal wire parallel to the stacking direction, meaning that the X and Y coordinates of the positive detection point 15 and the corresponding positive detection solder ball 16 are the same. The metal wire connecting the positive detection point 15 and the corresponding positive detection solder ball 16 passes through each metal wiring layer 11 and dielectric layer 12 below the target metal wiring layer where the positive detection point 15 is located, and then becomes electrically connected to the corresponding positive detection solder ball 16. When the metal wire passes through the metal wiring layer 11, it is insulated from the metal traces and metal planes on the metal wiring layer 11.

[0053] In this embodiment, the positive detection point 15 and the corresponding positive detection solder ball 16 are electrically connected by a metal wire parallel to the stacking direction. This metal wire between the positive detection point 15 and the corresponding positive detection solder ball 16 has a high-resistance characteristic relative to the positive power supply line, ensuring that the voltage at the positive detection point 15 is equal to the voltage at the corresponding positive detection solder ball 16. This allows the voltage at the corresponding positive detection point 15 to be detected by the positive detection solder ball 16, guaranteeing the accuracy of the fitted mapping relationship. Connecting the positive detection point 15 and the corresponding positive detection solder ball 16 by a metal wire parallel to the stacking direction simplifies the design of the electrical connection path and does not affect the power supply and signal paths of the chip 20 in the package structure 10.

[0054] In one possible implementation, such as Figure 4 As shown, chip 20 has a positive power supply bump 21 and a negative power supply bump 22. The package structure 10 forms a power supply circuit for chip 20 through the positive power supply bump 21 and the negative power supply bump 22. A negative power supply pin 17 for electrical connection with the negative power supply bump 22 is provided on the top dielectric layer, and a negative power supply solder ball 18 is provided on the bottom dielectric layer. The negative power supply pin 17 and the negative power supply solder ball 18 are electrically connected through multiple metal wiring layers 11. It should be noted that chip 20 may include multiple negative power supply bumps 22. Different negative power supply bumps 22 and corresponding positive power supply bumps 21 are connected in the chip to form a power supply circuit for chip 20. Correspondingly, multiple negative power supply pins 17 are provided on the top dielectric layer. The package structure 10 has similar designs for different negative power supply pins 17. This embodiment of the disclosure takes the provision of one negative power supply pin 17 on the top dielectric layer as an example for illustration.

[0055] The negative power supply line between the negative power supply pin 17 and the negative power supply solder ball 18 is formed by interconnecting metal traces or metal planes on each metal wiring layer 11. Metal traces or metal planes on adjacent metal wiring layers 11 are electrically connected through vias penetrating the dielectric layer 12 between these two metal wiring layers 11. Therefore, the negative power supply line includes metal traces / metal planes on the metal wiring layers 11 and multiple vias penetrating each dielectric layer 12. The relative positions of the vias included in the negative power supply line on the corresponding dielectric layer 12 can be different; that is, the axis of each via is parallel to the stacking direction, but the axes of different vias do not need to coincide. For example... Figure 4 As shown, following the top-to-bottom order in the diagram, among the vias included in the negative power supply line, the axis of the via located in the first dielectric layer 12 does not coincide with the axis of the vias located in the second to thirteenth dielectric layers 12; the axis of the via located in the second dielectric layer 12 coincides with the axis of the via located in the third dielectric layer 12; the axis of the via located in the second dielectric layer 12 does not coincide with the axis of the vias located in the fourth to thirteenth dielectric layers 12; and the axes of the vias located in the fourth to thirteenth dielectric layers 12 coincide with each other. The routing method of the negative power supply line can be referred to the positive power supply line in the aforementioned embodiment, and will not be repeated here.

[0056] At least a portion of the target metal wiring layer has a negative electrode detection point 19, and the negative electrode detection point 19 and the corresponding positive electrode detection point 15 are located on the same target metal wiring layer, such as... Figure 4 As shown, in top-to-bottom order, the first target metal wiring layer with a positive electrode detection point 15 does not have a negative electrode detection point 19, while the second and third target metal wiring layers with positive electrode detection points 15 have negative electrode detection points 19. When a target metal wiring layer has multiple positive electrode detection points 15, the negative electrode detection points 19 on that target metal wiring layer can correspond to multiple positive electrode detection points 15, such as... Figure 4 As shown, in the order from left to right, the first negative electrode detection point 19 corresponds to the second and third positive electrode detection points 15, and the second negative electrode detection point 19 corresponds to the fourth positive electrode detection point 15.

[0057] If a positive detection point 15 is provided on a target metal wiring layer, but no negative detection point 19 is provided, then when measuring the voltage value at the positive detection point 15 on the target metal wiring layer, the test voltage is applied between the positive detection solder ball 16 and the negative power supply solder ball 18, which are electrically connected to the positive detection point 15.

[0058] The negative electrode detection point 19 is electrically connected to the negative electrode power supply line through the target metal wiring layer it resides in. The negative electrode detection point 19 is also electrically connected to the negative electrode power supply line through a metal trace or metal plane within the target metal wiring layer. At least one negative electrode detection solder ball 110 is provided on the bottom dielectric layer. The number of negative electrode detection solder balls 110 is equal to the number of negative electrode detection points 19, with each negative electrode detection solder ball 110 corresponding to one negative electrode detection point 19. Different negative electrode detection points 19 correspond to different negative electrode detection solder balls 110, and the negative electrode detection point 19 is electrically connected to its corresponding negative electrode detection solder ball 110. The negative electrode power supply line is in a low-resistance state.

[0059] The negative electrode detection point 19 and the negative electrode detection solder ball 110 can form a detection circuit with the positive electrode detection point 15 and the positive electrode detection solder ball 16 when determining the voltage value of the positive electrode power supply bump 21. For example... Figure 4 As shown, when measuring the voltage at the positive detection point 15, after applying a first voltage between the positive power supply solder ball 14 and the negative power supply solder ball 18, the voltage between the first positive detection solder ball 16 and the negative detection solder ball 110 is measured in the following order from left to right as shown in the figure, and this voltage is taken as the voltage at the first positive detection point 15. The voltage between the second positive detection solder ball 16 and the first negative detection solder ball 110 is measured and this voltage is taken as the voltage at the second positive detection point 15. The voltage between the third positive detection solder ball 16 and the first negative detection solder ball 110 is measured and this voltage is taken as the voltage at the third positive detection point 15. The voltage between the fourth positive detection solder ball 16 and the second negative detection solder ball 110 is measured and this voltage is taken as the voltage at the fourth positive detection point 15.

[0060] In this embodiment, the positive power supply bump 21 and the negative power supply bump 22 are input differential power supply signals. By setting a negative detection point 19 and a negative detection solder ball 110, when detecting the voltage at the positive detection point 15, the voltage between the positive power supply solder ball 14 connected to the positive detection point 15 and the corresponding negative detection solder ball 110 is measured as the voltage at the positive detection point 15. This eliminates the interference of common-mode interference factors, ensuring the accuracy of the measured voltage value at the positive detection point 15, and thus ensuring the accuracy of the determined voltage value at the positive power supply bump 21. When there is no negative detection point 19 on the target metal wiring layer, the voltage between the positive power supply solder ball 14 connected to the positive detection point 15 and the negative power supply solder ball 18 on the target metal wiring layer is measured as the voltage at the positive detection point 15. Although the measurement result has a small error, the voltage value at the positive power supply bump 21 can still be determined, and the determined voltage value at the positive power supply bump 21 still has reference value.

[0061] In one possible implementation, such as Figure 4As shown, the negative electrode detection point 19 is electrically connected to the corresponding negative electrode detection solder ball 110 through a metal wire, and the stacking direction of the metal wiring layer 11 and the dielectric layer 12 is parallel to the metal wire.

[0062] The negative electrode detection point 19 is electrically connected to the corresponding negative electrode detection solder ball 110 via a metal wire parallel to the stacking direction, meaning that the X and Y coordinates of the negative electrode detection point 19 and the corresponding negative electrode detection solder ball 110 are the same. The metal wire connecting the negative electrode detection point 19 and the corresponding negative electrode detection solder ball 110 passes through each metal wiring layer 11 and dielectric layer 12 below the target metal wiring layer where the negative electrode detection point 19 is located, and then becomes electrically connected to the corresponding negative electrode detection solder ball 110. When the metal wire passes through the metal wiring layer 11, it is insulated from the metal traces and metal planes on the metal wiring layer 11.

[0063] In this embodiment, the negative electrode detection point 19 and the corresponding negative electrode detection solder ball 110 are electrically connected by a metal wire parallel to the stacking direction. This makes the metal wire between the negative electrode detection point 19 and the corresponding negative electrode detection solder ball 110 have high resistance characteristics relative to the negative power supply line. Consequently, the line between the positive electrode detection solder ball 16 and the corresponding negative electrode detection solder ball 110 has high resistance characteristics, resulting in the voltage at the positive electrode detection point 15 being equal to the voltage at the corresponding positive electrode detection solder ball 16. This allows the voltage at the corresponding positive electrode detection point 15 to be detected by the positive electrode detection solder ball 16, ensuring the accuracy of the fitted mapping relationship. Connecting the negative electrode detection point 19 and the corresponding negative electrode detection solder ball 110 by a metal wire parallel to the stacking direction facilitates the design of the electrical connection path and does not affect the power supply and signal paths of the chip 20 in the package structure 10.

[0064] It should be noted that the relevant features of the negative electrode detection point 19 can be found in the description of the positive electrode detection point 15 in the previous embodiment, and the relevant features of the negative electrode detection solder ball 110 can be found in the description of the positive electrode detection solder ball 16 in the previous embodiment, and will not be repeated here.

[0065] Packaged chip

[0066] Figure 5 A packaged chip according to one embodiment of this disclosure is shown, such as Figure 5 As shown, the packaged chip 500 includes a chip 20 and a packaged structure 10 as described in any of the above embodiments. The chip 20 is bonded to the top dielectric layer of the packaged structure 10, and the positive power supply bump 21 of the chip 20 is electrically connected to the positive power supply pin 13 of the packaged structure 10. The negative power supply bump 22 of the chip 20 is electrically connected to the negative power supply pin 17 of the packaged structure 10.

[0067] Chip 20 can be any chip that needs to be packaged by the packaging structure 10. The present disclosure does not limit the function of chip 20.

[0068] It should be noted that the packaged chip 500 in this embodiment is based on the same concept as the packaged structure 10 in the previous embodiment and has the beneficial effects of the aforementioned packaged structure embodiments, which will not be repeated here.

[0069] Voltage detection method

[0070] Figure 6 A flowchart of a voltage value detection method according to an embodiment of this disclosure is shown. This method is used to detect the voltage value at the positive power supply bump 21 of the chip 20 in the packaged chip 500 in any of the above embodiments. Figure 6 As shown, the voltage value detection method includes the following steps:

[0071] Step 601: After the first voltage is applied to the positive power supply solder ball, the second voltage of the positive detection point electrically connected to the positive detection solder ball is measured through the positive detection solder ball.

[0072] like Figure 4 As shown, a first voltage is applied between the positive power supply solder ball 14 and the negative power supply solder ball 18. This first voltage is the voltage that needs to be applied between the positive power supply solder ball 14 and the negative power supply solder ball 18 when the chip 20 is working normally. After applying the first voltage, the voltage between the positive detection solder ball 16 and the corresponding negative detection solder ball 110 / negative power supply solder ball 18 is measured. The measured voltage is used as the second voltage of the positive detection point 15 electrically connected to the positive detection solder ball 16.

[0073] In one possible implementation, if the package structure 10 includes a negative detection point 19 corresponding to the positive detection point 15, the second voltage at the positive detection point 15 is measured using a positive detection solder ball 16 connected to the positive detection point 15 and a negative detection solder ball 110 electrically connected to the negative detection point 19. If the package structure does not include a negative detection point 19 corresponding to the positive detection point 15, the second voltage at the positive detection point 15 is measured using a positive detection solder ball 16 electrically connected to the positive detection point 15 and a negative power supply solder ball 18 included in the package structure 10.

[0074] For example, such as Figure 4As shown, after applying the first voltage, the voltage between the first positive detection solder ball 16 and the negative detection solder ball 110 is measured in the following order from left to right, as the second voltage at the first positive detection point 15. The voltage between the second positive detection solder ball 16 and the first negative detection solder ball 110 is measured, as the second voltage at the second positive detection point 15. The voltage between the third positive detection solder ball 16 and the first negative detection solder ball 110 is measured, as the second voltage at the third positive detection point 15. The voltage between the fourth positive detection solder ball 16 and the second negative detection solder ball 110 is measured, as the second voltage at the fourth positive detection point 15.

[0075] In this embodiment, when the package structure 10 includes a negative detection point 19 corresponding to the positive detection point 15, the second voltage at the positive detection point 15 is detected by the corresponding positive detection solder ball 16 and negative detection solder ball 110. This eliminates the interference of common-mode interference factors, making the measured second voltage closer to the actual voltage at the positive detection point 15, thereby ensuring the accuracy of the voltage at the subsequently calculated positive power supply bump 21. When the package structure 10 does not include the negative detection point 19 corresponding to the positive detection point 15, the second voltage at the positive detection point 15 is detected by the positive detection solder ball 16 and negative power supply solder ball 18 electrically connected to the positive detection point 15. While there may be errors due to common-mode interference factors in the measurement results, the accuracy requirements for detecting the voltage at the positive power supply bump 21 can still be met, thereby improving the applicability of the voltage detection method.

[0076] Step 602: Calculate the first impedance between the positive detection point and the positive power supply solder ball based on the second voltage and the first voltage of the positive detection point.

[0077] The current in the line between the positive detection point 15 and the positive power supply solder ball 14 is equal to the current in the positive power supply line, which is a known quantity. The voltage at the positive detection solder ball 16 is equal to the first voltage, and the voltage at the positive detection point 15 is the second voltage. Therefore, the first impedance between the positive detection point 15 and the positive power supply solder ball 14 can be calculated based on the first voltage, the second voltage at the positive detection point 15, and the current in the positive power supply line.

[0078] In one possible implementation, the first impedance between the positive detection point 15 and the positive power supply solder ball 14 can be calculated using the following formula (1):

[0079] Z1=(V1-V2) / I#(1)

[0080] In the above formula (1), Z1 represents the first impedance between the positive detection point 15 and the positive power supply solder ball 14, V1 represents the first voltage, V2 represents the second voltage at the positive detection point 15, and I represents the current on the positive power supply line.

[0081] The above formula (1) can be used to calculate the following respectively. Figure 4 The first impedance between the four positive detection points 15 and the positive power supply solder ball 14.

[0082] In this embodiment of the disclosure, based on the second voltage at the positive detection point 15, the first voltage at the positive power supply solder ball 14, and the current on the positive power supply line, the first impedance between the positive detection point 15 and the positive power supply solder ball 14 is calculated using Ohm's law, ensuring the accuracy of the calculated first impedance.

[0083] Step 603: Determine the second impedance between the positive power supply bump and the positive power supply solder ball based on the multiple first impedances and the target metal wiring layer where the positive detection point is located.

[0084] The target point is a point on the positive power supply line. As the distance between the target point and the positive power supply solder ball 14 increases, the impedance between the target point and the positive power supply solder ball 14 increases linearly. That is, the impedance between the target point and the positive power supply solder ball 14 is linearly related to the position of the target point on the positive power supply line. Since the circuit connecting the positive detection point 15 and the positive detection solder ball 16 has a high impedance characteristic, the voltage at the target point on the positive power supply line located in the same metal wiring layer 11 as the positive detection point 15 is equal to the voltage at the positive detection point 15. Therefore, based on the second voltage of each positive detection point 15 and the target metal wiring layer it is located in, the mapping relationship between the impedance between the target point and the positive power supply solder ball 14 and the metal wiring layer 11 where the target point is located can be fitted. Since the impedance between the positive power supply bump 21 and the target point located in the top metal wiring layer is approximately equal to 0, the impedance between the target point located in the top metal wiring layer and the positive power supply solder ball 14 can be calculated through the above mapping relationship, and this impedance is determined as the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14.

[0085] In one possible implementation, when determining the second impedance based on the first impedance and the target metal wiring layer where the positive detection point 15 is located, the impedance formula can be recursively derived using the least squares method based on the first impedance and the target metal wiring layer where the positive detection point 15 is located. The impedance formula indicates the mapping relationship between the location information of the target point on the positive power supply line and the impedance between the target point and the positive power supply solder ball 14. The impedance formula is shown in the following formula (2):

[0086] y=kx+b#(2)

[0087] In formula (2) above, y represents the impedance between the target point and the positive power supply solder ball 14 on the positive power supply line, x represents the position information of the target point, which is determined according to the position of the target metal wiring layer in the stacked multiple metal wiring layers, and k and b are constants. When the number of vias in the area where each positive detection point 15 is located on the target metal wiring layer is the same, x represents the change in the number of metal wiring layers. Figure 4 The order shown from top to bottom is as follows: b represents the inherent impedance below the 6th metal wiring layer 11. k represents the impedance change ratio for each metal wiring layer 11.

[0088] When deriving the impedance formula using the least squares method, if the difference in the number of vias in the region where each positive detection point 15 is located on the target metal wiring layer is less than a threshold, meaning the number of vias in the region where different positive detection points 15 are located on the target metal wiring layer is not significantly different, then the layer number corresponding to the metal wiring layer where the positive detection point 15 is located is determined as the location information of the positive detection point 15, according to the order of the metal wiring layers 11 from top to bottom. For example, according to... Figure 4 As shown in the top-to-bottom order, the position information of the positive detection point 15 on the 3rd metal wiring layer 11 is 4 (=6-3+1), the position information of the positive detection point 15 on the 4th metal wiring layer 11 is 3 (=6-4+1), and the position information of the positive detection point 15 on the 6th metal wiring layer 11 is 1 (=6-6+1).

[0089] If the difference in the number of vias in the region where each positive electrode detection point 15 is located on the target metal wiring layer is greater than a threshold, meaning the number of vias in the region where different positive electrode detection points 15 are located on the target metal wiring layer is large, then for positive electrode detection points 15 with a smaller number of vias in their respective regions, the location information of the positive electrode detection point 15 is equal to the product of the layer number of the target metal wiring layer in which the positive electrode detection point 15 is located and the influence coefficient, where the influence coefficient is a real number greater than or equal to 1. The positive electrode detection point 15 with the largest number of vias in its region is defined as the reference positive electrode detection point. The influence coefficient corresponding to the positive electrode detection point 15 is determined based on the difference between the number of vias in the region where the reference positive electrode detection point is located and the number of vias in the region where the positive electrode detection point 15 is located. The influence coefficient is positively correlated with this difference. For example, according to... Figure 4As shown in the top-to-bottom order, the area where the positive electrode detection point 15 is located on the 3rd metal wiring layer 11 has a relatively large number of vias, and the influence coefficient corresponding to the positive electrode detection point 15 is 1, so the position information of the positive electrode detection point 15 is 4. The area where the positive electrode detection point 15 is located on the 4th metal wiring layer 11 has a relatively small number of vias, and the influence coefficient corresponding to the positive electrode detection point 15 is 1.2, so the position information of the positive electrode detection point 15 is 3.6. The area where the positive electrode detection point 15 is located on the 6th metal wiring layer 11 has an even smaller number of vias, and the influence coefficient corresponding to the positive electrode detection point 15 is 1.4, so the position information of the positive electrode detection point 15 is 1.4.

[0090] In one example Figure 7 A schematic diagram of the straight line represented by the impedance formula is shown, with points 701 to 704 corresponding to... Figure 4 The impedance between the four positive detection points 15 and the positive power supply solder ball 14 is derived using the least squares method based on points 701 to 704. The straight line represented by the impedance formula is 705.

[0091] After obtaining the impedance formula, the position information of the positive power supply bump 21 is substituted into the impedance formula to calculate the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14. Since the impedance between the positive power supply bump 21 and the target point located on the top metal wiring layer is approximately equal to 0, the position information of the target point on the top metal wiring layer can be substituted into the impedance formula to calculate the impedance between the target point on the top metal wiring layer and the positive power supply solder ball 14, and this impedance is determined as the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14.

[0092] In one example, the impedance formula is y = 0.0058x + 0.0068, as follows: Figure 4 As shown, the location information of the target point on the top metal wiring layer is 6, and the impedance between the target point on the top metal wiring layer and the positive power supply solder ball 14 is 0.0416 ohms.

[0093] In this embodiment, since the impedance between the target point and the positive power supply solder ball 14 on the positive power supply line is linearly related to the distance between the target point and the positive power supply solder ball 14, the target metal wiring layer where the target point is located can indicate the distance between the target point and the positive power supply solder ball 14. The impedance between the positive detection point 15 on the same target metal wiring layer and the target point is approximately equal to 0. Therefore, based on the first impedance between the positive detection point 15 and the positive power supply solder ball 14 and the target metal wiring layer where the positive detection point 15 is located, the impedance formula can be recursively derived. Then, the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14 can be calculated based on the impedance formula, ensuring the accuracy of the calculated second impedance.

[0094] Step 604: Determine the voltage value at the positive power supply bump based on the first voltage and the second impedance.

[0095] The current on the positive power supply line is known. After obtaining the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14 and the first voltage at the positive power supply solder ball 14, the voltage value at the positive power supply bump 21 can be calculated using Ohm's law based on the second resistance, the first voltage and the circuit on the positive power supply line.

[0096] In one possible implementation, the voltage at the positive power supply bump 21 is calculated using the following formula (3):

[0097] V3=V1-Z2·I#(3)

[0098] In the above formula (3), V3 represents the voltage value at the positive power supply bump 21, V1 represents the first voltage, Z2 represents the second impedance, and I represents the current on the positive power supply line.

[0099] In this embodiment of the disclosure, the voltage value at the positive power supply bump 21 is calculated using Ohm's law based on the first voltage at the positive power supply solder ball 14, the second impedance between the positive power supply bump 21 and the positive power supply solder ball 14, and the current on the positive power supply line, thus ensuring the accuracy of the calculation results.

[0100] The voltage detection method provided in this embodiment draws multiple positive detection points from the positive power supply line. Each positive detection point is electrically connected to a corresponding positive detection solder ball. By detecting the voltage at the positive detection solder ball, the voltage at each positive detection point can be obtained. Based on the voltage at each positive detection point, a mapping relationship can be fitted between the impedance between the connection point on the power supply line and the positive power supply solder ball, and the metal wiring layer where the connection point is located. Since the impedance between the connection point located on the top metal wiring layer and the positive power supply bump is approximately zero, the impedance between the positive power supply bump and the positive power supply solder ball can be determined based on this mapping relationship. Furthermore, based on the impedance between the positive power supply bump and the positive power supply solder ball and the test voltage acting on the positive power supply solder ball, the voltage at the positive power supply bump can be determined. Based on the above packaging structure, the voltage value at the positive power supply bump can be detected through the positive detection points and positive detection solder balls. This achieves power integrity testing of the chip without occupying the limited number of bumps on the chip, reducing the design complexity of the chip.

[0101] It should be noted that the voltage detection method in this embodiment is based on the packaged chip and packaged structure in the foregoing embodiments, and has the beneficial effects of the packaged chip embodiment and the packaged structure embodiment. The specific process of detecting the voltage value can be found in the descriptions in the foregoing packaged chip embodiment and packaged structure embodiment, and will not be repeated here.

[0102] electronic devices

[0103] Figure 8 This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Specific embodiments of this disclosure do not limit the specific implementation of the electronic device. Figure 8 As shown, the electronic device may include: a processor 802, a communications interface 804, a memory 806, and a communications bus 808. Wherein:

[0104] The processor 802, communication interface 804, and memory 806 communicate with each other through the communication bus 808.

[0105] Communication interface 804 is used to communicate with other electronic devices or servers.

[0106] The processor 802 is used to execute program 8010, which can specifically execute the relevant steps in any of the aforementioned voltage value detection method embodiments.

[0107] Specifically, program 8010 may include program code that includes computer operation instructions.

[0108] The processor 802 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0109] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects such as microcontrollers and FPGA chips, and can be specifically applied to fields such as IoT security, industrial control, mobile phones, and personal computers. Because it was designed with small size, speed, and low power consumption in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems.

[0110] The computer operation instructions in this embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 802 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the voltage value detection method in the above embodiment.

[0111] Memory 806 is used to store program 8010. Memory 806 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0112] Specifically, program 8010 can be used to cause processor 802 to execute the voltage value detection method in any of the foregoing embodiments.

[0113] The specific implementation of each step in program 8010 can be found in the corresponding steps and units described in any of the aforementioned voltage value detection method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0114] The electronic device according to this disclosure embodiment has multiple positive detection points led out from the positive power supply line. Each positive detection point is electrically connected to a corresponding positive detection solder ball. By detecting the voltage at the positive detection solder ball, the voltage at each positive detection point can be obtained. Based on the voltage at each positive detection point, a mapping relationship can be fitted between the impedance between the connection point on the power supply line and the positive power supply solder ball, and the metal wiring layer where the connection point is located. Since the impedance between the connection point on the top metal wiring layer and the positive power supply bump is approximately zero, the impedance between the positive power supply bump and the positive power supply solder ball can be determined based on this mapping relationship. Furthermore, based on the impedance between the positive power supply bump and the positive power supply solder ball and the test voltage applied to the positive power supply solder ball, the voltage at the positive power supply bump can be determined. Based on the above packaging structure, the voltage value at the positive power supply bump can be detected using positive detection points and positive detection solder balls. This achieves power integrity testing of the chip without occupying a limited number of bumps on the chip, reducing the design complexity of the chip.

[0115] Computer storage media

[0116] This disclosure also provides a computer-readable storage medium storing instructions for causing a machine to perform the voltage value detection method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0117] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this disclosure.

[0118] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0119] Computer program products

[0120] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0121] It should be understood that the various embodiments in this description are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0122] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0123] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply a limitation on the number of such elements to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0124] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A packaging structure for electrically connecting a chip, wherein a positive power supply bump is provided on the surface of the chip, the packaging structure comprising: Multiple metal wiring layers and multiple dielectric layers; The metal wiring layer and the dielectric layer are stacked vertically and spaced apart, and the top and bottom layers of the stacked metal wiring layer and the dielectric layer are both the dielectric layer; A positive power supply pin is provided on the top dielectric layer for electrical connection with the positive power supply bump, and a positive power supply solder ball is provided on the bottom dielectric layer. The positive power supply pin and the positive power supply solder ball are electrically connected through the plurality of metal wiring layers. Positive detection points are provided on multiple target metal wiring layers among the plurality of metal wiring layers, and at least one positive detection point is provided on each target metal wiring layer. The positive detection point is electrically connected to the positive power supply line between the positive power supply pin and the positive power supply solder ball through the target metal wiring layer to which it is located. Multiple positive electrode detection solder balls are disposed on the bottom dielectric layer. The positive electrode detection solder balls are electrically connected to the corresponding positive electrode detection points. Different positive electrode detection solder balls correspond to different positive electrode detection points. The positive electrode detection point and the positive electrode detection solder ball are used to determine the voltage value at the positive electrode power supply bump.

2. The packaging structure according to claim 1, wherein, The plurality of dielectric layers includes a first dielectric layer and a plurality of second dielectric layers, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer; There is at least one metal wiring layer between the first dielectric layer and the top dielectric layer, and there is at least one metal wiring layer between the first dielectric layer and the bottom dielectric layer, wherein the top dielectric layer and the bottom dielectric layer are both the second dielectric layer; The target metal wiring layer is located between the first dielectric layer and the top dielectric layer.

3. The packaging structure according to claim 2, wherein, The target metal wiring layer is provided with the power plane of the chip.

4. The packaging structure according to claim 1, wherein, In the stacking direction of the metal wiring layer and the dielectric layer, the distance between the projection of the positive electrode detection point and the positive electrode power supply pin on the bottom dielectric layer is less than a distance threshold, and the distance between the projection of the positive electrode power supply pin on the bottom dielectric layer and the positive electrode detection solder ball is less than the distance threshold.

5. The packaging structure according to claim 4, wherein, The positive electrode detection point and the corresponding positive electrode detection solder ball are electrically connected by a metal wire, which is parallel to the stacking direction.

6. The packaging structure according to any one of claims 1-5, wherein, The top dielectric layer is provided with a negative power supply pin for electrical connection with the negative power supply bump of the chip, and the bottom dielectric layer is provided with a negative power supply solder ball. The negative power supply pin and the negative power supply solder ball are electrically connected through the plurality of metal wiring layers. At least a portion of the target metal wiring layer is provided with a negative electrode detection point. The negative electrode detection point and the corresponding positive electrode detection point are located on the same target metal wiring layer. The negative electrode detection point is electrically connected to the negative electrode power supply line between the negative electrode power supply pin and the negative electrode power supply solder ball through the target metal wiring layer where it is located. At least one negative electrode detection solder ball is disposed on the bottom dielectric layer. The negative electrode detection solder ball is electrically connected to the corresponding negative electrode detection point. Different negative electrode detection solder balls correspond to different negative electrode detection points. The negative electrode detection point and the negative electrode detection solder ball are used to form a detection circuit with the positive electrode detection point and the positive electrode detection solder ball when determining the voltage value at the positive electrode power supply bump.

7. In the packaging structure according to claim 6, the negative electrode detection point and the corresponding negative electrode detection solder ball are electrically connected by a metal wire, and the stacking direction of the metal wiring layer and the dielectric layer is parallel to the metal wire.

8. A packaged chip, comprising: The chip and the packaging structure as described in any one of claims 1-7, wherein the chip is bonded to the top dielectric layer of the packaging structure, and the positive power supply bump of the chip is electrically connected to the positive power supply pin included in the packaging structure.

9. A voltage value detection method for detecting the voltage value at the positive power supply bump in the packaged chip as described in claim 8, the method comprising: After the positive electrode power supply solder ball applies the first voltage, the second voltage of the positive electrode detection point electrically connected to the positive electrode detection solder ball is measured through the positive electrode detection solder ball. Calculate the first impedance between the positive electrode detection point and the positive electrode power supply solder ball based on the second voltage and the first voltage at the positive electrode detection point; Based on the multiple first impedances and the target metal wiring layer where the positive electrode detection point is located, determine the second impedance between the positive electrode power supply bump and the positive electrode power supply solder ball; The voltage value at the positive power supply bump is determined based on the first voltage and the second impedance.

10. The method according to claim 9, wherein, The step of calculating the first impedance between the positive electrode detection point and the positive electrode power supply solder ball based on the second voltage and the first voltage of the positive electrode detection point includes: The first impedance is calculated using the formula Z1 = (V1 - V2) / I, where Z1 represents the first impedance, V1 represents the first voltage, V2 represents the second voltage, and I represents the current on the positive power supply line.

11. The method according to claim 9, wherein, The step of determining the second impedance between the positive power supply bump and the positive power supply solder ball based on multiple first impedances and the target metal wiring layer where the positive detection point is located includes: Based on the multiple first impedances and the target metal wiring layer where the positive detection point is located, the impedance formula y = kx + b is determined, where y represents the impedance between the target point and the positive power supply bump on the positive power supply line, x represents the position information of the target point, and the position information is determined according to the position of the target metal wiring layer where the target point is located in the multiple stacked metal wiring layers, and k and b are constants. Substitute the position information of the positive power supply bump into the impedance formula to calculate the second impedance between the positive power supply bump and the positive power supply solder ball.

12. The method according to claim 9, wherein, Determining the voltage value at the positive power supply bump based on the first voltage and the second impedance includes: The voltage value at the positive power supply bump is calculated using the formula V3 = V1 - Z2·I, where V3 represents the voltage value at the positive power supply bump, V1 represents the first voltage, Z2 represents the second impedance, and I represents the current on the positive power supply line.

13. The method according to any one of claims 9-12, wherein, The step of measuring the second voltage at the positive detection point electrically connected to the positive detection solder ball via the positive detection solder ball includes: If the packaging structure includes a negative detection point corresponding to the positive detection point, then the second voltage of the positive detection point is measured by the positive detection solder ball electrically connected to the positive detection point and the negative detection solder ball electrically connected to the negative detection point corresponding to the positive detection point. If the package structure does not include a negative detection point corresponding to the positive detection point, the second voltage of the positive detection point is measured by the positive detection solder ball electrically connected to the positive detection point and the negative power supply solder ball included in the package structure.

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