Semiconductor wafer and method of forming semiconductor die

Abstract

A semiconductor wafer and a method of forming semiconductor dies are provided. The semiconductor wafer includes a substrate and a test structure. The substrate includes an array of die regions and a scribe line between the die regions. The test structure is disposed in the scribe line on the substrate. The test structure includes a first probe pad and a second probe pad spaced apart from each other. The first probe pad and the second probe pad each include a first portion, a second portion adjacent to but separated from the first portion, and a first test circuit electrically connected between the first probe pad and the second probe pad, wherein one of the first portion and the second portion of the first probe pad is physically and electrically connected to the first test circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor wafer and a method for forming semiconductor dies, and more particularly to a semiconductor wafer having a test structure and a method for forming semiconductor dies from the semiconductor wafer. Background Technology

[0002] After wafer testing, a simplification process is typically performed. One such simplification process is stealth dicing, which uses a laser beam focused inside the semiconductor substrate to create crack initiation points. External stress is then applied to the wafer to separate it into multiple grains. Stealth dicing minimizes the dicing path and generates very little debris during the process. However, some of the laser beam may irradiate the probe pads of the test element group formed along the laser path on the dicing path, and these probe pads may reflect laser energy onto the semiconductor substrate that is not located on the laser path. This can cause cracks to form on the wafer at unexpected locations (e.g., grain regions), leading to reduced yield. Summary of the Invention

[0003] The present invention relates to a semiconductor wafer and a method for forming semiconductor dies, which has improved yield.

[0004] According to an embodiment of the present invention, a semiconductor wafer includes a substrate and a test structure. The substrate includes grain regions arranged in an array and dicing lines between the grain regions. The test structure is disposed in the dicing lines on the substrate. The test structure includes a first probe pad and a second probe pad spatially separated. Each of the first and second probe pads includes a first portion, a second portion adjacent to but separated from the first portion, and a first test circuit electrically connected between the first and second probe pads, wherein one of the first and second portions of the first probe pad is physically and electrically connected to the first test circuit.

[0005] In a semiconductor wafer according to an embodiment of the present invention, one of the first and second portions of the second probe pad is physically and electrically connected to the first test circuit.

[0006] In a semiconductor wafer according to an embodiment of the present invention, the laser path for a single-process dicing line is defined as having a first region and a second region, wherein the first region and the second region are located on opposite sides of the laser path. A first portion of a first probe pad and a first portion of a second probe pad are located in the first region, and a second portion of a first probe pad and a second portion of a second probe pad are located in the second region.

[0007] In a semiconductor wafer according to an embodiment of the present invention, the gap between the first portion and the second portion of the first probe pad and the gap between the first portion and the second portion of the second probe pad extend along the laser path.

[0008] In a semiconductor wafer according to an embodiment of the present invention, the test structure further includes a dielectric layer disposed on a substrate, and a first probe pad and a second probe pad disposed on the dielectric layer. The first test circuit includes an upper line segment disposed on the dielectric layer, a lower line segment disposed in the dielectric layer and located below the upper line segment, and a conductive via disposed in the dielectric layer and connecting the upper line segment and the lower line segment.

[0009] In a semiconductor wafer according to an embodiment of the present invention, the upper segment of the first test circuit does not overlap with the laser path used for the unification process.

[0010] In a semiconductor wafer according to an embodiment of the present invention, one of the upper segments is in direct contact with one of the first and second portions of the first probe pad, and the other of the upper segments is in direct contact with one of the first and second portions of the second probe pad.

[0011] In a semiconductor wafer according to an embodiment of the present invention, one of the upper line segments is located in a second region and is in direct contact with a second portion of a first probe pad. The other upper line segment is located in a first region and is in direct contact with a first portion of a second probe pad.

[0012] In a semiconductor wafer according to an embodiment of the present invention, the test structure further includes a third probe pad, a fourth probe pad, and a second test circuit electrically connected between the third probe pad and the fourth probe pad. One of the conductive vias of the first test circuit is shared by the first test circuit and the second test circuit.

[0013] In a semiconductor wafer according to an embodiment of the present invention, a second test circuit includes a first upper line segment disposed on a dielectric layer and physically connected to a third probe pad, a second upper line segment disposed on a dielectric layer and physically connected to a fourth probe pad, a first lower line segment disposed in the dielectric layer, a first conductive via disposed in the dielectric layer and connected between the first upper line segment and the first lower line segment, and a second conductive via disposed in the dielectric layer and connected between the second upper line segment and the first lower line segment. The second conductive via of the second test circuit is shared with one of the conductive vias of the first test circuit.

[0014] In a semiconductor wafer according to an embodiment of the present invention, a first probe pad and a second probe pad are configured to receive and transmit current from a pair of test probes, and a third probe pad and a fourth probe pad are configured to measure the voltage between them via another pair of test probes.

[0015] According to another embodiment of the present invention, a method for forming a semiconductor die includes the following steps: A semiconductor wafer is provided. The semiconductor wafer includes a substrate and a test structure. The substrate includes an array of die regions and dicing lines between the die regions. The test structure is disposed in the dicing lines on the front side of the substrate. The test structure includes a first probe pad and a second probe pad spatially separated from each other. Each of the first and second probe pads includes a first portion, a second portion adjacent to but separated from the first portion, and a first test circuit electrically connected between the first and second probe pads, wherein one of the first and second portions of the first probe pad is physically and electrically connected to the first test circuit. An electrical test is performed on the test structure. A single-process is performed to form the semiconductor die.

[0016] In a method according to an embodiment of the invention, the unification process includes the following steps: A laser beam scan is performed along a laser path in a dicing line from the back side of the substrate, wherein the back side is opposite to the front side. External stress is applied to the semiconductor wafer to separate the semiconductor wafer into semiconductor grains.

[0017] In the method according to an embodiment of the present invention, the laser path does not overlap with the first probe pad and the second probe pad.

[0018] In the method according to an embodiment of the present invention, the laser path extends along the gap between the first portion and the second portion of the first probe pad and the gap between the first portion and the second portion of the second probe pad.

[0019] In the method according to an embodiment of the present invention, a modification layer is formed in the substrate during laser beam scanning, and the modification layer overlaps with the laser path.

[0020] Based on the above, the semiconductor wafer of this application includes probe pads in the dicing lines, and each probe pad does not overlap with the laser path used for the unification process. Therefore, during the unification process, the probability of the laser beam irradiating the probe pads is reduced when the laser beam scans along the laser path, thus reducing the risk of unintended wafer cracks and improving the yield of the semiconductor die.

[0021] To make the foregoing more understandable, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of this disclosure and form part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0023] Figure 1 This is a top view schematic diagram of a portion of a semiconductor wafer according to an embodiment of the present invention;

[0024] Figure 2 This is an enlarged top view of a dicing line in a semiconductor wafer according to an embodiment of the present invention;

[0025] Figure 3 It is along Figure 2 A cross-sectional view of line A-A' shown in the diagram;

[0026] Figure 4 It is along Figure 2 A cross-sectional view of line B-B' shown in the diagram;

[0027] Figure 5 It is along Figure 2 A cross-sectional view of line C-C' shown in the diagram;

[0028] Figure 6 and Figure 7 This is a cross-sectional schematic diagram of a method for forming semiconductor grains according to an embodiment of the present invention. Detailed Implementation

[0029] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0030] In the text, terms such as “contains,” “including,” “containing,” and “having” are all open-ended terms, meaning “including but not limited to.”

[0031] When terms such as "first" and "second" are used to describe components, they are only used to distinguish the components from each other and do not limit the order or importance of the devices. Therefore, in some cases, a first component may also be referred to as a second component, and a second component may also be referred to as a first component, which does not exceed the scope of this invention.

[0032] Furthermore, directional terms used in this document, such as "on," "above," "below," and "below," are used only to refer to the orientation of the accompanying drawings and are not intended to limit the invention.

[0033] Furthermore, the use of "from one value to another" to indicate a range is a general way of representing a range to avoid listing all values ​​within that range in the specification. Therefore, a description of a specific numerical range includes any value within that range, as well as the smaller range of values ​​defined by any value within that range.

[0034] Figure 1 This is a top view schematic diagram of a portion of a semiconductor wafer according to an embodiment of the present invention. Figure 2 This is an enlarged top view of a dicing line in a semiconductor wafer according to an embodiment of the present invention. Figure 3 It is along Figure 2The diagram shows a cross-sectional view of line A-A'. Figure 4 It is along Figure 2 A cross-sectional view of line B-B' shown in the diagram.

[0035] Figure 5 It is along Figure 2 A schematic cross-sectional view of line C-C' shown in the diagram. For clarity, Figure 1 Only the grain region DR and cleavage line SL are displayed, while other components (such as test structures) are omitted. Figure 2 It can be Figure 1 The image shows an enlarged view of region R, and some components (such as dielectric layer 150 and substrate 110) are omitted. Figure 2 Displayed in perspective.

[0036] Reference Figures 1 to 5 Semiconductor wafer 100 includes a substrate 110 and a test structure 120. The substrate 110 includes grain regions DR arranged in an array and dicing lines SL located between adjacent grain regions DR. The test structure 120 is disposed on the substrate 110 within the dicing lines SL. The test structure 120 includes a first probe pad 122, a second probe pad 124, and a first test circuit 130 electrically connected between the first probe pad 122 and the second probe pad 124. In some embodiments, the first probe pad 122 and the second probe pad 124 are arranged side-by-side within the dicing lines SL, and the second probe pad 124 is spatially spaced from the first probe pad 122. In some embodiments, the substrate 110 is a semiconductor substrate. The material of the substrate 110 includes silicon, germanium, or other suitable semiconductor materials. Devices (not shown) and interconnects (not shown) may be formed within the grain regions DR. In some embodiments, the test structure 120 includes one or more conductive materials, such as metals (e.g., copper, aluminum, titanium, tungsten, combinations thereof, alloys thereof, or the like), polycrystalline silicon, or other suitable conductive materials. Figure 2 The diagram shows a test structure 120, but it should be understood that one or more test structures 120 may be formed in the cut line, which is not limited.

[0037] The first probe pad 122 and the second probe pad 124 each include a first portion (such as the first portion 122a of the first probe pad 122 and the first portion 124a of the second probe pad 124) and a second portion (such as the second portion 122b of the first probe pad 122 and the second portion 124b of the second probe pad 124). The second portion (such as 122b or 124b) is adjacent to but separate from the first portion (such as 122a or 122b). That is, the first portion and the second portion of the probe pad (such as the first portion 122a and the second portion 122b of the first probe pad 122 or the first portion 124a and the second portion 124b of the second probe pad 124) are not electrically connected to each other without the application of external components (such as probes (not shown)).

[0038] In some embodiments, the cutting line SL is used in a single-process laser path LP defined as having a first region R1 and a second region R2, with the first region R1 and the second region R2 located on opposite sides of the laser path LP. For example, in Figure 2 In this process, the region above the laser path LP, where the cutting line SL is located, is the first region R1, while the region below the laser path LP, where the cutting line SL is located, is the second region R2. In some embodiments, the first portion 122a of the first probe pad 122 and the first portion 124a of the second probe pad 124 are located in the first region R1, while the second portion 122b of the first probe pad 122 and the second portion 124b of the second probe pad 124 are located in the second region R2. Here, the laser path LP refers to the scanning path of the laser beam during the single-stage process.

[0039] In some embodiments, the gap g1 between the first portion 122a and the second portion 122b of the first probe pad 122 and the gap g2 between the first portion 124a and the second portion 124b of the second probe pad 124 extend along the laser path LP. Therefore, the first probe pad 122 and the second probe pad 124 do not overlap with the laser path LP, which prevents or reduces the risk of accidental wafer cracking caused by the laser beam irradiating the first probe pad 122 and the second probe pad 124 during subsequent singlet processes.

[0040] In some embodiments, such as Figure 3 As shown, the test structure 120 also includes a dielectric layer 150 disposed on the substrate 110, and the first probe pad 122 and the second probe pad 124 are disposed on the dielectric layer 150.

[0041] In some embodiments, the first test circuit 130 includes an upper line segment 132 (including 132a, 132b, 132c, 132d, and 132e) disposed on a dielectric layer 150, a lower line segment 134 (including 134a, 134b, 134c, and 134d) disposed in the dielectric layer 150 and located below the upper line segment 132, and a conductive via 136 (including 136a, 136b, 136c, 136d, 136e, 136f, 136g, and 136h) disposed in the dielectric layer 150 and connecting the upper line segment 132 and the lower line segment 134. In some embodiments, the upper line segment 132 is located at the same layer as the first probe pad 122 and the second probe pad 124. Although Figure 3 For clarity, only one metallization layer is shown in dielectric layer 150, but it will be understood that multiple metallization layers may be present in dielectric layer 150 when devices or interconnects are formed in the die region DR. In some embodiments, the lower segment 134 may be a metallization layer embedded in any level of dielectric layer 150, which is not limited.

[0042] In some embodiments, the first probe pad 122, the second probe pad 124, and the upper segment 132 of the first test circuit 130 have substantially the same thickness. In some embodiments, the thickness T1 of the first probe pad 122, the second probe pad 124, or the upper segment 132 of the first test circuit 130 is greater than the thickness T2 of the lower segment 134 of the first test circuit 130.

[0043] In some embodiments, the upper segment 132 and the conductive via 136 of the first test circuit 130 do not overlap with the laser path LP to prevent or reduce the laser beam from irradiating the upper segment 132 or the conductive via 136 during subsequent singlet processes and causing unexpected wafer cracks. Therefore, each upper segment 132 and each conductive via 136 is located in either a first region R1 or a second region R2, without crossing between the first and second regions R1. For example, upper segments 132a, 132b, and 132c and conductive vias 136a, 136b, 136c, 136d, and 136e are located in the second region R2, while upper segments 132d and 132e and conductive vias 136f, 136g, and 136h are located in the first region R1.

[0044] In some embodiments, the lower segment 134 is connected to adjacent upper segments 132 via corresponding conductive vias 136. For example, the lower segment 134a in the second region R2 is connected to the upper segments 132a and 132b via conductive vias 136a and 136b. The lower segment 134b in the second region R2 is connected to the upper segments 132b and 132c via conductive vias 136c and 136d. The lower segment 134d in the first region R1 is connected to the upper segments 132d and 132e via conductive vias 136g and 136h. The lower segment 134c extends from the second region R2 to the first region R1 and connects the upper segment 132c in the second region R2 and the upper segment 132d in the first region R1 via conductive vias 136e and 136f. In this case, the lower segment 134c may overlap with a portion of the laser path LP. Because the lower segment 134 is relatively thin, laser energy is rarely reflected by the overlapping portion of the lower segment 134c during subsequent unification processes, thus preventing accidental cracks in the wafer.

[0045] In some embodiments, one of the upper segments 132 of the first test circuit 130 is in direct contact with one of the first portions 122a and 122b of the first probe pad 122, while the other of the upper segments 132 of the first test circuit 130 is in direct contact with one of the first portions 124a and 124b of the second probe pad 124. For example, in Figure 2 In the first test circuit 122, the second portion 122b of the first probe pad 122 is in direct contact with the upper segment 132a of the first test circuit 130, but the first portion 122a of the first probe pad 122 is not in direct contact with the first test circuit 130. Similarly, the first portion 124a of the second probe pad 124 is in direct contact with the upper segment 132e of the first test circuit 130, but the second portion 124b of the second probe pad 124 is not in direct contact with the first test circuit 130. That is, one of the first portion 122a and the second portion 122b of the first probe pad 122 is physically and electrically connected to the first test circuit 130. The other of the first portion 122a and the second portion 122b of the first probe pad 122 is not physically connected to the first test circuit 130, but can be electrically connected to the first test circuit 130 by applying an external component (such as a probe) to the first probe pad 122. Furthermore, one of the first portion 124a and the second portion 124b of the second probe pad 124 is physically and electrically connected to the first test circuit 130. The other of the first portion 124a and the second portion 124b of the second probe pad 124 is not physically connected to the first test circuit 130, but can be electrically connected to the first test circuit 130 by applying an external component (such as a probe) to the second probe pad 124.

[0046] In some embodiments, portions of the probe pads not physically connected to the first test circuit 130 (such as a first portion 122a of the first probe pad 122, a second portion 124b of the second probe pad 124, or the like) are configured to enhance alignment and conductivity between the probe and the probe pad.

[0047] Figure 2 The schematic diagram shows that the first test circuit 130 includes some upper line segments 132, some lower line segments 134, and some conductive vias 136, but the invention is not limited thereto. The number and layout of the upper line segments 132, lower line segments 134, and conductive vias 136 can be adjusted according to actual needs. For example, the number and layout of the upper line segments 132, lower line segments 134, and conductive vias 136 can be adjusted according to the design resistance of the first test circuit 130.

[0048] In some embodiments, the test structure 120 further includes a third probe pad 126, a fourth probe pad 128, and a second test circuit 140 electrically connected between the third probe pad 126 and the fourth probe pad 128. In some embodiments, the third probe pad 126 and the fourth probe pad 128 are arranged side-by-side in a dicing line SL, and the third probe pad 126 and the fourth probe pad 128 are spatially spaced apart. Figure 2 In the design, the first probe pad 122, the second probe pad 124, the third probe pad 126, and the fourth probe pad 128 are spatially spaced apart from each other. The second probe pad 124 is located between the first probe pad 122 and the third probe pad 126, and the third probe pad 126 is located between the second probe pad 124 and the fourth probe pad 128.

[0049] In some embodiments, similar to the first probe pad 122 and the second probe pad 124, the third probe pad 126 and the fourth probe pad 128 each include a first portion located in the first region R1 (such as the first portion 126a of the third probe pad 126 and the first portion 128a of the fourth probe pad 128) and a second portion located in the second region R2 (such as the second portion 126b of the third probe pad 126 and the second portion 128b of the fourth probe pad 128).

[0050] In some embodiments, the gap g3 between the first portion 126a and the second portion 126b of the third probe pad 126 and the gap g4 between the first portion 128a and the second portion 128b of the fourth probe pad 128 extend along the laser path LP. Therefore, the third probe pad 126 and the fourth probe pad 128 do not overlap with the laser path LP, which prevents or reduces the laser beam from irradiating the third probe pad 126 and the fourth probe pad 128 during subsequent singlet processes and causing unexpected wafer cracks.

[0051] In some embodiments, the second test circuit 140 includes an upper line segment 142 (including 142a and 142b) disposed on the dielectric layer 150, a lower line segment 144 disposed in the dielectric layer 150 and located below the upper line segment 142, and a conductive via 146 (including 146a and 146b) disposed in the dielectric layer 150 and connecting the upper line segment 142 and the lower line segment 144. For example, the conductive via 146a connects the upper line segment 142a and the lower line segment 144, and the conductive via 146b connects the upper line segment 142b and the lower line segment 144.

[0052] Figure 2 The diagram schematically shows the second test circuit 130 including upper line segments 142, lower line segments 144, and conductive vias 146, but the invention is not limited thereto. The number and layout of the upper line segments 142, lower line segments 144, and conductive vias 146 can be adjusted according to actual needs. For example, the number and layout of the upper line segments 142, lower line segments 144, and conductive vias 146 can be adjusted according to the design resistance of the second test circuit 140.

[0053] In some embodiments, the third probe pad 126, the fourth probe pad 128, and the upper segment 142 have substantially the same thickness T1 as the first probe pad 122, the second probe pad 124, and the upper segment 132 of the first test circuit 130, and are located at the same level as the first probe pad 122, the second probe pad 124, and the upper segment 132 of the first test circuit 130. The lower segment 144 has substantially the same thickness T2 as the lower segment 134 of the first test circuit 130, and is located at the same level as the lower segment 134 of the first test circuit 130.

[0054] In some embodiments, the upper segment 142 and the conductive via 146 of the second test circuit 140 do not overlap with the laser path LP to prevent or reduce accidental wafer cracking caused by the laser beam irradiating the upper segment 142 or the conductive via 146 during subsequent singlet processes. Therefore, each upper segment 142 and each conductive via 146 is located in either the first region R1 or the second region R2, but does not cross between the first region R1 and the second region R2. For example, upper segments 142a and 142b and conductive vias 146a and 146b are all located in the first region R1.

[0055] In some embodiments, the lower segment 144 in the first region R1 is connected between the upper segments 142a and 142b via conductive vias 146a and 146b. The upper segment 142a of the second test circuit 140 is in direct contact with the first portion 126a of the third probe pad 126, but the second portion 126b of the third probe pad 126 is not in direct contact with the second test circuit 140. The upper segment 142b of the second test circuit 140 is in direct contact with the first portion 128a of the fourth probe pad 128, but the second portion 128b of the fourth probe pad 128 is not in direct contact with the fourth test circuit 140. That is, one of the first portion 126a and the second portion 126b of the third probe pad 126 is physically and electrically connected to the second test circuit 140. The other of the first portion 126a and the second portion 126b of the third probe pad 126 is not physically connected to the second test circuit 140, but can be electrically connected to the second test circuit 140 by applying an external component (e.g., a probe) to the third probe pad 126. Furthermore, one of the first portion 128a and the second portion 128b of the fourth probe pad 128 is physically and electrically connected to the second test circuit 140. The other of the first portion 128a and the second portion 128b of the fourth probe pad 128 is not physically connected to the second test circuit 140, but can be electrically connected to the second test circuit 140 by applying an external component (e.g., a probe) to the fourth probe pad 128.

[0056] In some embodiments, portions of the probe pads not physically connected to the second test circuit 140 (e.g., the second portion 126b of the third probe pad 126, the second portion 128b of the fourth probe pad 128, or the like) are configured to enhance alignment and conductivity between the probe and the probe pad.

[0057] In some embodiments, upper segment 132a is located between the first probe pad 122 and the second probe pad 124 in the second region R2. Upper segment 132b is located between the second probe pad 124 and the third probe pad 126 in the second region R2. Upper segment 132c is located between the third probe pad 126 and the fourth probe pad 128 in the second region R2. Upper segments 132d and 142b are located between the third probe pad 126 and the fourth probe pad 128 in the first region R1.

[0058] In some embodiments, the orthographic projection of the lower line segment 134a on the substrate 110 overlaps with the orthographic projection of the second portion 124b of the second probe pad 124b on the substrate 110, the orthographic projection of the conductive via 136a on the substrate 110, the orthographic projection of the conductive via 136b on the substrate 110, a portion of the orthographic projection of the upper line segment 132a on the substrate 110, and a portion of the orthographic projection of the upper line segment 132b on the substrate 110.

[0059] In some embodiments, the orthographic projection of the lower line segment 134b on the substrate 110 overlaps with the orthographic projection of the second portion 126b of the third probe pad 126 on the substrate 110, the orthographic projection of the conductive via 136c on the substrate 110, the orthographic projection of the conductive via 136d on the substrate 110, a portion of the orthographic projection of the upper line segment 132b on the substrate 110, and a portion of the orthographic projection of the upper line segment 132c on the substrate 110.

[0060] In some embodiments, the orthographic projection of the lower line segment 134c on the substrate 110 overlaps with the orthographic projection of the second portion 128b of the fourth probe pad 128 on the substrate 110, the orthographic projection of the first portion 128a of the fourth probe pad 128 on the substrate 110, the orthographic projection of the conductive via 136e on the substrate 110, the orthographic projection of the conductive via 136f on the substrate 110, a portion of the orthographic projection of the upper line segment 132c on the substrate 110, and a portion of the orthographic projection of the upper line segment 132d on the substrate 110.

[0061] In some embodiments, the orthographic projection of the lower line segment 134d on the substrate 110 overlaps with the orthographic projection of the first portion 126a of the third probe pad 126 on the substrate 110, the orthographic projection of the first portion 124a of the second probe pad 124 on the substrate 110, the orthographic projection of the conductive via 136g on the substrate 110, the orthographic projection of the conductive via 136h on the substrate 110, a portion of the orthographic projection of the upper line segment 132d on the substrate 110, and the orthographic projection of the upper line segment 132e on the substrate 110.

[0062] In some embodiments, the orthographic projection of the lower line segment 144 on the substrate 110 overlaps with the orthographic projection of the first portion 126a of the third probe pad 126 on the substrate 110, the orthographic projection of the conductive via 146a on the substrate 110, the orthographic projection of the conductive via 146b on the substrate 110, and the orthographic projection of the upper line segment 142b on the substrate 110.

[0063] In some embodiments, the conductive via 146b of the second test circuit 140 and the conductive via 136f of the first test circuit 130 are shared. That is, one of the conductive vias 136 of the first test circuit 130 or one of the conductive vias 146 of the second test circuit 140 is shared by both the first test circuit 130 and the second test circuit 140. Furthermore, the portion of the upper segment 142b of the second test circuit 140 overlapping with the conductive via 146b is shared with the upper segment 132d of the first test circuit 130, and the portion of the lower segment 144 of the second test circuit 140 overlapping with the conductive via 146b is shared with the lower segment 134c of the first test circuit 130. Therefore, the first test circuit 130 can be electrically connected to the second test circuit 140.

[0064] In some embodiments, the first probe pad 122 and the second probe pad 124 are configured to transmit current from a pair of test probes (not shown), allowing current to flow through the first test circuit 130 and the second test circuit 140, and the third probe pad 126 and the fourth probe pad 128 are configured to measure the voltage between them via another pair of test probes (not shown). A test component (e.g., a material or device to be tested) may be formed at the conductive via 146b, and the electrical characteristics of the test component can be determined by the obtained voltage.

[0065] In some embodiments, the semiconductor wafer 100 further includes a dummy probe pad 129 on a substrate 110 in a dicing line SL. The dummy probe pad 129 may be similar to other probe pads and includes a first portion 129a in a first region R1 and a second portion 129b in a second region R2. A gap g5 between the first portion 129a and the second portion 129b extends along the laser path LP. Therefore, the dummy probe pad 129 does not overlap with the laser path LP, which prevents or reduces the laser beam from irradiating the dummy probe pad 129 during subsequent singlet processes and causing unintended wafer cracks.

[0066] In some embodiments, the gap distances (e.g., d1, d2, d3, d4, and d5) of the gaps (g1, g2, g3, g4, and g5) are larger than the laser beam size of the laser beam used for the single-process and smaller than the diameter of the probe tip of the probe used for probe testing. In some embodiments, the gap distances d1, d2, d3, d4, and d5 are in the range of 3 μm to 7 μm.

[0067] Figure 6 and Figure 7 This is a cross-sectional schematic diagram of a method for forming semiconductor grains according to an embodiment of the present invention. Figure 6 and Figure 7 It can be along Figure 2 The diagram shows a cross-sectional view along line C-C'. It is important to note here that... Figure 6 and Figure 7 The embodiments continue to be used Figures 1 to 5 The component reference numbers and partial content in the embodiments are described below, wherein the same or similar reference numbers are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiments, and the detailed content will not be repeated here.

[0068] Reference Figure 6 A semiconductor wafer 100 is provided, comprising a substrate 110 and a test structure 120. The test structure 120 is formed on the front side 110a of the substrate 110. The semiconductor wafer 100, the substrate 110, and the test structure 120 may be similar to... Figures 1 to 4 The embodiments described herein.

[0069] Then, an electrical test is performed on test structure 120. For example, the probe tips of a pair of test probes (not shown) contact the first probe pad 122 and the second probe pad 124 (not shown, see reference 124) respectively. Figure 2 For reference, current is applied to test structure 120. On the other hand, the probe tips of another pair of test probes (not shown) contact the third probe pad 126 and the fourth probe pad 128 (not shown, see reference) respectively. Figure 2 (As a reference) to measure the voltage between them to determine whether the electrical characteristics of the test component meet expectations.

[0070] Reference Figure 6 and Figure 7 A single process is performed to form multiple semiconductor chips 10. For example, in Figure 6 In the middle, from the back side 110b of the substrate 110 along the laser path LP in the dicing line SL (refer to...) Figure 2 (For reference) A laser beam LB scan is performed, wherein the back side 110b is opposite to the front side 110a. In some embodiments, during the laser beam LB scan, a modified layer 160 is formed in the substrate 110 to generate internal cracks in the substrate 110, and the modified layer 160 overlaps with the laser path LP.

[0071] Then, in Figure 7 In this process, external stress is applied to the semiconductor wafer 100 to separate the semiconductor wafer 110 into semiconductor grains 10. For example, the substrate 110 is placed and fixed on a tape (not shown) (e.g., cut tape), with the back side 110b of the substrate 110 facing the tape. An expansion process is then performed on the tape to extend it in the peripheral direction, thereby applying stress to the semiconductor wafer 100. Internal cracks in the modification layer 160 may extend due to stress, thus the semiconductor wafer 100 may crack along the modification layer 160 to form multiple semiconductor grains 10.

[0072] Because the probe pads in the test structure 120 (e.g., the first probe pad 122, the second probe pad 124, the third probe pad 126, the fourth probe pad 128, or the like) are formed with a first portion and a second portion and do not overlap with the laser path LP, the possibility of the laser beam LB irradiating the probe pads and causing an accidental wafer crack is low.

[0073] Based on the above, the semiconductor wafer of this application includes probe pads in the dicing lines, and each probe pad does not overlap with the laser path used in the unification process. Therefore, during the unification process, the probability of the laser beam irradiating the probe pads is reduced when the laser beam scans along the laser path, thus reducing the risk of unintended wafer cracks and improving the yield of the semiconductor die.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor wafer, characterized in that, include: Substrate, including: Grain regions arranged in an array; and Cutting lines are located between the grain regions; and A test structure is disposed in the dicing line on the substrate, wherein the test structure comprises: A first probe pad and a second probe pad are spatially spaced apart from each other, wherein each of the first probe pad and the second probe pad comprises: Part One; and The second part is adjacent to but separate from the first part; and A first test circuit is electrically connected between the first probe pad and the second probe pad, wherein one of the first portion and the second portion of the first probe pad is physically and electrically connected to the first test circuit.

2. The semiconductor wafer according to claim 1, characterized in that, One of the first and second portions of the second probe pad is physically and electrically connected to the first test circuit.

3. The semiconductor wafer according to claim 2, characterized in that, The cutting line used in the single-process laser path is defined as having a first region and a second region, wherein the first region and the second region are located on opposite sides of the laser path. The first portion of the first probe pad and the first portion of the second probe pad are located in the first region, and the second portion of the first probe pad and the second portion of the second probe pad are located in the second region.

4. The semiconductor wafer according to claim 3, characterized in that, The gap between the first portion and the second portion of the first probe pad and the gap between the first portion and the second portion of the second probe pad extend along the laser path.

5. The semiconductor wafer according to claim 3, characterized in that, The test structure further includes a dielectric layer disposed on the substrate, and the first probe pad and the second probe pad are disposed on the dielectric layer. The first test circuit includes: The upper line segment is disposed on the dielectric layer; The lower line segment is disposed in the dielectric layer and located below the upper line segment; and A conductive via is disposed in the dielectric layer and connected between the upper line segment and the lower line segment.

6. The semiconductor wafer according to claim 5, characterized in that, The upper segment of the first test circuit does not overlap with the laser path used for the simplification process.

7. The semiconductor wafer according to claim 5, characterized in that, One of the upper line segments is in direct contact with one of the first and second portions of the first probe pad, and Another of the upper segments is in direct contact with one of the first and second portions of the second probe pad.

8. The semiconductor wafer according to claim 7, characterized in that, One of the upper line segments is located in the second region and directly contacts the second portion of the first probe pad, and The other of the upper segments is located in the first region and directly contacts the first portion of the second probe pad.

9. The semiconductor wafer according to claim 5, characterized in that, The test structure also includes: The third and fourth probe pads; and The second test circuit is electrically connected between the third probe pad and the fourth probe pad. One of the conductive vias in the first test circuit is shared by the first test circuit and the second test circuit.

10. The semiconductor wafer according to claim 9, characterized in that, The second test circuit includes: The first upper line segment is disposed on the dielectric layer and physically connected to the third probe pad; The second upper line segment is disposed on the dielectric layer and physically connected to the fourth probe pad; The first lower segment is disposed in the dielectric layer; A first conductive via is disposed in the dielectric layer and connects the first upper line segment and the first lower line segment; and A second conductive via is disposed in the dielectric layer and connects the second upper line segment and the first lower line segment. The second conductive via of the second test circuit is shared with one of the conductive vias of the first test circuit.

11. The semiconductor wafer according to claim 9, characterized in that, The first probe pad and the second probe pad are configured to receive and transmit current from a pair of test probes, and The third and fourth probe pads are configured to measure the voltage between them via another pair of test probes.

12. A method for forming semiconductor grains, characterized in that, include: A semiconductor wafer is provided, wherein the semiconductor wafer comprises: Substrate, wherein the substrate comprises: Grain regions arranged in an array; and Cutting lines between the grain regions; and A test structure in the dicing line on the front side of the substrate, wherein the test structure includes: A first probe pad and a second probe pad are spatially spaced apart from each other, wherein each of the first probe pad and the second probe pad comprises: Part One; and The second part is adjacent to but separate from the first part; and A first test circuit is electrically connected between the first probe pad and the second probe pad, wherein one of the first portion and the second portion of the first probe pad is physically and electrically connected to the first test circuit. Perform electrical tests on the test structure; and A single process is used to form semiconductor chips.

13. The method according to claim 12, characterized in that, The standardization process includes: A laser beam scan is performed from the back side of the substrate along the laser path in the dicing line, wherein the back side is opposite to the front side; and External stress is applied to the semiconductor wafer to separate the semiconductor wafer into semiconductor grains.

14. The method according to claim 13, characterized in that, The laser path does not overlap with the first probe pad and the second probe pad.

15. The method according to claim 13, characterized in that, The laser path extends along the gap between the first and second portions of the first probe pad and the gap between the first and second portions of the second probe pad.

16. The method according to claim 13, characterized in that, During the laser beam scanning, a modification layer is formed in the substrate, and the modification layer overlaps with the laser path.

Images