Through-silicon via anneal process test structure and through-silicon via anneal process determination method

Abstract

The application provides a through silicon via annealing process test structure and a through silicon via annealing process determination method. The through silicon via annealing process test structure comprises a detection group and a reference group. The detection group comprises a through silicon via, a detection metal wire and a connecting metal wire. The detection metal wire is located on the upper layer of the through silicon via, and the connecting metal wire is located on the lower layer of the through silicon via. The reference group comprises a reference metal wire, and the reference metal wire is located on the upper layer of the through silicon via. The head of the detection metal wire and the head of the reference metal wire are connected with a lead wire respectively, and the tail of the detection metal wire and the tail of the reference metal wire are connected with each other and connected with the same lead wire. The application can determine whether the annealing process of the through silicon via is qualified by applying the same current to the detection group and the reference group and comparing the resistance difference between the two groups. The method is simple and fast, and can reduce the scrap rate of products.

Description

Technical Field

[0001] This invention belongs to the field of chip interconnect and chip packaging technology, and specifically relates to a test structure for through-silicon via (TSV) annealing process and a method for determining the TSV annealing process. Background Technology

[0002] Through-Silicon Vias (TSVs) are an indispensable and irreplaceable core interconnect technology for advanced 3D integrated circuits (3D ICs). The application of TSVs enables truly high-density, high-performance 3D IC manufacturing processes. During 3D IC manufacturing, precise control of thermal annealing process parameters is crucial for ensuring TSV quality and long-term device stability. Inadequate TSV annealing leads to a failure to effectively control copper diffusion, release internal stress, and optimize interface characteristics. This directly results in geometric deformation, stress concentration, and interface weakening in the TSV structure, ultimately affecting the reliability and lifespan of the 3D integrated circuit.

[0003] Please see Figure 1 Inadequate annealing of the through-silicon via (01) can lead to deformation and bulging. For further details, please refer to [link to relevant documentation]. Figure 2 Excessive stress concentration leading to excessive swelling can cause the barrier layer (O2) to crack, severely impacting the reliability of the through-silicon via (TSV) structure. Often, extensive failure analysis (FA) slices are required during the R&D phase to verify the process, which is time-consuming and labor-intensive.

[0004] Therefore, it is necessary to establish a test structure and judgment method for the through-silicon via (TSV) annealing process that can quickly and accurately determine whether the TSV annealing process is qualified (i.e., in place). Summary of the Invention

[0005] The purpose of this invention is to provide a test structure for through-silicon via (TSV) annealing process and a method for determining the TSV annealing process, so as to solve the problem of time-consuming and labor-intensive TSV annealing process determination.

[0006] To address the aforementioned technical problems, this invention provides a test structure for through-silicon via (TSV) annealing processes, comprising: a detection group and a reference group, wherein...

[0007] The detection group includes through-silicon vias, detection metal lines, and connecting metal lines. The detection metal lines are located on the upper layer of the through-silicon vias, and the connecting metal lines are located on the lower layer of the through-silicon vias.

[0008] The reference group includes a reference metal line, wherein the reference metal line is located on the upper layer of the through silicon via, the beginning of the detection metal line and the beginning of the reference metal line are respectively connected to the lead, and the end of the detection metal line and the end of the reference metal line are connected to each other and are connected to the same lead.

[0009] Optionally, the detection metal wire is an aluminum wire.

[0010] Optionally, the reference metal line is an aluminum wire, and its wiring method, width, thickness and length are the same as those of the detection metal line.

[0011] Optionally, both the detection metal line and the reference metal line are disposed on the aluminum pad metal layer, and the aluminum pad metal layer is located on top of the through silicon via.

[0012] Optionally, the through-silicon via includes at least one of cylindrical through-silicon vias and truncated silicon vias.

[0013] Optionally, both the detection group and the reference group are disposed inside the three-dimensional integrated circuit, and the three-dimensional integrated circuit includes multiple silicon substrates, with each silicon substrate layer stacked and bonded in a vertical direction to form a stacked structure.

[0014] Optionally, the multilayer silicon substrate is prepared by stacking at least two wafers using a bonding process.

[0015] Optionally, the silicon substrate is provided with a plurality of stacked metal interconnect layers, and the connecting metal line is any one of the stacked metal interconnect layers of the silicon substrate under the through-silicon via.

[0016] Optionally, the metal interconnect layer includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, which are arranged sequentially from bottom to top in the vertical direction, with the first metal layer M1 being the bottommost metal interconnect layer.

[0017] Optionally, a barrier layer is laid on the inner wall and bottom wall of the through silicon via, and the barrier layer completely covers the inner wall of the cavity of the through silicon via.

[0018] To address the aforementioned technical problems, this invention also provides a method for determining the annealing process of through-silicon vias (TSVs). This method is applicable to the aforementioned test structures for TSV annealing processes, and the steps of this method are as follows:

[0019] The same test current I is applied to the detection metal line and the reference metal line through the lead wire, and the voltage on the detection metal line and the voltage on the reference metal line are measured respectively through the lead wire.

[0020] The resistance values ​​R1 of the detection metal line and R2 of the reference metal line are calculated based on the measured voltage on the detection metal line and the voltage on the reference metal line, respectively.

[0021] The annealing index value β is calculated based on the resistance value R1 of the detection metal wire and the resistance value R2 of the reference metal wire, and the process is judged to be qualified based on the value of β.

[0022] Optionally, the annealing index value β is calculated using the formula β = R1 / R2.

[0023] Optionally, if the value of β is between A1 and A2, the through-silicon via annealing process is qualified, with the theoretical value of A1 being 0.95 and the theoretical value of A2 being 1.1.

[0024] Optionally, if the value of β is between A2 and B, the through-silicon via annealing process is unqualified, resulting in the through-silicon via swelling. The theoretical value of A2 is 1.1, and the theoretical value of B is 1.8~2.

[0025] Optionally, if the value of β is greater than or equal to B, the through-silicon via annealing process is unqualified, resulting in the through-silicon via swelling and damage to the barrier layer structure. The theoretical value of B is 1.8 to 2.

[0026] This invention establishes a detection group and a reference group, applies test current and measures corresponding voltages to the detection and reference metal lines via leads, and calculates the resistance values ​​R1 and R2 of the detection and reference metal lines using Ohm's law. An annealing index value β is defined as R1 / R2, and finally, the annealing index value β is used to determine whether the annealing process of the through-silicon via (TSV) is qualified. The TSV annealing process test structure and TSV annealing process judgment method provided by this invention are simple and convenient, avoiding the drawbacks of requiring time-consuming failure analysis and slab preparation to determine process abnormalities, while effectively reducing the scrap rate of wafer products. Attached Figure Description

[0027] Figure 1 This is a cross-sectional view of the bulging of a through-silicon via under an electron microscope in the prior art;

[0028] Figure 2 This is a cross-sectional view of the rupture of the barrier layer in a through-silicon via under an electron microscope, as shown in the prior art.

[0029] Figure 3 This is a top view of a test structure for a through-silicon via (TSV) annealing process according to an embodiment of the present invention;

[0030] Figure 4 This is a cross-sectional view of the test structure for the through-silicon via annealing process in one embodiment of the present invention;

[0031] Figure 5 This is a flowchart illustrating the method for determining the through-silicon via annealing process in one embodiment of the present invention;

[0032] in, Figures 1-2 middle:

[0033] 01-Through Silicon Via; 02-Barrier Layer;

[0034] Figures 3-5 middle:

[0035] 10 - Reference metal line; 20 - Lead; 30 - Detection group; 301 - Detection metal line; 302 - Connecting metal line; 303 - Through silicon via. Detailed Implementation

[0036] The core idea of ​​this invention is to provide a test structure for through-silicon via (TSV) annealing process and a method for determining the TSV annealing process, so as to quickly and accurately determine whether the TSV annealing process is qualified.

[0037] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a test structure for through-silicon via (TSV) annealing processes and a method for determining TSV annealing process specifications. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] In the description of the embodiments disclosed in this invention, the term "comprising" and similar terms should be understood as open inclusion, that is, "including but not limited to". The terms "first", "second", and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] The through-silicon via (TSV) annealing process test structure provided by this invention may include: a detection group 30 and a reference group, wherein,

[0040] The detection group 30 includes a through-silicon via 303, a detection metal line 301, and a connecting metal line 302. The detection metal line 301 is located on the upper layer of the through-silicon via 303, and the connecting metal line 302 is located on the lower layer of the through-silicon via 303.

[0041] The reference group includes a reference metal line 10, wherein the reference metal line 10 is located on the upper layer of the through silicon via 303, the beginning of the detection metal line 301 and the beginning of the reference metal line 10 are respectively connected to the lead 20, and the end of the detection metal line 301 and the end of the reference metal line 10 are connected to each other and are connected to the same lead 20.

[0042] For details, please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of a test structure for a through-silicon via (TSV) annealing process according to an embodiment of the present invention. Figure 4This is a cross-sectional view of a test structure for a through-silicon via (TSV) annealing process according to an embodiment of the present invention. The detection group 30 may include the TSV 303, the detection metal line 301, and the connecting metal line 302. The reference group may include the reference metal line 10.

[0043] from Figure 4 As can be seen from the cross-sectional view, the detection metal line 301 is located on the upper layer of the through-silicon via 303, and the reference metal line 10 is also located on the upper layer of the through-silicon via 303, while the connecting metal line 302 is located on the lower layer of the through-silicon via 303. Both the detection metal line 301 and the reference metal line 10 are disposed on an aluminum pad metal layer (APL). Since both the detection metal line 301 and the reference metal line 10 are part of the aluminum pad metal layer, and the aluminum pad metal layer is located on the upper layer of the through-silicon via 303, the detection metal line 301 must be an aluminum wire, and the reference metal line 10 must also be an aluminum wire. Furthermore, the detection metal line 301 and the reference metal line 10 have the same wiring method, width, thickness, and length. The wiring method, width, thickness, and length of the detection metal line 301 and the reference metal line 10 are not fixed and can be flexibly adjusted according to the layout design and device performance requirements of different process nodes. This structure is not limited by a single process node and can be adapted to various process nodes, making it suitable for a wide range of applications. For example, the detection metal line 301 and the reference metal line 10 can preferably be an array-arranged U-shaped conductive trace structure. The number of the detection metal line 301, the reference metal line 10, the connecting metal line 302, and the through-silicon vias 303 can be flexibly adjusted according to the layout design and device performance requirements of different process nodes. The spacing between the through-silicon vias 303 can also be flexibly adjusted according to different process nodes and design rules.

[0044] The through-silicon via 303 is not limited to a single via structure, and may specifically include at least one of cylindrical through-silicon via and trapezoidal through-silicon via; both of these through-silicon via structures can realize vertical interconnection of upper and lower metal lines, and can be flexibly selected according to packaging process, wiring layout and process node.

[0045] Both the detection group 30 and the reference group are disposed inside the three-dimensional integrated circuit, which includes a multilayer silicon substrate. The silicon substrate layers are stacked and bonded vertically to form a stacked structure, and the multilayer silicon substrate is prepared by stacking at least two wafers using a bonding process. Furthermore, multiple stacked metal interconnect layers are disposed on the silicon substrate, and the connecting metal line 302 is any one of the stacked metal interconnect layers on the silicon substrate below the through-silicon via 303. The metal interconnect layers may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, arranged vertically from bottom to top, with the first metal layer M1 being the bottommost metal interconnect layer. In addition, this embodiment can be extended to include more back-end metal interconnect layers such as a fifth metal layer M5 and a sixth metal layer M6 according to process design requirements. The scope of this application covers all back-end metal interconnect layers of the chip, and can also be adapted to top metal layers, top thickened metal layers, and redistribution layers. Furthermore, a barrier layer can be deposited on the inner wall and bottom wall of the through-silicon via 303, completely covering the inner wall of the cavity of the through-silicon via 303. The barrier layer can prevent copper diffusion, and the specific parameters of the barrier layer can be flexibly selected according to the process technology and process node.

[0046] Furthermore, this invention also provides a method for determining the annealing process of through-silicon vias (TSVs), which is implemented using the aforementioned TSV annealing process test structure. Wherein, Figure 5 This is a flowchart illustrating a method for determining the annealing process of through-silicon vias (TSVs) according to an embodiment of the present invention. The method for determining the annealing process of TSVs may include the following steps:

[0047] Step S1: Apply the same test current I to the detection metal line 301 and the reference metal line 10 through the lead 20, and measure the voltage on the detection metal line 301 and the voltage on the reference metal line 10 through the lead 20 respectively.

[0048] Step S2: Calculate the resistance value R1 of the detection metal line 301 and the resistance value R2 of the reference metal line 10 based on the measured voltage on the detection metal line 301 and the voltage on the reference metal line 10, respectively.

[0049] Step S3: Calculate the annealing index value β based on the calculated resistance value R1 of the detection metal line 301 and the resistance value R2 of the reference metal line 10, and determine whether the process is qualified based on the value of β.

[0050] In step S1 of this embodiment, because the number of vias in the through-silicon via 303 varies under different processes, the resistance of the through-silicon via 303 varies greatly under different processes. Therefore, this embodiment can estimate a suitable test current I based on the specific resistance value. This embodiment can try several different sets of experimental currents and observe whether the resistance of the through-silicon via 303 is stable. If the resistance of the through-silicon via 303 is stable under a certain set of experimental currents, then that set of experimental currents can be determined as the suitable test current I. After determining the test current I, this embodiment measures the voltage between the detection metal line 301 and the reference metal line 10 through the lead 20.

[0051] In step S2 of this embodiment, the voltage of the detection metal line 301 and the reference metal line 10 are obtained by measurement, and the resistance values ​​of the detection metal line 301 and the reference metal line 10 are calculated using Ohm's law. The resistance value of the detection metal line 301 is recorded as R1, and the resistance value of the reference metal line 10 is recorded as R2.

[0052] In step S3 of this embodiment, the annealing index value β is calculated based on the calculated resistance value R1 of the detection metal line 301 and the resistance value R2 of the reference metal line 10. The formula for calculating the annealing index value β is β=R1 / R2. Then, the process is judged to be qualified based on the value of β. The specific judgment criteria are as follows:

[0053] If the value of β is between A1 and A2, then the through-silicon via annealing process is qualified;

[0054] If the value of β is between A2 and B, the through-silicon via annealing process is unqualified, resulting in the through-silicon via 303 bulging.

[0055] If the value of β is greater than or equal to B, the through-silicon via (TSV) annealing process is unqualified, causing the TSV 303 to bulge and resulting in damage to the barrier layer structure of the TSV 303. The barrier layer is applied to the inner wall and bottom wall of the TSV 303, completely covering the inner wall of the cavity. Because within the annealing temperature range of 150℃ to 250℃, the copper in the TSV 303 and the aluminum in the detection metal line 301 of the upper aluminum pad metal layer easily form copper aluminide (CuAl) or copper dialuminide (CuAl2) alloys. Since the resistivity of copper-aluminum alloys is approximately 3 to 4 times that of aluminum, based on this resistivity difference, once the barrier layer breaks, the copper in the TSV 303 enters the aluminum in the upper detection metal line 301, and the value of β will increase significantly. A significant increase in the value of β will directly lead to problems such as geometric deformation, stress concentration, and interface weakening of the through-silicon via 303, ultimately affecting the reliability and lifespan of the three-dimensional integrated circuit.

[0056] The theoretical value of A1 can be 0.95, the theoretical value of A2 can be 1.1, and the theoretical value of B can be 1.8~2. In this embodiment, the values ​​of A1, A2 and B can be measured in batches during the initial production phase of the through-silicon via annealing process, and a reference database can be formed. In subsequent production, the range of values ​​of A1, A2 and B can be determined by combining the theoretical range and the database samples, thereby determining whether the through-silicon via annealing process is qualified.

[0057] In summary, the embodiments of the present invention can first set up a detection group and a reference group, then apply the same test current to the detection metal line and the reference metal line using leads, and measure the corresponding voltage through the leads. Finally, the annealing process of the through-silicon via (TSV) is judged to be qualified using Ohm's law and the calculation formula of the annealing index value β. The embodiments of the present invention have a simple structure, which can avoid the drawbacks of traditional processes that rely on slice failure analysis for judgment, and can also reduce the scrap rate of product wafers.

[0058] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A test structure for through-silicon via (TSV) annealing process, characterized in that, include: The detection group and the baseline group, among which, The detection group includes through-silicon vias, detection metal lines, and connecting metal lines. The detection metal lines are located on the upper layer of the through-silicon vias, and the connecting metal lines are located on the lower layer of the through-silicon vias. The reference group includes a reference metal line, wherein the reference metal line is located on the upper layer of the through silicon via. The beginning ends of the detection metal line and the reference metal line are respectively connected to the lead. The end ends of the detection metal line and the reference metal line are connected to each other and are connected to the same lead.

2. The test structure for through-silicon via (TSV) annealing process as described in claim 1, characterized in that, The detection metal wire is an aluminum wire.

3. The through-silicon via (TSV) annealing process test structure as described in claim 1, characterized in that, The reference metal line is an aluminum wire, and its wiring method, width, thickness and length are the same as those of the detection metal line.

4. The through-silicon via (TSV) annealing process test structure as described in claim 1, characterized in that, Both the detection metal line and the reference metal line are disposed on the aluminum pad metal layer, and the aluminum pad metal layer is located on top of the through silicon via.

5. The through-silicon via (TSV) annealing process test structure as described in claim 1, characterized in that, The through-silicon via includes at least one of cylindrical through-silicon vias and frustum-shaped through-silicon vias.

6. The through-silicon via (TSV) annealing process test structure as described in claim 1, characterized in that, Both the detection group and the reference group are located inside the three-dimensional integrated circuit, and the three-dimensional integrated circuit contains multiple silicon substrates, with each silicon substrate layer stacked and bonded in a vertical direction to form a stacked structure.

7. The through-silicon via (TSV) annealing process test structure as described in claim 6, characterized in that, The multilayer silicon substrate is prepared by stacking at least two wafers using a bonding process.

8. The through-silicon via (TSV) annealing process test structure as described in claim 6, characterized in that, The silicon substrate has multiple stacked metal interconnect layers, and the connecting metal line is any one of the stacked metal interconnect layers of the silicon substrate under the through-silicon via.

9. The through-silicon via (TSV) annealing process test structure as described in claim 8, characterized in that, The metal interconnect layer includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4. The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are arranged in a vertical direction from bottom to top, and the first metal layer M1 is the bottom metal interconnect layer.

10. The through-silicon via (TSV) annealing process test structure as described in claim 1, characterized in that, A barrier layer is laid on the inner wall and bottom wall of the through silicon via, and the barrier layer completely covers the inner wall of the cavity of the through silicon via.

11. A method for determining the annealing process of through-silicon vias (TSVs), characterized in that, The test structure is achieved using the through-silicon via (TSV) annealing process described in any one of claims 1 to 10, and includes the following steps: The same test current I is applied to the detection metal line and the reference metal line through the lead wire, and the voltage on the detection metal line and the voltage on the reference metal line are measured respectively through the lead wire. The resistance values ​​R1 of the detection metal line and R2 of the reference metal line are calculated based on the measured voltage on the detection metal line and the voltage on the reference metal line, respectively. The annealing index value β is calculated based on the resistance value R1 of the detection metal wire and the resistance value R2 of the reference metal wire, and the process is judged to be qualified based on the value of β.

12. The method for determining the through-silicon via (TSV) annealing process as described in claim 11, characterized in that, The formula for calculating the annealing index value β is β=R1 / R2.

13. The method for determining the through-silicon via (TSV) annealing process as described in claim 11, characterized in that, If the value of β is between A1 and A2, then the through-silicon via annealing process is qualified. The theoretical value of A1 is 0.95, and the theoretical value of A2 is 1.

1.

14. The method for determining the through-silicon via (TSV) annealing process as described in claim 11, characterized in that, If the value of β is between A2 and B, the through-silicon via annealing process is unqualified, resulting in the through-silicon via swelling. The theoretical value of A2 is 1.1, and the theoretical value of B is 1.8~2.

15. The method for determining the through-silicon via (TSV) annealing process as described in claim 11, characterized in that, If the value of β is greater than or equal to B, the through-silicon via annealing process is unqualified, resulting in the through-silicon via swelling and damage to the barrier layer structure. The theoretical value of B is 1.8 to 2.

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