A method for transferring a semiconductor epitaxial layer

Abstract

The application provides a transfer method of a semiconductor epitaxial layer, which comprises the following steps: firstly, performing hydrophilic bonding on a semiconductor epitaxial structure and a porous silicon carrier plate; secondly, performing thinning treatment on a substrate, and then bonding the substrate and a device wafer to form a second temporary bonding structure; and thirdly, etching the porous silicon carrier plate to complete the transfer of the epitaxial layer. Different from traditional organic glue solidification, the application adopts low-temperature medium bonding in the bonding stage, strictly controls the annealing temperature, and thereby inhibits the generation of thermal stress; in the peeling stage, the third medium layer is etched and released by using hydrofluoric acid, so that the transfer stress tends to be zero; different medium materials are adopted in the bonding process, so that the residual organic glue is eliminated, the cleanliness of the bonding interface is ensured, excellent mechanical support force can be provided, the total thickness variation of the bonding layer can be stably controlled to be less than or equal to 2 microns by medium bonding, the risk of cracking in the thinning process is greatly reduced, and the excellent heat resistance of the bonding layer makes it perfectly adapt to the high-temperature process requirement of a large-size wafer, thereby improving the production yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for transferring semiconductor epitaxial layers. Background Technology

[0002] In recent years, with the rapid development of fifth-generation mobile communication (5G), phased array radar, satellite communication, new energy vehicles, and smart grids, semiconductor devices are accelerating their evolution towards high frequency, high voltage, high power density, and high-density integration. Traditional single-material substrates are no longer sufficient to simultaneously meet the comprehensive requirements of integrated circuits for high integration, high-speed computing, and high-power processing capabilities. Against this backdrop, heterogeneous integration technology, by integrating mature, precise, and low-cost silicon-based integrated circuits with compound semiconductor devices (such as GaN devices) possessing high frequency, high voltage, and high efficiency characteristics into the same microsystem, can fully leverage the performance advantages of different material systems and overcome the inherent limitations of single-substrate materials in terms of carrier mobility, breakdown electric field, and thermal conductivity, becoming a key path for the development of integrated circuits in the post-Moore's Law era.

[0003] Epitaxial layer transfer technology is one of the core processes for achieving heterogeneous integration. It typically requires temporarily bonding a functional wafer with completed front-side device fabrication to a carrier substrate, thinning the wafer to an ultrathin thickness of tens or even a few micrometers, before peeling it off and transferring it to the target substrate to achieve high-performance heterogeneous integration. However, for micrometer-thick epitaxial layers, existing epitaxial layer transfer technologies face the following challenges in application, mainly in the following aspects:

[0004] First, traditional transfer processes often use organic adhesive layers such as epoxy resin and PMMA for temporary bonding. During subsequent curing, high-temperature annealing, and final peeling, the organic adhesive layer will generate significant thermal mismatch stress and mechanical shear stress. For brittle compound semiconductor materials with a thickness on the order of micrometers, the stress accumulation during the transfer process can easily lead to epitaxial layer damage, resulting in device failure and extremely poor process compatibility.

[0005] Secondly, after the organic adhesive layer is peeled off, it is very easy for difficult-to-remove polymer impurities to remain on the surface of the epitaxial layer; if a metal bonding layer is used, there is a risk that metal atoms will diffuse into the epitaxial layer at high temperatures. The above-mentioned interface contamination affects the electrical performance of the device and seriously restricts the improvement of device yield.

[0006] Secondly, on the one hand, the total thickness variation (TTV) of the organic adhesive layer itself is usually large (≥5μm), and it is prone to flow deformation during high-temperature bonding, leading to uneven wafer stress during subsequent precision thinning and chemical mechanical polishing processes, causing the risk of wafer cracking and failing to meet the requirements of high-precision integration processes. On the other hand, existing adhesives exhibit significant elastic characteristics even at room temperature (elastic modulus of approximately 1GPa), lacking sufficient rigid support. This makes it impossible to precisely control the final thickness during the thinning process of the epitaxial layer, resulting in poor thickness consistency.

[0007] Finally, some advanced transfer processes require temperatures exceeding 250°C, which existing organic adhesive systems generally cannot withstand, leading to carbonization or degradation. Furthermore, traditional temporary bonding solutions are ill-suited for the uniform coating and stress control requirements of 8-inch and larger wafers, limiting their large-scale application.

[0008] Therefore, developing an epitaxial layer transfer technology that simultaneously achieves high rigidity mechanical support, low stress bonding, residue-free and non-destructive peeling, and high process compatibility for micron-thickness epitaxial layer transfer has become an extremely urgent technical requirement in the field of heterogeneous integration. This technology is of great significance for promoting the industrialization of next-generation high-frequency, high-voltage, and high-power-density integrated chips. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor epitaxial layer transfer method to solve the problems of stress damage, insufficient mechanical support, interface contamination and residue, and low transfer yield and poor process compatibility of epitaxial layers caused by large variations in the total thickness of the organic binder layer during the existing transfer process for epitaxial layers with a thickness of micrometers.

[0010] To achieve the above and other related objectives, the present invention provides a method for transferring a semiconductor epitaxial layer, comprising the following steps:

[0011] A support substrate is provided, the support substrate having a first surface and a second surface disposed opposite to each other, and a first dielectric layer is formed on the first surface and the second surface of the support substrate;

[0012] The supporting substrate is subjected to deep silicon etching to form through-silicon vias, and the first dielectric layer is removed by wet etching to form a porous silicon substrate.

[0013] A second dielectric layer is formed on both sides of the porous silicon substrate, the second dielectric layer fills the silicon vias, and a third dielectric layer is formed on the surface of the porous silicon substrate;

[0014] A semiconductor epitaxial structure is provided, the semiconductor epitaxial structure including at least a substrate, an epitaxial layer and a fourth dielectric layer disposed on the epitaxial layer; the fourth dielectric layer is bonded to the third dielectric layer to form a first temporary bonding structure;

[0015] The substrate of the semiconductor epitaxial structure in the first temporary bonding structure is thinned to achieve the removal of the substrate, providing a wafer device, and the first temporary bonding structure is bonded to the wafer device to form a second temporary bonding structure;

[0016] The third dielectric layer is treated with hydrofluoric acid to separate the porous silicon substrate from the second temporary bonding structure, thereby achieving heterogeneous integration of the epitaxial layer and the wafer structure in the semiconductor epitaxial structure.

[0017] Optionally, the thickness of the first dielectric layer on the first surface of the supporting substrate is 1.8~2.2μm, the thickness of the first dielectric layer on the second surface of the supporting substrate is 1.8~2.2μm, and before forming the first dielectric layer, the supporting substrate is further cleaned.

[0018] Optionally, forming the through-silicon vias includes: forming a first photoresist layer on the surface of the first dielectric layer located on a first surface of the support substrate; exposing and developing the first photoresist layer to form a matrix pattern in the first photoresist layer; exposing the first dielectric layer by the pattern; etching the first dielectric layer based on the pattern to expose the support substrate; and performing deep silicon etching on the exposed support substrate to form a plurality of through-silicon vias in the support substrate.

[0019] Optionally, the through-silicon vias are arranged in an array, with a lateral distance of 5 μm between adjacent through-silicon vias and a vertical distance of 4 μm between adjacent through-silicon vias, and the size of the through-silicon vias is 5 μm * 2 μm.

[0020] Optionally, after forming the second dielectric layer, the surface of the second dielectric layer is further subjected to chemical mechanical polishing planarization to make the surface roughness of the second dielectric layer <1nm. After forming the third dielectric layer, the surface of the second dielectric layer is further subjected to chemical mechanical polishing planarization to make the surface roughness of the third dielectric layer <1nm.

[0021] Optionally, the thickness of the second dielectric layer is at least 2 μm, and the total thickness variation of the second dielectric layer is less than 2 μm; the thickness of the third dielectric layer is 6000 Å, and the total thickness variation of the third dielectric layer is less than 2 μm.

[0022] Optionally, the first dielectric layer is a silicon nitride layer, the second dielectric layer is a silicon oxide layer, the third dielectric layer is a silicon nitride layer, and the fourth dielectric layer is a silicon oxide layer.

[0023] Optionally, after performing a hydrophilic bonding process on the fourth dielectric layer and the third dielectric layer to form a first temporary bonding structure, the process further includes annealing the formed first temporary bonding structure at 170°C for 48 hours.

[0024] Optionally, a fifth dielectric layer is formed on the surface of the wafer device, such that the first temporary bonding structure is bonded to the wafer device by dielectric bonding.

[0025] Optionally, the hydrofluoric acid treatment method includes soaking in a hydrofluoric acid solution, wherein the mass percentage concentration of the hydrofluoric acid solution is 5% to 20%; the temperature of the hydrofluoric acid solution treatment is 10 to 50°C, and the time is 10 minutes.

[0026] As described above, the semiconductor epitaxial layer transfer method of the present invention has the following beneficial effects: a porous silicon substrate is formed by processing a supporting substrate, and a second dielectric layer and a third dielectric layer are sequentially formed on the porous silicon substrate. The semiconductor epitaxial structure is first hydrophilically bonded to the third dielectric layer to form a first temporary bonding structure. After thinning the substrate in the semiconductor epitaxial structure, the device wafer is then bonded to the epitaxial layer of the first temporary bonding structure to form a second temporary bonding structure. The porous silicon substrate is then etched to achieve the release of the porous silicon substrate without external force, thereby completing the epitaxial layer transfer and realizing heterogeneous integration. Unlike traditional organic adhesives that generate thermal stress and mechanical peeling forces during curing, this invention employs a low-temperature dielectric bonding process at each bonding stage, strictly controlling the annealing temperature below 150°C to suppress thermal stress. During the peeling stage of the porous silicon substrate, hydrofluoric acid is used to isotropically etch and release the third dielectric layer, resulting in near-zero stress during the transfer process. Furthermore, the use of different dielectric materials throughout the bonding process eliminates organic adhesive residue, ensuring an extremely clean interface. The dielectric material layer also provides excellent mechanical support. In addition, the dielectric bonding process can stably control the total thickness variation of the bonding layer to ≤2μm, far superior to the ≥5μm level of traditional organic adhesives, significantly reducing the risk of wafer cracking during subsequent thinning and CMP processes. The excellent heat resistance of the bonding layer makes it perfectly suited to the high-temperature process requirements of large-size wafers, thereby improving production yield. Attached Figure Description

[0027] Figure 1 The diagram shows a process flow chart of the semiconductor epitaxial layer transfer method provided by the present invention.

[0028] Figures 2 to 12The diagram shows the cross-sectional structure of each step in the semiconductor epitaxial layer transfer method provided by the present invention.

[0029] Component designation explanation

[0030] 10. Supporting substrate; 101. First surface; 102. Second surface; 11. First dielectric layer; 12. Through-silicon via (TSV); 13. Porous silicon substrate; 131. Second dielectric layer; 132. Third dielectric layer; 14. Semiconductor epitaxial structure; 141. Substrate; 142. Epitaxial layer; 143. Fourth dielectric layer; 144. Source; 145. Drain; 146. Gate; 15. First temporary bonding structure; 16. Wafer device; 161. Fifth dielectric layer; 17. Second temporary bonding structure; S1~S6: Steps. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0033] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0034] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] This invention provides a method for transferring a semiconductor epitaxial layer, such as... Figure 1 As shown, it is a process flow diagram of the method for transferring the semiconductor epitaxial layer, including the following steps:

[0037] S1: A support substrate 10 is provided, the support substrate 10 having a first surface 101 and a second surface 102 disposed opposite to each other, and a first dielectric layer 11 is formed on the first surface 101 and the second surface 102 of the support substrate 10;

[0038] S2: Deep silicon etching is performed on the support substrate 10 to form silicon vias 12, and wet etching is performed to remove the first dielectric layer 11 to form a porous silicon substrate 13.

[0039] S3: A second dielectric layer 131 is formed on both sides of the porous silicon substrate 13, the second dielectric layer 131 fills the silicon via 12, and a third dielectric layer 132 is formed on the surface of the porous silicon substrate 13.

[0040] S4: A semiconductor epitaxial structure 14 is provided, the semiconductor epitaxial structure 14 including at least a substrate 141, an epitaxial layer 142 and a fourth dielectric layer 143 disposed on the epitaxial layer 142; the fourth dielectric layer 143 is bonded to the third dielectric layer 132 to form a first temporary bonding structure 15.

[0041] S5: Thin the substrate 141 of the semiconductor epitaxial structure 14 in the first temporary bonding structure 15 to remove the substrate 141, provide a wafer device 16, and bond the first temporary bonding structure 15 to the wafer device 16 to form a second temporary bonding structure 17.

[0042] S6: The third dielectric layer 132 is treated with hydrofluoric acid to separate the porous silicon substrate 13 from the second temporary bonding structure 17, thereby achieving heterogeneous integration of the epitaxial layer 142 in the semiconductor epitaxial structure 14 with the wafer structure.

[0043] It should be noted that the above order does not strictly represent the order of the semiconductor epitaxial layer 142 transfer method protected by this invention. Those skilled in the art can modify it according to the actual preparation steps. The following is a further description of the relevant semiconductor epitaxial layer 142 transfer method with reference to the accompanying drawings:

[0044] In step S1, please refer to Figure 2 and Figure 3 A support substrate 10 is provided, the support substrate 10 having a first surface 101 and a second surface 102 disposed opposite to each other, and a first dielectric layer 11 is formed on the first surface 101 and the second surface 102 of the support substrate 10.

[0045] As an example, such as Figure 2 As shown, the supporting substrate 10 has a first surface 101 and a second surface 102 disposed opposite to each other. Optionally, the supporting substrate 10 is a wafer-type substrate 141, and its size can be set to be the same as that of 6-inch, 8-inch or 12-inch wafers commonly used in integrated circuit manufacturing, so that the semiconductor epitaxial layer 142 transfer method described in this invention can be integrated into existing integrated circuit production lines and realize the mass production of related devices.

[0046] Optionally, the material of the support substrate 10 can be a silicon-based material, such as silicon wafer, silicon carbide, or silicon oxide, and its shape can be circular, square, or any other desired shape. In addition, the material of the support substrate 10 can also include any one or a combination of materials selected from single-crystal sapphire, aluminum nitride, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, and quartz, without particular limitation. Before forming the first dielectric layer 11 on the first surface 101 and the second surface 102 of the support substrate 10, the support substrate 10 needs to be cleaned. For example, the natural oxide layer on the first surface 101 and the second surface 102 of the support substrate 10 can be completely removed using a diluted acid solution, followed by rinsing with deionized water, and finally drying with high-purity nitrogen gas to ensure complete removal of contaminants from the first surface 101 and the second surface 102 of the support substrate 10.

[0047] Specifically, in this embodiment, the supporting substrate 10 is a wafer substrate 141 formed of single-crystal silicon, the supporting substrate 10 has a size of 8 inches, a thickness of 400 μm, and a surface roughness of <1 nm.

[0048] Specifically, such as Figure 3 As shown, a first dielectric layer 11 is formed on the first surface 101 and the second surface 102 of the support substrate 10. The first dielectric layer 11 is a silicon nitride layer. The thickness of the first dielectric layer 11 on the first surface 101 of the support substrate 10 is 1.8~2.2μm, for example, the thickness of the first dielectric layer 11 on the first surface 101 is 1.8μm, 2μm or 2.2μm. The thickness of the first dielectric layer 11 on the second surface 102 of the support substrate 10 is 1.8~2.2μm, for example, the thickness of the first dielectric layer 11 on the second surface 102 is 1.8μm, 2μm or 2.2μm. The formed first dielectric layer 11 completely covers the support substrate 10.

[0049] Specifically, the method for forming the first dielectric layer 11 includes physical vapor deposition or other suitable methods.

[0050] In step S2, please refer to Figures 4 to 6The supporting substrate 10 is subjected to deep silicon etching to form silicon through-holes 12, and the first dielectric layer 11 is removed by wet etching to form a porous silicon substrate 13.

[0051] Specifically, such as Figure 4 As shown, a spin-coating process is performed on the surface of the first dielectric layer 11 located on the first surface 101 of the support substrate 10 to form a first photoresist layer with a thickness of 3 μm. Then, the first photoresist layer is dried and cured at a temperature of 110°C for 180 s. The first photoresist layer is then subjected to a patterning process involving exposure and development to form a matrix-arranged pattern in the first photoresist layer. The bottom of the pattern exposes the first dielectric layer 11. Based on the pattern, the first dielectric layer 11 is etched to expose the support substrate 10. The exposed support substrate 10 is then subjected to further deep silicon etching to form a plurality of through-silicon vias 12 in the support substrate 10.

[0052] Specifically, after forming multiple through-silicon vias 12, the first photoresist layer needs to be removed, and the remaining first dielectric layer 11 needs to be subjected to a wet etching process to remove the first dielectric layer 11 on the surface of the supporting substrate 10, exposing the supporting substrate 10, thereby forming a porous silicon substrate 13. Figure 5 It is known that the through-silicon vias 12 are arranged in an array and the distance between adjacent through-silicon vias 12 in the horizontal direction is 5μm, the distance between adjacent through-silicon vias 12 in the vertical direction is 4μm, and the size of the through-silicon vias 12 is 5μm*2μm.

[0053] In step S3, please refer to Figure 6 and Figure 7 A second dielectric layer 131 is formed on both sides of the porous silicon substrate 13, the second dielectric layer 131 fills the silicon via 12, and a third dielectric layer 132 is formed on the surface of the porous silicon substrate 13.

[0054] Specifically, the method for forming the second dielectric layer 131 includes physical vapor deposition or other suitable methods. The second dielectric layer 131 is a silicon oxide layer, and the formed silicon oxide layer fills the silicon vias 12 of the porous silicon substrate 13 to achieve sealing of the silicon vias 12.

[0055] Specifically, such as Figure 6 As shown, after forming the second dielectric layer 131, the surface of the second dielectric layer 131 is further subjected to chemical mechanical polishing planarization to make the surface roughness of the second dielectric layer 131 < 1 nm, and the thickness of the second dielectric layer 131 is at least 2 μm, and the total thickness variation of the second dielectric layer 131 is less than 2 μm.

[0056] Specifically, the method for forming the third dielectric layer 132 includes physical vapor deposition or other suitable methods. The third dielectric layer 132 is a silicon nitride layer, which serves as a protective layer when the final porous silicon substrate 13 is released.

[0057] Specifically, such as Figure 7 As shown, after forming the third dielectric layer 132, the surface of the third dielectric layer 132 is further subjected to chemical mechanical polishing planarization to make the surface roughness of the third dielectric layer 132 < 1 nm. The final thickness of the third dielectric layer 132 is 6000 Å, and the total thickness change of the second dielectric layer 131 is less than 2 μm.

[0058] In step S4, please refer to Figure 8 and Figure 9 A semiconductor epitaxial structure 14 is provided, the semiconductor epitaxial structure 14 including at least a substrate 141, an epitaxial layer 142 and a fourth dielectric layer 143 disposed on the epitaxial layer 142; the fourth dielectric layer 143 is bonded to the third dielectric layer 132 to form a first temporary bonding structure 15.

[0059] Specifically, such as Figure 8 As shown, a semiconductor epitaxial structure 14 is provided. The semiconductor epitaxial structure 14 includes at least a substrate 141, an epitaxial layer 142, and a source 144, a gate 146, and a drain 145 disposed on the epitaxial layer 142. The source 144, the gate 146, and the drain 145 are covered by a fourth dielectric layer 143 formed on the epitaxial layer 142, and the fourth dielectric layer 143 is a silicon oxide layer. The substrate 141 can be made of silicon-based materials, such as silicon wafers, silicon carbide, or silicon oxide, and its shape can be circular, square, or any other desired shape. In addition, the substrate 141 can also be made of any one of single-crystal sapphire, aluminum nitride, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, and quartz, without particular limitation. The material of the substrate 141 can be the same as that of the supporting substrate 10 or different from that of the supporting substrate 10. Preferably, in this embodiment, the material of the substrate 141 is the same as that of the supporting substrate 10.

[0060] Specifically, the method for forming the fourth dielectric layer 143 includes physical vapor deposition or other suitable methods. Furthermore, after forming the fourth dielectric layer 143, the surface of the fourth dielectric layer 143 is further subjected to chemical mechanical polishing to planarize it, resulting in a surface roughness of the fourth dielectric layer 143 < 1 nm.

[0061] like Figure 9As shown, the fourth dielectric layer 143 and the third dielectric layer 132 are subjected to a hydrophilic bonding process to form a first temporary bonded structure 15. Specifically, firstly, the bonding surfaces of the fourth dielectric layer 143 and the third dielectric layer 132 are activated by 40W oxygen plasma; then, the particles and organic residues on the bonding surfaces are removed by two-fluid cleaning; subsequently, a pressure of 5N is applied at a vacuum of 0.3 Pa and room temperature to complete the pre-bonding of the fourth dielectric layer 143 and the third dielectric layer 132; finally, annealing is performed at 150°C for 48 h, thereby enhancing the bonding interface strength between the fourth dielectric layer 143 and the third dielectric layer 132 and obtaining a stable first temporary bonded structure 15.

[0062] In step S5, please refer to Figure 10 and Figure 11 The substrate 141 of the semiconductor epitaxial structure 14 in the first temporary bonding structure 15 is thinned to remove the substrate 141 and provide a wafer device 16. The first temporary bonding structure 15 is then bonded to the wafer device 16 to form a second temporary bonding structure 17.

[0063] Specifically, such as Figure 10 As shown, the substrate 141 of the semiconductor epitaxial structure 14 in the first temporary bonding structure 15 is thinned to achieve the removal of the substrate 141. The process of thinning the substrate 141 includes chemical mechanical polishing or plasma dry etching. After the substrate 141 is removed, the bottom of the first temporary bonding structure 15 is the epitaxial layer 142.

[0064] Specifically, such as Figure 11 As shown, a wafer device 16 is provided, and a fifth dielectric layer 161 is formed on the surface of the wafer device 16. The fifth dielectric layer 161 is a silicon oxide layer. The epitaxial layer 142 at the bottom of the first temporary bonding structure 15 is bonded to the wafer device 16 to form a second temporary bonding structure 17. The first temporary bonding structure 15 is bonded to the wafer device 16 by dielectric bonding.

[0065] In step S6, please refer to Figure 12 The third dielectric layer 132 is treated with hydrofluoric acid to separate the porous silicon substrate 13 from the second temporary bonding structure 17, thereby achieving heterogeneous integration of the epitaxial layer 142 and the wafer structure in the semiconductor epitaxial structure 14.

[0066] As an example, the method of hydrofluoric acid treatment includes soaking in a hydrofluoric acid solution, wherein the mass percentage concentration of the hydrofluoric acid solution is 5% to 20%; the temperature of the hydrofluoric acid solution treatment is 10 to 50°C, and the time is 10 minutes.

[0067] Specifically, such as Figure 12 As shown, the third dielectric layer 132 is immersed in a hydrofluoric acid solution with a mass percentage concentration of 10%, the temperature of the hydrofluoric acid solution treatment is 25°C, and the immersion time is 10 minutes. Through immersion in the hydrofluoric acid solution, the porous silicon substrate 13 separates from the second temporary bonding structure 17, realizing the release of the porous silicon substrate 13 without external force, and completing the heterogeneous integration of the epitaxial layer 142 in the semiconductor epitaxial structure 14 with the wafer structure.

[0068] In summary, this invention provides a method for transferring a semiconductor epitaxial layer. A porous silicon substrate is formed by processing a supporting substrate, and a second dielectric layer and a third dielectric layer are sequentially formed on the porous silicon substrate. First, the semiconductor epitaxial structure is hydrophilically bonded to the third dielectric layer to form a first temporary bonding structure. After thinning the substrate in the semiconductor epitaxial structure, the device wafer is bonded to the epitaxial layer of the first temporary bonding structure to form a second temporary bonding structure. Then, the porous silicon substrate is etched to release the porous silicon substrate without external force, thereby completing the epitaxial layer transfer and achieving heterogeneous integration. Unlike traditional organic adhesives that generate thermal stress and mechanical peeling forces during curing, this invention employs a low-temperature dielectric bonding process at each bonding stage, strictly controlling the annealing temperature below 150°C to suppress thermal stress. During the peeling stage of the porous silicon substrate, hydrofluoric acid is used to isotropically etch and release the third dielectric layer, resulting in near-zero stress during the transfer process. Furthermore, the use of different dielectric materials throughout the bonding process eliminates organic adhesive residue, ensuring an extremely clean interface. The dielectric material layer also provides excellent mechanical support. In addition, the dielectric bonding process can stably control the total thickness variation of the bonding layer to ≤2μm, far superior to the ≥5μm level of traditional organic adhesives, significantly reducing the risk of wafer cracking during subsequent thinning and CMP processes. The excellent heat resistance of the bonding layer makes it perfectly suited to the high-temperature process requirements of large-size wafers, thereby improving production yield.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for transferring a semiconductor epitaxial layer, characterized in that, Includes the following steps: A support substrate is provided, the support substrate having a first surface and a second surface disposed opposite to each other, and a first dielectric layer is formed on the first surface and the second surface of the support substrate; The supporting substrate is subjected to deep silicon etching to form through-silicon vias, and the first dielectric layer is removed by wet etching to form a porous silicon substrate. A second dielectric layer is formed on both sides of the porous silicon substrate, the second dielectric layer fills the silicon vias, and a third dielectric layer is formed on the surface of the porous silicon substrate; A semiconductor epitaxial structure is provided, the semiconductor epitaxial structure including at least a substrate, an epitaxial layer and a fourth dielectric layer disposed on the epitaxial layer; the fourth dielectric layer is bonded to the third dielectric layer to form a first temporary bonding structure; The substrate of the semiconductor epitaxial structure in the first temporary bonding structure is thinned to achieve the removal of the substrate, providing a wafer device, and the first temporary bonding structure is bonded to the wafer device to form a second temporary bonding structure; The third dielectric layer is treated with hydrofluoric acid to separate the porous silicon substrate from the second temporary bonding structure, thereby achieving heterogeneous integration of the epitaxial layer and the wafer structure in the semiconductor epitaxial structure.

2. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, The thickness of the first dielectric layer located on the first surface of the supporting substrate is 1.8~2.2μm, the thickness of the first dielectric layer located on the second surface of the supporting substrate is 1.8~2.2μm, and before forming the first dielectric layer, the supporting substrate is further cleaned.

3. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, Forming the through-silicon vias includes: forming a first photoresist layer on the surface of the first dielectric layer located on a first surface of the support substrate; exposing and developing the first photoresist layer to form a matrix pattern in the first photoresist layer; exposing the first dielectric layer by the pattern; etching the first dielectric layer based on the pattern to expose the support substrate; and performing deep silicon etching on the exposed support substrate to form a plurality of through-silicon vias in the support substrate.

4. The method for transferring a semiconductor epitaxial layer according to claim 3, characterized in that, The through-silicon vias are arranged in an array, with a horizontal distance of 5 μm between adjacent through-silicon vias and a vertical distance of 4 μm between adjacent through-silicon vias. The size of each through-silicon via is 5 μm * 2 μm.

5. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, After forming the second dielectric layer, the surface of the second dielectric layer is further subjected to chemical mechanical polishing planarization to make the surface roughness of the second dielectric layer <1nm. After forming the third dielectric layer, the surface of the second dielectric layer is further subjected to chemical mechanical polishing planarization to make the surface roughness of the third dielectric layer <1nm.

6. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, The thickness of the second dielectric layer is at least 2 μm, and the total thickness variation of the second dielectric layer is less than 2 μm. The thickness of the third dielectric layer is 6000 Å, and the total thickness variation of the third dielectric layer is less than 2 μm.

7. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, The first dielectric layer is a silicon nitride layer, the second dielectric layer is a silicon oxide layer, the third dielectric layer is a silicon nitride layer, and the fourth dielectric layer is a silicon oxide layer.

8. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, After performing a hydrophilic bonding process on the fourth dielectric layer and the third dielectric layer to form a first temporary bond structure, the process further includes annealing the formed first temporary bond structure at 150°C for 48 hours.

9. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that, A fifth dielectric layer is formed on the surface of the wafer device, such that the first temporary bonding structure is bonded to the wafer device by dielectric bonding.

10. The method for transferring a semiconductor epitaxial layer according to claim 1, characterized in that... The method of hydrofluoric acid treatment includes soaking in a hydrofluoric acid solution, wherein the mass percentage concentration of the hydrofluoric acid solution is 5% to 20%; the temperature of the hydrofluoric acid solution treatment is 10 to 50°C, and the time is 10 minutes.

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