Silicon-on-insulator substrate and method for manufacturing the same

Abstract

The application provides a silicon-on-insulator substrate and a preparation method thereof. A wafer substrate includes a support substrate, a buried oxygen layer, and a top silicon layer, the top silicon layer including a first single-crystal silicon layer, an amorphous silicon interface layer, and a second single-crystal silicon layer, the amorphous silicon interface layer being formed by surface-activated bonding of the two single-crystal silicon layers. Pulsed laser irradiation is applied to the wafer substrate, the optical penetration depth of the pulsed laser in the single-crystal silicon being greater than the embedding depth of the amorphous silicon interface layer in the top silicon layer, so that the pulsed laser reaches and is absorbed by the amorphous silicon interface layer. The processed silicon-on-insulator substrate has a crystalline silicon interface region formed by pulsed laser recrystallization between the two single-crystal silicon layers, which is conducive to improving the electrical properties of the top silicon layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor substrate fabrication technology, specifically to silicon-on-insulator (SOI) substrates and their fabrication methods. Background Technology

[0002] A silicon-on-insulator (SiI) substrate comprises a top silicon layer, a buried oxide layer, and a support substrate stacked sequentially. The top silicon layer is used to form semiconductor devices, the buried oxide layer is used to achieve electrical isolation between the top silicon layer and the support substrate, and the support substrate is used to provide mechanical support.

[0003] The electrical properties of the top silicon layer affect the operating performance of semiconductor devices. Electron mobility and minority carrier lifetime are parameters characterizing the electrical properties of the top silicon layer, reflecting the carrier transport capacity and recombination characteristics, respectively.

[0004] When surface-activated bonding (SAB) is used to connect monocrystalline silicon layers to form the top silicon layer, a nanoscale amorphous silicon interface layer is formed at the bonding interface. The presence of the amorphous silicon interface layer affects the electrical properties of the top silicon layer. Summary of the Invention

[0005] This application provides a method for fabricating a silicon-on-insulator substrate. The method includes providing a wafer substrate to be processed, the wafer substrate comprising a support substrate, a buried oxide layer on the support substrate, and a top silicon layer on the buried oxide layer. The top silicon layer comprises a first monocrystalline silicon layer, an amorphous silicon interface layer, and a second monocrystalline silicon layer, the amorphous silicon interface layer being formed by surface activation bonding of the first and second monocrystalline silicon layers. The wafer substrate is irradiated with a pulsed laser, the wavelength of which causes the optical penetration depth of the pulsed laser in the monocrystalline silicon to be greater than the embedment depth of the amorphous silicon interface layer in the top silicon layer. The pulsed laser reaches the amorphous silicon interface layer and is absorbed by it, causing the amorphous silicon interface layer to recrystallize, thus obtaining a silicon-on-insulator substrate.

[0006] This application also provides a silicon-on-insulator substrate. The silicon-on-insulator substrate includes a supporting substrate, a buried oxide layer on the supporting substrate, and a top silicon layer on the buried oxide layer. The top silicon layer includes a first monocrystalline silicon layer, a crystalline silicon interface region, and a second monocrystalline silicon layer. The crystalline silicon interface region is formed by recrystallizing an amorphous silicon interface layer formed by surface activation bonding of the first and second monocrystalline silicon layers under pulsed laser irradiation. During the formation of the crystalline silicon interface region, the wavelength of the pulsed laser ensures that the optical penetration depth of the pulsed laser in the monocrystalline silicon is greater than the embedment depth of the amorphous silicon interface layer in the top silicon layer. The pulsed laser reaches the amorphous silicon interface layer and is absorbed by it. The thickness of the amorphous silicon interface layer is... . Attached Figure Description

[0007] Figure 1 A flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided in an embodiment of this application.

[0008] Figure 2 This is a schematic diagram of the structure of the wafer substrate provided in an embodiment of this application.

[0009] Figure 3 This is a schematic diagram of the structure of the wafer substrate provided in the embodiments of this application during preheating and pulsed laser processing.

[0010] Figure 4 This is a schematic diagram of the structure of a silicon-on-insulator substrate after pulsed laser treatment, provided in an embodiment of this application.

[0011] Figure 5 This is a schematic diagram of pulsed laser scanning on the surface of a first single-crystal silicon layer, provided as an embodiment of this application. Detailed Implementation

[0012] A surface-activated bonded amorphous silicon interface layer is embedded within the top silicon layer and covered by monocrystalline silicon. The amorphous structure increases carrier scattering and trapping, affecting carrier transport and recombination behavior. When laser treatment is applied to the buried interface, the light propagation in the capping layer and the energy absorption at the interface jointly affect the treatment result.

[0013] Pulsed laser processing can be performed without preheating the wafer substrate. Preheating is an optional process, increasing the initial temperature of the amorphous silicon interface layer and the adjacent monocrystalline silicon region, thereby reducing the heating amount and local instantaneous temperature difference borne by the pulsed laser.

[0014] See Figure 1 The fabrication method includes step S101 of providing a wafer substrate and step S103 of applying a pulsed laser. The dashed box indicates an optional preheating step S102. When preheating is used, step S102 is performed after step S101 and before step S103; when preheating is not used, it proceeds along... Figure 1 The path indicated by the arrow on the left leads directly from step S101 to step S103.

[0015] In step S101, a wafer substrate to be processed is provided. The wafer substrate includes a first single-crystal silicon layer, an amorphous silicon interface layer, a second single-crystal silicon layer, a buried oxide layer, and a support substrate stacked sequentially. The amorphous silicon interface layer is formed by surface activation bonding of the first single-crystal silicon layer and the second single-crystal silicon layer.

[0016] The amorphous silicon interface layer is located between the first and second monocrystalline silicon layers, with the first monocrystalline silicon layer situated on the pulsed laser incident side. Thus, the first monocrystalline silicon layer constitutes the capping layer that the pulsed laser must pass through before reaching the amorphous silicon interface layer.

[0017] When preheating is used, the wafer substrate is preheated in step S102. Preheating gives the amorphous silicon interface layer and adjacent areas an initial temperature higher than room temperature before receiving the pulsed laser, and the sample stage can be used as a heat-providing device.

[0018] Preheating reduces the temperature rise required for subsequent pulsed laser treatment to bring the amorphous silicon interface layer to the recrystallization stage. Preheating also reduces the instantaneous temperature difference between the interface and the adjacent monocrystalline silicon region, providing a stable initial thermal state for subsequent laser processing.

[0019] In step S103, a pulsed laser is applied from the side of the first monocrystalline silicon layer away from the amorphous silicon interface layer. After passing through the first monocrystalline silicon layer, the pulsed laser acts on the amorphous silicon interface layer, causing the amorphous silicon interface layer to recrystallize and form a crystalline silicon interface region.

[0020] The optical penetration depth of a pulsed laser in monocrystalline silicon is greater than the embedment depth of the amorphous silicon interface layer within the top silicon layer. The embedment depth refers to the distance from the laser incident surface along the incident direction to the incident boundary of the amorphous silicon interface layer; in a structure where the laser is incident perpendicularly from the surface of the first monocrystalline silicon layer, the embedment depth corresponds to the thickness of the first monocrystalline silicon layer.

[0021] In one wavelength selection method, the absorption coefficient of the amorphous silicon interface layer for pulsed laser light is greater than that of the first monocrystalline silicon layer. The difference in absorption coefficient reflects the difference in light intensity attenuation per unit optical path. The actual absorbed energy at the interface is also related to the layer thickness, the light intensity reaching the interface, and the pulse parameters.

[0022] When the amorphous silicon interface layer absorbs pulsed laser energy, it recrystallizes, and crystalline silicon interface regions form at the original amorphous interface locations. This change reduces the amorphous structure in the interface, but is not necessarily limited by a specific crystal orientation continuity.

[0023] Figure 1 The fabrication method shown involves selecting a pulsed laser wavelength so that the optical penetration depth of the pulsed laser in single-crystal silicon is greater than the embedding depth of the amorphous silicon interface layer within the top silicon layer. The pulsed laser reaches and is absorbed by the amorphous silicon interface layer, prompting recrystallization. Preheating is an optional auxiliary condition and is not a prerequisite for achieving interface recrystallization.

[0024] Reducing the amorphous structure at the interface decreases carrier scattering and trapping associated with the amorphous structure, thereby improving the electrical performance of the top silicon layer. Electron mobility and minority carrier lifetime tests in the examples were used to characterize the impact of the interface treatment on the electrical performance of the top silicon layer.

[0025] Figure 1 The flow chart of the preparation method is shown, and the relative positions of each layer are determined by... Figure 2 The structural diagram is shown. Figure 2 The layer thicknesses are drawn to the indicated scale.

[0026] See Figure 2 The substrate structure 100 forms the wafer substrate to be processed before pulsed laser processing. A buried oxide layer 140 is provided on the support substrate 150, and a top silicon layer is provided on the buried oxide layer 140; the top silicon layer includes a second single crystal silicon layer 130, an amorphous silicon interface layer 120 and a first single crystal silicon layer 110 in the direction away from the buried oxide layer 140.

[0027] The first monocrystalline silicon layer 110 and the second monocrystalline silicon layer 130 are made of monocrystalline silicon material and are bonded together by surface activation. An amorphous silicon interface layer 120 is formed at the surface activation bonding interface of the two monocrystalline silicon layers and is located between the first monocrystalline silicon layer 110 and the second monocrystalline silicon layer 130.

[0028] Surface activation treatment removes oxides from the silicon surface to be bonded using ion or atomic beams, forming an active surface. Two active surfaces come into contact to form a bonding interface, and the structurally altered regions near the bonding interface together constitute the amorphous silicon interface layer 120.

[0029] The first monocrystalline silicon layer 110, the amorphous silicon interface layer 120, and the second monocrystalline silicon layer 130 together constitute the top silicon layer before processing. The buried oxide layer 140 is located between the second monocrystalline silicon layer 130 and the supporting substrate 150, which provides mechanical support.

[0030] The amorphous silicon interface layer 120 is located inside the substrate structure 100 and is covered by the first monocrystalline silicon layer 110. When the pulsed laser is incident from the first monocrystalline silicon layer 110, it needs to pass through the first monocrystalline silicon layer 110 before reaching the amorphous silicon interface layer 120.

[0031] For example, the substrate structure 100 can be On a silicon-on-insulator substrate, the thicknesses of the first single-crystal silicon layer 110 and the second single-crystal silicon layer 130 are both approximately... The thickness of the amorphous silicon interface layer 120 can be... ,For example The thickness of the buried oxide layer 140 is approximately .

[0032] The total thickness of the top silicon layer is greater than and not greater than The thickness of the first single-crystal silicon layer 110 is The thickness of each layer should collectively meet the total thickness requirement of the top silicon layer; the thickness of the first single-crystal silicon layer 110 is... When both the amorphous silicon interface layer 120 and the second monocrystalline silicon layer 130 have thickness, the total thickness of the top silicon layer is greater than [amount missing]. .

[0033] Figure 2The thickness of the amorphous silicon interface layer 120 is schematically magnified to show its position in the top silicon layer. Figure 2 The relative dimensions in the text do not represent the actual size ratio of each layer.

[0034] Depend on Figure 2 The relative position of the interface to be processed and the incident surface of the pulsed laser can be determined. This positional relationship provides a structural basis for subsequently selecting laser propagation conditions based on the thickness of the first single-crystal silicon layer 110.

[0035] Figure 2 The layering relationship and buried interface location of the wafer substrate before processing are shown. Figure 3 This illustrates the substrate bearing and energy input method when preheating is employed.

[0036] See Figure 3 The substrate structure 100 is supported on the sample stage 200, and the supporting substrate 150 is adjacent to the sample stage 200. The first single-crystal silicon layer 110 is located on the side of the substrate structure 100 away from the sample stage 200 and serves as the incident side of the pulsed laser.

[0037] Figure 3 The dashed arrows at the top indicate that the pulsed laser is incident from one side of the first single-crystal silicon layer 110, and the dashed arrows inside the sample stage 200 indicate the direction of heat transfer during the preheating process. Both sets of arrows are used to indicate energy transfer paths and do not represent solid components within the substrate structure 100.

[0038] When preheating is used, the substrate structure 100 is preheated via the sample stage 200 before pulsed laser processing. Heat is transferred to the substrate structure 100 from the supporting substrate 150 side, causing the amorphous silicon interface layer 120 and the adjacent monocrystalline silicon region to reach a predetermined initial temperature.

[0039] The preheated amorphous silicon interface layer 120 is already heated before absorbing pulsed laser energy. Therefore, the subsequent pulsed laser can mainly provide the transient energy required for interface recrystallization.

[0040] Preheating reduces the amount of temperature rise that the pulsed laser has to bear from a lower initial temperature. Preheating also reduces the instantaneous temperature difference between the amorphous silicon interface layer 120 and the adjacent monocrystalline silicon region.

[0041] The amorphous silicon interface layer 120 is a nanometer-thin layer. When pulsed laser energy is input for a short period of time, a temperature change will occur near the interface. By increasing the initial temperature of the substrate structure 100, the impact of local thermal mismatch on the processing stability can be reduced.

[0042] use When using pulsed lasers, the preheating temperature of the wafer substrate can be... ,For example Preheating can be performed via the sample stage 200. Preheating can be carried out in an inert protective atmosphere formed by nitrogen or argon to reduce the possibility of the substrate surface coming into contact with reactive gases during processing.

[0043] After preheating, a pulsed laser is applied from the side of the first monocrystalline silicon layer 110 away from the amorphous silicon interface layer 120. The pulsed laser enters the first monocrystalline silicon layer 110 and propagates towards the amorphous silicon interface layer 120.

[0044] The thickness of the first single-crystal silicon layer 110 and the propagation capability of the pulsed laser in the single-crystal silicon jointly affect the laser energy reaching the interface. The thicker the first single-crystal silicon layer 110, the higher the requirements for the propagation conditions of the pulsed laser of the same wavelength.

[0045] Under conditions where light is incident perpendicularly from the surface of the first monocrystalline silicon layer 110, the optical penetration depth is greater than the thickness of the first monocrystalline silicon layer 110, corresponding to an optical penetration depth greater than the embedment depth of the amorphous silicon interface layer 120. The optical penetration depth represents the percentage of light intensity that decreases to the incident light intensity due to absorption. The distance of light propagation is not the point where light stops.

[0046] When using the exponential absorption model in a homogeneous medium, the optical penetration depth With absorption coefficient satisfy . by When indicating, The unit is ; converted to hour, Converted to hour, This model describes the attenuation caused by material absorption, but does not include the effects of surface reflection and multilayer thin film interference.

[0047] The absorption coefficient of laser light in single-crystal silicon varies with wavelength, and the optical penetration depth also varies accordingly. Therefore, the pulsed laser wavelength can be selected based on the thickness of the first single-crystal silicon layer 110.

[0048] Table 1 lists the absorption coefficient values ​​for different wavelengths and the optical penetration depth calculated using the reciprocal relationship. The wavelength selection must use an absorption coefficient that is compatible with the material state and processing temperature, while simultaneously satisfying the burial depth and interface absorption conditions.

[0049] Table 1. Conversion between absorption coefficient values ​​and optical penetration depth

[0050] According to Table 1 The absorption coefficient is calculated, and the optical penetration depth is... ,and The burial depths are equal. This value does not satisfy the condition that the optical penetration depth is greater than the burial depth, therefore it cannot be determined solely based on... Candidate bands are used to determine whether a certain wavelength is applicable.

[0051] After the pulsed laser reaches the amorphous silicon interface layer 120, the amorphous silicon interface layer 120 still needs to absorb the laser energy that has reached the interface. The first single-crystal silicon layer 110 and the amorphous silicon interface layer 120 have different crystal structures, so their absorption characteristics for the same wavelength of laser are different.

[0052] In one embodiment, at the selected wavelength, the absorption coefficient of the amorphous silicon interface layer 120 for the pulsed laser is greater than that of the first monocrystalline silicon layer 110 for the pulsed laser. This relationship facilitates the continued absorption of the pulsed laser by the amorphous silicon interface layer 120 after it has passed through the first monocrystalline silicon layer 110.

[0053] Optical penetration depth is used to evaluate the propagation of pulsed laser light in the first single-crystal silicon layer 110, while absorption coefficient and interface layer thickness are used to evaluate the energy absorption of the amorphous silicon interface layer 120. When selecting parameters, both propagation and absorption must be considered simultaneously; a larger optical penetration depth alone cannot guarantee sufficient interface absorption.

[0054] This can be considered as a candidate range for pulsed laser wavelengths. For the first single-crystal silicon layer with a thickness of 110... The structure, and the selected wavelength, must also satisfy the requirement that the optical penetration depth is greater than... This causes the laser energy reaching the amorphous silicon interface layer 120 to be absorbed.

[0055] The band gap of amorphous silicon can vary with the material state, approximately This can serve as a reference for qualitative analysis. As the wavelength increases, the photon energy decreases. In this example, it serves as the upper endpoint of the candidate band; this endpoint cannot be determined directly by the band gap value alone, but must be selected in combination with absorption characteristics and recrystallization results.

[0056] by The absorption coefficient of pulsed laser in single-crystal silicon is taken as For example, the optical penetration depth calculated using the reciprocal relationship is approximately The calculated value is greater than However, the penetration depth in the actual process needs to be determined according to the absorption coefficient of the corresponding temperature and material state.

[0057] exist In the vicinity, the absorption coefficients of amorphous silicon and monocrystalline silicon may differ by about an order of magnitude. A larger amorphous silicon absorption coefficient indicates stronger absorption per unit optical path, but this cannot be used to infer that the total energy absorbed by the interface layer of a few nanometers is greater than the total energy absorbed by the layer covering the monocrystalline silicon.

[0058] Pulse width characterizes the duration of a single pulse, while single-pulse energy density characterizes the laser energy gained per unit area in a single pulse. Both parameters, along with wavelength and preheating temperature, affect the transient energy input to the interface.

[0059] The pulse width can be ,For example The single-pulse energy density can be ,For example The specific parameters can be selected within a given range based on the thickness of the first monocrystalline silicon layer 110 and the location of the target interface.

[0060] After absorbing pulsed laser energy, the amorphous silicon interface layer 120 undergoes solid-phase epitaxial recrystallization, forming a crystalline silicon interface region at the original amorphous interface location. Solid-phase epitaxial recrystallization is used to describe solid-phase processes based on adjacent single-crystal silicon crystal growth, without considering local melting as the processing mechanism. The structural and electrical characterization results of the processing are used to evaluate the changes in crystal state and properties, respectively.

[0061] In one embodiment, the wafer substrate is preheated before pulsed laser irradiation, and both preheating and pulsed laser irradiation are performed in an inert protective atmosphere. After pulsed laser irradiation, the silicon-on-insulator substrate is then placed in an inert protective atmosphere at a temperature not exceeding [value missing]. The temperature is reduced to room temperature at a decreasing rate. The inert protective atmosphere may include nitrogen or argon.

[0062] Figure 3 The structure shown places the preheating direction of the sample stage 200 and the incident direction of the pulsed laser on opposite sides of the substrate structure 100. This spatial relationship facilitates the input of pulsed laser energy from one side of the first single-crystal silicon layer 110 to the buried interface after the initial thermal state has been established.

[0063] Figure 3 The energy transfer path is shown when preheating is used, and laser treatment causes recrystallization of the buried amorphous interface. Figure 4 The product structure shows the formation of a crystalline silicon interface region after processing.

[0064] See Figure 4 The processed substrate structure 100 includes a supporting substrate 150, a buried oxide layer 140 on the supporting substrate 150, and a top silicon layer on the buried oxide layer 140. The top silicon layer includes a second single-crystal silicon layer 130, a crystalline silicon interface region 160, and a first single-crystal silicon layer 110 in a direction away from the buried oxide layer 140.

[0065] The crystalline silicon interface region 160 is located at the surface activation bonding interface of the first monocrystalline silicon layer 110 and the second monocrystalline silicon layer 130. This location corresponds to the amorphous silicon interface layer before processing, and forms the crystalline silicon interface region 160 after pulsed laser processing.

[0066] One side of the crystalline silicon interface region 160 is adjacent to the first single-crystal silicon layer 110, and the other side is adjacent to the second single-crystal silicon layer 130. This region is used to characterize the position where the interface changes from an amorphous structure to a crystalline structure before and after treatment, and does not limit a specific crystal orientation relationship.

[0067] Compared to the state before treatment where an amorphous silicon interface layer was present, the amorphous structure at the corresponding position in the crystalline silicon interface region 160 was reduced. The carrier scattering and trapping caused by the amorphous structure were thus reduced, which is beneficial for improving the electrical performance of the top silicon layer.

[0068] The thickness of the amorphous silicon interface layer before the formation of the crystalline silicon interface region 160 can be... ,For example . Figure 4 The interface area after processing is directly represented, so the amorphous silicon interface layer before processing is no longer drawn.

[0069] The total thickness of the top silicon layer is greater than and not greater than The thickness of the first single-crystal silicon layer 110 is The first single-crystal silicon layer 110 and the second single-crystal silicon layer 130 are located on both sides of the crystalline silicon interface region 160, respectively. The thickness of the second single-crystal silicon layer 130 is, for example, approximately... The thickness of the buried oxide layer 140 can be approximately... It is located between the top silicon layer and the supporting substrate 150.

[0070] Figure 4 The thickness of the crystalline silicon interface region 160 is schematically magnified to show the location of this region. Figure 4 The relative dimensions in the text do not represent the actual size ratio of each layer.

[0071] Figure 4 The boundary lines in the diagram are used to distinguish the schematic locations of the first single-crystal silicon layer 110, the crystalline silicon interface region 160, and the second single-crystal silicon layer 130. The boundary lines in the diagram do not indicate the presence of additional material layers or specific crystal orientation discontinuities at the corresponding locations.

[0072] The crystalline silicon interface region 160 is formed by recrystallization of the untreated amorphous silicon interface layer using a pulsed laser. The optical penetration depth of the pulsed laser forming the crystalline silicon interface region in the monocrystalline silicon is greater than the embedding depth of the amorphous silicon interface layer in the top silicon layer, allowing the pulsed laser to reach and be absorbed by the amorphous silicon interface layer.

[0073] Figure 4 The electrical properties of the top silicon layer of the substrate shown can be characterized by electron mobility and minority carrier lifetime. These two parameters are used to evaluate the performance recovery after laser treatment and are not considered as the lower limit of the performance of the product in this example.

[0074] X-ray diffraction (XRD) was used to compare the integrated intensities of the Si(111) diffraction peaks of the processed sample and the original single-crystal silicon reference sample, and the ratio of the integrated intensities was used as the evaluation caliber for "XRD crystallinity" in Table 2. Electron mobility was measured using the Hall effect test, and minority carrier lifetime was measured using the surface photovoltage (SPV) method. The XRD integrated intensity ratio and electrical parameters reflect changes in the sample before and after processing, but are not directly equivalent to evidence that the nanoscale interface has been completely single-crystalized or is continuous with the lattices on both sides.

[0075] The crystalline silicon interface region 160 corresponds to the interface position after laser treatment, and the top silicon layer is retained between the buried oxide layer 140 and the incident surface. Figure 5 This illustrates a scanning method that extends localized laser irradiation to the area to be processed on the wafer surface.

[0076] See Figure 5 The multiple dashed circular outlines represent the laser irradiation areas sequentially formed on the surface of the first single-crystal silicon layer 110 by the pulsed laser, and the solid arrows indicate the scanning direction. The intersection of adjacent circular outlines indicates partial overlap between adjacent laser irradiation areas. This indicates the diameter of the light spot.

[0077] As the pulsed laser moves along the scanning direction, multiple irradiation areas sequentially cover the surface of the first single-crystal silicon layer 110. The buried interface beneath each irradiation area is treated by the pulsed laser during the scanning process.

[0078] When adjacent laser irradiation areas partially overlap, the same surface location can be repeatedly irradiated during adjacent pulses. This overlap reduces the unprocessed interval between adjacent spots and improves the continuous coverage along the scanning path.

[0079] Partial overlap of laser spot sizes between adjacent pulses means that the spots formed by adjacent pulses have overlapping areas, but are not completely identical. The degree of overlap along the scanning direction is expressed as a linear overlap rate. The scanning speed is denoted as... The diameter of the light spot is denoted as (usually adopted) (The spot diameter is defined by the type), and the pulse frequency is denoted as... , correspond Figure 5 In Under the conditions of uniform scanning speed, fixed spot diameter, and fixed pulse frequency, the center-to-center distance between adjacent pulse spots is... The linear overlap rate satisfies .when by express, by express, by When indicating, correspond This indicates that adjacent pulse spots partially overlap.

[0080] The diameter of the light spot can be ,For example The pulse frequency can be The scanning speed can be Selection of the inner bonding spot diameter. All parameters must meet the following requirements. Only when adjacent pulse spots overlap can there be a partial overlap condition; any combination within the range does not necessarily satisfy the condition of partial overlap.

[0081] when , , At that time, the center-to-center distance between adjacent pulse spots is The linear overlap rate is Overlap rate correspond ;Keep and At that time, the corresponding scanning speed is This parameter relationship is a selected parameter relationship calculated according to a formula, and the example uses... correspond .

[0082] Before the pulsed laser is incident on the first single-crystal silicon layer 110, a homogenizing system can be used to homogenize the pulsed laser, so that the pulsed laser forms a light spot with uniform energy distribution on the surface of the first single-crystal silicon layer 110. The homogenizing process is used to reduce the energy difference between different positions within the same light spot.

[0083] Uniform beam control controls the energy distribution within a single beam spot, while partial overlap controls the spatial connection between adjacent beam spots. The combination of these two methods improves the consistency of laser treatment received at the burial interface along the scanning path.

[0084] As the laser spot moves along the surface of the first single-crystal silicon layer 110, the buried interfaces corresponding to each irradiated area are sequentially treated by pulsed laser. When adjacent irradiated areas partially overlap, the interface treatment areas are continuously connected along the scanning direction.

[0085] Pulsed lasers can scan along a predetermined path to cover the area to be processed. The scanning path can be determined based on the wafer size, spot size, and processing range.

[0086] Figure 5 The scanning method shown extends the local processing of a single spot into a continuous in-plane processing process. The uniformity of the in-plane processing is affected by factors such as homogenization, spot size, pulse frequency, and scanning speed.

[0087] Examples and Comparative Examples Examples and comparative experiments were conducted using wafer substrates with the same layered structure. The wafer substrate was... The thickness of the first single-crystal silicon layer and the second single-crystal silicon layer on the silicon-on-insulator substrate is approximately [missing information]. The thickness of the amorphous silicon interface layer between the two is approximately The thickness of the buried oxygen layer is approximately The resistivity of both the first and second monocrystalline silicon layers is... .

[0088] All sample groups were preheated under the same conditions, with the sample stage heated to [temperature missing]. The wafer substrate is then preheated. After preheating, a pulsed laser is applied to ensure that the interface has the same initial thermal state as before receiving the pulsed laser.

[0089] The laser beam is formed after being processed by the homogenizing system. Light spot, pulse frequency is The pulse width is The single-pulse energy density is The scanning speed is The light spot scans along the surface of the first single-crystal silicon layer, and the linear overlap rate of adjacent pulse spots along the scanning direction is... After processing, the sample was cooled to room temperature in an inert protective atmosphere.

[0090] Example 1 Example 1 uses a wavelength of The pulsed laser is a neodymium-doped yttrium aluminum garnet (Nd:YAG) Q-switched laser. The thickness of the first single-crystal silicon layer is approximately... , The optical penetration depth of the laser is greater than this thickness.

[0091] After the pulsed laser passes through the first monocrystalline silicon layer, it reaches the amorphous silicon interface layer. The amorphous silicon interface layer absorbs this wavelength more readily than the first monocrystalline silicon layer. Upon absorbing the laser energy, the amorphous silicon interface layer recrystallizes and forms a crystalline silicon interface region.

[0092] After processing in Example 1, the crystallinity was characterized using XRD, Hall effect, and SPV testing methods. The XRD crystallinity was... Electron mobility The minority carrier lifetime is .

[0093] Example 2 Example 2 uses a wavelength of The pulsed laser used in this example had the same preheating, pulse width, energy density, and scanning conditions as in Example 1. The thickness of the first single-crystal silicon layer was approximately... wafer substrate.

[0094] When the pulsed laser reaches the amorphous silicon interface layer, it is absorbed by the interface, causing recrystallization. After treatment, a crystalline silicon interface region at the same layer level as in Example 1 is obtained.

[0095] The XRD crystallinity of Example 2 was Electron mobility The minority carrier lifetime is These indicators are higher than the corresponding results for the untreated sample after surface activation bonding.

[0096] Example 3 Example 3 uses a wavelength of The pulsed laser used was an optical parametric oscillator (OPO) laser. Other processing conditions were the same as in Example 1.

[0097] The optical penetration depth of the pulsed laser in the first single-crystal silicon layer is greater than approximately The laser energy can reach the amorphous silicon interface layer. The amorphous silicon interface layer recrystallizes after absorbing the laser energy.

[0098] The XRD crystallinity of Example 3 was Electron mobility The minority carrier lifetime is These indicators are higher than the corresponding results for the untreated sample after surface activation bonding.

[0099] Comparative Example 1 Comparative Example 1 uses a wavelength of The Xenon Chloride (XeCl) excimer laser was used, and other processing conditions were the same as in Example 1. The optical penetration depth of laser light in single-crystal silicon is less than approximately The thickness of the first single-crystal silicon layer.

[0100] When the laser beam is incident on the surface of the first single-crystal silicon layer, it is mainly absorbed in the region near the surface, and less energy reaches the amorphous silicon interface layer. Therefore, the degree of interface recrystallization under this condition is lower than that in Example 1.

[0101] The XRD crystallinity of Comparative Example 1 is Electron mobility The minority carrier lifetime is The improvement in this set of data was significantly lower than that of the others. , and Example.

[0102] Comparative Example 2 Comparative Example 2 uses a wavelength of The Nd:YAG fundamental frequency laser was used, and other processing conditions were the same as in Example 1. The laser can penetrate the first monocrystalline silicon layer to reach the amorphous silicon interface layer.

[0103] amorphous silicon The absorption capacity of laser light is lower than that of [other materials / materials]. Due to the limited absorption capacity of the laser wavelength, the laser energy reaching the interface is difficult for the amorphous silicon interface layer to fully absorb. Therefore, under these conditions, the recrystallization energy obtained at the interface is lower than that in Example 1.

[0104] The XRD crystallinity of Comparative Example 2 is Electron mobility The minority carrier lifetime is The improvement in this set of data was less than... , and Example.

[0105] Reference sample and untreated sample The XRD crystallinity of the original single-crystal silicon reference sample is Electron mobility The minority carrier lifetime is approximately The XRD crystallinity of the untreated sample after surface activation bonding was... Electron mobility The minority carrier lifetime is .

[0106] Examples 1 to 3 respectively adopted , and Pulsed lasers were used to process samples with the same structure. The XRD crystallinity, electron mobility, and minority carrier lifetime of the processed samples were higher than those of the unprocessed samples. The relationship between wavelength and penetration depth needs to be determined in conjunction with the actual optical conditions of each group.

[0107] Comparative Example 1 is mainly limited by The optical penetration depth of the laser in the first single-crystal silicon layer, as shown in Comparative Example 2, is mainly limited by the amorphous silicon interface layer. Laser absorption capacity. Two comparative examples illustrate from different perspectives that propagation conditions and interface absorption conditions need to be considered simultaneously.

[0108] Under the conditions of this set of experiments, The XRD crystallinity of the example is Electron mobility The minority carrier lifetime is This set of data is higher than and The example is significantly better than the two comparative examples.

[0109] Compared with the untreated sample after surface activation bonding, The XRD crystallinity of the embodiment is determined by Increase to Electron mobility from Increase to The minority carrier lifetime is Increase to Based on the original single-crystal silicon reference sample, the electron mobility recovery rate is approximately... The minority carrier lifetime recovery rate is It is used to characterize the recovery of electrical properties after laser treatment.

[0110] and Comparative examples were used to compare propagation conditions for shorter wavelengths and interface absorption conditions for longer wavelengths. The effects of the examples and comparative examples were compared using the same preheating and scanning parameters, and the evaluation conclusions are limited to the samples and process conditions listed in Table 2.

[0111] The results are shown in Table 2. The processing results for different wavelengths can be directly compared.

[0112] Table 2. Process conditions and test results for the examples and comparative examples.

[0113] Electron mobility recovery rate is calculated as the ratio of the electron mobility of the test sample to that of the original single-crystal silicon reference sample. Minority carrier lifetime recovery rate is calculated as the ratio of the minority carrier lifetime of the test sample to that of the original single-crystal silicon reference sample.

[0114] Table 2 shows that, , and Each group achieved higher test results than the untreated sample under the same preheating and scanning conditions. Differences exist in the processing results for different wavelengths, requiring analysis in conjunction with the propagation of the coating layer and interface absorption conditions.

[0115] Experimental results show that pulsed laser treatment is related to changes in the crystallization state and electrical properties of the sample. For buried amorphous silicon interface layers, it is necessary to combine capping layer propagation, interface absorption, and pulse energy to determine whether recrystallization conditions can be met. Preheating and scanning parameters are used to adjust the specific treatment process.

[0116] For silicon-on-insulator substrates with surface-activated bonding interfaces, laser parameters can be selected based on the thickness of the overlying monocrystalline silicon layer and the target interface location. The treated substrate can be used for the fabrication of substrates for radio frequency devices, sensors, or three-dimensional integrated circuits; the specific applicability is determined in conjunction with the electrical requirements of the respective devices.

[0117] This application is not limited to the listed embodiments. Those skilled in the art can modify the specific embodiments or make equivalent substitutions for some technical features without departing from the technical concept of this application. The scope of protection of this application is determined by the claims.

Claims

1. A method for preparing a silicon-on-insulator substrate, characterized in that, include: A wafer substrate to be processed is provided, the wafer substrate including a support substrate, a buried oxide layer on the support substrate, and a top silicon layer on the buried oxide layer, the top silicon layer including a first single crystal silicon layer, an amorphous silicon interface layer, and a second single crystal silicon layer, the amorphous silicon interface layer being formed by surface activation bonding of the first single crystal silicon layer and the second single crystal silicon layer; A pulsed laser is applied to the wafer substrate, the wavelength of which makes the optical penetration depth of the pulsed laser in the single-crystal silicon greater than the embedding depth of the amorphous silicon interface layer in the top silicon layer. The pulsed laser reaches the amorphous silicon interface layer and is absorbed by the amorphous silicon interface layer, causing the amorphous silicon interface layer to recrystallize, thus obtaining a silicon-on-insulator substrate.

2. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The wavelength of the pulsed laser is .

3. The method for preparing a silicon-on-insulator substrate according to claim 2, characterized in that, The wavelength of the pulsed laser is .

4. The method for preparing a silicon-on-insulator substrate according to claim 3, characterized in that, The wafer substrate is preheated before being irradiated by the pulsed laser, and the preheating temperature is [temperature missing]. .

5. The method for preparing a silicon-on-insulator substrate according to claim 4, characterized in that, The preheating temperature is .

6. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The pulse width of the pulsed laser is .

7. The method for preparing a silicon-on-insulator substrate according to claim 6, characterized in that, The pulse width of the pulsed laser is .

8. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The single-pulse energy density of the pulsed laser is .

9. The method for preparing a silicon-on-insulator substrate according to claim 8, characterized in that, The single-pulse energy density of the pulsed laser is .

10. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The pulsed laser irradiation employs a spot scanning method, and the spot portions of adjacent laser pulses overlap.

11. The method for preparing a silicon-on-insulator substrate according to claim 10, characterized in that, The pulsed laser undergoes homogenization before being incident on the first single-crystal silicon layer, forming a light spot with uniform energy distribution on the surface of the first single-crystal silicon layer.

12. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The wafer substrate is preheated before being irradiated by the pulsed laser. The preheating and the pulsed laser irradiation are carried out in an inert protective atmosphere; After being irradiated by the pulsed laser, the silicon-on-insulator substrate is placed in the inert protective atmosphere at a temperature not exceeding [amount missing]. Cooled to room temperature at a cooling rate; The inert protective atmosphere includes nitrogen or argon.

13. The method for preparing a silicon-on-insulator substrate according to claim 2, characterized in that, The thickness of the amorphous silicon interface layer is .

14. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The total thickness of the top silicon layer is greater than and not greater than The thickness of the first single-crystal silicon layer is .

15. A silicon-on-insulator substrate, characterized in that, It includes a supporting substrate, a buried oxide layer on the supporting substrate, and a top silicon layer on the buried oxide layer, wherein the top silicon layer includes a first single-crystal silicon layer, a crystalline silicon interface region, and a second single-crystal silicon layer; The crystalline silicon interface region is formed by recrystallization of an amorphous silicon interface layer formed by surface activation bonding of the first monocrystalline silicon layer and the second monocrystalline silicon layer through pulsed laser irradiation. When the crystalline silicon interface region is formed, the wavelength of the pulsed laser makes the optical penetration depth of the pulsed laser in the single crystal silicon greater than the embedding depth of the amorphous silicon interface layer in the top silicon layer. The pulsed laser reaches the amorphous silicon interface layer and is absorbed by the amorphous silicon interface layer. The thickness of the amorphous silicon interface layer is .

16. The silicon-on-insulator substrate according to claim 15, characterized in that, The thickness of the amorphous silicon interface layer is .

17. The silicon-on-insulator substrate according to claim 15, characterized in that, The total thickness of the top silicon layer is greater than and not greater than The thickness of the first single-crystal silicon layer is .

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