A substrate processing technique for reducing noise in radio frequency devices

Abstract

The present application relates to the technical field of semiconductor manufacturing, in particular to a substrate processing technology for reducing noise of radio frequency devices, which combines plasma annealing and gradient doping to repair lattice defects and optimize substrate resistivity through accurate doping to reduce noise in the process of carrier migration; a composite passivation layer realizes double effects of interface state suppression and parasitic parameter control, the dielectric loss tangent value is controlled below 0.001 to avoid parasitic noise generation under high frequency; the whole process temperature is below 900 DEG C, which does not exceed the heat resistance threshold of radio frequency device substrate; the noise processing effect on radio frequency devices is achieved, and the problem that noise processing on radio frequency devices by only a single process cannot simultaneously solve composite noise caused by lattice defects, impurity residues and interface states is solved; after simultaneous processing, the matching degree of resistivity and dielectric constant of the substrate is insufficient, parasitic capacitance is easily generated under high frequency, and noise is even aggravated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically a substrate processing technology for reducing noise in radio frequency devices. Background Technology

[0002] The noise performance of radio frequency devices is one of their core indicators. Noise mainly comes from the device itself and the semiconductor substrate that supports the device. Free carriers in the substrate will generate parasitic coupling, eddy current loss and substrate noise under the action of high frequency signals, which will seriously degrade radio frequency performance.

[0003] Currently, most substrate processing technologies employ a single process, such as ion implantation doping, surface polishing, or dielectric layer deposition, to reduce noise in radio frequency devices.

[0004] However, noise reduction of RF devices using only a single process and noise source optimization cannot simultaneously solve the combined noise caused by lattice defects, impurity residues, and interface states. At the same time, the resistivity and dielectric constant of the substrate after treatment are not well matched, and parasitic capacitance is easily generated at high frequencies, which exacerbates the noise problem. Therefore, a substrate treatment technology to reduce the noise of RF devices is proposed to address the above problems. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art and solve at least one of the technical problems mentioned in the background art, the present invention proposes a substrate processing technology for reducing the noise of radio frequency devices.

[0006] The technical solution adopted by this invention to solve its technical problem is: a substrate processing technology for reducing noise in radio frequency devices, comprising the following steps: S1. Plasma-assisted annealing defect repair: The substrate is placed in a vacuum annealing furnace and evacuated to a vacuum level of 1×10⁻⁶. -5 Pa, heat to 800-900℃ and hold for 30 min, introduce argon-hydrogen mixed gas, and start the radio frequency plasma generator to process for 60-90 min; S2. Gradient doping and impurity purification: Maintain the substrate temperature at 600-700℃, implant boron ions to form a gradient doped layer, and then perform secondary oxygen annealing at 750℃ for 40 minutes. S3. Surface Microcavity Array Etching and Passivation: On the substrate surface, a periodic or non-periodic array of micron / submicron blind holes is formed using photolithography and dry / wet etching techniques; subsequently, the etched surface, including the inner walls of the microcavities, is thermally oxidized or a high-quality dielectric layer is deposited to form a dense passivation layer. S4. Gradient doped energy trap layer fabrication: After forming the surface microcavity structure, multiple ion implantation processes with different energies are used to implant the same type of dopant from the substrate surface into the bulk. The gradient doped energy trap layer and the surface microcavity array are spatially staggered and overlapped. S5. Dielectric layer composite modification: 200-300nm silicon nitride dielectric layer is sputtered by magnetron sputtering, and finally treated with ultraviolet ozone for 15 minutes.

[0007] Preferably, the plasma generator in S1 has a power of 300-400W and a frequency of 13.56MHz.

[0008] Preferably, the boron ion doping concentration in S1 is 1×10⁻⁶. 16 -1×10 17 cm -3 The injection depth is 1-5 μm.

[0009] Preferably, the microcavity array in S3 is a blind hole array with a depth of 1-10 micrometers and a diameter of 0.1-2 micrometers.

[0010] Preferably, the passivation treatment in S3 is a thermal oxidation growth of a SiO2 layer or a chemical vapor deposition of a SiN layer.

[0011] Preferably, the gradient-doped energy trap layer in S4 is formed by multiple ion implantation processes with different energies, and the implanted impurity type is the same as the substrate conductivity type.

[0012] Preferably, in S5, the magnetron sputtering deposition power is 200-250W and the argon pressure is 0.5Pa.

[0013] Preferably, the ultraviolet ozone treatment wavelength in S5 is 254nm and the power is 100W.

[0014] Preferably, the substrate is a silicon substrate, a gallium nitride substrate, or a silicon carbide substrate, and the resistivity of the substrate after treatment is controlled at 1000-5000 Ω·cm, and the dielectric loss tangent is ≤0.001.

[0015] The advantages of this invention are: This invention employs a combination of plasma annealing and gradient doping to repair lattice defects and optimize substrate resistivity through precise doping, reducing noise during carrier migration. The composite passivation layer achieves dual effects of interface state suppression and parasitic parameter control, keeping the dielectric loss tangent below 0.001 to avoid parasitic noise at high frequencies. The entire process temperature is below 900℃, which does not exceed the heat resistance threshold of the RF device substrate. This invention achieves noise reduction for RF devices, solving the problem of using only a single process for noise reduction. While noise source optimization cannot simultaneously address the combined noise caused by lattice defects, impurity residues, and interface states, the problem of insufficient matching between the resistivity and dielectric constant of the treated substrate, leading to parasitic capacitance at high frequencies and exacerbating noise issues, is addressed. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the processing technology of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The following is in conjunction with the appendix Figure 1 This application will be described in further detail. This application discloses a substrate processing technique for reducing noise in radio frequency devices, including the following steps: S1. Plasma-assisted annealing defect repair: The substrate is placed in a vacuum annealing furnace and evacuated to a vacuum level of 1×10⁻⁶. -5 Pa, heat to 800-900℃ and hold for 30 min, introduce argon-hydrogen mixed gas, and start the radio frequency plasma generator to process for 60-90 min; S2. Gradient doping and impurity purification: Maintain the substrate temperature at 600-700℃, implant boron ions to form a gradient doped layer, and then perform secondary oxygen annealing at 750℃ for 40 minutes. S3. Surface Microcavity Array Etching and Passivation: On the substrate surface, a periodic or non-periodic array of micron / submicron blind holes is formed using photolithography and dry / wet etching techniques; subsequently, the etched surface, including the inner walls of the microcavities, is thermally oxidized or a high-quality dielectric layer is deposited to form a dense passivation layer. S4. Gradient doped energy trap layer fabrication: After forming the surface microcavity structure, multiple ion implantation processes with different energies are used to implant the same type of dopant from the substrate surface into the bulk. The gradient doped energy trap layer and the surface microcavity array are spatially staggered and overlapped. S5. Dielectric layer composite modification: 200-300nm silicon nitride dielectric layer is sputtered by magnetron sputtering, and finally treated with ultraviolet ozone for 15 minutes.

[0020] The plasma generator in S1 has a power of 300-400W and a frequency of 13.56MHz; the boron ion doping concentration is 1×10⁻⁶. 16 -1×10 17 cm -3 The implantation depth is 1-5 μm. During operation, a standard P-type single-crystal silicon substrate is selected and subjected to standard RCA cleaning to remove surface organic matter, metal particles, and the native oxide layer. The cleaned silicon substrate is then placed on the sample stage of a high-vacuum annealing furnace. The furnace cavity is closed, and the vacuum pump group is started to evacuate the furnace to a background vacuum level better than 1×10⁻⁶. -5 Pa; subsequently, the substrate temperature was raised to 850°C at a controlled rate and maintained at this temperature for 30 minutes; this step aims to preheat the substrate, making its temperature uniform and preparing it for subsequent processing; the temperature was then maintained at 850°C, and a mixture of argon and hydrogen gas in a 9:1 volume ratio was introduced into the furnace chamber to stabilize the chamber pressure at approximately 1.0 Pa. A 13.56 MHz radio frequency plasma generator was activated, and the power was set to 350 W to generate argon-hydrogen plasma. The processing lasted for 75 minutes; at high temperatures, the active hydrogen atoms in the hydrogen plasma can effectively diffuse to the near-surface region of the substrate, combining with dangling bonds, dislocations, and other defects in the silicon lattice to achieve passivation repair; the argon plasma provides moderate physical bombardment, which helps to activate the surface and promote hydrogen penetration. This step reduces the background defect density at the bulk material level. These defects are important sources of 1 / f noise and generation-recombination noise; the energy of the plasma excites the rearrangement of substrate lattice atoms, repairing dislocations, vacancies, and other defects generated during the preparation process, and reducing carrier scattering sites.

[0021] After completing S1, the substrate temperature was lowered to 650°C and stabilized. Boron ions were then implanted into the substrate using an ion implanter; the implantation energy and dose were designed to achieve a peak concentration of approximately 5 × 10⁻⁶ ions within a depth range of 1–5 μm below the surface. 16 cm -3A relatively uniformly distributed P-type doped layer is implanted; this implanted layer provides the basis for the subsequent formation of a finer gradient structure; after implantation, the substrate temperature is raised to 750°C in an environment with pure oxygen and annealed for 40 minutes; this annealing has a dual purpose: first, to activate the implanted boron ions and allow them to enter the lattice substitution sites; second, to use oxygen to grow a thin layer of high-quality silicon dioxide on the substrate surface. This oxide layer can absorb some fast-diffusing metal impurities on and near the substrate surface, playing a gettering and purification role, and further reducing potential noise generation centers.

[0022] The microcavity array in S3 is a blind via array with a depth of 1-10 micrometers and a diameter of 0.1-2 micrometers. Passivation in S3 involves thermal oxidation to grow a SiO2 layer or chemical vapor deposition of a SiN layer. Photoresist is spin-coated onto the substrate surface treated in S2, and a periodic circular dot pattern is defined using photolithography. A dry etching process is then used to precisely etch the blind via array. Specific parameters can be set as follows: depth 2.0 micrometers, diameter 0.8 micrometers, and center-to-center spacing between adjacent blind vias 2.5 micrometers. This array structure is key to disrupting surface parasitic waveguide modes and increasing the effective surface area. After etching, the photoresist is removed and the area is cleaned. Subsequently, thermal oxidation is performed in 950°C moist oxygen gas to grow a SiO2 layer approximately 30 nm thick. The thermal oxidation process ensures that the SiO2 layer not only covers the flat surface but also completely covers the inner walls and bottom of each microcavity. This dense dielectric layer effectively passivates the surface states and dangling bonds generated during etching, preventing them from becoming charge traps and noise sources, while also providing a stable interface for subsequent processes.

[0023] In S4, the gradient-doped energy trap layer is formed through multiple ion implantation processes at different energies, with the implanted impurity type matching the substrate's conductivity type. During operation, multiple boron ion implantations are performed on the substrate, which already has a microcavity structure and a surface oxide layer. The implantation scheme is designed with three energy steps; for example: low energy 10 keV / dose 1×10 13 cm -2 Medium energy 50 keV / dose 3×10 12 cm -2 High energy 120 keV / dose 1×10 12 cm -2 .

[0024] After multiple implantation stacks, a region extending approximately 1.5 micrometers from the lower interface of the surface oxide layer into the substrate is formed, where the doping concentration of P decreases gradually from the surface inwards. +The energy trap layer spatially overlaps with the microcavity array formed by S3. The high-concentration near-surface region generates a built-in electric field gradient, which, like a funnel, guides the minority carriers randomly diffused within the substrate to the area beneath the microcavities. The large surface area and defect states on the sidewalls and bottom of the microcavities cause these guided carriers to recombine rapidly, resulting in a clean region with low free carrier concentration beneath the active region of the RF device. In S5, magnetron sputtering deposition power is 200-250W, argon pressure is 0.5Pa; ultraviolet ozone treatment wavelength is 254nm, power is 100W, substrate is silicon, gallium nitride, or silicon carbide substrate, substrate resistivity after treatment is controlled at 1000-5000Ω·cm, dielectric loss tangent ≤0.001; during operation, magnetron sputtering equipment is used, with 99.999% pure silicon as the target material, and a silicon nitride dielectric film is deposited on the substrate surface in a mixed atmosphere of high-purity nitrogen and argon; process parameters are set as follows: sputtering power 220 W, chamber argon working pressure 0.5 Pa, film thickness controlled at 250 nm; this SiN x The layer is dense and has good insulation properties, providing excellent surface protection and passivation. Finally, the deposited SiN... x The substrate of the layer was treated in an ultraviolet ozone cleaning device for 15 minutes. The ultraviolet wavelength was 254 nm, and the lamp power was 100 W. The high-energy ultraviolet light excited oxygen to produce ozone and atomic oxygen, which could effectively decompose and remove trace organic pollutants that might remain on the surface of the dielectric layer. At the same time, ultraviolet photons had a certain densification effect on the surface of the dielectric layer, which helped to reduce dielectric loss. This step ensured the final chemical cleanliness and high quality of the substrate surface and the dielectric layer.

[0025] Working principle: A standard P-type single-crystal silicon substrate is selected and cleaned using RCA standard cleaning to remove surface organic matter, metal particles, and the natural oxide layer, ensuring a clean substrate surface; then the cleaned substrate is placed in the sample stage of a high-vacuum annealing furnace, the furnace cavity is closed, and a vacuum of 1×10⁻⁶ is applied. -5Above Pa, the temperature is raised to 850℃ at a controllable rate and held for 30 minutes to ensure uniform substrate temperature, preparing for subsequent processing. While maintaining the 850℃ temperature, an argon-hydrogen mixture (9:1 volume ratio) is introduced into the furnace to stabilize the chamber pressure to 1.0 Pa. A 13.56MHz RF plasma generator is activated at 350W to generate argon-hydrogen plasma, which is then continuously processed for 75 minutes. This allows active hydrogen atoms to diffuse to the near-surface of the substrate, combining with lattice dangling bonds and dislocations to achieve passivation repair. The argon plasma physically bombards and activates the surface, promoting hydrogen permeation and simultaneously exciting lattice atomic rearrangement, repairing defects such as dislocations and vacancies, and reducing carrier scattering sites. The substrate temperature is then lowered to 650℃ and stabilized. Boron ions are implanted into the substrate using an ion implanter, with controlled implantation energy and dosage, to achieve a peak concentration of approximately 5 × 10⁻⁵ ions at a depth of 1-5 μm below the surface. 16 cm -3 A uniform P-type doped layer was formed; after implantation, pure oxygen was introduced, and the substrate temperature was raised to 750℃ and held for 40 minutes. This activated boron ions, allowing them to enter lattice substitution sites. Simultaneously, a thin layer of high-quality silicon dioxide was grown on the substrate surface to remove fast-diffusion metal impurities from the surface and near the surface, achieving getter purification. Photoresist was spin-coated onto the S2-treated substrate surface, and a periodic circular dot pattern was defined using photolithography. A dry etching process was used to etch a blind-hole microcavity array with a depth of 2.0 μm, a diameter of 0.8 μm, and an adjacent center-to-center spacing of 2.5 μm, disrupting surface parasitic waveguide modes and increasing the effective surface area. After etching, the photoresist was removed and the substrate was cleaned. The substrate was placed in 950℃ humid oxygen gas to grow a 30 nm thick SiO2 layer, ensuring the oxide layer completely covered the flat surface of the substrate and the inner walls and bottom of the microcavities, passivating the surface states and dangling bonds generated by etching. Three boron ion implantations with different energies were performed on the substrate with the microcavity structure and oxide layer. Specifically, the implantation scheme was: low energy 10 keV / Dosage 1×10 13 cm -2 Medium energy 50keV / dose 3×10 12 cm -2 High energy 120keV / dose 1×10 12 cm -2 After multiple implantation stackings, a P-type doping layer with a decreasing doping concentration from the surface to the interior forms in a region approximately 1.5 μm from the lower oxide layer interface to the substrate interior. +The energy trap layer overlaps with the microcavity array, guiding minority carriers to the area below the microcavity via a built-in electric field gradient. The large surface area of ​​the microcavity promotes rapid carrier recombination, forming a clean region with low free carrier concentration. Then, using magnetron sputtering with 99.999% pure silicon as the target, a silicon nitride dielectric film is deposited on the substrate surface in a high-purity nitrogen-argon mixed atmosphere. The sputtering power is set to 220W, the argon pressure in the chamber to 0.5Pa, and the film thickness to 250nm, achieving surface protection and passivation. The deposited substrate is then placed in an ultraviolet ozone cleaning device with an ultraviolet wavelength of 254nm and a lamp power of 100W for 15 minutes. High-energy ultraviolet light excites oxygen to produce ozone and atomic oxygen, removing residual organic contaminants from the dielectric layer surface and simultaneously densifying the dielectric layer to reduce dielectric loss. Finally, the substrate resistivity is controlled at 1000-5000Ω·cm, and the dielectric loss tangent is ≤0.001, meeting the low-noise operation requirements of RF devices.

[0026] This embodiment fully demonstrates a multi-dimensional and synergistic substrate processing flow, from bulk defect repair, near-surface cleaning, and geometric modification to functional layer preparation and final surface treatment. By precisely controlling the process parameters at each step, the goal of significantly reducing the substrate noise of radio frequency devices from a physical source is ultimately achieved. Those skilled in the art can adaptively adjust the parameters within the framework defined by the above claims according to the actual substrate material and device requirements.

[0027] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A substrate processing technique for reducing noise in radio frequency devices, characterized in that: Includes the following steps: S1. Plasma-assisted annealing defect repair: The substrate is placed in a vacuum annealing furnace and evacuated to a vacuum level of 1×10⁻⁶. -5 Pa, heat to 800-900℃ and hold for 30 min, introduce argon-hydrogen mixed gas, and start the radio frequency plasma generator to process for 60-90 min; S2. Gradient doping and impurity purification: Maintain the substrate temperature at 600-700℃, implant boron ions to form a gradient doped layer, and then perform secondary oxygen annealing at 750℃ for 40 minutes. S3. Surface microcavity array etching and passivation: On the substrate surface, a micron / submicron level blind hole array is formed by using photolithography and dry / wet etching techniques. Subsequently, the etched surface, including the inner wall of the microcavity, is thermally oxidized or a high-quality dielectric layer is deposited to form a dense passivation layer. S4. Gradient doped energy trap layer fabrication: After forming the surface microcavity structure, multiple ion implantation processes with different energies are used to implant the same type of dopant from the substrate surface into the bulk. The gradient doped energy trap layer and the surface microcavity array are spatially staggered and overlapped. S5. Dielectric layer composite modification: 200-300nm silicon nitride dielectric layer is sputtered by magnetron sputtering, and finally treated with ultraviolet ozone for 15 minutes.

2. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The plasma generator in S1 has a power of 300-400W and a frequency of 13.56MHz.

3. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The boron ion doping concentration in S1 is 1×10⁻⁶. 16 -1×10 17 cm -3 The injection depth is 1-5 μm.

4. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The microcavity array in S3 is a blind hole array with a depth of 1-10 micrometers and a diameter of 0.1-2 micrometers.

5. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The passivation treatment in S3 is either thermal oxidation to grow a SiO2 layer or chemical vapor deposition of a SiN layer.

6. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The gradient-doped energy trap layer in S4 is formed through multiple ion implantation processes with different energies, and the implanted impurity type is the same as the substrate conductivity type.

7. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: In the S5, the magnetron sputtering deposition power is 200-250W, and the argon pressure is 0.5Pa.

8. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The ultraviolet ozone treatment in S5 has a wavelength of 254nm and a power of 100W.

9. The substrate processing technology for reducing radio frequency device noise according to claim 1, characterized in that: The substrate is a silicon substrate, a gallium nitride substrate, or a silicon carbide substrate. After processing, the substrate resistivity is controlled at 1000-5000 Ω·cm, and the dielectric loss tangent is ≤0.001.

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