Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device, and belongs to the technical field of semiconductors. The semiconductor device manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises an active region, and the substrate is provided with an isolation groove arranged around the active region; performing self-aligned chemical bonding on an interface between the isolation groove and the active region to form a self-aligned chemical bonding layer covering the interface; and forming a device structure in the active region. The application can improve the uniformity and stability of the threshold voltage of the device, thereby improving the yield and reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] While isolation trenches can effectively define the active region, stress concentration and interface defects exist at the interface between the isolation trench and the active region, resulting in large deviations in the threshold voltage of different devices (such as MOSFETs), affecting device consistency and yield. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for fabricating a semiconductor device and a semiconductor device that can improve the uniformity and stability of the device's threshold voltage, thereby improving device yield and reliability.

[0004] Firstly, this application provides a method for fabricating a semiconductor device.

[0005] A substrate is provided, the substrate including an active region, and an isolation trench disposed around the active region in the substrate;

[0006] Self-aligned chemical bonding is performed on the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface;

[0007] The device structure is formed in the active region.

[0008] According to the semiconductor device fabrication method of this application, a self-aligned chemical bonding layer covering the interface is formed by performing self-aligned chemical bonding on the interface between the isolation trench and the active region, thereby achieving ordered passivation of the interface, reducing the interface state density and the number of trap regions, improving the uniformity and stability of the threshold voltage of the device, and improving the device yield and reliability.

[0009] According to one embodiment of this application, the step of performing self-aligned chemical bonding on the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface includes:

[0010] Self-aligned chemical bonding is performed on the interface between the isolation trench and the active region, as well as on the upper surface of the active region, to form an initial self-aligned chemical bonding layer covering the interface and the upper surface of the active region.

[0011] Remove the initial self-aligned chemical bonding layer on the upper surface of the active region to form a self-aligned chemical bonding layer covering the interface.

[0012] According to one embodiment of this application, the material of the bottom surface of the isolation trench is different from the material of the active region;

[0013] Alternatively, the material of the bottom surface of the isolation trench is the same as the material of the active region, and the method further includes covering the bottom surface of the isolation trench with a mask layer before performing self-aligned chemical bonding on the interface between the isolation trench and the active region and on the upper surface of the active region.

[0014] According to one embodiment of this application, the self-aligned chemical bonding of the interface between the isolation trench and the active region, and the upper surface of the active region, includes:

[0015] The substrate is immersed in an organic molecular precursor solution, so that the organic molecular precursor is self-aligned chemically bonded to the interface between the isolation trench and the active region and the upper surface of the active region.

[0016] According to one embodiment of this application, the active region is made of monocrystalline silicon, and the organic molecular precursor includes functional groups having silane, mercapto, or phosphonic acid groups.

[0017] According to one embodiment of this application, the substrate is immersed in the organic molecular precursor solution for 30 minutes to 24 hours; and / or,

[0018] The concentration of the organic molecule precursor solution is 0.1% to 1%; and / or,

[0019] The pH value of the organic molecule precursor solution is 5 to 9.

[0020] According to one embodiment of this application, the temperature for the self-aligned chemical bonding is room temperature to 200°C.

[0021] According to one embodiment of this application, the self-aligned chemical bonding layer comprises a self-aligned monomolecular organic layer.

[0022] According to one embodiment of this application, prior to performing self-aligned chemical bonding at the interface between the isolation trench and the active region, the method further includes:

[0023] The substrate is cleaned;

[0024] The substrate is pretreated to remove oxides from its surface.

[0025] Secondly, this application provides a semiconductor device, comprising:

[0026] A substrate, the substrate including an active region, wherein an isolation trench is provided in the substrate surrounding the active region;

[0027] A self-aligned chemical bonding layer covers the interface between the isolation trench and the active region;

[0028] The device structure is located in the active region.

[0029] According to one embodiment of this application, the self-aligned chemical bonding layer comprises a self-aligned monomolecular organic layer.

[0030] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0031] By performing self-aligned chemical bonding on the interface between the isolation trench and the active region, a self-aligned chemical bonding layer is formed covering the interface, achieving ordered passivation of the interface, reducing the interface state density and the number of traps, improving the uniformity and stability of the threshold voltage of the device, and improving the device yield and reliability.

[0032] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0033] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0034] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0035] Figure 2 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0036] Figure 3 This is a second schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0037] Figure 4 This is the third structural schematic diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0038] Figure 5 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this application. Detailed Implementation

[0039] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0040] The following description, with reference to the accompanying drawings, describes the method for fabricating a semiconductor device and the semiconductor device itself, as provided in the embodiments of this application.

[0041] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. The semiconductor device may include CMOS (Complementary Metal-Oxide-Semiconductor) devices, FinFET (Fin Field-Effect Transistor) devices, or MOS (Metal-Oxide-Semiconductor) devices, etc.

[0042] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in this application includes steps 110 to 130.

[0043] Step 110: Provide a substrate, the substrate including an active region, and an isolation trench disposed around the active region in the substrate.

[0044] like Figure 2 As shown, substrate 1 is provided first. Substrate 1 may include a monocrystalline silicon substrate, meaning that the material of substrate 1 includes monocrystalline silicon. Substrate 1 may also be an SOI (Silicon-On-Insulator) substrate. The SOI substrate may include a monocrystalline silicon substrate 11, a buried oxide layer 12, and a monocrystalline silicon layer 13, with the buried oxide layer 12 located on the monocrystalline silicon substrate 11 and the monocrystalline silicon layer 13 located on the buried oxide layer 12. The material of the buried oxide layer 12 may include silicon oxide, etc.

[0045] The substrate 1 includes an active region 10. An isolation trench 2 is formed in the substrate 1 by etching to surround the active region 10, that is, the isolation trench 2 defines the active region 10. The isolation trench 2 can be shallow trench isolation (STI).

[0046] When the substrate 1 is a monocrystalline silicon substrate, the monocrystalline silicon substrate includes an active region 10. An isolation trench 2 is etched in the monocrystalline silicon substrate to form an isolation trench 2 surrounding the active region 10, and the bottom of the isolation trench 2 is located within the monocrystalline silicon substrate. The material of the bottom surface of the isolation trench 2 is the same as the material of the active region 10, which is monocrystalline silicon.

[0047] When the substrate 1 is an SOI substrate, the single-crystal silicon layer 13 includes an active region 10. An isolation trench 2 is etched in the single-crystal silicon layer 13 to form an area surrounding the active region 10, and the isolation trench 2 penetrates the single-crystal silicon layer 13. The bottom of the isolation trench 2 is a buried oxide layer 12. The material of the bottom surface of the isolation trench 2 (such as silicon oxide) is different from the material of the active region 10 (single-crystal silicon).

[0048] In some embodiments, the substrate 1 may include a plurality of active regions 10, and isolation trenches 2 are disposed around each active region 10 to isolate the plurality of active regions 10.

[0049] In some embodiments, prior to step 120, the method for fabricating the semiconductor device further includes: forming a well region in the active region using an ion implantation process.

[0050] It should be noted that, prior to step 120, the method for fabricating the semiconductor device may also include other basic front-end process steps, which are not specifically limited here.

[0051] Step 120: Perform self-aligned chemical bonding on the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface.

[0052] In this process, the isolation trench 2 exposes the side surface of the active region 10. The interface between the isolation trench 2 and the active region 10 is the exposed side surface of the active region 10. Self-aligned chemical bonding is performed on the exposed side surface of the active region 10, and the resulting self-aligned chemical bonding layer covers the side surface of the active region 10. In other words, the self-aligned chemical bonding layer covers the interface between the isolation trench 2 and the active region 10, thereby passivating the interface between the isolation trench 2 and the active region 10, reducing the interface state density and the number of traps, reducing possible stress concentration and boundary defect problems, and improving the uniformity and stability of the threshold voltage of the subsequently formed device structure.

[0053] Since the upper surface of the active region 10 is exposed, and the materials of the upper surface and the side surface of the active region 10 are the same, a specific area of ​​the active region 10 (i.e., the upper surface of the active region 10) can be selectively pre-treated (e.g., modified using micromask technology to make the characteristics of the upper surface and the side surface of the active region 10 different) to define the self-aligned chemical bonding region (i.e., the side surface of the active region 10). This avoids performing self-aligned chemical bonding on the upper surface of the active region 10, and only performs self-aligned chemical bonding on the side surface of the active region 10, that is, only performs self-aligned chemical bonding at the interface between the isolation trench 2 and the active region 10, so as to precisely control the growth range of the self-aligned chemical bonding layer. It should be noted that other methods can also be used to perform self-aligned chemical bonding only at the interface between the isolation trench 2 and the active region 10.

[0054] When the substrate 1 includes monocrystalline silicon, the side surface of the active region 10 is a silicon surface. The silicon surface has dangling bonds, and organic molecules can react with the dangling bonds on the silicon surface to form chemical bonds, thereby forming a dense and uniform self-aligned chemical bonding layer on the silicon surface. That is, the self-aligned chemical bonding layer covers the interface between the isolation trench 2 and the active region 10, so as to passivate the interface between the isolation trench 2 and the active region 10, reduce the interface state density and the number of traps.

[0055] In some embodiments, step 120 involves performing self-aligned chemical bonding at the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface, including:

[0056] Self-aligned chemical bonding is performed on the interface between the isolation trench and the active region, as well as on the upper surface of the active region, to form an initial self-aligned chemical bonding layer covering the interface and the upper surface of the active region.

[0057] Remove the initial self-aligned chemical bonding layer on the upper surface of the active region to form a self-aligned chemical bonding layer covering the interface.

[0058] The material of the bottom surface of the isolation trench 2 can be different from that of the active region 10. For example, if the substrate 1 is an SOI substrate, the material of the bottom surface of the isolation trench 2 is silicon oxide, and the material of the active region 10 is single crystal silicon.

[0059] When the active region 10 is made of monocrystalline silicon and the bottom surface of the isolation trench 2 is not made of monocrystalline silicon, both the side and top surfaces of the active region 10 are silicon surfaces, while the bottom surface of the isolation trench 2 is not a silicon surface. Chemical bonds are formed by the reaction of organic molecules with dangling bonds on the silicon surface, resulting in a dense and uniform initial self-aligned chemical bonding layer 3 on the side and top surfaces of the active region 10. Figure 3 As shown. However, the initial self-aligned chemical bonding layer 3 on the upper surface of the active region 10 will affect the formation of the subsequent device structure. Therefore, the initial self-aligned chemical bonding layer 3 on the upper surface of the active region 10 is removed, for example, by chemical mechanical polishing, leaving only the initial self-aligned chemical bonding layer 3 on the side surface of the active region 10. The initial self-aligned chemical bonding layer 3 on the side surface of the active region 10 constitutes a self-aligned chemical bonding layer 3', that is, the self-aligned chemical bonding layer 3' only covers the interface between the isolation trench 2 and the active region 10, such as... Figure 4 As shown.

[0060] In some embodiments, the material of the bottom surface of the isolation trench 2 can be the same as the material of the active region 10. For example, if the substrate 1 is a single-crystal silicon substrate, the material of the bottom surface of the isolation trench 2 is single-crystal silicon, and the material of the active region 10 is single-crystal silicon.

[0061] Prior to the step of performing self-aligned chemical bonding on the interface between the isolation trench and the active region and on the upper surface of the active region, the method for fabricating the semiconductor device further includes covering the bottom surface of the isolation trench with a mask layer.

[0062] When the materials of the active region 10 and the bottom surface of the isolation trench 2 are both monocrystalline silicon, the side and top surfaces of the active region 10 and the bottom surface of the isolation trench 2 are also silicon surfaces. To prevent the organic molecular precursor from forming a self-aligned chemical bond with the bottom of the isolation trench 2, the bottom surface of the isolation trench 2 can be treated first, such as by covering it with a mask layer. The material of the mask layer can be silicon oxide, which is different from the material of monocrystalline silicon. A dense and uniform initial self-aligned chemical bonding layer 3 is formed on the side and top surfaces of the active region 10. Then, the initial self-aligned chemical bonding layer 3 on the top surface of the active region 10 is removed, and the initial self-aligned chemical bonding layer 3 on the side surface of the active region 10 constitutes a self-aligned chemical bonding layer 3'. It should be noted that an insulating layer will be filled into the isolation trench 2 later. The material of the mask layer is an insulating material (such as silicon oxide), so the mask layer at the bottom of the isolation trench 2 does not need to be removed.

[0063] In some embodiments, self-aligned chemical bonding is performed on the interface between the isolation trench and the active region, as well as on the upper surface of the active region, including:

[0064] The substrate is immersed in an organic molecular precursor solution, allowing the organic molecular precursor to undergo self-aligned chemical bonding with the interface between the isolation trench and the active region, as well as the upper surface of the active region.

[0065] Using self-assembled monolayers (SAM) technology, substrate 1 is completely immersed in an organic molecular precursor solution to passivate the side and top surfaces of the active region 10. Organic molecules spontaneously align on the side and top surfaces of the active region 10 to form stable monomolecular ordered films (i.e., the initial self-aligned chemical bonding layer 3), forming stable chemical bonds with the dangling bonds on the side and top surfaces of the active region 10, thereby reducing the interface state density and minimizing trap formation. This self-aligned chemical bonding does not require large-area film thickness adjustment or high-temperature annealing, and is independent of ion implantation, wet etching, and laser irradiation, enabling it to be achieved under relatively mild conditions and avoiding potential damage to the device.

[0066] In some embodiments, the self-aligned chemical bonding layer 3' comprises a self-aligned monomolecular organic layer. In this embodiment, the self-aligned chemical bonding layer 3' employs a self-aligned monomolecular organic layer, ensuring the uniformity of the self-aligned chemical bonding layer 3' and effectively reducing the interface state density and the number of trapped regions.

[0067] In some embodiments, the active region 10 is made of monocrystalline silicon, and the organic molecular precursor includes functional groups having silane, mercapto, or phosphonic acid groups.

[0068] For example, organic molecular precursors include silane coupling agents, such as triethoxysilanes and aminopropyltriethoxysilanes (APTES). Under hydrolysis conditions, silane coupling agents react only with dangling bonds (Si-H or Si-Si) on the silicon surface. Since the silicon oxide surface is passivated and has low chemical activity, the reaction between the silane coupling agent and the silicon oxide surface is minimal, ensuring self-aligned chemical bonding at the interface between the isolation trench 2 and the active region 10.

[0069] In this embodiment, the organic molecular precursor can form strong bonds on the silicon surface, thereby forming a self-aligned chemical bonding layer at the interface between the isolation trench 2 and the active region 10, which can stably reduce the interface state density and the number of traps over a long period of time.

[0070] In some embodiments, the substrate 1 is immersed in the organic molecular precursor solution for 30 minutes to 24 hours. The immersion time of the substrate 1 in the organic molecular precursor solution affects the assembly degree and uniformity of the self-aligned chemical bonding layer. Excessive immersion time leads to the self-aligned chemical bonding layer becoming thicker, forming a multilayer structure instead of a single layer, and the film thickness varies significantly at different locations, affecting the uniformity of the film thickness. Conversely, insufficient immersion time is detrimental to the integrity and uniformity of the self-aligned chemical bonding layer formation, potentially resulting in some interfaces not being chemically bonded, i.e., the self-aligned chemical bonding layer not covering all interfaces.

[0071] In some embodiments, the concentration of the organic molecular precursor solution is 0.1% to 1%. The concentration of the organic molecular precursor solution affects the quality and thickness of the self-aligned chemical bonded layer. Choosing an appropriate concentration can ensure the density and uniformity of the self-aligned chemical bonded layer.

[0072] For example, organic molecular precursors include APTES. A 1-5 mM APTES solution is dissolved in 99.9% high-purity anhydrous ethanol, and the water content in the solution is controlled at 0.1%-1% to ensure proper hydrolysis reaction.

[0073] In some embodiments, the pH of the organic molecular precursor solution is 5 to 9, which facilitates self-aligned chemical bonding between the organic molecular precursor and the interface between the isolation trench 2 and the active region 10.

[0074] In some embodiments, the temperature for self-aligned chemical bonding is room temperature to 200°C. Under milder temperature conditions, self-aligned chemical bonding can be performed at the interface between the organic molecular precursor and the isolation trench 2 and the active region 10, avoiding potential damage to the device from high temperature and intense etching, and avoiding large amounts of ion irradiation.

[0075] In some embodiments, prior to the self-aligned chemical bonding of the interface between the isolation trench and the active region in step 120, the method for fabricating the semiconductor device further includes:

[0076] Clean the substrate;

[0077] The substrate is pretreated to remove oxides from its surface.

[0078] An isolation trench 2 is formed in the substrate 1. After an interface is formed between the isolation trench 2 and the active region 10, the surface of the substrate 1 is routinely cleaned to remove particles and organic contaminants from the surface of the substrate 1.

[0079] Then, the cleaned substrate is pretreated to remove oxides from the surface of substrate 1. For example, the material of substrate 1 includes monocrystalline silicon, that is, the material of active region 10 includes monocrystalline silicon, making the surface of active region 10 readily oxidized to a silicon oxide layer. Active region 10 is pretreated with HF dilution solution to remove the native oxide layer on the surface of active region 10, thereby exposing the silicon surface for self-aligned chemical bonding.

[0080] Step 130: Form the device structure in the active region.

[0081] Device structure 4 may include transistors. For example... Figure 5 As shown, the transistor includes a source region 41, a drain region 42, and a gate structure 43. The gate structure 43 is located on the active region 10, and the source region 41 and the drain region 42 are located in the active regions 10 on opposite sides of the gate structure 42.

[0082] The gate structure 43 may include a gate oxide layer and a gate. For example, a gate oxide layer is first formed on the active region 10 using a thin-film deposition process. Then, a gate is formed on the gate oxide layer using a thin-film deposition process. The gate oxide layer may include silicon oxide, etc., and the gate may include polysilicon, etc. Then, a source region 41 and a drain region 42 are formed in the active regions 10 on opposite sides of the gate structure 43 using an ion implantation process.

[0083] After forming device structure 4 in active region 10, a passivation layer covering device structure 4 can also be formed. Then, gate contact structure, source contact structure and drain contact structure are formed. The gate contact structure penetrates the passivation layer and is connected to gate structure 43. The source contact structure penetrates the passivation layer and is connected to source region 41. The drain contact structure penetrates the passivation layer and is connected to drain region 42.

[0084] It should be noted that further processing of semiconductor devices can be carried out, but this will not be elaborated on here.

[0085] In some embodiments, prior to forming the device structure in the active region in step 130, the method for fabricating the semiconductor device further includes filling an insulating layer in an isolation trench.

[0086] As semiconductor devices continue to shrink, their performance becomes increasingly sensitive to interface state defects. While isolation trenches can define active regions, stress concentration and interface defects exist at the interface between the isolation trench and the active region, resulting in significant deviations in threshold voltage across different devices—that is, poor threshold voltage uniformity. This non-uniformity exacerbates the dispersion of device parameter distribution, affecting device consistency and yield. To improve the uniformity of the threshold voltage, related technologies deposit inorganic films at the interface between the isolation trench and the active region, and reduce the interface state density and the number of traps through annealing and ion treatment. However, these methods require high processing temperatures, harsh chemical conditions, and complex equipment and control methods, and also interfere with other areas of the device.

[0087] This embodiment employs self-aligned chemical bonding between organic molecules and the interface between the isolation trench and the active region, forming a self-aligned chemical bonding layer covering this interface. This achieves ordered passivation of the interface, stably reducing the interface state density and the number of traps over a long period, improving the uniformity and stability of the device's threshold voltage, resulting in a more concentrated threshold voltage distribution and improved device consistency and yield. Furthermore, self-aligned chemical bonding can be achieved under relatively mild conditions, avoiding damage to the device caused by high temperatures and intense etching. This embodiment addresses the issue from the perspective of microstructure control at the chemical bonding level, fundamentally different from related technologies such as film thickness adjustment, hydrogen beam passivation, stress modulation, or laser processing, providing a completely new solution for improving the uniformity of semiconductor devices.

[0088] Accordingly, this application also provides a semiconductor device that can be fabricated using the semiconductor device fabrication method described in the above embodiments.

[0089] like Figure 5 As shown, the semiconductor device provided in this application embodiment includes a substrate 1, a self-aligned chemical bonding layer 3', and a device structure 4.

[0090] Substrate 1 includes an active region 10, and an isolation trench 2 is provided in substrate 1 surrounding the active region 10. Substrate 1 may include a monocrystalline silicon substrate, that is, the material of substrate 1 includes monocrystalline silicon. Substrate 1 may also be an SOI substrate. The SOI substrate may include a monocrystalline silicon substrate 11, a buried oxide layer 12, and a monocrystalline silicon layer 13, wherein the buried oxide layer 12 is located on the monocrystalline silicon substrate 11, and the monocrystalline silicon layer 13 is located on the buried oxide layer 12. The monocrystalline silicon layer 13 includes the active region 10, and an isolation trench 2 is provided in monocrystalline silicon layer 13 surrounding the active region 10.

[0091] A self-aligned chemical bonding layer 3' covers the interface between the isolation trench 2 and the active region 10. The interface between the isolation trench 2 and the active region 10 is the side surface of the active region 10, and the self-aligned chemical bonding layer 3' covers this side surface. The self-aligned chemical bonding layer 3' is formed by self-aligned chemical bonding between organic molecules and the interface between the isolation trench 2 and the active region 10. The self-aligned chemical bonding layer 3' provides ordered passivation to the interface between the organic molecules and the isolation trench 2 and the active region 10, reducing the interface state density and minimizing trap formation.

[0092] Device structure 4 is located in the active region 10. Device structure 4 may include transistors. For example... Figure 5 As shown, the transistor includes a source region 41, a drain region 42, and a gate structure 43. The gate structure 43 is located on the active region 10, and the source region 41 and drain region 42 are located in the active regions 10 on opposite sides of the gate structure 43. The gate structure 43 may include a gate oxide layer and a gate. The gate oxide layer is located on the active region 10, and the gate is located on the gate oxide layer. The gate oxide layer may include silicon oxide, etc., and the gate may include polysilicon, etc.

[0093] In some embodiments, the self-aligned chemical bonding layer 3' comprises a self-aligned monomolecular organic layer. In this embodiment, the self-aligned chemical bonding layer 3' employs a self-aligned monomolecular organic layer, ensuring the uniformity of the self-aligned chemical bonding layer 3' and effectively reducing the interface state density and the number of trapped regions.

[0094] According to the semiconductor device provided in the embodiments of this application, the interface between the isolation trench 2 and the active region 10 is passivated in an orderly manner by a self-aligned chemical bonding layer 3', which reduces the interface state density and the number of trap regions, improves the uniformity and stability of the threshold voltage of the device, and improves the device yield and reliability.

[0095] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0096] In the description of this application, "multiple" means two or more.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0098] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including an active region, and an isolation trench disposed around the active region in the substrate; Self-aligned chemical bonding is performed on the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface; The device structure is formed in the active region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of performing self-aligned chemical bonding at the interface between the isolation trench and the active region to form a self-aligned chemical bonding layer covering the interface includes: Self-aligned chemical bonding is performed on the interface between the isolation trench and the active region, as well as on the upper surface of the active region, to form an initial self-aligned chemical bonding layer covering the interface and the upper surface of the active region. Remove the initial self-aligned chemical bonding layer on the upper surface of the active region to form a self-aligned chemical bonding layer covering the interface.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The material of the bottom surface of the isolation trench is different from the material of the active area; Alternatively, the material of the bottom surface of the isolation trench is the same as the material of the active region, and the method further includes covering the bottom surface of the isolation trench with a mask layer before performing self-aligned chemical bonding on the interface between the isolation trench and the active region and on the upper surface of the active region.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of performing self-aligned chemical bonding on the interface between the isolation trench and the active region, as well as on the upper surface of the active region, includes: The substrate is immersed in an organic molecular precursor solution, so that the organic molecular precursor is self-aligned chemically bonded to the interface between the isolation trench and the active region and the upper surface of the active region.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The active region is made of monocrystalline silicon, and the organic molecular precursor includes functional groups having silane, mercapto, or phosphonic acid groups.

6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The substrate is immersed in the organic molecular precursor solution for 30 minutes to 24 hours; and / or, The concentration of the organic molecule precursor solution is 0.1% to 1%; and / or, The pH value of the organic molecule precursor solution is 5 to 9.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The temperature range for the self-aligned chemical bonding is room temperature to 200°C.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The self-aligned chemical bonding layer includes a self-aligned monomolecular organic layer.

9. The method for fabricating a semiconductor device according to any one of claims 1-8, characterized in that, Prior to performing self-aligned chemical bonding at the interface between the isolation trench and the active region, the method further includes: The substrate is cleaned; The substrate is pretreated to remove oxides from its surface.

10. A semiconductor device, characterized in that, include: A substrate, the substrate including an active region, wherein an isolation trench is provided in the substrate surrounding the active region; A self-aligned chemical bonding layer covers the interface between the isolation trench and the active region; The device structure is located in the active region.

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