Semiconductor wafers and their fabrication methods

Abstract

This application provides a semiconductor wafer and a method for fabricating the same. The semiconductor wafer includes: a monocrystalline silicon substrate; a first polycrystalline silicon layer disposed on one side of the monocrystalline silicon substrate; a spacer layer disposed on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate, the spacer layer having a plurality of holes; and a second polycrystalline silicon layer disposed on the side of the spacer layer away from the first polycrystalline silicon layer, the second polycrystalline silicon layer filling the plurality of holes, and the second polycrystalline silicon layer being connected to the first polycrystalline silicon layer through the plurality of holes.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, and in particular to semiconductor wafers and methods for fabricating them. Background Technology

[0002] In the fabrication of radio frequency (RF) devices, the devices are typically fabricated on silicon-on-insulator (SOI) structures or high-resistivity single-crystal silicon substrates. To reduce parasitic power loss of RF signals in the substrate and suppress nonlinear distortion, the processing substrate used for RF devices usually needs to maintain a high effective resistivity.

[0003] In related technologies, a polycrystalline silicon charge cutoff layer is typically deposited between a monocrystalline silicon substrate and a buried oxide layer to maintain the high resistance characteristics of the substrate and thereby improve the performance of radio frequency devices.

[0004] However, the charge cutoff capability of polysilicon charge cutoff layers in related technologies is insufficient to meet the ever-increasing demand for substrate isolation in radio frequency devices. Summary of the Invention

[0005] This application provides a semiconductor wafer and a method for fabricating the same. By introducing a spacer layer with holes between a first polysilicon layer and a second polysilicon layer, and allowing the second polysilicon layer to fill the holes and connect with the first polysilicon layer through the holes, the direct contact interface between the two polysilicon layers can be increased, thereby increasing the charge recombination path and improving charge cutoff performance.

[0006] This application provides a semiconductor wafer in one aspect. The semiconductor wafer includes: a monocrystalline silicon substrate, a first polycrystalline silicon layer, a spacer layer, and a second polycrystalline silicon layer. The first polycrystalline silicon layer is disposed on one side of the monocrystalline silicon substrate. The spacer layer is disposed on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate, and a plurality of holes are formed in the spacer layer. The second polycrystalline silicon layer is disposed on the side of the spacer layer away from the first polycrystalline silicon layer, the second polycrystalline silicon layer fills the plurality of holes, and the second polycrystalline silicon layer is connected to the first polycrystalline silicon layer through the holes.

[0007] In another aspect, this application provides a method for fabricating a semiconductor wafer. The method includes: providing a monocrystalline silicon substrate; forming a first polycrystalline silicon layer on one side of the monocrystalline silicon substrate; forming a spacer layer on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate; etching the spacer layer to form a plurality of holes in the spacer layer, the walls of the holes being defined by the spacer layer; and forming a second polycrystalline silicon layer on the side of the spacer layer away from the first polycrystalline silicon layer, the second polycrystalline silicon layer filling the plurality of holes, and the second polycrystalline silicon layer being connected to the first polycrystalline silicon layer through the plurality of holes.

[0008] This application provides a semiconductor wafer and a method for fabricating the same. By introducing a spacer layer with holes between a first polysilicon layer and a second polysilicon layer, the second polysilicon layer fills the holes and connects to the first polysilicon layer through the holes, forming a direct contact interface between the two polysilicon layers at the hole locations. The grain boundary defects at this direct contact interface, together with the grain boundary defects within the two polysilicon layers, constitute a three-dimensional interconnected network of charge recombination centers, thereby improving the density of charge recombination centers. Based on this, it is possible to reduce the parasitic power loss of high-resistivity substrates under RF operating conditions and improve the isolation and linearity of RF devices. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a single-layer polycrystalline silicon charge cutoff layer structure in related technologies.

[0010] Figure 2 This is a schematic cross-sectional view of a semiconductor wafer provided in an embodiment of this application.

[0011] Figure 3 This is a partially enlarged schematic diagram of the spacer layer and hole structure provided in the embodiments of this application.

[0012] Figure 4 This is a schematic diagram of stress changes before and after etching the spacer layer in an embodiment of this application.

[0013] Figure 5 This is a flowchart of a semiconductor wafer fabrication method provided in an embodiment of this application.

[0014] Figure 6 This is a schematic diagram illustrating the changes in wafer bow shape after each process step, as provided in the embodiments of this application.

[0015] Figure 7 This is an atomic force microscope (AFM) image of the surface morphology after the spacer layer has been deposited in an embodiment of this application.

[0016] Figure 8 This is a surface topography diagram of AFM after the etching spacer layer forms holes in the embodiment of this application.

[0017] Figure 9 This is a surface morphology diagram of the AFM after the deposition of the second polysilicon layer in an embodiment of this application.

[0018] Figure 10 This is a graph showing the evolution of surface roughness with process steps in the embodiments of this application. Detailed Implementation

[0019] The technical solutions in this application will now be clearly and completely described with reference to the accompanying drawings.

[0020] See Figure 1 In the fabrication of radio frequency devices, the devices are typically fabricated on silicon-on-insulator (SOI) structures or high-resistivity single-crystal silicon substrates. To enable the substrate to effectively cut off charges, a polycrystalline silicon charge cutoff layer 200 needs to be deposited on the surface of the single-crystal silicon substrate 100.

[0021] Polycrystalline silicon is composed of numerous fine grains, and the grain boundary regions between these grains contain many dangling bonds and lattice defects. When free charge carriers, i.e., electrons or holes, move to these defect locations, they are captured by the defects and recombine with opposite charge carriers, thus disappearing. This process is also known as charge recombination. Through this mechanism, the polycrystalline silicon charge cutoff layer 200 can prevent free charge carriers from accumulating in the monocrystalline silicon substrate 100 to form conductive channels, thereby maintaining the high-resistivity characteristics of the substrate and reducing parasitic losses in radio frequency devices.

[0022] The number of effectively captured grain boundaries is closely related to the grain size. In polycrystalline silicon thin films of the same volume, the larger the total area of ​​grain boundaries, the more sites can be captured for charge carriers, the higher the probability of charge recombination, and the better the charge cutoff effect.

[0023] In related technologies, the directly deposited polycrystalline silicon charge cutoff layer 200 tends to grow after undergoing high-temperature thermal processes in subsequent wafer fabrication and device manufacturing, resulting in a reduction in the number of effectively captured grain boundaries per unit area and limiting the charge cutoff capability.

[0024] Furthermore, the mismatch in thermal expansion coefficients between the polycrystalline silicon thin film and the monocrystalline silicon substrate causes compressive stress introduced during deposition, leading to wafer deformation. This deformation can be characterized by bowing (BOW). Bowing refers to the positional deviation of the wafer's center point relative to a reference plane determined by edge reference points.

[0025] When the wafer center bulges towards the front side (the side with the deposited thin film) relative to the edge, it is defined as positive bowing, or simply positive BOW. When the wafer center is recessed towards the front side relative to the edge, it is defined as negative bowing, or simply negative BOW. In actual processes, due to stress mismatch, the wafer bowing can increase from the initial ±2μm to 20μm to 40μm, and it usually exhibits positive bowing, thus affecting subsequent processes, such as the alignment accuracy and focus depth of photolithography.

[0026] See Figure 2 This application provides a semiconductor wafer 10. Along... Figure 2 From bottom to top, the semiconductor wafer 10 sequentially includes: a single-crystal silicon substrate 100, a first polycrystalline silicon layer 120, a spacer layer 140, and a second polycrystalline silicon layer 160.

[0027] According to this embodiment, a spacer layer 140 with multiple holes 142 is introduced between the first polysilicon layer 120 and the second polysilicon layer 160, so that the second polysilicon layer 160 fills the holes 142 and is connected to the first polysilicon layer 120 through the holes 142. A direct contact interface 162 between the two polysilicon layers is formed at the location of the holes 142, thereby introducing additional charge recombination paths in the stacked structure and improving the overall charge recombination center density.

[0028] In some embodiments, the first polysilicon layer 120 and the second polysilicon layer 160 may have compressive stress, and the spacer layer 140 may have tensile stress. The semiconductor wafer 10 may also have a warpage toward the side of the monocrystalline silicon substrate 100, which can be characterized by bowing.

[0029] The single-crystal silicon substrate 100 is a high-resistivity single-crystal silicon substrate for radio frequency devices. The bulk resistivity of the single-crystal silicon substrate 100 is greater than 1000 Ω·cm to ensure that the radio frequency devices subsequently fabricated have sufficiently low substrate loss.

[0030] See Figure 2 A first polycrystalline silicon layer 120 is disposed on one side of a single-crystal silicon substrate 100, in direct contact with the single-crystal silicon substrate 100, serving as a first charge cutoff layer. The first polycrystalline silicon layer 120 is an undoped polycrystalline silicon thin film, composed of randomly oriented polycrystalline silicon grains, with grain boundaries formed between adjacent grains. The grain boundary regions are rich in lattice defects such as dangling bonds and dislocations, forming deep-level traps that can effectively capture and recombine free carriers induced at the buried oxide layer interface.

[0031] The thickness of the first polysilicon layer 120 can, for example, be in the range of 0.5 μm to 1.5 μm. Setting the upper limit of the thickness to 1.5 μm ensures that the monolayer deposition time is within a reasonable range and that the compressive stress introduced by the polysilicon film is controlled within an acceptable range, avoiding wafer bowing exceeding the tolerance of subsequent processes. The lower limit of the thickness is set to 0.5 μm to ensure that the first polysilicon layer 120 has a sufficient number of grain boundaries as charge recombination interfaces.

[0032] Based on the inhibitory effect of the spacer layer 140 on polysilicon grain growth described below, the grain size of the first polysilicon layer 120 after subsequent high-temperature thermal processing can, for example, be in the range of 300 nm to 500 nm. The first polysilicon layer 120 can be formed by chemical vapor deposition (CVD). The spacer layer 140 can, on the one hand, physically block the merging of interlayer grains between the first polysilicon layer 120 and the second polysilicon layer 160; on the other hand, when the spacer layer 140 includes silicon nitride, the nitrogen element in the spacer layer 140 can inhibit the migration of polysilicon grain boundaries. Through these two effects, it is beneficial to suppress the growth of polysilicon grains during high-temperature thermal processing.

[0033] See Figure 2 and Figure 3 The spacer layer 140 is disposed on the side of the first polysilicon layer 120 away from the monocrystalline silicon substrate 100 and is in direct contact with the surface of the first polysilicon layer 120. A plurality of holes 142 are formed on the spacer layer 140.

[0034] See Figure 3 The hole 142 extends from the side of the spacer layer 140 away from the first polysilicon layer 120 to the side of the spacer layer 140 close to the first polysilicon layer 120, and the hole wall of the hole 142 is defined by the spacer layer 140. Before the formation of the second polysilicon layer 160, the bottom of the hole 142 exposes a portion of the surface of the first polysilicon layer 120.

[0035] The formation of the voids 142 results in a discontinuous distribution of the spacer layer 140 on the surface of the first polysilicon layer 120. The voids 142 are located in areas where the spacer layer 140 material is missing. The continuous portions of the spacer layer 140 provide structural support for the growth of the second polysilicon layer 160 and prevent cross-layer grain merging between the first polysilicon layer 120 and the second polysilicon layer 160. The discontinuous portions of the spacer layer 140, i.e., the voids 142, provide a direct connection channel between the second polysilicon layer 160 and the first polysilicon layer 120.

[0036] See Figure 4 On the upper side, before the formation of the hole 142, the spacer layer 140 is a continuous thin film with mutually constrained tensile stresses inside, as shown by the inward arrow in the figure. This continuously distributed tensile stress is opposite in direction to the compressive stress introduced by the first polysilicon layer 120, and the two together affect the stress state and bowing of the wafer.

[0037] See Figure 4On the lower side, after multiple holes 142 are formed on the spacer layer 140 through an etching process, the spacer layer 140 changes from a continuous film to a discontinuous form. At this time, the originally stress-constrained area is partially removed, so that the remaining spacer layer material no longer bears complete and continuous stress constraints, and the continuity of stress distribution is broken. Through this physical structural blockage, the tensile stress inside the spacer layer 140 is dispersed or released, thereby adjusting the overall bow shape of the wafer. By adjusting the morphology and density of the holes 142, the degree of tensile stress release in the spacer layer 140 can be adjusted, thereby adjusting the bow shape of the wafer.

[0038] The thickness of the spacer layer 140 is, for example, less than 500 nm. The deposited material of the second polysilicon layer 160 can enter the holes 142 and form a direct contact interface 162 with the first polysilicon layer 120 through the holes 142.

[0039] Spacer layer 140 may include, for example, silicon nitride. Since silicon nitride has a higher etch selectivity than polysilicon in hot phosphoric acid solution, typically greater than 50:1 in hot phosphoric acid solution at 160°C, the impact on the surface of the first polysilicon layer 120 can be reduced during the etching of spacer layer 140 to form aperture 142.

[0040] Furthermore, the tensile stress generated during the deposition of the silicon nitride thin film is opposite in direction to the compressive stress generated by the polycrystalline silicon layer, which can offset the influence of polycrystalline silicon deposition on the wafer bowing. By etching to form the holes 142, the spacer layer 140 is transformed from a continuous thin film into a discontinuous form, and the wafer bowing can be controlled within the target range by adjusting the degree of tensile stress release.

[0041] Furthermore, nitrogen atoms in the spacer layer 140 can generate a Zener pinning effect. Specifically, nitrogen atoms or nitride microparticles distributed at the polycrystalline silicon grain boundaries can generate pinning forces that hinder grain boundary migration. These pinning forces counteract the driving force of polycrystalline silicon grain growth, thereby limiting grain boundary movement. During subsequent high-temperature heat treatment, this mechanism can prevent polycrystalline silicon grains from growing through grain boundary merging, helping to maintain the grain size of the polycrystalline silicon layer within a predetermined range and preserving the thermal stability of the charge-stop layer.

[0042] Since silicon nitride can maintain structural stability in high-temperature environments above 1000°C, spacer layer 140 can maintain its morphological integrity even after undergoing multiple high-temperature heat treatments during SOI wafer fabrication.

[0043] In other embodiments, the spacer layer 140 may also be made of other insulating materials that can be selectively removed by a specific etchant. The specific material of the spacer layer 140 is not limited in the embodiments of this application.

[0044] See Figure 2 The second polysilicon layer 160 is disposed on the side of the spacer layer 140 away from the first polysilicon layer 120. The second polysilicon layer 160 fills a plurality of holes 142, and the second polysilicon layer 160 is connected to the first polysilicon layer 120 through the holes 142.

[0045] Specifically, see Figure 3 The second polysilicon layer 160 extends towards the first polysilicon layer 120 at the location of the hole 142 and essentially fills the entire internal space of the hole 142. The second polysilicon layer 160 is in direct contact with the region of the first polysilicon layer 120 exposed by the bottom of the hole, forming a direct contact interface 162 between the two polysilicon layers. Crystallographically, the direct contact interface 162 is represented as the interface grain boundary between the first polysilicon layer 120 and the second polysilicon layer 160. Due to the irregular atomic arrangement at this interface, a high density of dangling bonds and lattice defects can be generated, thereby forming deep-level traps in the band gap. These deep-level traps provide lateral carrier recombination paths in addition to the original vertical grain boundary recombination paths within the first polysilicon layer 120 and the second polysilicon layer 160, increasing the probability of carrier capture and recombination.

[0046] The aforementioned direct contact interface 162 is formed by the second polysilicon layer 160 directly contacting the first polysilicon layer 120 within the hole 142. At the location of the hole 142, there is no dielectric barrier between the polysilicon material of the second polysilicon layer 160 and the polysilicon material of the first polysilicon layer 120, and the two are in direct contact.

[0047] The thickness of the second polysilicon layer 160 can be, for example, in the range of 0.5 μm to 1.5 μm. The considerations for setting the thickness range of the second polysilicon layer 160 are the same as those for the first polysilicon layer 120. Based on the inhibitory effect of the spacer layer 140 on the growth of polysilicon grains, the grain size of the second polysilicon layer 160 after undergoing subsequent high-temperature thermal processing can be, for example, in the range of 300 nm to 500 nm.

[0048] Compared with the single-layer polysilicon solution in related technologies, the semiconductor wafer provided in this application, under the same polysilicon grain size, introduces an additional charge recombination path through the hole wall interface of the hole 142 and the direct contact interface 162, thereby increasing the total area of ​​the effective recombination interface and the charge recombination center density.

[0049] See Figure 5 This application also provides a method for preparing a semiconductor wafer, which includes steps S100 to S180. The following description combines structural features with the preparation method.

[0050] In step S100, a single-crystal silicon substrate is provided.

[0051] A single-crystal silicon substrate 100 is provided. The single-crystal silicon substrate 100 is a high-resistivity single-crystal silicon substrate for radio frequency devices, with a bulk resistivity greater than 1000 Ω·cm.

[0052] Before forming the first polycrystalline silicon layer 120, the monocrystalline silicon substrate 100 can be cleaned to remove surface organic contaminants, metal ions, and the native oxide layer, ensuring that the subsequently deposited first polycrystalline silicon layer 120 can nucleate and grow on a clean silicon surface. The cleaning process can adopt a standard RCA cleaning process, including SC-1 cleaning and SC-2 cleaning steps. After cleaning, it is rinsed with deionized water and dried with nitrogen. The specific method of the cleaning process is not limited in the embodiments of this application.

[0053] In step S120, a first polycrystalline silicon layer is formed on one side of the monocrystalline silicon substrate.

[0054] A first polycrystalline silicon layer 120 is formed on one side of the monocrystalline silicon substrate 100. Figure 2 The first polycrystalline silicon layer 120 is disposed on the front side of the monocrystalline silicon substrate 100 and is in direct contact with the monocrystalline silicon substrate 100. The first polycrystalline silicon layer 120 is formed by chemical vapor deposition, specifically by low-pressure chemical vapor deposition (LPCVD) or atmospheric-pressure chemical vapor deposition (APCVD).

[0055] For example, when depositing the first polycrystalline silicon layer 120, the chemical vapor deposition temperature is 600°C to 1000°C, the pressure is 10 Pa to 100 Pa, the silicon source gas includes trichlorosilane (TCS, chemical formula SiHCl3), and the carrier gas includes hydrogen (H2). In one specific embodiment, the deposition temperature is 900°C, the chamber pressure is 50 Pa, the silicon source gas is trichlorosilane, the carrier gas is hydrogen, and the deposition reaches a target thickness of 1.0 μm.

[0056] Regarding the selection of the deposition temperature range, the lower limit is set at 600℃ to account for the thermal decomposition reaction of trichlorosilane. Below 600℃, the thermal decomposition rate decreases, making it difficult to meet the efficiency requirements of the process flow. The upper limit is set at 1000℃ to control the morphology of polycrystalline silicon and substrate stability. Above 1000℃, polycrystalline silicon grains are prone to overgrowth during deposition, and the higher thermal budget can affect the performance stability of the monocrystalline silicon substrate.

[0057] It is understood that, in addition to trichlorosilane, silicon source gas can also be silane (SiH4), dichlorosilane (SiH2Cl2), or silicon tetrachloride (SiCl4), etc. The specific type of silicon source gas is not limited in the embodiments of this application.

[0058] For example, after deposition, the thickness of the first polycrystalline silicon layer 120 can be in the range of 0.5 μm to 1.5 μm. For example, the film thickness can be measured using an ellipsometry. After subsequent high-temperature thermal processing, the polycrystalline silicon grain size can be observed using a scanning electron microscope (SEM).

[0059] After step S120 is completed, due to the mismatch in thermal expansion coefficients between the polycrystalline silicon thin film and the monocrystalline silicon substrate, the polycrystalline silicon deposition introduces compressive stress, and the wafer bow increases from the initial value to 20μm to 40μm, exhibiting a positive BOW (Bow Overlap). Figure 6 As shown.

[0060] In step S140, a spacer layer is formed on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate.

[0061] A spacer layer 140 is formed on the side of the first polysilicon layer 120 away from the monocrystalline silicon substrate 100. The spacer layer 140 forms a continuous silicon nitride thin film on the surface of the first polysilicon layer 120 away from the monocrystalline silicon substrate 100. In embodiments of this application, the spacer layer 140 can be formed by depositing silicon nitride material on the surface of the first polysilicon layer 120 using atomic layer deposition (ALD).

[0062] For example, when forming the spacer layer 140, silicon nitride material can be deposited on the surface of the first polycrystalline silicon layer 120 at a temperature of 300°C to 450°C using atomic layer deposition, and trimethylaminosilane is used as the silicon source gas, and ammonia (NH3) or nitrous oxide (N2O) is used as the nitrogen source gas.

[0063] Atomic layer deposition (ALD) can employ a molecular layer-by-layer deposition mode. Each deposition cycle includes: a trimethylaminosilane pulse, inert gas purging, an ammonia pulse, and another inert gas purging, enabling control over the thickness of spacer layer 140. For example, the thickness of spacer layer 140 is less than 500 nm.

[0064] The deposition temperature of the spacer layer 140 is set in the range of 300°C to 450°C. This is because the atomic layer deposition process can achieve self-limiting growth within this temperature window, which is conducive to forming a relatively uniform and dense silicon nitride film, providing a basis for subsequent etching to form the holes 142. On the other hand, this temperature is lower than the deposition temperature of the first polysilicon layer 120, so it will not cause additional thermal disturbance to the grain structure in the deposited first polysilicon layer 120.

[0065] like Figure 7 As shown, the spacer layer 140 is, for example, a silicon nitride thin film. After the spacer layer 140 is deposited, the surface exhibits high flatness and density. As can be seen from the vertical height scale (-0.8 nm to 0.4 nm) of the AFM image, the film has not yet developed any undulations and is in a uniform and continuous coverage state, which provides a good initial surface for subsequent precise etching.

[0066] In other embodiments, the spacer layer 140 may also be formed by chemical vapor deposition or plasma-enhanced chemical vapor deposition. The specific deposition process of the spacer layer 140 is not limited in the embodiments of this application.

[0067] See Figure 6 After step S140 is completed, the silicon nitride film generates tensile stress during the deposition process. When superimposed with the compressive stress introduced by the polycrystalline silicon in step S120, the wafer bow shape changes from positive BOW, for example, from 20μm to 40μm, to negative BOW, for example, from -30μm to -50μm.

[0068] In step S160, the spacer layer is etched to create multiple holes in the spacer layer.

[0069] The spacer layer 140 is etched to create a plurality of holes 142 in the spacer layer 140, the walls of the holes 142 being defined by the spacer layer 140.

[0070] As an example, this etching step can employ a phosphoric acid solution to perform wet etching on the spacer layer 140, wherein the temperature of the phosphoric acid solution is in the range of 140°C to 180°C. More specifically, the temperature of the phosphoric acid solution can be 160°C.

[0071] Please refer to Table 1 below. In a hot phosphoric acid solution at 140°C to 180°C, the etching rate of silicon nitride is approximately 0.5 nm / min to 50 nm / min, while the etching rate of polysilicon is close to 0 to 0.2 nm / min in the 140°C to 170°C range, with an etching selectivity greater than 50:1 in the same range. The lower limit of 140°C was set to account for process efficiency requirements. If the temperature is below 140°C, the etching rate decreases, prolonging the formation cycle of via 142. The upper limit of 180°C was set to ensure low damage to polysilicon. If the temperature is above 180°C, the polysilicon etching rate increases significantly, and the etching selectivity between silicon nitride and polysilicon decreases significantly, leading to increased etching damage to polysilicon.

[0072] Table 1

[0073] In some embodiments, the etching temperature is set to 160°C to balance etching rate and process stability, and to utilize the higher etching selectivity at this temperature to reduce etching damage to the first polysilicon layer 120.

[0074] Phosphoric acid exhibits strong chemical attack on the Si-N bonds in Si3N4 at high temperatures. Si3N4 reacts with phosphoric acid to form soluble phosphosilicates, thereby achieving isotropic wet etching of the silicon nitride film. Since phosphoric acid has weaker chemical attack on the Si-Si bonds in polycrystalline silicon, the etching reaction automatically slows down after the silicon nitride film is etched and the surface of the first polycrystalline silicon layer 120 is exposed, effectively protecting the first polycrystalline silicon layer 120.

[0075] Combination Figure 8 As shown, the surface morphology of spacer layer 140 changed significantly after hot phosphoric acid etching. AFM images revealed irregular island-like structures (bright areas) and recessed areas (black areas) on the surface. The increase in the vertical height scale (-100nm to 200nm) indicates that spacer layer 140 changed from a continuous thin film to a discontinuous morphology. The black recessed areas correspond to the holes 142 that penetrate spacer layer 140, and these holes form the connection channels between the first polysilicon layer 120 and subsequent deposited layers.

[0076] After etching, for example, the wafer can be rinsed with deionized water and dried. At this point, combined with... Figure 3 A plurality of holes 142 are formed on the spacer layer 140. The holes 142 extend from the side of the spacer layer 140 away from the first polysilicon layer 120 to the side of the spacer layer 140 close to the first polysilicon layer 120. The walls of the holes 142 are defined by the spacer layer 140. The bottom of the holes 142 exposes a portion of the surface of the first polysilicon layer 120.

[0077] The abundance of the pores 142 on the spacer layer 140 is characterized by areal density. Areal density refers to the number of pores 142 distributed per unit area parallel to the surface of the single-crystal silicon substrate. The areal density and size distribution of the pores 142 are jointly determined by the film quality of the atomic layer deposition process and the thermal phosphoric acid etching time. For example, within the above process parameter range, the average diameter of the pores 142 is between 1 nm and 10 nm.

[0078] Combination Figure 9 As shown, after the second polysilicon layer 160 is deposited, the surface morphology becomes smooth again. (Comparison) Figure 8 and Figure 9 As can be seen, the originally undulating porous areas have been filled and covered by the newly added polycrystalline silicon material, and the image shows the grain texture unique to polycrystalline silicon. The vertical height scale falls within the range of -100nm to 100nm. This indicates the effective filling and surface planarization effect of the second polycrystalline silicon layer 160 on the underlying porous structure.

[0079] See Figure 6 After step S160 is completed, the hot phosphoric acid etching disrupts the continuity of the silicon nitride spacer layer 140, and the tensile stress of the spacer layer 140 is partially released. The wafer bow width is repaired from negative BOW, specifically, from -30μm to -50μm, to -10μm to -30μm.

[0080] In step S180, a second polysilicon layer is formed on the side of the spacer layer away from the first polysilicon layer.

[0081] A second polysilicon layer 160 is formed on the side of the spacer layer 140 away from the first polysilicon layer 120. The second polysilicon layer 160 is filled with a plurality of holes 142 and is connected to the first polysilicon layer 120 through the plurality of holes 142.

[0082] For example, the second polysilicon layer 160 is formed by the same chemical vapor deposition process as the first polysilicon layer 120, with a chemical vapor deposition temperature of 600°C to 1000°C and a pressure of 10 Pa to 100 Pa. The silicon source gas includes trichlorosilane, the carrier gas includes hydrogen, and the target thickness is in the range of 0.5 μm to 1.5 μm.

[0083] During the deposition of the second polysilicon layer 160, polysilicon simultaneously nucleates and grows at the bottom of the holes 142, i.e., on the exposed surface of the first polysilicon layer 120, and on the surface of the spacer layer 140. Inside the holes 142, the polysilicon growing upward from the bottom of the holes merges with the polysilicon extending laterally from the sidewalls of the holes 142, gradually filling the internal space of the holes 142 and forming a direct contact interface 162.

[0084] When the deposition thickness of the second polysilicon layer 160 exceeds the thickness of the spacer layer 140, the holes 142 are filled. The second polysilicon layer 160 grows continuously on the surface of the spacer layer 140 and covers the entire spacer layer, forming a uniform and continuous polysilicon thin film. See also Figure 9 and Figure 10 After the second polysilicon layer 160 is deposited, the surface roughness of the wafer can be reduced from about 50 nm after etching to about 31 nm, which is beneficial to the subsequent bonding process.

[0085] At the direct contact interface 162, the second polysilicon layer 160 and the first polysilicon layer 120 form a physical contact, and there is no insulating medium blocking them. Due to the lattice mismatch and dangling bonds at the contact interface 162, a high density of deep-level traps is formed in the band gap. These deep-level traps are distributed in the plane containing the holes 142 and are connected to the original grain boundaries inside the first polysilicon layer 120 and the second polysilicon layer 160, thereby constructing a three-dimensional interconnected charge recombination network. This network increases the probability of capturing free carriers near the substrate surface by increasing the transverse and longitudinal interwoven recombination paths, improving the charge recombination efficiency, and thus suppressing the parasitic conductivity effect of the substrate under radio frequency signals, which helps to improve the linearity of the device.

[0086] See Figure 6 For example, after step S180 is completed, the compressive stress of the second polysilicon layer 160 further adjusts the wafer bowing from -10μm to -30μm to within ±10μm, so as to meet the requirements of subsequent photolithography processes for wafer flatness.

[0087] Examples and Comparative Examples To verify the technical effectiveness of the semiconductor wafer fabrication method provided in the embodiments of this application, the following embodiments and comparative examples were designed for comparative experiments. All samples used a single-crystal silicon substrate with a bulk resistivity greater than 1000 Ω·cm. In Examples 1 to 4 and Comparative Example 2, the first and second polycrystalline silicon layers used the same deposition process parameters: chemical vapor deposition temperature 900℃, pressure 50 Pa, silicon source gas was trichlorosilane, carrier gas was hydrogen, and the target thickness of each layer was 1.0 μm. The specific process parameters of Comparative Example 1 are described below.

[0088] After the structure of each sample is prepared, it is subjected to heat treatment to simulate the high-temperature thermal environment that may be experienced in subsequent SOI wafer fabrication and device processes.

[0089] After heat treatment, the size of polysilicon grains in the first and second polysilicon layers was measured by scanning electron microscopy (SEM), the wafer bow shape was measured by optical interferometer, and the surface roughness of the second polysilicon layer after deposition was measured by atomic force microscopy (AFM).

[0090] Example 1 Example 1 uses the preparation method provided in the embodiments of this application to sequentially form a first polycrystalline silicon layer, a spacer layer and a second polycrystalline silicon layer on a single-crystal silicon substrate.

[0091] For the first polycrystalline silicon layer, a low-pressure chemical vapor deposition process was used, with a deposition temperature of 900℃ and a pressure of 50Pa. The silicon source gas was trichlorosilane, and the carrier gas was hydrogen. The deposition thickness was 1.0 μm. After the step was completed, the wafer bow increased to approximately 30 μm, i.e., positive BOW.

[0092] For the spacer layer, atomic layer deposition (ALD) was used at 350°C, with trimethylaminosilane as the silicon source gas and ammonia as the nitrogen source gas, to deposit silicon nitride material on the surface of the first polycrystalline silicon layer, with a deposition thickness of 40 nm. After the step, the tensile stress of the silicon nitride caused the wafer bow shape to change to approximately -40 μm, i.e., negative BOW.

[0093] For the etching step, a phosphoric acid solution at 160°C was used to wet-etch the spacer layer for 180 seconds to create multiple holes in the spacer layer. The hole walls were defined by the spacer layer. The bottom of the holes exposed a portion of the surface of the first polysilicon layer. After etching, the surface roughness measured by AFM was approximately 52 nm, and the wafer bow was restored to approximately -20 μm.

[0094] For the second polysilicon layer, the same low-pressure chemical vapor deposition process parameters as the first polysilicon layer were used, with a deposition thickness of 1.0 μm. During deposition, the second polysilicon layer filled the voids and connected to the first polysilicon layer through these voids, forming a direct contact interface between the two polysilicon layers at the void locations. See [link to documentation]. Figure 6 , Figure 9 and Figure 10 After the second polysilicon layer is deposited, the surface roughness is reduced to about 31 nm, and the wafer bow is adjusted to about -5 μm, which is within ±10 μm.

[0095] After heat treatment, SEM observation revealed that the polysilicon grain size in both the first and second polysilicon layers was in the range of 300 nm to 500 nm. Compared to Comparative Example 1, the polysilicon grain size after heat treatment in Example 1 was smaller, indicating that the spacer layer helps suppress polysilicon grain growth during high-temperature heat treatment. A direct contact interface is formed between the first and second polysilicon layers at the location of the pores, which can provide additional charge recombination pathways.

[0096] Example 2 The difference between Example 2 and Example 1 is that the thickness of the spacer layer is adjusted to 20nm, while the other process parameters are the same as in Example 1.

[0097] During the etching step, the phosphoric acid solution temperature was maintained at 160°C, and the etching time was adjusted to 150 seconds. After the spacer layer deposition was completed, the wafer bow shape became approximately -20 μm. Due to the reduced tensile stress introduced by the decreased spacer layer thickness, the absolute value of this negative bow shape was less than that in Example 1. After etching, the wafer bow shape recovered to approximately -10 μm, and after the second polysilicon layer deposition was completed, the bow shape was finally adjusted to approximately 0 μm.

[0098] After heat treatment, SEM measurements showed that the grain size was in the range of 300 nm to 500 nm, consistent with the results of Example 1. This indicates that under the spacer layer thickness conditions used in Examples 1 and 2, the spacer layer can effectively block the merging of interlayer grains. Due to the thinner spacer layer thickness and smaller depth-to-width ratio of the pores, the filling degree of the pores by the second polysilicon layer can be improved, thus enhancing the formation quality of the direct contact interface.

[0099] Example 3 The difference between Example 3 and Example 1 is that the thickness of the spacer layer is adjusted to 100nm, while the other process parameters are the same as those in Example 1.

[0100] During the etching step, the phosphoric acid solution temperature was maintained at 160°C, and the etching time was adjusted to 8 minutes. Based on the etching rate of silicon nitride at this temperature, the average etching removal corresponding to 8 minutes of etching is approximately 16 nm to 80 nm. Due to the certain non-uniformity of the film thickness, in some local areas, the etching can penetrate the spacer layer to form a small number of through-holes, exposing part of the surface of the first polysilicon layer. This allows the subsequently formed second polysilicon layer to connect with the first polysilicon layer through the through-holes.

[0101] After the spacer layer was deposited, the wafer bow shape changed to approximately -45 μm; after etching, the wafer bow shape was restored to approximately -25 μm; after the second polysilicon layer was deposited, the wafer bow shape was adjusted to approximately -8 μm, still within ±10 μm. Because the number of through-holes formed in Example 3 was relatively small, the degree of stress release from etching on the spacer layer was relatively low, therefore the effect on controlling the wafer bow shape was weaker than in Examples 1 and 2.

[0102] After heat treatment, SEM measurements showed that the polysilicon grain size in the first and second polysilicon layers was in the range of 300 nm to 500 nm, indicating that under the spacer layer thickness conditions of Example 3, the spacer layer can still block the merging of cross-layer grains between the first and second polysilicon layers.

[0103] Example 4 The difference between Example 4 and Example 1 is that the temperature of the phosphoric acid solution was adjusted to 180°C and the etching time was adjusted to 30 seconds when etching the spacer layer. The other process parameters are the same as those in Example 1.

[0104] After heat treatment, SEM measurements showed that the grain size was in the range of 300 nm to 500 nm, consistent with the results of Example 1. This indicates that within the phosphoric acid solution temperature range of 140°C to 180°C, the silicon nitride spacer layer can be effectively etched to form pores while maintaining low damage to the first polysilicon layer. According to Table 1, when the phosphoric acid solution temperature is reduced to 140°C, the etching rate of silicon nitride is lower, thus allowing for a correspondingly longer etching time.

[0105] Comparative Example 1 Comparative Example 1 uses the direct growth method in related technologies to deposit a polycrystalline silicon charge cutoff layer of about 2.0 μm thickness on a single-crystal silicon substrate in one step. No spacer layer is set, no etching step is set, the deposition temperature is 900℃, the pressure is 50Pa, the silicon source gas is trichlorosilane, and the carrier gas is hydrogen.

[0106] After heat treatment, SEM measurements showed that the grain size was in the range of 400 nm to 650 nm, which was larger than the grain size after heat treatment in Examples 1 to 4. The wafer bow was approximately 35 μm.

[0107] The results of Comparative Example 1 show that, without the spacer layer, the polycrystalline silicon grain size after heat treatment is relatively large, and the wafer bowing is also relatively large.

[0108] Comparative Example 2 The difference between Comparative Example 2 and Example 1 is that the etching step is omitted. That is, after depositing a 40nm thick continuous silicon nitride film on the first polysilicon layer, no etching process is performed, and a second polysilicon layer is directly deposited on the continuous silicon nitride film. The remaining process parameters are the same as those in Example 1.

[0109] In Comparative Example 2, since no etching process was performed, the silicon nitride film remained continuous, and the second polysilicon layer was separated from the first polysilicon layer by a continuous silicon nitride film, with no direct contact interface between the two polysilicon layers.

[0110] After heat treatment, SEM measurements showed grain sizes in the range of 300 nm to 500 nm, similar to Example 1, indicating that the continuous silicon nitride film also helps to prevent cross-layer grain merging between the first and second polysilicon layers. However, since the two polysilicon layers are separated by a continuous silicon nitride film, there is no direct contact interface, and the charge recombination path density of the stacked structure is lower than that in Example 1. Regarding wafer bowing, since no etching was performed, the tensile stress of the silicon nitride was not released, and the bowing after the deposition of the second polysilicon layer was approximately -15 μm, exceeding the process requirement range of ±10 μm.

[0111] The comparison between Comparative Example 2 and Example 1 shows that after etching the spacer layer to form a hole, a direct contact interface can be formed between the first polysilicon layer and the second polysilicon layer, and some of the tensile stress in the spacer layer can be released, which is beneficial to improving the charge recombination capability of the stacked structure and controlling the wafer bow shape.

[0112] Table 2

[0113] The summary table above reveals the following patterns.

[0114] The comparison between Examples 1 to 4 and Comparative Example 1 shows that introducing a spacer layer between two polysilicon layers and forming holes through etching helps to suppress the growth of polysilicon grains during high-temperature heat treatment, keeping the grain size after heat treatment within the range of 300nm to 500nm. Comparative Example 1 did not have a spacer layer, and its polysilicon grain size after heat treatment was 400nm to 650nm, which is larger than the grain size after heat treatment in Examples 1 to 4, and the wafer bowing is relatively large.

[0115] The comparison between Example 1 and Comparative Example 2 shows that after etching the spacer layer to form a hole, a direct contact interface can be formed, and some of the tensile stress in the spacer layer can be released, which is beneficial to improving the charge recombination capability of the stacked structure and controlling the wafer bowing amount. When only the continuous spacer layer is retained without etching, although grain coarsening is suppressed, the direct contact interface is missing, and the tensile stress of silicon nitride is not released, and the wafer bowing amount exceeds the process allowable range.

[0116] The results of Examples 1 to 3 show that, under spacer layer thicknesses of 20 nm, 40 nm, and 100 nm, the spacer layer can block the merging of interlayer grains between the first and second polysilicon layers. In Example 3, due to the relatively small number of through-holes formed, the degree of stress release in the spacer layer is relatively low, therefore the effect of controlling the wafer bow shape is weaker than that in Examples 1 and 2.

[0117] A comparison of Examples 1 and 4 shows that selective etching of the spacer layer can be performed within a phosphoric acid solution temperature range of 140°C to 180°C. For example, a temperature of 160°C can balance etching rate and process stability.

[0118] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor wafer, characterized in that, include: Single-crystal silicon substrate; A first polycrystalline silicon layer is disposed on one side of the monocrystalline silicon substrate; A spacer layer is disposed on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate, and the spacer layer has a plurality of holes; and A second polysilicon layer is disposed on the side of the spacer layer away from the first polysilicon layer. The second polysilicon layer fills the plurality of holes and is connected to the first polysilicon layer through the plurality of holes.

2. The semiconductor wafer according to claim 1, characterized in that, The thickness of the first polycrystalline silicon layer is in the range of 0.5 μm to 1.5 μm. The thickness of the second polycrystalline silicon layer is in the range of 0.5 μm to 1.5 μm.

3. The semiconductor wafer according to claim 1, characterized in that, The grain size within the first polycrystalline silicon layer is in the range of 300 nm to 500 nm. The grain size within the second polycrystalline silicon layer is in the range of 300 nm to 500 nm.

4. The semiconductor wafer according to claim 1, characterized in that, The spacer layer comprises silicon nitride.

5. The semiconductor wafer according to claim 1, characterized in that, The thickness of the spacer layer is less than 500 nm.

6. The semiconductor wafer according to claim 1, characterized in that, The hole extends from the side of the spacer layer away from the first polysilicon layer to the side of the spacer layer closer to the first polysilicon layer. The walls of the hole are defined by the spacer layer. The bottom of the hole exposes a portion of the surface of the first polycrystalline silicon layer.

7. The semiconductor wafer according to any one of claims 1 to 6, characterized in that, The first polysilicon layer and the second polysilicon layer have compressive stress, and the spacer layer has tensile stress. The tensile stress of the spacer layer at least partially offsets the compressive stress of the first polysilicon layer and the second polysilicon layer to regulate the bow shape of the semiconductor wafer.

8. The semiconductor wafer according to any one of claims 1 to 6, characterized in that, The semiconductor wafer has a warping deformation toward the side of the monocrystalline silicon substrate.

9. The semiconductor wafer according to any one of claims 1 to 6, characterized in that, The bulk resistivity of the single-crystal silicon substrate is greater than 1000 Ω·cm.

10. A method for fabricating a semiconductor wafer, characterized in that, include: Provide single-crystal silicon substrates; A first polycrystalline silicon layer is formed on one side of the monocrystalline silicon substrate; A spacer layer is formed on the side of the first polycrystalline silicon layer away from the monocrystalline silicon substrate; The spacer layer is etched to create a plurality of holes in the spacer layer, the walls of the holes being defined by the spacer layer; and A second polysilicon layer is formed on the side of the spacer layer away from the first polysilicon layer. The second polysilicon layer fills the plurality of holes and is connected to the first polysilicon layer through the plurality of holes.

11. The method for preparing a semiconductor wafer according to claim 10, characterized in that, The first polysilicon layer and the second polysilicon layer have compressive stress, and the spacer layer has tensile stress. The tensile stress of the spacer layer at least partially offsets the compressive stress of the first polysilicon layer and the second polysilicon layer to regulate the bow shape of the semiconductor wafer.

12. The method for preparing a semiconductor wafer according to claim 10, characterized in that, The first polycrystalline silicon layer and the second polycrystalline silicon layer are formed by chemical vapor deposition, wherein the temperature of the chemical vapor deposition is 600°C to 1000°C, the pressure is 10Pa to 100Pa, and the silicon source gas includes trichlorosilane.

13. The method for preparing a semiconductor wafer according to claim 10, characterized in that, When forming the spacer layer, silicon nitride material is deposited on the surface of the first polycrystalline silicon layer using atomic layer deposition at a temperature of 300°C to 450°C, and trimethylaminosilane is used as the silicon source gas.

14. The method for preparing a semiconductor wafer according to claim 10, characterized in that, When etching the spacer layer, a phosphoric acid solution is used to perform wet etching on the spacer layer, and the temperature of the phosphoric acid solution is in the range of 140°C to 180°C.

15. The method for preparing a semiconductor wafer according to claim 14, characterized in that, The temperature of the phosphoric acid solution is 160°C.

16. The method for preparing a semiconductor wafer according to claim 10, characterized in that, The bulk resistivity of the single-crystal silicon substrate is greater than 1000 Ω·cm.

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