A semiconductor structure and a method of forming the same

Abstract

The application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer in sequence on the top surface of the substrate; forming a first via, the first via penetrating the second interlayer dielectric layer and exposing the etching stop layer; deepening the first via to form a second via, the second via penetrating the etching stop layer and the first interlayer dielectric layer; and forming a metal layer, the metal layer filling the first via and the second via. The application also provides a semiconductor structure. The semiconductor structure and the method for forming the same can improve the dielectric breakdown performance between the via and the metal layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of integrated circuits and the shrinking of critical dimensions, metal interconnects are becoming longer and the distance between metals is becoming smaller. In the reliability assessment of large-scale mass production, inter-metal dielectric-time dependent dielectric breakdown (IMD-TDDB) is becoming increasingly important and risky.

[0003] The dielectric breakdown over time (TDDB) between a via and a metal layer is more likely to fail than the dielectric breakdown over time between metal layers. Specifically, refer to... Figure 1 Connecting different metal layers ( Figure 1 The via 30 (which consists of the first metal layer 10 and the second metal layer 20) is generally an inverted trapezoid due to the etching process. During the overlay process of the via 30 and the metal line 101 in the first metal layer 10, even a slight deviation may cause the dielectric between the via 30 and the metal line 102 to fail early due to time breakdown.

[0004] Therefore, it is necessary to develop a semiconductor structure and its formation method to improve the dielectric breakdown performance between vias and metal layers over time. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor structure and a method for forming the same, so as to improve the dielectric breakdown performance of the via and the metal layer over time.

[0006] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a first interlayer dielectric layer, an etch stop layer, and a second interlayer dielectric layer sequentially stacked on the top surface of the substrate; forming a first via, the first via penetrating the second interlayer dielectric layer and exposing the etch stop layer; deepening the first via to form a second via, the second via penetrating the etch stop layer and the first interlayer dielectric layer; and forming a metal layer that fills the first via and the second via.

[0007] In some embodiments, the width of the first through hole gradually decreases from top to bottom, while the width of the second through hole remains constant from top to bottom.

[0008] In some embodiments, the thickness ratio of the first interlayer dielectric layer to the thickness of the second interlayer dielectric layer is 1:(0.2 to 5).

[0009] In some embodiments, the ratio of the width of the bottom of the first through hole to the width of the top of the first through hole is 1:(2-5).

[0010] In some embodiments, the method of forming the metal layer includes: forming a barrier layer that covers the sidewall of the second through-hole and the sidewall of the first through-hole; forming the metal layer that fills the second through-hole; and continuing to form the metal layer such that the metal layer covers and fills the first through-hole.

[0011] In some embodiments, the method of forming the barrier layer includes: forming the barrier layer covering the bottom surface and sidewall of the second through hole and the sidewall of the first through hole; and removing the barrier layer located on the bottom surface of the second through hole.

[0012] In some embodiments, the method of forming the metal layer that fills the second via includes electroless deposition.

[0013] In some embodiments, the method of forming the metal layer includes: forming a barrier layer that covers the bottom surface and sidewall of the second through hole and the sidewall of the first through hole; and forming the metal layer covering the barrier layer by electroplating, such that the metal layer fills the first through hole and the second through hole.

[0014] In some embodiments, the method for forming a semiconductor structure provided in this application further includes: before forming the first via: forming a hard mask layer, the hard mask layer covering the second interlayer dielectric layer; and forming a trench, the trench being located in the hard mask layer and the bottom of the trench exposing the second interlayer dielectric layer; and during the formation of the first via, etching the bottom of the trench to form the first via penetrating the second interlayer dielectric layer.

[0015] Secondly, embodiments of this application also provide a semiconductor structure, including: a substrate; a first interlayer dielectric layer, an etch stop layer, and a second interlayer dielectric layer sequentially stacked on the top surface of the substrate; a first via, the first via penetrating the second interlayer dielectric layer, the width of the first via gradually decreasing from the top to the bottom; a second via, the second via penetrating the etch stop layer and the first interlayer dielectric layer, the width of the second via remaining consistent from the top to the bottom; and a metal layer, the metal layer filling the first via and the second via.

[0016] In some embodiments, the width of the first through hole gradually decreases from top to bottom, while the width of the second through hole remains constant from top to bottom.

[0017] In some embodiments, the thickness ratio of the first interlayer dielectric layer to the thickness of the second interlayer dielectric layer is 1:(0.2 to 5).

[0018] The beneficial effects of the semiconductor structure and its formation method provided in this application include, but are not limited to, the following:

[0019] The semiconductor structure provided in this application has a first through-hole and a second through-hole that extend vertically. The width of the first through-hole gradually decreases from the top to the bottom, while the width of the second through-hole remains constant from the top to the bottom. The first through-hole and the second through-hole together function as a via. Compared with the inverted trapezoidal through-hole in the prior art, the second through-hole near the lower metal layer in this application is cylindrical. The boundary of the sidewall of the second through-hole is perpendicular to the top surface of the lower metal layer. Even if a deviation occurs during the alignment process, it is not easy to cause the dielectric between the through-hole and the lower metal layer to break down prematurely.

[0020] In the semiconductor structure provided in this application, the contact area between the bottom of the via (i.e., the bottom of the second via) and the metal layer is larger than that between the bottom of the via and the metal layer in the prior art, which reduces the resistance between the via and the metal layer and also reduces the probability of an open circuit between the via and the metal layer.

[0021] In addition, this application also provides a method of filling the second through hole with metal from bottom to top, which can effectively avoid void defects caused by the premature closure of the metal growing along the sidewall of the second through hole during electroplating deposition. Attached Figure Description

[0022] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0023] in:

[0024] Figure 1 This is a schematic diagram of a semiconductor structure in the prior art;

[0025] Figures 2-32 This is a schematic diagram of the formation process of a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0026] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0027] This application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first interlayer dielectric layer, an etch stop layer, and a second interlayer dielectric layer sequentially stacked on the top surface of the substrate; forming a first via, the first via penetrating the second interlayer dielectric layer and exposing the etch stop layer; deepening the first via to form a second via, the second via penetrating the etch stop layer and the first interlayer dielectric layer; and forming a metal layer that fills the first via and the second via.

[0028] The method for forming the semiconductor structure provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.

[0029] refer to Figures 2-4 Substrate 100 is provided. Wherein, Figure 2 This is a top view of the substrate 100; Figure 3 For the substrate 100 along Figure 2 The cross-sectional view along direction AA is shown. Figure 4 This is a cross-sectional view of the substrate 100 along the BB direction.

[0030] It should be noted that in the following figures, those marked with AA are cross-sectional views of the substrate 100 (i.e., the semiconductor structure) along the AA direction; those marked with BB are cross-sectional views of the substrate 100 (i.e., the semiconductor structure) along the BB direction; and those without AA or BB markings are top views of the substrate 100 (i.e., the semiconductor structure). For the sake of brevity, this will not be further elaborated in the subsequent description.

[0031] In some embodiments, the substrate 100 includes a dielectric substrate layer 110 and a first metal layer 120 located in the dielectric substrate layer 110.

[0032] In some embodiments, the material of the dielectric substrate 110 includes a material having an ultra-low dielectric constant K, such as SiOC, SiCOH, or a combination thereof with a dielectric constant of 2.2 to 2.4.

[0033] The first metal layer 120 is any metal layer of the metal interconnect structure in the subsequent process (except for the last metal layer).

[0034] In some embodiments, reference Figure 2 The first metal layer 120 is in the Y direction along its length.

[0035] In some embodiments, the material of the first metal layer 120 includes copper.

[0036] refer to Figures 5-7 A first interlayer dielectric layer 210, an etch stop layer 220, and a second interlayer dielectric layer 230 are formed on the top surface of the substrate 100 in sequence.

[0037] In some embodiments, prior to forming the first interlayer dielectric layer 210, a dielectric barrier layer 130 is formed on the top surface of the substrate 100.

[0038] In some embodiments, the dielectric barrier layer 130 is made of doped silicon carbide (NDC).

[0039] In some embodiments, the material of the first interlayer dielectric layer 210 includes SiOC, SiCOH, SiO2, SiCOHF, or a combination thereof.

[0040] In some embodiments, the material of the etching stop layer 220 includes silicon nitride or tantalum nitride.

[0041] In some embodiments, the material of the second interlayer dielectric layer 230 includes SiOC, SiCOH, SiO2, SiCOHF, or a combination thereof.

[0042] In some embodiments, the thickness ratio of the first interlayer dielectric layer 210 to the thickness of the second interlayer dielectric layer 230 is 1:(0.2 to 5), for example, 1:0.2, 1:0.5, 1:1, 1:3 or 1:5.

[0043] Continue to refer to Figures 5-7 A hard mask layer 300 is formed, which covers the second interlayer dielectric layer 230.

[0044] In some embodiments, the hard mask layer 300 includes a first hard mask layer 310 and a second hard mask layer 320 sequentially stacked on the top surface of the second interlayer dielectric layer 230. In some embodiments, the material of the first hard mask layer 310 includes TiN; the material of the second hard mask layer includes SiOC.

[0045] refer to Figures 5-10 A trench 330 is formed, the trench 330 being located in the hard mask layer 300 and the bottom of the trench 330 exposing the second interlayer dielectric layer 230.

[0046] In some embodiments, the groove 330 includes a first groove 331 and a second groove 332. In some embodiments, the length direction of the first groove 331 and the second groove 332 is parallel to the AA direction.

[0047] In some embodiments, the method of forming the first trench 331 and the second trench 332 includes photolithography. Specifically, refer to Figure 5-7 A first photolithography layer 400 is formed on the top surface of the hard mask layer 300. The first photolithography layer 400 includes a first organic carbon layer (ODL) 410, a first anti-reflective coating (SiARC) 420, and a first photoresist layer (PR) 430 sequentially stacked on the top surface of the hard mask layer 300. The first photoresist layer 430 has patterns 441 and 442 formed therein, respectively for forming the first trench 331 and the second trench 332. Then, referring to… Figure 8-10 The first trench 331 and the second trench 332 are formed by etching in the hard mask layer 300, and the first photolithography layer 400 is removed.

[0048] refer to Figures 11-16 The bottom of the trench 330 is etched to form a first via 231 penetrating the second interlayer dielectric layer 230, as referenced. Figures 14-16 The first through hole 231 is approximately frustum-shaped, and therefore appears as an inverted trapezoid in the cross-sectional view in the AA or BB direction.

[0049] In some embodiments, the number of first through holes 231 is multiple, and the multiple first through holes 231 are arranged at intervals along the length direction of the first groove 331 and the second groove 332.

[0050] In some embodiments, the method of forming the first via 231 includes photolithography. Specifically, refer to... Figure 11-13 A second photolithography layer 500 is formed on the top surface of the hard mask layer 300 and the second interlayer dielectric layer 230. The second photolithography layer 500 includes a second organic carbon layer 510, a second anti-reflective coating 520, and a second photoresist layer 530 stacked sequentially. The second photoresist layer 530 has a pattern 531 formed therein for forming the first via 231. Then, referring to… Figure 14-16 The first through-hole 231 is formed by etching, and the second photolithography layer 500 is removed.

[0051] In some embodiments, the method of etching to form the first via 231 includes anisotropic etching.

[0052] In some embodiments, the ratio of the width of the bottom of the first through hole 231 to the width of the top of the first through hole 231 is 1:(1.5~3), for example 1:1.5, 1:2, 1:2.5 or 1:3.

[0053] refer to Figure 17 and 18 The first through hole 231 is deepened to form a second through hole 211. The second through hole 211 penetrates the etched stop layer 220 and the first interlayer dielectric layer 210. The second through hole is cylindrical and the width of the second through hole 211 remains consistent from top to bottom.

[0054] In some embodiments, the width of the second through hole 211 is approximately the same as the width of the bottom of the first through hole 231.

[0055] In existing technologies, the ratio of the width of the bottom of a via to the width of the top is generally 1:(3.5~5). To ensure the dielectric breakdown performance between metal layers over time, the standard size of the top of the via is not set too large. This results in a limited contact area between the bottom of the via and the underlying metal layer, causing excessive resistance (Rc) between the via and the metal layer. In addition, misalignment during registration can easily lead to an open circuit between the via and the metal layer.

[0056] In this application, the through holes are configured as a first through hole 231 and a second through hole 211 that are connected vertically. The first through hole 231 is configured as an inverted trapezoid, and the ratio of the width of the bottom of the first through hole 231 to the width of the top of the first through hole 231 is 1:(1.5~3). The width of the second through hole 211 is consistent from top to bottom and is approximately the same as the width of the bottom of the first through hole 231. When the size of the top of the through hole is the same (i.e., the size of the top of the first through hole 231 is the same as the size of the top of the through hole in the prior art), the contact area between the bottom of the through hole (i.e. the bottom of the second through hole 211) and the metal layer in this application is larger than the contact area between the bottom of the through hole and the metal layer in the prior art, which reduces the resistance between the through hole and the metal layer and reduces the probability of an open circuit between the through hole and the metal layer.

[0057] In some embodiments, the method of deepening the first via 231 to form the second via 211 includes anisotropic etching.

[0058] The second through hole 211 has a consistent width from top to bottom, that is, the second through hole 211 is cylindrical. The boundary of the sidewall of the second through hole 211 is perpendicular to the top surface of the first metal layer 120. The closest adjacent metal position is between two adjacent metal lines of the first metal layer 120 rather than between the first metal layer 120 and the second through hole 211. Even if a deviation occurs during the alignment process, it is not easy to cause the dielectric between the second through hole 211 and the first metal layer 120 to fail prematurely due to breakdown over time.

[0059] refer to Figure 17 and 18 During the etching process to form the second via 211, the second interlayer dielectric layer 230, which is not covered by the hard mask layer 300, is simultaneously etched, forming a third trench 232 on the top of the second interlayer dielectric layer 230.

[0060] refer to Figures 19-24 A second metal layer 700 is formed, which fills the first through hole 231, the second through hole 211 and the third trench 232.

[0061] In some embodiments, the method of forming the second metal layer 700 includes electroplating.

[0062] Specifically, in some embodiments, the electroplating includes: [reference] Figure 19 and 20 A barrier layer 600 is formed, which covers the sidewalls and bottom surface of the second via 211, the sidewalls of the first via 231, the surface of the third trench 232, the top surface of the second interlayer dielectric layer 230, and the top surface of the first hard mask layer 310 (the second hard mask layer 320 is removed simultaneously when the second via 211 is etched); Reference Figure 21 and 22 The second metal layer 700 is formed by electroplating on the surface of the barrier layer 600, so that the second metal layer 700 fills the first through hole 231, the second through hole 211 and the third trench 232; and, referring to Figure 23 and 24 The second metal layer 700 is planarized so that the top surface of the second metal layer 700 is flush with the top surface of the second interlayer dielectric layer 230.

[0063] In some embodiments, after forming the barrier layer 600 and before forming the second metal layer 700, a seed layer (not shown) is further formed, the seed layer covering the top surface of the barrier layer 600.

[0064] In some embodiments, the method for planarizing the second metal layer 700 includes chemical mechanical polishing.

[0065] refer to Figures 25-32 In other embodiments, the method of forming the metal layer includes: referring to Figure 25 and 26 A barrier layer 800 is formed, which covers the sidewalls of the second through-hole 211, the sidewalls of the first through-hole 231, the surface of the third trench 232, the top surface of the second interlayer dielectric layer 230, and the top surface of the first hard mask layer 310; Reference Figure 27 and 28 This forms the second metal layer 700 that fills the second through-hole 211; Reference Figure 29 and 30 Continue forming the second metal layer 700, such that the second metal layer 700 covers and fills the first through-hole 231 and the third trench 232; and, refer to Figure 31 and 32 The second metal layer 700 is planarized so that the top surface of the second metal layer 700 is flush with the top surface of the second interlayer dielectric layer 230.

[0066] In some embodiments, the method of forming the barrier layer 800 includes: forming the barrier layer 800 covering the bottom surface and sidewall of the second through hole 211 and the sidewall of the first through hole 231; and removing the barrier layer 800 located on the bottom surface of the second through hole 211.

[0067] In some embodiments, the method of forming the barrier layer 800 covering the bottom surface and sidewall of the second through-hole 211 and the sidewall of the first through-hole 231 includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a combination thereof.

[0068] In some embodiments, the method for removing the barrier layer 800 located on the bottom surface of the second via 211 includes physical etching, chemical etching, or a combination thereof.

[0069] In some embodiments, the method for forming the second metal layer 700 filling the second via 211 includes growing the second metal layer 700 from bottom to top using an electroless deposition process. Compared to electroplating, electroless deposition involves direct nucleation of the second metal layer 700 on the surface of the first metal layer 120 via a reduction reaction of a Cu precursor, followed by vertical growth from bottom to top. This method is more convenient, facilitates metal deposition in small spaces, and the bottom-up formation process effectively avoids void defects caused by premature closure of the metal growing along the sidewall of the second via 211 during electroplating deposition.

[0070] In some embodiments, the method for further forming the metal layer includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, and electroplating. The first via 231 is an inverted trapezoid with a small depth-to-width ratio, requiring a lower step coverage in the deposition process. Using electroplating to further form the second metal layer 700 to fill the first via 231 can improve deposition efficiency while meeting quality requirements.

[0071] In some embodiments, the method for planarizing the second metal layer 700 includes chemical mechanical polishing.

[0072] This application also provides a semiconductor structure, see reference. Figure 23 or Figure 31 The semiconductor structure includes: a substrate 100, the substrate 100 including a dielectric substrate layer 110 and a first metal layer 120 located in the dielectric substrate layer 110; a first interlayer dielectric layer 210, an etch stop layer 220 and a second interlayer dielectric layer 230 stacked sequentially on the top surface of the substrate 100; a first via 231 penetrating the second interlayer dielectric layer 230, the width of the first via 231 gradually decreasing from top to bottom; a second via 211 penetrating the etch stop layer 220 and the first interlayer dielectric layer 210, the width of the second via 211 remaining constant from top to bottom; and a second metal layer 700 filling the first via 231 and the second via 211.

[0073] It should be noted that, Figure 23 Or in the semiconductor structure shown in 31, and Figures 2 to 23 The semiconductor structure shown is formed using methods that share some conventional structures. Therefore, for the sake of brevity, some repetitive conventional structures will not be described again here.

[0074] In some embodiments, the thickness ratio of the first interlayer dielectric layer 210 to the thickness of the second interlayer dielectric layer 230 is 1:(0.2 to 5), for example, 1:0.2, 1:0.5, 1:1, 1:3 or 1:5.

[0075] The beneficial effects of the semiconductor structure and its formation method provided in this application include, but are not limited to, the following:

[0076] The semiconductor structure provided in this application has a first through-hole and a second through-hole that extend vertically. The width of the first through-hole gradually decreases from the top to the bottom, while the width of the second through-hole remains constant from the top to the bottom. The first through-hole and the second through-hole together function as a via. Compared with the inverted trapezoidal through-hole in the prior art, the second through-hole near the lower metal layer in this application is cylindrical. The boundary of the sidewall of the second through-hole is perpendicular to the top surface of the lower metal layer. Even if a deviation occurs during the alignment process, it is not easy to cause the dielectric between the through-hole and the lower metal layer to break down prematurely.

[0077] In the semiconductor structure provided in this application, the contact area between the bottom of the via (i.e., the bottom of the second via) and the metal layer is larger than that between the bottom of the via and the metal layer in the prior art, which reduces the resistance between the via and the metal layer and also reduces the probability of an open circuit between the via and the metal layer.

[0078] In addition, this application also provides a method of filling the second through hole with metal from bottom to top, which can effectively avoid void defects caused by the premature closure of the metal growing along the sidewall of the second through hole during electroplating deposition.

[0079] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0080] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0081] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0082] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first interlayer dielectric layer, an etching stop layer, and a second interlayer dielectric layer are formed and stacked sequentially on the top surface of the substrate. A first via is formed, which penetrates the second interlayer dielectric layer and exposes the etch stop layer; The first via is deepened to form a second via, which penetrates the etched stop layer and the first interlayer dielectric layer. as well as A metal layer is formed, which fills the first through-hole and the second through-hole.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The width of the first through hole gradually decreases from top to bottom, while the width of the second through hole remains constant from top to bottom.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The thickness ratio of the first interlayer dielectric layer to the thickness of the second interlayer dielectric layer is 1:(0.2~5).

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The ratio of the width of the bottom of the first through hole to the width of the top of the first through hole is 1:(2~5).

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The method of forming the metal layer includes: A barrier layer is formed, which covers the sidewall of the second through hole and the sidewall of the first through hole; Forming the metal layer that fills the second through-hole; and Continue forming the metal layer until it covers and fills the first through-hole.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The method of forming the barrier layer includes: Forming the barrier layer covering the bottom surface and sidewall of the second through-hole, and the sidewall of the first through-hole; and Remove the barrier layer located at the bottom surface of the second through hole.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The method for forming the metal layer that fills the second via includes electroless deposition.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of forming the metal layer includes: A barrier layer is formed, which covers the bottom surface and sidewall of the second through hole and the sidewall of the first through hole; The metal layer covering the barrier layer is formed by electroplating, thereby filling the first through hole and the second through hole.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: Before the formation of the first through hole: A hard mask layer is formed, which covers the second interlayer dielectric layer; as well as A trench is formed, the trench being located within the hard mask layer and the bottom of the trench exposing the second interlayer dielectric layer; When forming the first via, the bottom of the trench is etched to form the first via penetrating the second interlayer dielectric layer.

10. A semiconductor structure, characterized in that, include: Substrate; A first interlayer dielectric layer, an etching stop layer, and a second interlayer dielectric layer are sequentially stacked on the top surface of the substrate. The first via penetrates the second interlayer dielectric layer; A second via, the second via penetrating the etched stop layer and the first interlayer dielectric layer; and A metal layer that fills the first through-hole and the second through-hole.

11. The semiconductor structure according to claim 10, characterized in that, The width of the first through hole gradually decreases from top to bottom, while the width of the second through hole remains constant from top to bottom.

12. The semiconductor structure according to claim 11, characterized in that, The thickness ratio of the first interlayer dielectric layer to the thickness of the second interlayer dielectric layer is 1:(0.2~5).

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