Advanced package power distribution network architecture

Abstract

The application discloses a power distribution network structure of advanced packaging and relates to the technical field of integrated circuits. A specific implementation scheme is that the structure comprises a silicon interposer and a target metal layer located above the silicon interposer and closest to the silicon interposer; wherein the target metal layer is provided with first grounding bumps and first power supply bumps; the first grounding bumps are regularly aligned in a horizontal direction and a vertical direction in the plane of the target metal layer, forming a grid-shaped distribution, and each first power supply bump is surrounded by a plurality of first grounding bumps; in the target metal layer, a grounding network is a grid-shaped network formed according to the distribution rule of the first grounding bumps, and a power supply network is formed based on the first power supply bumps; and a deep trench capacitor (DTC) embedded in the silicon interposer is connected to the grounding network and the power supply network through the shortest path respectively.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and specifically to an advanced packaged power distribution network structure. Background Technology

[0002] As the computing power requirements of artificial intelligence (AI) chips continue to increase, the number of processor cores continues to rise, and the high-speed bus and memory interface frequently switch between light and heavy loads, causing the power supply current to fluctuate drastically in the frequency band of hundreds of MHz to GHz, resulting in significant voltage fluctuations and power supply noise, which in turn affects chip performance.

[0003] Deep trench capacitors (DTCs) are introduced into silicon interposers to improve decoupling capabilities due to their high capacitance density. However, the actual performance of DTCs is still limited by the physical arrangement of bumps and the routing of power and ground networks. Even if the capacitance values ​​can be stacked significantly, their effective bandwidth is generally difficult to exceed 100MHz, and they cannot effectively suppress current fluctuations at higher frequencies. Summary of the Invention

[0004] This application provides an advanced packaged power distribution network structure. The specific solution is as follows:

[0005] According to one aspect of this application, an advanced packaged power distribution network structure is provided, comprising: A silicon interposer and a target metal layer located on top of and closest to the silicon interposer; wherein the target metal layer has a first ground bump and a first power bump; The first grounding bumps are regularly aligned in the horizontal and vertical directions within the plane of the target metal layer, forming a grid-like distribution, and each first power bump is surrounded by multiple first grounding bumps; In the target metal layer, the grounding network is a grid-like network formed by wiring according to the distribution pattern of the first grounding bumps, and the power network is formed based on the wiring of the first power bumps; The deep trench capacitors (DTCs) embedded in the silicon interposer are connected to the ground network and the power network via the shortest path, respectively.

[0006] According to another aspect of this application, a chip is provided that is powered by the advanced packaged power distribution network structure described in one of the above embodiments.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0008] The accompanying drawings are provided for a better understanding of this solution and do not constitute a limitation of this application. Wherein: Figure 1 A schematic diagram of an advanced packaged power distribution network structure provided in an embodiment of this application; Figure 2 A schematic diagram of an advanced packaged power distribution network structure provided in another embodiment of this application; Figure 3 This is a cross-sectional schematic diagram of an advanced packaged power distribution network structure provided in an embodiment of this application. Detailed Implementation

[0009] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of this application, including various details to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0010] It should be noted that the acquisition, storage, use, and processing of data in this application comply with the relevant provisions of national laws and regulations and do not violate public order and good morals.

[0011] The advanced packaged power distribution network structure of this application embodiment is described below with reference to the accompanying drawings.

[0012] Figure 1 This is a schematic diagram of an advanced packaged power distribution network structure provided in an embodiment of this application. The advanced packaged power distribution network structure can be understood as the structure of a power distribution network packaged using advanced packaging technology. This power distribution network structure may include a silicon interposer, a target metal layer located on top of the silicon interposer and closest to it, etc.

[0013] This diagram can be understood as a planar schematic of the target metal layer in a power distribution network structure. For example... Figure 1 As shown, the target metal layer has multiple bumps, which may include a first ground bump 111, a first power bump 112, etc. Figure 1 The dashed circle in the diagram represents the first grounding protrusion 111, and the solid circle represents the first power supply protrusion 112.

[0014] For example, the voltage domains of different first power supply bumps on the target metal layer may be the same or different, and there is no limitation thereto.

[0015] For example, the space beneath the silicon interposer may be a packaging substrate, which contains a power layer and a ground layer to provide a stable DC voltage.

[0016] For example, the first ground bump 111 is used to receive a ground signal from the package substrate, and the first power bump 112 is used to receive a power signal from the package substrate.

[0017] For example, the first grounding bumps 111 are regularly aligned in the horizontal and vertical directions in the plane of the target metal layer to form a grid-like distribution, and each first power bump 112 is surrounded by multiple first grounding bumps 111.

[0018] As an example, the first ground bumps 111 are aligned horizontally and vertically in the plane of the target metal layer. In the horizontal direction, a row of first power bumps 112 can be provided between every two rows of first ground bumps 111. In the vertical direction, each row of first ground bumps 111 is adjacent to a row of first power bumps 112 on the left and to the right, so that each first power bump 112 is surrounded by multiple first ground bumps 111.

[0019] In the target metal layer, the grounding network can be a grid-like network formed by wiring according to the distribution pattern of the first grounding bumps 111, and the power network can be formed based on the wiring of the first power bumps 112.

[0020] As an example, a distributed "grid" structure, or grid-like distribution, can be formed on the horizontal and vertical interconnecting lines based on the center coordinates of the first grounding protrusion 111, such as... Figure 1 The solid lines in the diagram show the routing of the first power bump 112 in the target metal layer, which is shown as dashed lines, realizing a structure in which the power bump is surrounded by the ground bump.

[0021] It should be noted that, Figure 1 Along the horizontal direction, there are three solid lines passing through the first grounding protrusion 111 in the same row. Along the vertical direction, there are also three solid lines passing through the first grounding protrusion 111 in the same column. The number of grounding network lines is only an example and can be one or more. This application does not limit the number of grounding network lines.

[0022] It should be noted that, Figure 1 Along the horizontal direction, there are three dashed lines passing through the first power supply protrusion 112 in the same column. The number of power network lines is only an example and can be one or more. This application does not limit the number of power network lines.

[0023] In this application, at least one DTC is embedded within the silicon interposer.

[0024] In some embodiments, the DTCs embedded in the silicon interposer can be arranged in a regular two-dimensional array, wherein the row direction extends horizontally and the column direction extends vertically.

[0025] As an example, such as Figure 1 As shown, the DTCs 120 embedded in the silicon interposer can be arranged in a regular two-dimensional array. Each row of DTCs 120 is located between the first ground bump 111 and the first power bump 112 of the two adjacent rows, and the row of DTCs 120 can correspond to the first power bump 112 of the adjacent row. This allows for the deployment of large-area distributed DTCs, ensuring a seamless interconnection path for each DTC with ultra-low power distribution network impedance.

[0026] In other embodiments, for one or more grids (or well grids) in a grounding network, one or more DTCs may be laid between the first grounding bump 111 and the first power bump 112 in the grid.

[0027] It should be noted that, Figure 1 The DTC deployment method in the example is only for illustration, for example, Figure 1 A DTC may not be laid at a certain DTC location, or multiple DTCs may be laid. The specific laying of DTCs can be based on actual needs, and this application does not impose any restrictions on this.

[0028] In this application, the DTC 120 embedded in the silicon interposer can be connected to the ground network and power network in the target metal layer through the shortest path, respectively.

[0029] For example, such as Figure 1 As shown, the power electrode 121 of the DTC 120 can be connected to the power network in the target metal layer via the shortest path, and the ground electrode 122 of the DTC 120 can be connected to the ground network in the target metal layer via the shortest path.

[0030] like Figure 1 As shown, a low-impedance connection from the DTC 120 to the power network and ground network interconnects can be achieved through the target metal layer, forming distributed external interconnect electrodes in the horizontal and vertical directions.

[0031] from Figure 1 As can be seen, in the target metal layer, DTC 120 connects the power electrode 121 and the ground electrode 122 to the corresponding power network and ground network through the shortest path, realizing low impedance interconnection of all distributed DTCs.

[0032] It should be noted that, Figure 1 One of the DTCs 120 can be a structural example of a DTC, or it can be an array of multiple DTCs. Figure 1 The DTC 120 in this application is merely an example of a capacitor electrode, and this application does not limit the process structure of the DTC.

[0033] In this application, power can be supplied to a chip located above the silicon interposer based on this power distribution network structure. This chip can be an AI chip or other types of chips; there is no limitation on the specific type.

[0034] In this embodiment, based on the first ground bumps arranged in a grid pattern in the horizontal and vertical directions within the target metal layer, and each first power bump surrounded by multiple first ground bumps, a highly symmetrical and densely distributed ground and power network is constructed. This can significantly shorten the return path between power and ground, reduce the parasitic inductance and path resistance of the power distribution network, and the DTC is directly connected to the grid-like ground and power network with the shortest path, reducing the path impedance of high-frequency transient currents. This achieves low impedance and high bandwidth power supply capability, which can significantly improve the power supply integrity and system stability of the chip under high load conditions.

[0035] In some embodiments of this application, the grounding network may be formed by interconnecting the first grounding bumps in the horizontal and vertical directions, respectively.

[0036] For example, based on the distribution pattern of the first grounding bumps, the first grounding bumps on the target metal layer can be interconnected in the horizontal and vertical directions to form a grounding network.

[0037] Since adjacent first power supply bumps in the same voltage domain within the same row can be interconnected, or each first power supply bump can be wired separately, and the wiring of the first power supply bumps may affect the wiring of the ground bumps, for example, a grounding network can be formed by interconnecting the first ground bumps in the horizontal and vertical directions based on the wiring of the first power supply bumps.

[0038] As an example, if adjacent first power bumps in the same voltage domain are interconnected in any row, then for the first ground bump, except for one or more columns of first ground bumps that are perpendicular to the interconnects of the adjacent first power bumps, the first ground bumps in the other columns are interconnected in the vertical direction.

[0039] For example, suppose Figure 2 In the second row, the voltage domains of the first power supply bumps from left to right are P1, P2, P2, P1, P2, P2, P1, and in the fourth row, the voltage domains of the first power supply bumps from left to right are P3, P2, P2, P3, P2, P2, P3. The first power supply bumps with adjacent voltage domains of P2 in the second row are interconnected, and the first power supply bumps with adjacent voltage domains of P2 in the fourth row are interconnected. Therefore, the first ground bumps in the second column are not interconnected, and the ground bumps in the fifth column are not interconnected. The ground bumps in other columns are interconnected in the vertical direction.

[0040] As another example, if each first power bump is wired separately, then each row of first ground bumps is interconnected horizontally and each column of first ground bumps is interconnected vertically to form a grounding network.

[0041] It should be noted that, in the same horizontal direction, adjacent first power supply bumps in the same voltage domain may or may not be interconnected; there is no limitation on this. That is, among the first power supply bumps in the same row, adjacent first power supply bumps in the same voltage domain may or may not be interconnected.

[0042] In this embodiment, the grounding network is based on the layout of the first power bumps and is obtained by interconnecting the first ground bumps in the horizontal and vertical directions, thereby constructing a grid-like grounding network in the target metal layer that matches the power distribution. This cooperative wiring method makes the grounding path tightly surround the power bumps, which can not only reduce the impedance of the overall power distribution network, but also effectively suppress voltage fluctuations and electromagnetic interference caused by high-frequency transient currents, thereby enhancing the power integrity of the chip in high-power or high-speed switching scenarios.

[0043] In this embodiment of the application, a continuous, low-impedance two-dimensional grid-like grounding network is constructed by interconnecting the first grounding bumps along the horizontal and vertical directions to form a grounding network. This structure can effectively reduce the parasitic resistance and inductance of the grounding loop and improve the overall stability of the power distribution network.

[0044] In one embodiment of this application, a power network can be formed by interconnecting the first power bumps on the target metal layer according to the target rules. That is, the power network can be formed by interconnecting the first power bumps on the target metal layer according to the target rules.

[0045] For example, the target rule may include: first power bumps that are adjacent and in the same voltage domain in the same horizontal direction are interconnected to form a continuous power transmission path.

[0046] This ensures that power bumps in the same voltage domain on the target metal layer are aggregated into a continuous power supply path in the horizontal direction, effectively reducing voltage drop and current congestion caused by wiring breaks or detours, and improving the uniformity and stability of power distribution. At the same time, this structured interconnection method simplifies the topology design of the power distribution network and enhances the feasibility of the manufacturing process, thereby improving the overall power supply efficiency and performance robustness of the chip or package system.

[0047] As an example, such as Figure 2 As shown, two first power supply bumps that are adjacent to each other and in the same voltage domain P2 are interconnected in the same horizontal direction.

[0048] For example, the target rule can also include separate routing on each first power bump. For instance... Figure 1 As shown, each first power bump 112 is individually wired.

[0049] Understandably, in the same horizontal direction, only adjacent first power supply bumps in the same voltage domain can be interconnected.

[0050] It should be noted that, in the same horizontal direction, adjacent first power supply bumps in the same voltage domain may or may not be interconnected, and there is no limitation on this.

[0051] It should be noted that the above target rules are merely examples, and target rules can be set according to actual needs. This application does not impose any restrictions on them.

[0052] In this embodiment, the first power bumps on the target metal layer are interconnected according to the target rules to form a power network, which can meet the chip power supply requirements of different scenarios.

[0053] In one embodiment of this application, a plurality of bumps are provided on the lower surface of the silicon interposer, including a second ground bump and a second power bump.

[0054] The second ground bump and the second power bump constitute an electrical connection between the silicon interposer and the packaging substrate. The second ground bump is used to receive a ground signal provided by the packaging substrate, and the second power bump is used to receive a power signal provided by the packaging substrate.

[0055] For example, the second ground bump corresponds one-to-one with the first ground bump in the vertical direction, and the second power bump corresponds one-to-one with the first power bump in the vertical direction. Alternatively, the first ground bump can be regarded as the vertical projection of the second ground bump onto the target metal layer, and the first power bump can be regarded as the vertical projection of the second power bump onto the target metal layer.

[0056] Based on this, the distribution pattern of the second ground bump is consistent with that of the first ground bump, and the distribution pattern of the second power bump is consistent with that of the first power bump. That is, the second ground bumps are regularly aligned and arranged in the horizontal and vertical directions in the plane of the lower surface of the silicon interposer, forming a grid-like distribution, with each second power bump surrounded by multiple second ground bumps.

[0057] In this embodiment, the one-to-one correspondence between the upper and lower protrusions ensures signal integrity and power supply stability, avoiding voltage disturbances or electromagnetic interference caused by misalignment or cross-domain connections.

[0058] For example, the second ground bump can be electrically connected to the first ground bump through a through-silicon via (or silicon via) through the silicon interposer.

[0059] Among them, a through-silicon via is a vertical conductive via that penetrates the entire silicon interposer and can be used to achieve electrical connections between upper and lower layers in the silicon interposer.

[0060] As an example, the first ground bump is located on the target metal layer, and its planar position is aligned with the second ground bump, forming a continuous ground path from the package substrate through the second ground bump, through the silicon via through the silicon interposer to the target metal layer.

[0061] In this application, the second ground bump penetrates the silicon interposer through a through-silicon via (TSV) and is electrically connected to the first ground bump. Similarly, the second power bump penetrates the silicon interposer through a TSV and is electrically connected to the first power bump. This structure fully utilizes the short vertical path characteristic of TSVs, significantly reducing parasitic resistance and inductance in the power distribution network. This effectively suppresses dynamic voltage drop and synchronous switching noise, thereby improving power supply stability. Furthermore, the direct penetration of the TSV through the silicon interposer enables a one-to-one electrical connection between the upper and lower bumps, which not only improves interconnect accuracy and integration density but also avoids the additional delays and losses caused by traditional wire bonding or rewiring layers. This provides an efficient and reliable power and ground transmission foundation for high-performance, high-bandwidth chip packaging.

[0062] For example, the second power bump penetrates the silicon interposer via a through-silicon via (TSV) and is electrically connected to the power bump on the chip side via multiple metal layers, including the target metal layer. This multi-layered metal-coordinated wiring enhances the redundancy and current-carrying capacity of the power network, significantly reducing dynamic noise. Furthermore, this vertical-horizontal hybrid interconnect architecture, while ensuring electrical performance, improves the layout flexibility and process compatibility of power paths, providing solid support for the stable operation of high-power, high-performance chips in advanced packages.

[0063] For example, the second ground bump can penetrate the silicon interposer through a through-silicon via and be electrically connected to the ground bump on the chip side via multiple metal layers, including the target metal layer.

[0064] Therefore, by utilizing the vertical short-path characteristics of through-silicon vias (TSVs), the ground return current path can be significantly shortened. Simultaneously, the efficient horizontal convergence and dispersion of return current through multi-layered metal effectively reduces the parasitic inductance and resistance of the grounding network. This not only significantly suppresses ground bounce and common-mode noise, improving signal integrity and timing stability, but also enhances the overall robustness of the power-to-ground loop. The power bump on the chip side can be understood as the chip's power supply bump. The ground bump on the chip side can be understood as the chip's ground bump.

[0065] For example, the electrical connection to the power bump on the chip side via multiple metal layers, including the target metal layer, can be understood as connecting to the power bump on the chip side sequentially from bottom to top, passing through the target metal and other metal layers.

[0066] For example, the electrical connection to the ground bump on the chip side via multiple metal layers, including the target metal layer, can be understood as sequentially connecting to the ground bump on the chip side from bottom to top, passing through the target metal and other metal layers.

[0067] As an example, the second power bump can receive a power signal from the package substrate, pass through the silicon interposer via a through-silicon via, and transmit the power signal to the power bump on the chip side via multiple metal layers including the target metal layer. The second ground bump can receive a ground signal from the package substrate, pass through the silicon interposer via a through-silicon via a through-silicon via, and transmit the ground signal to the ground bump on the chip side via multiple metal layers including the target metal layer, thereby enabling the package substrate to supply power to the chip.

[0068] As can be seen, the silicon interposer achieves power and ground connections with the packaging substrate through the second power bump and the second ground bump, providing a power supply path for the upper-layer chip.

[0069] To facilitate understanding, the following will be combined with... Figure 3 Let's take three metal layers as an example for illustration. Figure 3 This is a cross-sectional schematic diagram of an advanced packaged power distribution network structure provided in an embodiment of this application.

[0070] like Figure 3 As shown, the lower surface of the silicon interposer has power bumps and ground bumps. The power bumps are of types PWR1 and PWR2, which represent different power rails (such as VDD1 and VDD2) or voltage domains to provide power to the chip. VSS represents the ground line. There are three metal layers from bottom to top: M1, M2, and M3. M1 is the target metal layer mentioned above. Above M3 are the chip-side bumps, which include power bumps and ground bumps. The voltage domains of the power bumps are PWR1 and PWR2.

[0071] Figure 3 Below the silicon interposer can be a packaging substrate. The power and ground signals of the packaging substrate pass through the power bumps and ground bumps on the lower surface of the silicon interposer, through through-silicon vias, and then through the M1 metal layer, M2 metal layer, and M3 metal layer to the power bumps and ground bumps on the chip side, forming a complete power supply network.

[0072] When the chip is working, if the transient current demand suddenly increases, the DTC embedded in the silicon interposer discharges. The power electrode and ground electrode of the DTC pass through the metal layer and connect to the power bump and ground bump on the chip side, thereby supplying power to the chip.

[0073] Therefore, in the vertical direction, through Figure 3 The layer-by-layer transition shown enables low-impedance interconnection from the bumps on the lower surface of the silicon interposer to the bumps on the chip side.

[0074] The advanced packaged power distribution network structure of this application embodiment can realize the parallel connection of DTCs and multiple paths of the power distribution network, which can greatly reduce the parasitic inductance and path resistance of the power distribution network. At the same time, it can realize the large-area distributed DTC deployment, ensuring that the interconnection path of each DTC has ultra-low power distribution network impedance without dead zones.

[0075] The power distribution network scheme of this application provides a relatively low impedance in the silicon interposer layer. Furthermore, the DTC performance and bandwidth of the silicon interposer are significantly improved.

[0076] To achieve the above embodiments, this application also proposes a chip that is powered by the advanced packaged power distribution network structure described in the above embodiments.

[0077] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An advanced packaged power distribution network structure, characterized in that, include: A silicon interposer and a target metal layer located on top of and closest to the silicon interposer; wherein the target metal layer has a first ground bump and a first power bump; The first grounding bumps are regularly aligned in the horizontal and vertical directions within the plane of the target metal layer, forming a grid-like distribution, and each first power bump is surrounded by multiple first grounding bumps; In the target metal layer, the grounding network is a grid-like network formed by wiring according to the distribution pattern of the first grounding bumps, and the power network is formed based on the wiring of the first power bumps; The deep trench capacitors (DTCs) embedded in the silicon interposer are connected to the ground network and the power network via the shortest path, respectively.

2. The power distribution network structure as described in claim 1, characterized in that, The grounding network is formed by interconnecting the first grounding bumps in the horizontal and vertical directions, respectively.

3. The power distribution network structure as described in claim 2, characterized in that, The grounding network is formed by interconnecting the first grounding bumps in both the horizontal and vertical directions based on the wiring of the first power supply bumps.

4. The power distribution network structure as described in claim 1, characterized in that, The power network is formed by interconnecting the first power bumps according to the target rules.

5. The power distribution network structure as described in claim 4, characterized in that, The target rule includes connecting adjacent first power bumps in the same horizontal direction and in the same voltage domain to form a continuous power transmission path.

6. The power distribution network structure as described in claim 1, characterized in that, The lower surface of the silicon interposer is provided with a second ground bump and a second power bump. The second ground bump and the first ground bump are vertically aligned. The second power bump and the first power bump are vertically aligned.

7. The power distribution network structure as described in claim 6, characterized in that, The second ground bump penetrates the silicon interposer through a through-silicon via and is electrically connected to the first ground bump; the second power bump penetrates the silicon interposer through a through-silicon via and is electrically connected to the first power bump.

8. The power distribution network structure as described in claim 6, characterized in that, The second power bump penetrates the silicon interposer through a through-silicon via and is electrically connected to the power bump on the chip side via multiple metal layers, including the target metal layer.

9. The power distribution network structure as described in claim 6, characterized in that, The second ground bump penetrates the silicon interposer through a through-silicon via and is electrically connected to the ground bump on the chip side via multiple metal layers, including the target metal layer.

10. The power distribution network structure as described in any one of claims 1-9, characterized in that, The DTCs embedded in the silicon interposer are arranged in a regular two-dimensional array, with rows extending horizontally and columns extending vertically.

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