Semiconductor device including wiring pattern

Abstract

A semiconductor device includes: a lower interlayer insulating layer; a first contact trench formed in the lower interlayer insulating layer; a first contact provided in the first contact trench; a first conductive layer provided on an upper surface of the first contact, the first conductive layer having a width in a first horizontal direction that is greater than a width of the first contact trench in the first horizontal direction, the first conductive layer extending in a second horizontal direction that is different from the first horizontal direction and including a metal; a second conductive layer in contact with an upper surface of the first conductive layer and including a metal nitride containing the metal; a third conductive layer in contact with an upper surface of the second conductive layer and including the metal; and a first upper interlayer insulating layer provided on an upper surface of the lower interlayer insulating layer and in contact with side walls of the first to third conductive layers in the first horizontal direction, wherein the side walls of the first to third conductive layers in contact with the first upper interlayer insulating layer in the first horizontal direction have a continuously inclined profile.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0053462, filed on April 24, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices including wiring patterns. Background Technology

[0003] With advancements in electronic technology, the size of semiconductor devices has shrunk rapidly in recent years, leading to an increased demand for higher integration and lower power consumption in semiconductor chips. As the spacing between circuit components, such as wiring patterns, becomes increasingly narrow, reliability issues may arise between the wiring patterns. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, which can reduce the complexity of the manufacturing process and the resistance of the wiring layers.

[0005] The aspects of this disclosure are not limited to those described above, and other aspects not explicitly mentioned will be readily apparent to those skilled in the art from the following description.

[0006] According to some embodiments of this disclosure, a semiconductor device is provided, comprising: a lower interlayer insulating layer; a first contact trench formed in the lower interlayer insulating layer; a first contact disposed in the first contact trench; a first conductive layer disposed on an upper surface of the first contact, the width of the first conductive layer in a first horizontal direction being greater than the width of the first contact trench in the first horizontal direction, the first conductive layer extending in a second horizontal direction different from the first horizontal direction, the first conductive layer comprising a metal; a second conductive layer contacting the upper surface of the first conductive layer, the second conductive layer comprising a metal nitride containing the metal; a third conductive layer contacting the upper surface of the second conductive layer, the third conductive layer comprising the metal; and a first upper interlayer insulating layer disposed on the upper surface of the lower interlayer insulating layer, the first upper interlayer insulating layer contacting sidewalls of the first to third conductive layers in the first horizontal direction, wherein the sidewalls of the first to third conductive layers in the first horizontal direction that contact the first upper interlayer insulating layer have a continuously inclined profile.

[0007] According to some embodiments of this disclosure, a semiconductor device is provided, comprising: a first contact; a first conductive layer disposed on an upper surface of the first contact, the first conductive layer comprising a metal; a second conductive layer contacting the upper surface of the first conductive layer, the second conductive layer comprising a metal nitride containing the metal; a third conductive layer contacting the upper surface of the second conductive layer, the third conductive layer comprising the metal; a first interlayer insulating layer contacting a sidewall of the first to third conductive layers in a first horizontal direction; a second interlayer insulating layer disposed on the upper surface of the first interlayer insulating layer; and an upper wiring pattern disposed on the upper surface of the third conductive layer, the upper wiring pattern extending in a second horizontal direction different from the first horizontal direction, the upper wiring pattern being electrically connected to the third conductive layer, wherein the width of the upper surface of the third conductive layer in the first horizontal direction is smaller than the width of the upper surface of the first conductive layer in the first horizontal direction.

[0008] According to some embodiments of this disclosure, a semiconductor device is provided, comprising: a lower interlayer insulating layer; a contact trench formed in the lower interlayer insulating layer; a contact disposed in the contact trench; a wiring barrier layer contacting an upper surface of the contact; a first conductive layer contacting an upper surface of the wiring barrier layer, the width of the first conductive layer in a first horizontal direction being greater than the width of the contact trench in the first horizontal direction, the first conductive layer extending in a second horizontal direction different from the first horizontal direction, the first conductive layer comprising ruthenium (Ru); a second conductive layer contacting an upper surface of the first conductive layer, the second conductive layer comprising ruthenium nitride (RuN), the second conductive layer extending in the second horizontal direction; a third conductive layer contacting an upper surface of the second conductive layer, the third conductive layer comprising ruthenium (Ru), the third conductive layer extending in the second horizontal direction; and a first upper interlayer insulating layer disposed in the lower interlayer insulating layer. On the upper surface, a first interlayer insulating layer contacts the sidewalls of the first to third conductive layers in the first horizontal direction, and the upper surface of the first interlayer insulating layer and the upper surface of the third conductive layer are formed on the same plane; a second interlayer insulating layer is disposed on the upper surface of the first interlayer insulating layer; a via is disposed in the second interlayer insulating layer and contacts the upper surface of the third conductive layer; and an upper wiring pattern is disposed in the second interlayer insulating layer and contacts the upper surface of the via, the upper wiring pattern and the via are integrally formed, the upper wiring pattern extends in the second horizontal direction, wherein the sidewalls of the first to third conductive layers in the first horizontal direction that contact the first interlayer insulating layer have a continuously inclined profile, and wherein the width of the upper surface of the third conductive layer in the first horizontal direction is smaller than the width of the upper surface of the first conductive layer in the first horizontal direction. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a layout diagram illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'; Figure 3 It is along Figure 1 A cross-sectional view taken from line B-B'; Figures 4 to 17 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; Figure 18 and Figure 19 This is a cross-sectional view used to illustrate some embodiments of a semiconductor device according to the present disclosure; Figures 20 to 27 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; Figure 28 This is a layout diagram illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 29 It is along Figure 28 A cross-sectional view taken from line C-C'; Figures 30 to 36 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure; Figure 37 This is a cross-sectional view used to illustrate a semiconductor device according to an embodiment of the present disclosure; and Figures 38 to 41 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0010] In the following text, the following will refer to Figures 1 to 3 A semiconductor device according to some embodiments of the present disclosure is described.

[0011] Figure 1 This is a layout diagram used to illustrate some embodiments of a semiconductor device according to the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'.

[0012] Reference Figures 1 to 3A semiconductor device according to some embodiments of the present disclosure includes a lower interlayer insulating layer 100, a first contact trench 110T, a first contact 110, a first upper interlayer insulating layer 120, a first lower wiring pattern 130, a first wiring barrier layer 141, a first conductive layer 142, a second conductive layer 143, a third conductive layer 144, a second upper interlayer insulating layer 150, a via 160, and an upper wiring pattern 170.

[0013] The lower interlayer insulating layer 100 may include one or more of the following: silicon oxide (SiO2), silicon nitride (SiN), SiCOH, silicon oxycarbide (SiOC), silicon oxynitride (SiON), and low-k dielectric materials. Low-k dielectric materials may include, for example, tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butyloxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorinated silicate glass), polyimide nanofoams such as polyoxypropylene, CDO (carbon-doped silica), OSG (organosilicon glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof. However, this disclosure is not limited thereto.

[0014] In the following text, the first horizontal direction DR1 and the second horizontal direction DR2 can each be defined as a direction parallel to the upper surface of the lower interlayer insulation layer 100. The second horizontal direction DR2 can be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 can be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 can be defined as a direction perpendicular to the upper surface of the lower interlayer insulation layer 100.

[0015] The first contact trench 110T can be formed in the lower interlayer insulating layer 100. For example, the first contact trench 110T can be formed to be recessed from the upper surface of the lower interlayer insulating layer 100 toward the lower interlayer insulating layer 100. For example, the width of the first contact trench 110T in the first horizontal direction DR1 can gradually increase toward the upper surface of the lower interlayer insulating layer 100. In addition, the width of the first contact trench 110T in the second horizontal direction DR2 can gradually increase toward the upper surface of the lower interlayer insulating layer 100.

[0016] The first contact 110 may be disposed in the first contact trench 110T. For example, the first contact 110 may fill a portion of the first contact trench 110T. For example, the upper surface of the first contact 110 may be formed to be lower than the upper surface of the lower interlayer insulating layer 100. For example, the two sidewalls of the first contact 110 in the first horizontal direction DR1 may contact the lower interlayer insulating layer 100. Additionally, the two sidewalls of the first contact 110 in the second horizontal direction DR2 may contact the lower interlayer insulating layer 100. For example, the width of the first contact 110 in the first horizontal direction DR1 may gradually increase towards the upper surface of the lower interlayer insulating layer 100. Furthermore, the width of the first contact 110 in the second horizontal direction DR2 may gradually increase towards the upper surface of the lower interlayer insulating layer 100. The first contact 110 may include a conductive material.

[0017] The first upper interlayer insulating layer 120 may be disposed on the upper surface of the lower interlayer insulating layer 100. For example, the first upper interlayer insulating layer 120 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), SiCOH, silicon carbide (SiOC), silicon oxynitride (SiON), and a low-k dielectric material. For example, the first upper interlayer insulating layer 120 may be in contact with the upper surface of the lower interlayer insulating layer 100. However, this disclosure is not limited thereto. In some embodiments, an etch stop layer may be disposed between the upper surface of the lower interlayer insulating layer 100 and the first upper interlayer insulating layer 120. For example, the etch stop layer can be aluminum nitride (AlN), aluminum oxide (Al2O3), hafnium oxide (HfO), zirconium oxide (ZrO), hafnium nitride (HfN), zirconium nitride (ZrN), yttrium oxide (Y2O3), yttrium nitride (YN), silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbon oxycarbonate (SiOC), silicon carbide (SiC), and low-k dielectric materials.

[0018] The first lower wiring pattern 130 may be disposed in the first upper interlayer insulation layer 120. The first lower wiring pattern 130 may be disposed on the upper surface of the first contact 110. For example, the first lower wiring pattern 130 may contact the upper surface of the first contact 110. The first lower wiring pattern 130 may be electrically connected to the first contact 110. For example, the first lower wiring pattern 130 may extend in the second horizontal direction DR2. For example, at least a portion of the first lower wiring pattern 130 may be disposed in the first contact trench 110T. For example, the first lower wiring pattern 130 may contact the upper surface of the lower interlayer insulation layer 100 adjacent to the first contact trench 110T. For example, the upper surface of the first lower wiring pattern 130 may be formed on the same plane as the upper surface of the first upper interlayer insulation layer 120.

[0019] For example, the width of the first lower wiring pattern 130 in the first horizontal direction DR1 may be greater than the width of the first contact trench 110T in the first horizontal direction DR1. For example, on the upper surface of the lower interlayer insulating layer 100, the two sidewalls of the first lower wiring pattern 130 in the first horizontal direction DR1 may contact the first upper interlayer insulating layer 120. For example, on the upper surface of the lower interlayer insulating layer 100, the sidewalls of the first lower wiring pattern 130 in the first horizontal direction DR1 may have a continuously inclined profile. That is, the sidewalls of the first lower wiring pattern 130 in the first horizontal direction DR1 that contact the first upper interlayer insulating layer 120 may have a continuously inclined profile. For example, the first lower wiring pattern 130 may include a first wiring barrier layer 141, a first conductive layer 142, a second conductive layer 143, and a third conductive layer 144.

[0020] For example, a first wiring barrier layer 141 may be disposed on the upper surface of the first contact 110 and the upper surface of the lower interlayer insulation layer 100. Alternatively, the first wiring barrier layer 141 may be disposed along the sidewall of the first contact trench 110T on the upper surface of the first contact 110. For example, the first wiring barrier layer 141 may contact the upper surface of the first contact 110 and the lower interlayer insulation layer 100. For example, the first wiring barrier layer 141 may be conformally formed. For example, on the upper surface of the lower interlayer insulation layer 100, the sidewall of the first wiring barrier layer 141 in the first horizontal direction DR1 may contact the first upper interlayer insulation layer 120.

[0021] The first wiring barrier layer 141 may include a conductive material. For example, the first wiring barrier layer 141 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof. However, this disclosure is not limited thereto.

[0022] The first conductive layer 142 may be disposed on the upper surface of the first wiring barrier layer 141. The lower surface of the first conductive layer 142 may contact the upper surface of the first wiring barrier layer 141. That is, the first wiring barrier layer 141 may be disposed between the upper surface of the first contact 110 and the lower surface of the first conductive layer 142. For example, the first conductive layer 142 may extend in the second horizontal direction DR2. For example, the width of the first conductive layer 142 in the first horizontal direction DR1 may be greater than the width of the first contact trench 110T in the first horizontal direction DR1. For example, at least a portion of the first conductive layer 142 may be disposed in the first contact trench 110T. For example, the two sidewalls of the first conductive layer 142 in the first horizontal direction DR1 may contact the first upper interlayer insulating layer 120.

[0023] The first conductive layer 142 may include a metal. For example, the metal included in the first conductive layer 142 may include ruthenium (Ru). In some embodiments, the metal included in the first conductive layer 142 may include any one of copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), tungsten (W), iridium (Ir), and rhodium (Rh).

[0024] The second conductive layer 143 can be disposed on the upper surface of the first conductive layer 142. The lower surface of the second conductive layer 143 can contact the upper surface of the first conductive layer 142. For example, the second conductive layer 143 can extend in the second horizontal direction DR2. Figure 2 and Figure 3 In the illustration, the thickness of the second conductive layer 143 in the vertical direction DR3 is shown to be uniformly formed, but this disclosure is not limited thereto. That is, in some embodiments, the thickness of the second conductive layer 143 in the vertical direction DR3 may be non-uniformly formed. For example, the two sidewalls of the second conductive layer 143 in the first horizontal direction DR1 may be in contact with the first upper interlayer insulating layer 120.

[0025] The second conductive layer 143 may include a metal nitride comprising the metal included in the first conductive layer 142. For example, if the first conductive layer 142 comprises ruthenium (Ru), then the second conductive layer 143 may include ruthenium nitride (RuN). In some embodiments, the metal nitride included in the second conductive layer 143 may include a nitride of any one of copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), tungsten (W), iridium (Ir), and rhodium (Rh).

[0026] The third conductive layer 144 can be disposed on the upper surface of the second conductive layer 143. The lower surface of the third conductive layer 144 can contact the upper surface of the second conductive layer 143. For example, the third conductive layer 144 can extend in the second horizontal direction DR2. Figure 2 and Figure 3 The diagram shows that the third conductive layer 144 is formed with a uniform thickness in the vertical direction DR3, but this disclosure is not limited thereto. That is, in some embodiments, the thickness of the third conductive layer 144 in the vertical direction DR3 may be formed non-uniformly.

[0027] For example, the two sidewalls of the third conductive layer 144 on the first horizontal direction DR1 may contact the first upper interlayer insulating layer 120. For example, the upper surface of the third conductive layer 144 may be formed on the same plane as the upper surface of the first upper interlayer insulating layer 120. For example, the sidewalls of each of the first wiring barrier layer 141, the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 on the first horizontal direction DR1 that contact the first upper interlayer insulating layer 120 may have a continuously inclined profile. For example, the width of the upper surface of the third conductive layer 144 on the first horizontal direction DR1 may be smaller than the width of the upper surface of the first conductive layer 142 on the first horizontal direction DR1.

[0028] The third conductive layer 144 may include the metal contained in the first conductive layer 142. That is, the third conductive layer 144 may include the same metal as the first conductive layer 142. For example, if the first conductive layer 142 includes ruthenium (Ru), then the third conductive layer 144 may include ruthenium (Ru). In some embodiments, the metal contained in the third conductive layer 144 may include any one of copper (Cu), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), tungsten (W), iridium (Ir), and rhodium (Rh).

[0029] In some embodiments, the first wiring barrier layer 141 may not be provided. In this case, the lower surface of the first conductive layer 142 may contact the upper surface of the first contact 110 and the lower interlayer insulating layer 100.

[0030] In some embodiments, at least one of the first conductive layer 142 and the third conductive layer 144 may further include nitrogen atoms. For example, if the first conductive layer 142 includes nitrogen atoms, the concentration of nitrogen atoms in the first conductive layer 142 can increase from the lower surface of the first conductive layer 142 toward the upper surface of the first conductive layer 142. For example, if the third conductive layer 144 includes nitrogen atoms, the concentration of nitrogen atoms in the third conductive layer 144 can increase from the upper surface of the third conductive layer 144 toward the lower surface of the third conductive layer 144. For example, if both the first conductive layer 142 and the third conductive layer 144 include nitrogen atoms, the concentration of nitrogen atoms in the third conductive layer 144 can be greater than the concentration of nitrogen atoms in the first conductive layer 142.

[0031] In some embodiments, the second conductive layer 143 may be omitted. That is, the third conductive layer 144 may be in contact with the upper surface of the first conductive layer 142. For example, in the manufacturing process described later, the third conductive layer 144 may replace the entire second conductive material layer 143M (see [link to manufacturing process]). Figure 12 and 13 This allows for the omission of the second conductive layer 143. For example, even without the second conductive layer 143, at least one of the first conductive layer 142 and the third conductive layer 144 may include nitrogen atoms. For example, if the first conductive layer 142 includes nitrogen atoms, the concentration of nitrogen atoms in the first conductive layer 142 can increase from the lower surface of the first conductive layer 142 toward the upper surface of the first conductive layer 142 that contacts the lower surface of the third conductive layer 144. For example, if the third conductive layer 144 includes nitrogen atoms, the concentration of nitrogen atoms in the third conductive layer 144 can increase from the upper surface of the third conductive layer 144 toward the lower surface of the third conductive layer 144 that contacts the upper surface of the first conductive layer 142. For example, when each of the first conductive layer 142 and the third conductive layer 144 contains nitrogen atoms, the concentration of nitrogen atoms in the third conductive layer 144 may be greater than the concentration of nitrogen atoms in the first conductive layer 142.

[0032] The second upper interlayer insulating layer 150 may be disposed on the upper surface of the first upper interlayer insulating layer 120. The lower surface of the second upper interlayer insulating layer 150 may contact the upper surface of the first upper interlayer insulating layer 120. For example, the second upper interlayer insulating layer 150 may comprise the same material as the first upper interlayer insulating layer 120. However, this disclosure is not limited thereto. In some embodiments, the second upper interlayer insulating layer 150 may comprise a material different from that of the first upper interlayer insulating layer 120. For example, the second upper interlayer insulating layer 150 may comprise one or more of silicon oxide (SiO2), silicon nitride (SiN), SiCOH, silicon carbide (SiOC), silicon oxynitride (SiON), and low-k dielectric materials.

[0033] Via element 160 can be disposed in the second upper interlayer insulating layer 150. Via element 160 can be disposed on the upper surface of the first lower wiring pattern 130. For example, via element 160 can contact the upper surface of the first lower wiring pattern 130. That is, via element 160 can contact the upper surface of the third conductive layer 144. Via element 160 can be electrically connected to the first lower wiring pattern 130. The sidewalls of via element 160 can be surrounded by the second upper interlayer insulating layer 150. For example, the two sidewalls of via element 160 in the first horizontal direction DR1 can contact the second upper interlayer insulating layer 150. In addition, the two sidewalls of via element 160 in the second horizontal direction DR2 can also contact the second upper interlayer insulating layer 150.

[0034] For example, the width of the via 160 in the first horizontal direction DR1 can gradually increase towards the upper surface of the second upper interlayer insulating layer 150. Similarly, the width of the via 160 in the second horizontal direction DR2 can also gradually increase towards the upper surface of the second upper interlayer insulating layer 150. Figure 2 In this embodiment, the width of the lower surface of the via 160 in the first horizontal direction DR1 is shown to be greater than the width of the upper surface of the third conductive layer 144 in the first horizontal direction DR1, but this disclosure is not limited thereto. In some embodiments, the width of the lower surface of the via 160 in the first horizontal direction DR1 may be smaller than the width of the upper surface of the third conductive layer in the first horizontal direction DR1. The via 160 may include a conductive material.

[0035] The upper wiring pattern 170 can be disposed in the second upper interlayer insulation layer 150. The upper wiring pattern 170 can be disposed on the upper surface of the via 160. For example, the upper wiring pattern 170 can contact the upper surface of the via 160. The upper wiring pattern 170 can be electrically connected to the via 160. That is, the upper wiring pattern 170 can be electrically connected to the first lower wiring pattern 130 through the via 160. For example, the upper wiring pattern 170 can extend in the second horizontal direction DR2. The two sidewalls of the upper wiring pattern 170 in the first horizontal direction DR1 can contact the second upper interlayer insulation layer 150.

[0036] For example, the upper surface of the upper wiring pattern 170 may be formed on the same plane as the upper surface of the second upper interlayer insulating layer 150. For example, the width of the lower surface of the upper wiring pattern 170 in the second horizontal direction DR2 may be greater than the width of the upper surface of the via 160 in the second horizontal direction DR2. Similarly, the width of the lower surface of the upper wiring pattern 170 in the first horizontal direction DR1 may be greater than the width of the upper surface of the via 160 in the first horizontal direction DR1. However, this disclosure is not limited thereto. In some embodiments, the width of the lower surface of the upper wiring pattern 170 in the first horizontal direction DR1 may be the same as the width of the upper surface of the via 160 in the first horizontal direction DR1. That is, the sidewall of the upper wiring pattern 170 in the first horizontal direction DR1 may form a continuously inclined profile with the sidewall of the via 160 in the first horizontal direction DR1.

[0037] For example, the width of the upper wiring pattern 170 in the first horizontal direction DR1 can gradually increase towards the upper surface of the second upper interlayer insulating layer 150. Additionally, the width of the upper wiring pattern 170 in the second horizontal direction DR2 can gradually increase towards the upper surface of the second upper interlayer insulating layer 150. For example, the upper wiring pattern 170 can be integrally formed with the via 160. That is, the upper wiring pattern 170 and the via 160 can be formed using the same manufacturing process. Furthermore, the upper wiring pattern 170 and the via 160 can comprise the same conductive material.

[0038] In the following text, reference will be made to Figures 2 to 17 Methods for manufacturing a semiconductor device according to some embodiments of the present disclosure are described.

[0039] Figures 4 to 17 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0040] Reference Figure 4 and Figure 5 A first contact trench 110T can be formed in the lower interlayer insulating layer 100. Subsequently, a first contact 110 can be formed in the first contact trench 110T. For example, the upper surface of the first contact 110 can be formed to be lower than the upper surface of the lower interlayer insulating layer 100.

[0041] Reference Figure 6 and Figure 7A wiring barrier material layer 141M can be formed on the upper surface of the first contact 110 and the upper surface of the lower interlayer insulating layer 100. Alternatively, the wiring barrier material layer 141M can be formed along the sidewall of the first contact trench 110T located on the upper surface of the first contact 110. For example, the wiring barrier material layer 141M can contact the upper surface of the first contact 110 and the lower interlayer insulating layer 100. The wiring barrier material layer 141M can be formed conformally. For example, the wiring barrier material layer 141M may include materials that are compatible with... Figure 2 and Figure 3 The first wiring barrier layer 141 shown is made of the same material.

[0042] Subsequently, a first conductive material layer 142M can be formed on the upper surface of the wiring barrier material layer 141M. For example, the first conductive material layer 142M can be in contact with the upper surface of the wiring barrier material layer 141M. For example, at least a portion of the first conductive material layer 142M can be formed in the first contact trench 110T. For example, the first conductive material layer 142M can include a conductive material layer 142M that is in contact with the upper surface of the wiring barrier material layer 141M. Figure 2 and Figure 3 The first conductive layer 142 shown is made of the same material. That is, the first conductive material layer 142M may include metal.

[0043] Next, a second conductive material layer 143M can be formed on the upper surface of the first conductive material layer 142M. For example, the second conductive material layer 143M can be in contact with the upper surface of the first conductive material layer 142M. For example, the second conductive material layer 143M can include surfaces that are in contact with the upper surface of the first conductive material layer 142M. Figure 2 and Figure 3 The second conductive layer 143 shown is made of the same material. That is, the second conductive material layer 143M may include a metal nitride containing the metal included in the first conductive material layer 142M.

[0044] Reference Figure 8 and Figure 9 A first mask pattern M1 can be formed on the upper surface of the second conductive material layer 143M. For example, the first mask pattern M1 can overlap with the first contact 110 in the vertical direction DR3. For example, the first mask pattern M1 can extend in the second horizontal direction DR2. Thereafter, using the first mask pattern M1 as a mask, a portion of the second conductive material layer 143M can be etched.

[0045] Reference Figure 10 and Figure 11 The first mask pattern M1 can be removed (see...) Figure 8 and Figure 9 Then, using the remaining second conductive material layer 143M as a mask, the first conductive material layer 142M can be etched (see...). Figure 8 and Figure 9Part of the wiring barrier material layer 141M (see) Figure 8 and Figure 9 Part of the first conductive material layer 142M (see [link]) after the etching process is completed. Figure 8 and Figure 9 ) can be defined as the first conductive layer 142, and the remaining wiring barrier material layer 141M (see Figure 8 and Figure 9 It can be defined as the first wiring barrier layer 141.

[0046] For example, the remaining second conductive material layer 143M, the first conductive layer 142, and the first wiring barrier layer 141 may each have a continuously inclined profile on their sidewalls in the first horizontal direction DR1. For example, the remaining second conductive material layer 143M and the first conductive layer 142 may each extend in the second horizontal direction DR2.

[0047] Reference Figure 12 and Figure 13 A first upper interlayer insulating layer 120 can be formed to cover the second conductive material layer 143M, the first conductive layer 142, and the first wiring barrier layer 141 on the upper surface of the lower interlayer insulating layer 100, respectively. Subsequently, a planarization process can be performed to expose the upper surface of the second conductive material layer 143M. As a result, the upper surface of the second conductive material layer 143M and the upper surface of the first upper interlayer insulating layer 120 can be formed on the same plane. For example, the first upper interlayer insulating layer 120 can contact two sidewalls of the second conductive material layer 143M, the first conductive layer 142, and the first wiring barrier layer 141 in the first horizontal direction DR1, respectively.

[0048] Reference Figure 14 and Figure 15 An annealing process can be performed to remove the second conductive material layer 143M (see...) Figure 12 and Figure 13 Nitrogen is removed from a portion of the material. For example, the second conductive material layer 143M (see...) Figure 12 and Figure 13 The second conductive material layer 143M (see) has been removed. Figure 12 and 13 The nitrogen-removed portion of the material can be defined as the third conductive layer 144. Additionally, the second conductive material layer 143M (see...) Figure 12 and Figure 13 The material not removed from the second conductive material layer 143M (see...) Figure 12 and Figure 13 The remaining portion after nitrogen removal can be defined as the second conductive layer 143.

[0049] For example, the second conductive layer 143 may be formed to contact the upper surface of the first conductive layer 142. The third conductive layer 144 may be formed on the upper surface of the second conductive layer 143. For example, the upper surface of the third conductive layer 144 may be formed on the same plane as the upper surface of the first interlayer insulating layer 120. For example, the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 may each extend in the second horizontal direction DR2. For example, the sidewalls of the first wiring barrier layer 141, the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 in the first horizontal direction DR1 may contact the first interlayer insulating layer 120. For example, the sidewalls of the first wiring barrier layer 141, the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 in the first horizontal direction DR1 that contact the first interlayer insulating layer 120 may have a continuously inclined profile.

[0050] Reference Figure 16 and Figure 17 A second upper interlayer insulating layer 150 can be formed on the upper surfaces of the first upper interlayer insulating layer 120 and the third conductive layer 144. Subsequently, via trenches 160T and upper wiring trenches 170T can be formed in the second upper interlayer insulating layer 150. For example, via trenches 160T can be formed on the upper surface of the third conductive layer 144. The upper surface of the third conductive layer 144 can be exposed through the bottom surface of the via trenches 160T.

[0051] An upper wiring trench 170T can be formed above the via trench 160T. For example, the width of the upper wiring trench 170T in the first horizontal direction DR1 can be greater than the width of the via trench 160T in the first horizontal direction DR1. For example, the upper wiring trench 170T can extend in the second horizontal direction DR2. For example, the via trench 160T and the upper wiring trench 170T can be formed by the same manufacturing process. However, this disclosure is not limited thereto.

[0052] Reference Figure 2 and Figure 3 It can be used in the through-hole trench 160T (see Figure 16 and Figure 17 A via 160 is formed in the ) and a wiring trench 170T (see) can be formed on it. Figure 16 and Figure 17 An upper wiring pattern 170 is formed in the third conductive layer 144. For example, the via 160 can contact the upper surface of the third conductive layer 144. The upper wiring pattern 170 can contact the upper surface of the via 160. For example, the via 160 and the upper wiring pattern 170 can be integrally formed. Through this manufacturing process, it is possible to manufacture... Figure 2 and Figure 3 The semiconductor device shown.

[0053] In a method for manufacturing a semiconductor device according to some embodiments of the present disclosure, after etching a second conductive material layer 143M using a first mask pattern M1 as a mask, the remaining second conductive material layer 143M can be used as a mask to etch a first conductive material layer 142M to form a first conductive layer 142. That is, by using the first mask pattern M1 as a mask to etch only the second conductive material layer 143M, instead of using the first mask pattern M1 as a mask to etch both the first conductive material layer 142M and the second conductive material layer 143M, the thickness of the first mask pattern M1 in the vertical direction DR3 can be relatively reduced. Therefore, the method for manufacturing a semiconductor device according to some embodiments of the present disclosure can reduce the aspect ratio of the first mask pattern M1, thereby reducing process complexity.

[0054] Furthermore, in some embodiments of this disclosure, the method for manufacturing a semiconductor device may include replacing a portion of the second conductive material layer 143M with a metal-containing third conductive layer 144 by removing nitrogen from a second conductive material layer 143M used as a mask for etching the first conductive material layer 142M. As a result, the method for manufacturing a semiconductor device according to some embodiments of this disclosure can reduce the resistance of the third conductive layer 144, thereby improving the electrical characteristics of the semiconductor device.

[0055] Semiconductor devices manufactured using the above-described manufacturing method according to some embodiments of the present disclosure may have a first conductive layer 142, a second conductive layer 143, and a third conductive layer 144 stacked sequentially, wherein the first conductive layer 142 and the third conductive layer 144 may comprise the same metal, and the second conductive layer 143 may comprise a metal nitride comprising the metal. Furthermore, a sidewall of each of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 in the first horizontal direction DR1 may contact a first upper interlayer insulating layer 120. The sidewall of each of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144 in contact with the first upper interlayer insulating layer 120 in the first horizontal direction DR1 may have a continuously inclined profile.

[0056] In the following text, refer to Figure 18 and Figure 19 It will focus on and Figures 1 to 3 The differences between the semiconductor devices shown are described in the semiconductor devices according to embodiments of this disclosure.

[0057] Figure 18 and Figure 19 This is a cross-sectional view used to illustrate a semiconductor device according to several embodiments of the present disclosure.

[0058] Reference Figure 18 and Figure 19The semiconductor device according to an embodiment of the present disclosure may have an upper wiring pattern 270 in contact with the upper surface of the third conductive layer 244.

[0059] For example, a second upper interlayer insulating layer 250 may be disposed on the upper surface of the first upper interlayer insulating layer 120. An upper wiring pattern 270 may be disposed in the second upper interlayer insulating layer 250. The upper wiring pattern 270 may extend in the second horizontal direction DR2. For example, the upper wiring pattern 270 may be electrically connected to the first lower wiring pattern 230 via a via 260. For example, the first lower wiring pattern 230 may include a first wiring barrier layer 141 and a first conductive layer 142. The first lower wiring pattern 230 may extend in the second horizontal direction DR2. That is, each of the first wiring barrier layer 141 and the first conductive layer 142 may extend in the second horizontal direction DR2. For example, the via 260 may include a second conductive layer 243 and a third conductive layer 244.

[0060] For example, the sidewalls of the first wiring barrier layer 141, the first conductive layer 142, the second conductive layer 243, and the third conductive layer 244 in the first horizontal direction DR1 (each sidewall contacting the first upper interlayer insulating layer 120) may have a continuously inclined profile. For example, the sidewalls of the second conductive layer 243 and the third conductive layer 244 in the second horizontal direction DR2 may contact the first upper interlayer insulating layer 120. For example, the upper surface of the first conductive layer 142 may contact the first upper interlayer insulating layer 120 on the sidewalls of the second conductive layer 243 and the third conductive layer 244 along the second horizontal direction DR2.

[0061] In some embodiments, the first wiring barrier layer 141 may be omitted. That is, the lower surface of the first conductive layer 142 may contact the upper surface of the first contact 110 and the interlayer insulating layer 100. In some embodiments, at least one of the first conductive layer 142 and the third conductive layer 244 may include nitrogen atoms. In some embodiments, the second conductive layer 243 may be omitted. That is, the third conductive layer 244 may contact the upper surface of the first conductive layer 142. For example, even without the second conductive layer 243, at least one of the first conductive layer 142 and the third conductive layer 244 may include nitrogen atoms. A description and reference are provided regarding the distribution and relative concentration difference of nitrogen atoms in the first conductive layer 142 and the third conductive layer 244. Figures 1 to 3 Since the descriptions are the same, detailed explanations will be omitted.

[0062] The following will refer to Figures 18 to 27 This disclosure describes methods for manufacturing a semiconductor device according to several embodiments of the present disclosure. The description will focus primarily on... Figures 4 to 17 The differences shown are in the methods used to manufacture semiconductor devices.

[0063] Figures 20 to 27 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to several embodiments of the present disclosure.

[0064] Reference Figure 20 and Figure 21 In execution Figures 4 to 13 Following the manufacturing process shown, a second mask pattern M2 can be formed on the upper surface of the remaining second conductive material layer 143M and the upper surface of the first upper interlayer insulating layer 120. The second mask pattern M2 can overlap with the first contact 110 in the vertical direction DR3. For example, in a cross-sectional view taken along the second horizontal direction DR2... Figure 21 In this process, a second mask pattern M2 can be formed on a portion of the upper surface of the remaining second conductive material layer 143M.

[0065] Subsequently, using the second mask pattern M2 as a mask, a portion of the second conductive material layer 143M can be etched. This etching process exposes the two sidewalls of the second conductive material layer 143M on the second horizontal direction DR2. After completing the etching process, the remaining first wiring barrier layer 141 and first conductive layer 142 can be defined as the first lower wiring pattern 230.

[0066] Reference Figure 22 and Figure 23 The second mask pattern M2 can be removed (see...) Figure 20 and Figure 21 Then, a first upper interlayer insulating layer 120 can be additionally formed to cover the two sidewalls and the upper surface of the second conductive material layer 143M on the second horizontal direction DR2. Afterward, a planarization process can be performed to expose the upper surface of the second conductive material layer 143M. The upper surface of the second conductive material layer 143M and the upper surface of the first upper interlayer insulating layer 120 can be formed on the same plane.

[0067] Reference Figure 24 and Figure 25 An annealing process can be performed to remove the second conductive material layer 143M (see...) Figure 22 and Figure 23 Nitrogen is removed from a portion of the material. For example, the second conductive material layer 143M (see...) Figure 22 and Figure 23 The portion from which nitrogen is removed can be defined as the third conductive layer 244. Additionally, the second conductive material layer 143M (see...) Figure 22 and Figure 23 ) from the second conductive material layer 143M (see Figure 22 and Figure 23The remaining portion of the material without nitrogen removal can be defined as the second conductive layer 243. For example, the second conductive layer 243 and the third conductive layer 244 can be defined as a via 260.

[0068] Reference Figure 26 and Figure 27 A second upper interlayer insulating layer 250 can be formed on the upper surface of the first upper interlayer insulating layer 120 and the upper surface of the third conductive layer 244. Then, an upper wiring trench 270T can be formed in the second upper interlayer insulating layer 250. For example, the upper wiring trench 270T can be formed on the upper surface of the third conductive layer 244. The upper surface of the third conductive layer 244 can be exposed through the bottom surface of the upper wiring trench 270T. For example, the upper wiring trench 270T can extend in the second horizontal direction DR2.

[0069] Reference Figure 18 and Figure 19 It can be used to install 270T wiring trenches (see...) Figure 26 and Figure 27 An upper wiring pattern 270 is formed in the [layer name missing]. For example, the upper wiring pattern 270 can contact the upper surface of the third conductive layer 244. Through the above manufacturing process, [the material / process] can be manufactured. Figure 18 and Figure 19 The semiconductor device shown.

[0070] In the following text, reference will be made to Figure 28 and Figure 29 A semiconductor device according to embodiments of the present disclosure is described. This description will focus on... Figures 1 to 3 The differences shown are in the semiconductor devices.

[0071] Figure 28 This is a layout diagram used to illustrate a semiconductor device according to an embodiment of the present disclosure. Figure 29 It is along Figure 28 The cross-sectional view taken from line C-C'.

[0072] Reference Figure 28 and 29 The semiconductor device according to embodiments of the present disclosure may include a second contact trench 310T, a second contact 310, and a second lower wiring pattern 330.

[0073] For example, a second contact trench 310T may be formed in the lower interlayer insulating layer 300. The second contact trench 310T may be spaced apart from the first contact trench 110T in the first horizontal direction DR1. For example, the second contact trench 310T may be recessed from the upper surface of the lower interlayer insulating layer 300 into the lower interlayer insulating layer 300. For example, the width of the second contact trench 310T in the first horizontal direction DR1 may gradually increase towards the upper surface of the lower interlayer insulating layer 300. For example, the upper surface of the lower interlayer insulating layer 300 may include a first upper surface 300u1 adjacent to the first contact trench 110T and a second upper surface 300u2 adjacent to the second contact trench 310T. For example, the second upper surface 300u2 of the lower interlayer insulating layer 300 may be disposed below the first upper surface 300u1 of the lower interlayer insulating layer 300.

[0074] For example, the second contact 310 may be disposed in the second contact trench 310T. For example, the second contact 310 may fill a portion of the second contact trench 310T. For example, the upper surface of the second contact 310 may be formed to be lower than the second upper surface 300u2 of the lower interlayer insulating layer 300. For example, the two sidewalls of the second contact 310 in the first horizontal direction DR1 may contact the lower interlayer insulating layer 300. For example, the width of the second contact 310 in the first horizontal direction DR1 may gradually increase towards the second upper surface 300u2 of the lower interlayer insulating layer 300. The second contact 310 may include a conductive material.

[0075] For example, a second lower wiring pattern 330 may be disposed in the first upper interlayer insulating layer 320. The second lower wiring pattern 330 may be disposed on the upper surface of the second contact 310. For example, the second lower wiring pattern 330 may contact the upper surface of the second contact 310. The second lower wiring pattern 330 may be electrically connected to the second contact 310. For example, the second lower wiring pattern 330 may be spaced apart from the first lower wiring pattern 130 in the first horizontal direction DR1. For example, the second lower wiring pattern 330 may extend in the second horizontal direction DR2. For example, at least a portion of the second lower wiring pattern 330 may be disposed in the second contact trench 310T. For example, the second lower wiring pattern 330 may contact the second upper surface 300u2 of the lower interlayer insulating layer 300 adjacent to the second contact trench 310T. For example, the upper surface of the second lower wiring pattern 330 may be formed on the same plane as the upper surface of the first upper interlayer insulating layer 320.

[0076] For example, the width of the second lower wiring pattern 330 in the first horizontal direction DR1 can be greater than the width of the second contact trench 310T in the first horizontal direction DR1. For example, the width of the second lower wiring pattern 330 in the first horizontal direction DR1 can be less than the width of the first lower wiring pattern 130 in the first horizontal direction DR1. For example, on the second upper surface 300u2 of the lower interlayer insulating layer 300, the two sidewalls of the second lower wiring pattern 330 in the first horizontal direction DR1 can contact the first upper interlayer insulating layer 320. For example, on the second upper surface 300u2 of the lower interlayer insulating layer 300, the sidewalls of the second lower wiring pattern 330 in the first horizontal direction DR1 can have a continuously inclined profile. That is, the sidewalls of the second lower wiring pattern 330 in the first horizontal direction DR1 that contact the first upper interlayer insulating layer 320 can have a continuously inclined profile. For example, the second lower wiring pattern 330 may include a second wiring barrier layer 341, a fourth conductive layer 342, a fifth conductive layer 343, and a sixth conductive layer 344.

[0077] For example, a second wiring barrier layer 341 may be disposed on the upper surface of the second contact 310 and on the second upper surface 300u2 of the lower interlayer insulation layer 300. Furthermore, the second wiring barrier layer 341 may also be formed along the sidewall of the second contact 310 on the upper surface of the second contact 310. For example, the second wiring barrier layer 341 may contact the upper surface of the second contact 310 and the lower interlayer insulation layer 300. For example, the second wiring barrier layer 341 may be formed conformally. For example, the sidewall of the second wiring barrier layer 341 located on the second upper surface 300u2 of the lower interlayer insulation layer 300 in the first horizontal direction DR1 may contact the first upper interlayer insulation layer 320. The second wiring barrier layer 341 may comprise the same material as the first wiring barrier layer 141.

[0078] For example, the fourth conductive layer 342 can be disposed on the upper surface of the second wiring barrier layer 341. The lower surface of the fourth conductive layer 342 can contact the upper surface of the second wiring barrier layer 341. That is, the second wiring barrier layer 341 can be disposed between the upper surface of the second contact 310 and the lower surface of the fourth conductive layer 342. The fourth conductive layer 342 can be spaced apart from the first conductive layer 142 in the first horizontal direction DR1. For example, the fourth conductive layer 342 can extend in the second horizontal direction DR2. The upper surface of the fourth conductive layer 342 can be formed to be lower than the upper surface of the first conductive layer 142.

[0079] For example, the width of the fourth conductive layer 342 in the first horizontal direction DR1 may be greater than the width of the second contact trench 310T in the first horizontal direction DR1. At least a portion of the fourth conductive layer 342 may be formed in the second contact trench 310T. For example, the two sidewalls of the fourth conductive layer 342 in the first horizontal direction DR1 may contact the first upper interlayer insulating layer 320. The fourth conductive layer 342 may include the same material as the first conductive layer 142. That is, the fourth conductive layer 342 may include the same metal as the metal included in the first conductive layer 142.

[0080] For example, a fifth conductive layer 343 can be disposed on the upper surface of the fourth conductive layer 342. The lower surface of the fifth conductive layer 343 can contact the upper surface of the fourth conductive layer 342. The fifth conductive layer 343 can extend in the second horizontal direction DR2. Figure 29 In the illustration, the thickness of the fifth conductive layer 343 in the vertical direction DR3 is shown to be uniformly formed, but this disclosure is not limited thereto. That is, in some embodiments, the thickness of the fifth conductive layer 343 in the vertical direction DR3 may be non-uniformly formed. For example, the two sidewalls of the fifth conductive layer 343 in the first horizontal direction DR1 may contact the first upper interlayer insulating layer 320. The fifth conductive layer 343 may include a metal nitride comprising the metal contained in the fourth conductive layer 342. For example, the fifth conductive layer 343 may include a metal nitride comprising the metal contained in the fourth conductive layer 342.

[0081] For example, a sixth conductive layer 344 can be disposed on the upper surface of the fifth conductive layer 343. The lower surface of the sixth conductive layer 344 can contact the upper surface of the fifth conductive layer 343. For example, the sixth conductive layer 344 can extend along a second horizontal direction DR2. Figure 29 In the diagram, the sixth conductive layer 344 is shown to have a uniform thickness in the vertical direction DR3. However, this disclosure is not limited thereto. In some embodiments, the sixth conductive layer 344 may have a non-uniform thickness in the vertical direction DR3. For example, the two sidewalls of the sixth conductive layer 344 in the first horizontal direction DR1 may be in contact with the first upper interlayer insulating layer 320.

[0082] For example, the upper surface of the sixth conductive layer 344 may be formed on the same plane as the upper surface of the first interlayer insulating layer 320. For example, the upper surface of the sixth conductive layer 344 may contact the second interlayer insulating layer 350. For example, each sidewall of the second wiring barrier layer 341, the fourth conductive layer 342, the fifth conductive layer 343, and the sixth conductive layer 344 that contacts the first interlayer insulating layer 320 in the first horizontal direction DR1 may have a continuously inclined profile. For example, the width of the upper surface of the sixth conductive layer 344 in the first horizontal direction DR1 may be smaller than the width of the upper surface of the fourth conductive layer 342 in the first horizontal direction DR1. For example, the sixth conductive layer 344 may include the same metal as the metal included in the fourth conductive layer 342.

[0083] In some embodiments, the first wiring barrier layer 141 and the second wiring barrier layer 341 may not be provided. That is, the lower surface of the first conductive layer 142 may contact the upper surface of the first contact 110 and the lower interlayer insulating layer 300, and the lower surface of the fourth conductive layer 342 may contact the upper surface of the second contact 310 and the lower interlayer insulating layer 300. In embodiments, at least one of the first conductive layer 142 and the third conductive layer 144 may include nitrogen atoms, and at least one of the fourth conductive layer 342 and the sixth conductive layer 344 may also include nitrogen atoms.

[0084] In another embodiment, the second conductive layer 143 and the fifth conductive layer 343 may be omitted. That is, the third conductive layer 144 may be in contact with the upper surface of the first conductive layer 142, and the sixth conductive layer 344 may be in contact with the upper surface of the fourth conductive layer 342. For example, even without the second conductive layer 143 and the fifth conductive layer 343, at least one of the first conductive layer 142 and the third conductive layer 144 may include nitrogen atoms, and at least one of the fourth conductive layer 342 and the sixth conductive layer 344 may also include nitrogen atoms. The description of the distribution and relative concentration difference of nitrogen atoms in the fourth conductive layer 342 and the sixth conductive layer 344 is consistent with... Figures 1 to 3 The description of the distribution and relative concentration difference of nitrogen atoms in the first conductive layer 142 and the third conductive layer 144 provided is similar. Therefore, detailed descriptions will be omitted.

[0085] The following will refer to Figures 29 to 36 This description describes methods for manufacturing a semiconductor device according to several embodiments of the present disclosure. The description will focus on... Figures 4 to 17 The differences in the methods of manufacturing semiconductor devices are shown.

[0086] Figures 30 to 36 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to several embodiments of the present disclosure.

[0087] Reference Figure 30 A first contact trench 110T and a second contact trench 310T can be formed in a lower interlayer insulating layer 300, including a first upper surface 300u1 and a second upper surface 300u2 having a step difference. The first contact trench 110T can be formed to be recessed from the first upper surface 300u1 into the lower interlayer insulating layer 300. The second contact trench 310T can be formed to be recessed from the second upper surface 300u2 into the lower interlayer insulating layer 300. The second upper surface 300u2 of the lower interlayer insulating layer 300 can be formed to be lower than the first upper surface 300u1 of the lower interlayer insulating layer 300. The second contact trench 310T can be spaced apart from the first contact trench 110T in a first horizontal direction DR1. Subsequently, a first contact 110 can be formed in the first contact trench 110T, and a second contact 310 can be formed in the second contact trench 310T.

[0088] Reference Figure 31 A wiring barrier material layer 341M, a first conductive material layer 342M, and a second conductive material layer 343M can be sequentially formed on the upper surface of the first contact 110, the upper surface of the second contact 310, and the upper surface of the lower interlayer insulating layer 300.

[0089] Reference Figure 32 A first mask pattern M31 can be formed on the upper surface of the second conductive material layer 343M. For example, the first mask pattern M31 can overlap with the first contact 110 and the second contact 310 in the vertical direction DR3. For example, the first mask pattern M31 can extend in the second horizontal direction DR2. Then, using the first mask pattern M31 as a mask, a portion of the second conductive material layer 343M can be etched.

[0090] Reference Figure 33 The first mask pattern M31 can be removed (see...) Figure 32 Then, using the remaining second conductive material layer 343M as a mask, the first conductive material layer 342M can be etched (see...). Figure 32 Part of the wiring barrier material layer 341M (see) Figure 32 Part of ). After the etching process is completed, the first conductive material layer 342M (see Figure 32 The portion of the material retained on the upper surface of the first contact 110 can be defined as the first conductive layer 142, and the first conductive material layer 342M (see...) Figure 32 The portion of the material remaining on the upper surface of the second contact 310 can be defined as the fourth conductive layer 342. Furthermore, after the etching process is completed, the wiring barrier material layer 341M (see...) Figure 32The portion of the wired wiring barrier layer 141 that remains on the upper surface of the first contact 110 can be defined as the first wiring barrier layer 141, and the wiring barrier material layer 341M (see...) Figure 32 The portion of the wires retained on the upper surface of the second contact 310 can be defined as the second wiring barrier layer 341.

[0091] For example, the sidewalls of the second conductive material layer 343M, the first conductive layer 142, and the first wiring barrier layer 141 retained on the upper surface of the first contact 110 in the first horizontal direction DR1 may have a continuously inclined profile. Furthermore, the sidewalls of each of the second conductive material layer 343M, the fourth conductive layer 342, and the second wiring barrier layer 341 retained on the upper surface of the second contact 310 in the first horizontal direction DR1 may have a continuously inclined profile.

[0092] Reference Figure 34 A first upper interlayer insulating layer 320 can be formed on the upper surface of the lower interlayer insulating layer 300 to cover the second conductive material layer 343M, the first conductive layer 142, the first wiring barrier layer 141, the fourth conductive layer 342, and the second wiring barrier layer 341. Subsequently, a planarization process can be performed to expose the upper surface of the second conductive material layer 343M.

[0093] Reference Figure 35 An annealing process can be performed to remove the second conductive material layer 343M (see...) Figure 34 Nitrogen is removed from part of the first contact 110. For example, on the upper surface of the first contact 110, a second conductive material layer 343M (see...) Figure 34 The second conductive material layer 343M (see) has been removed. Figure 34 The portion in which nitrogen is removed can be defined as the third conductive layer 144. Furthermore, on the upper surface of the second contact 310, a second conductive material layer 343M (see...) Figure 34 The second conductive material layer 343M (see) has been removed. Figure 34 The nitrogen-removed portion of the layer can be defined as the sixth conductive layer 344.

[0094] For example, on the upper surface of the first contact 110, the second conductive material layer 343M (see...) Figure 34 The second conductive material layer 343M (see) was not present. Figure 34 The remaining portion after nitrogen removal in the second contact 310 can be defined as the second conductive layer 143. Furthermore, on the upper surface of the second contact 310, a second conductive material layer 343M (see...) Figure 34 The second conductive material layer 343M (see) was not present. Figure 34 The remaining portion after removing nitrogen in the fifth conductive layer 343 can be defined as the fifth conductive layer 343.

[0095] For example, in the first horizontal direction DR1, the sidewalls of the second wiring barrier layer 341, the fourth conductive layer 342, the fifth conductive layer 343, and the sixth conductive layer 344 that contact the first upper interlayer insulating layer 320 can have continuously inclined profiles. For example, the upper surfaces of the third conductive layer 144, the sixth conductive layer 344, and the first upper interlayer insulating layer 320 can be formed on the same plane. For example, the thickness of the sixth conductive layer 344 in the vertical direction DR3 can be greater than the thickness of the third conductive layer 144 in the vertical direction DR3.

[0096] Reference Figure 36 A second upper interlayer insulating layer 350 can be formed on the upper surfaces of the first upper interlayer insulating layer 320, the third conductive layer 144, and the sixth conductive layer 344. Subsequently, via trenches 160T and upper wiring trenches 170T can be formed in the second upper interlayer insulating layer 350. For example, via trenches 160T can be formed on the upper surface of the third conductive layer 144. Upper wiring trenches 170T can be formed above via trenches 160T. For example, via trenches 160T and upper wiring trenches 170T can be formed using the same manufacturing process. However, this disclosure is not limited thereto.

[0097] Reference Figure 29 It can be used in the through-hole trench 160T (see Figure 36 A via 160 is formed in the ) and a wiring trench 170T (see) can be formed on it. Figure 36 An upper wiring pattern 170 is formed in the third conductive layer 144. For example, the via 160 can contact the upper surface of the third conductive layer 144. The upper wiring pattern 170 can contact the upper surface of the via 160. For example, the via 160 and the upper wiring pattern 170 can be integrally formed. Through this manufacturing process, it is possible to manufacture... Figure 29 The semiconductor device shown.

[0098] The following will refer to Figure 37 A semiconductor device according to another embodiment of the present disclosure is described. This description will focus on [the following] respectively […]. Figure 18 and Figure 19 as well as Figure 29 The differences are shown in the semiconductor device.

[0099] Figure 37 This is a cross-sectional view used to illustrate a semiconductor device according to an embodiment of the present disclosure.

[0100] Reference Figure 37 A semiconductor device according to another embodiment of the present disclosure may include a second lower wiring pattern 430, which includes a second wiring barrier layer 341 and a fourth conductive layer 342.

[0101] For example, a second upper interlayer insulating layer 450 may be disposed on the upper surface of the first upper interlayer insulating layer 320. An upper wiring pattern 270 may be disposed in the second upper interlayer insulating layer 450. For example, the upper wiring pattern 270 may be electrically connected to a first lower wiring pattern 230 via a via 260. For example, the first lower wiring pattern 230 may include a first wiring barrier layer 141 and a first conductive layer 142. The first lower wiring pattern 230 may extend along a second horizontal direction DR2. That is, the first wiring barrier layer 141 and the first conductive layer 142 may each extend along the second horizontal direction DR2. For example, the via 260 may include a second conductive layer 243 and a third conductive layer 244.

[0102] For example, the upper surface of the lower interlayer insulating layer 300 may include a first upper surface 300u1 adjacent to the first contact trench 110T and a second upper surface 300u2 adjacent to the second contact trench 310T. For example, the second upper surface 300u2 of the lower interlayer insulating layer 300 may be formed to be lower than the first upper surface 300u1 of the lower interlayer insulating layer 300. For example, a second wiring barrier layer 341 may be disposed on the upper surface of the second contact member 310 and on the second upper surface 300u2 of the lower interlayer insulating layer 300. Furthermore, the second wiring barrier layer 341 may be disposed on the upper surface of the second contact member 310 along the sidewall of the second contact trench 310T. A fourth conductive layer 342 may be disposed on the upper surface of the second wiring barrier layer 341. For example, the second wiring barrier layer 341 and the fourth conductive layer 342 may each extend along a second horizontal direction DR2. For example, the upper surface of the fourth conductive layer 342 may contact the first upper interlayer insulating layer 320. For example, the upper surface of the fourth conductive layer 342 can be formed to be lower than the upper surface of the first conductive layer 142.

[0103] In some embodiments, each of the first wiring barrier layer 141 and the second wiring barrier layer 341 may be omitted. That is, the lower surface of the first conductive layer 142 may contact the upper surface of the first contact 110 and the lower interlayer insulating layer 300, and the lower surface of the fourth conductive layer 342 may contact the upper surface of the second contact 310 and the lower interlayer insulating layer 300. In some embodiments, at least one of the first conductive layer 142 and the third conductive layer 244 may include nitrogen atoms, and the fourth conductive layer 342 may also include nitrogen atoms.

[0104] In some embodiments, the second conductive layer 243 may not be provided. That is, the third conductive layer 244 may be in contact with the upper surface of the first conductive layer 142. For example, even without the second conductive layer 243, at least one of the first conductive layer 142 and the third conductive layer 244 may include nitrogen atoms, and the fourth conductive layer 342 may include nitrogen atoms. For example, if the fourth conductive layer 342 contains nitrogen atoms, the concentration of nitrogen atoms in the fourth conductive layer 342 may increase from the lower surface of the fourth conductive layer 342 toward the upper surface of the fourth conductive layer 342. The description of the distribution and relative concentration difference of nitrogen atoms in the first conductive layer 142 and the third conductive layer 244 is consistent with... Figures 1 to 3 The description is the same as that in the previous text, therefore, a detailed description will be omitted.

[0105] The following will refer to Figures 37 to 41 A method for manufacturing a semiconductor device according to another embodiment of the present disclosure is described. This description will focus on... Figures 30 to 36 The differences shown are in the methods used to manufacture semiconductor devices.

[0106] Figures 38 to 41 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0107] Reference Figure 38 In execution Figures 30 to 34 Following the manufacturing process shown, a second mask pattern M42 can be formed on the upper surface of the remaining second conductive material layer 343M and the upper surface of the first upper interlayer insulating layer 320. The second mask pattern M42 can overlap with the first contact 110 in the vertical direction DR3. For example, the second mask pattern M42 can expose the upper surface of the second conductive material layer 343M formed on the upper surface of the second contact 310.

[0108] Subsequently, using the second mask pattern M42 as a mask, the second conductive material layer 343M formed on the upper surface of the second contact 310 can be etched. This etching process exposes the upper surface of the fourth conductive layer 342. After the etching process is completed, the remaining second wiring barrier layer 341 and fourth conductive layer 342 can be defined as the second lower wiring pattern 430.

[0109] Reference Figure 39 The second mask pattern M42 can be removed (see...) Figure 38 Subsequently, a first interlayer insulating layer 320 may be formed on the upper surface of the fourth conductive layer 342. For example, a first interlayer insulating layer 320 may also be formed on the upper surface of the second conductive material layer 343M. Then, a planarization process may be performed to expose the upper surface of the second conductive material layer 343M.

[0110] Reference Figure 40 An annealing process can be performed to remove the second conductive material layer 343M (see...) Figure 39 Nitrogen is removed from a portion of the material. For example, the second conductive material layer 343M (see...) Figure 39 The second conductive material layer 343M (see) has been removed. Figure 39 The nitrogen-removed portion in the structure can be defined as the third conductive layer 244. Furthermore, the second conductive material layer 343M (see...) Figure 39 The second conductive material layer 343M (see) was not present. Figure 39 The remaining portion after nitrogen removal in the process can be defined as the second conductive layer 243. For example, the second conductive layer 243 and the third conductive layer 244 can be defined as a via 260.

[0111] Reference Figure 41 A second upper interlayer insulating layer 450 can be formed on the upper surface of the first upper interlayer insulating layer 320 and the upper surface of the third conductive layer 244. Then, an upper wiring trench 270T can be formed in the second upper interlayer insulating layer 450. For example, the upper wiring trench 270T can be formed on the upper surface of the third conductive layer 244. The upper surface of the third conductive layer 244 can be exposed through the bottom surface of the upper wiring trench 270T. For example, the upper wiring trench 270T can extend in the second horizontal direction DR2.

[0112] Reference Figure 37 It can be used to install 270T wiring trenches (see...) Figure 41 An upper wiring pattern 270 is formed in the process. For example, the upper wiring pattern 270 can contact the upper surface of the third conductive layer 244. This manufacturing process allows for the fabrication of... Figure 37 The semiconductor device shown.

[0113] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a contact in a lower interlayer insulating layer; forming a first conductive material layer comprising a metal on an upper surface of the lower interlayer insulating layer and an upper surface of the contact; forming a second conductive material layer comprising a metal nitride containing the metal on the upper surface of the first conductive material layer; etching a portion of the second conductive material layer; etching a portion of the first conductive material layer using the remaining portion of the second conductive material layer as a mask, wherein the remaining portion of the first conductive material layer is defined as the first conductive layer; forming a first upper interlayer insulating layer covering the sidewalls of each of the first conductive layer and the second conductive material layer in a first horizontal direction; and forming a third conductive layer comprising the metal by removing nitrogen from a portion of the second conductive material layer, wherein the remaining portion of the second conductive material layer from which nitrogen has not been removed is defined as the second conductive layer, wherein the sidewalls of the first conductive layer to the third conductive layer that contact the first upper interlayer insulating layer in the first horizontal direction have a continuously inclined profile.

[0114] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, including wherein a first conductive layer to a third conductive layer extends in a second horizontal direction different from a first horizontal direction.

[0115] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a mask pattern on the upper surface of the remaining portion of a second conductive material layer and on the upper surface of a first upper interlayer insulating layer before forming a third conductive layer; exposing the sidewalls of the second conductive material layer in a second horizontal direction different from a first horizontal direction by using the mask pattern as a mask to etch a portion of the second conductive material layer; and further forming a first upper interlayer insulating layer to cover the sidewalls of the second conductive material layer in the second horizontal direction.

[0116] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: after forming a third conductive layer, forming a second upper interlayer insulating layer on the upper surface of a first upper interlayer insulating layer and on the upper surface of the third conductive layer, and forming a via and an upper wiring pattern on the upper surface of the third conductive layer in the second upper interlayer insulating layer, wherein the via is in contact with the upper surface of the third conductive layer, the upper wiring pattern is in contact with the upper surface of the via, and the via and the upper wiring pattern are integrally formed.

[0117] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: after forming a third conductive layer, forming a second upper interlayer insulating layer on the upper surface of a first upper interlayer insulating layer and on the upper surface of the third conductive layer, and forming an upper wiring pattern in the second upper interlayer insulating layer that contacts the upper surface of the third conductive layer.

[0118] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood that the present disclosure is not limited to the above embodiments and can be implemented in various other forms. Those skilled in the art to which this disclosure pertains will understand that the present disclosure can be implemented in other specific forms without altering the technical concept or essential features. Therefore, the above embodiments should be understood as exemplary and not restrictive in all respects.

Claims

1. A semiconductor device, comprising: Lower interlayer insulation layer; The first contact trench is formed in the lower interlayer insulation layer; The first contact element is disposed in the first contact groove; A first conductive layer is disposed on the upper surface of the first contact member. The width of the first conductive layer in a first horizontal direction is greater than the width of the first contact groove in the first horizontal direction. The first conductive layer extends in a second horizontal direction different from the first horizontal direction. The first conductive layer includes metal. A second conductive layer is in contact with the upper surface of the first conductive layer, and the second conductive layer includes a metal nitride containing the metal; A third conductive layer, which is in contact with the upper surface of the second conductive layer, the third conductive layer comprising the metal; and A first upper interlayer insulating layer is disposed on the upper surface of the lower interlayer insulating layer, and the first upper interlayer insulating layer is in contact with the sidewalls of the first conductive layer to the third conductive layer in the first horizontal direction. Wherein, the sidewalls of the first conductive layer to the third conductive layer that contact the first upper interlayer insulating layer in the first horizontal direction have a continuously inclined profile.

2. The semiconductor device according to claim 1, wherein, The width of the upper surface of the third conductive layer in the first horizontal direction is smaller than the width of the upper surface of the first conductive layer in the first horizontal direction.

3. The semiconductor device according to claim 1, wherein, The first upper interlayer insulation layer is in contact with the upper surface of the lower interlayer insulation layer.

4. The semiconductor device according to claim 1, wherein, At least a portion of the first conductive layer is disposed in the first contact trench.

5. The semiconductor device according to claim 1, wherein, The metal is ruthenium (Ru), and the metal nitride is ruthenium nitride (RuN).

6. The semiconductor device according to claim 1, wherein, Each of the second conductive layer and the third conductive layer extends in the second horizontal direction.

7. The semiconductor device according to claim 1, wherein, The upper surface of the first conductive layer contacts the first upper interlayer insulating layer on the sidewall of each of the second and third conductive layers in the second horizontal direction.

8. The semiconductor device according to claim 1, further comprising: The second interlayer insulation layer is disposed on the upper surface of the first interlayer insulation layer; A via is disposed in the second upper interlayer insulating layer, and the via is in contact with the upper surface of the third conductive layer; as well as An upper wiring pattern is disposed in the second upper interlayer insulating layer, the upper wiring pattern is in contact with the upper surface of the via, the upper wiring pattern is integrally formed with the via, and the upper wiring pattern extends in the second horizontal direction.

9. The semiconductor device according to claim 1, further comprising: The second interlayer insulation layer is disposed on the upper surface of the first interlayer insulation layer; as well as An upper wiring pattern is disposed in the second upper interlayer insulating layer, the upper wiring pattern is in contact with the upper surface of the third conductive layer, and the upper wiring pattern extends in the second horizontal direction.

10. The semiconductor device of claim 1, further comprising: A second contact trench is formed in the lower interlayer insulating layer, and the second contact trench is spaced apart from the first contact trench in the first horizontal direction; The second contact element is disposed in the second contact groove; as well as A fourth conductive layer is disposed on the upper surface of the second contact member. The fourth conductive layer is spaced apart from the first conductive layer in the first horizontal direction and extends in the second horizontal direction. The fourth conductive layer comprises the metal. The upper surface of the fourth conductive layer is lower than the upper surface of the first conductive layer.

11. The semiconductor device according to claim 10, wherein, The upper surface of the lower interlayer insulation layer includes a first upper surface adjacent to the first contact trench and a second upper surface adjacent to the second contact trench, and Wherein, the second upper surface of the lower interlayer insulation layer is lower than the first upper surface of the lower interlayer insulation layer.

12. The semiconductor device of claim 10, further comprising: A fifth conductive layer is in contact with the upper surface of the fourth conductive layer, and the fifth conductive layer includes the metal nitride; as well as A sixth conductive layer, which is in contact with the upper surface of the fifth conductive layer, the sixth conductive layer comprising the metal, and the upper surface of the sixth conductive layer being formed on the same plane as the upper surface of the third conductive layer. The fourth to sixth conductive layers have a continuously inclined profile on their sidewalls in the first horizontal direction.

13. A semiconductor device, comprising: First contact element; A first conductive layer is disposed on the upper surface of the first contact element, and the first conductive layer comprises metal. A second conductive layer is in contact with the upper surface of the first conductive layer, and the second conductive layer includes a metal nitride containing the metal; A third conductive layer is in contact with the upper surface of the second conductive layer, and the third conductive layer includes the metal. A first upper interlayer insulating layer is in contact with the sidewalls of the first conductive layer to the third conductive layer in a first horizontal direction; The second interlayer insulation layer is disposed on the upper surface of the first interlayer insulation layer; as well as An upper wiring pattern is disposed on the upper surface of the third conductive layer, the upper wiring pattern extending in a second horizontal direction different from the first horizontal direction, and the upper wiring pattern being electrically connected to the third conductive layer. Wherein, the width of the upper surface of the third conductive layer in the first horizontal direction is smaller than the width of the upper surface of the first conductive layer in the first horizontal direction.

14. The semiconductor device according to claim 13, wherein, The sidewalls of the first conductive layer to the third conductive layer that contact the first upper interlayer insulating layer in the first horizontal direction have a continuously inclined profile.

15. The semiconductor device according to claim 13, wherein, The upper surface of the third conductive layer and the upper surface of the first interlayer insulating layer are formed on the same plane.

16. The semiconductor device of claim 13, further comprising: A wiring barrier layer is disposed between the upper surface of the first contact and the first conductive layer.

17. The semiconductor device according to claim 13, wherein, Each of the second conductive layer and the third conductive layer extends in the second horizontal direction.

18. The semiconductor device of claim 13, further comprising: The second contact is spaced apart from the first contact in the first horizontal direction; as well as A fourth conductive layer is disposed on the upper surface of the second contact member. The fourth conductive layer is spaced apart from the first conductive layer in the first horizontal direction and extends in the second horizontal direction. The fourth conductive layer comprises the metal. The upper surface of the fourth conductive layer is lower than the upper surface of the first conductive layer.

19. The semiconductor device of claim 18, further comprising: A fifth conductive layer is in contact with the upper surface of the fourth conductive layer, and the fifth conductive layer includes the metal nitride; as well as A sixth conductive layer, which is in contact with the upper surface of the fifth conductive layer, the sixth conductive layer comprising the metal, and the upper surface of the sixth conductive layer being formed on the same plane as the upper surface of the third conductive layer. The fourth to sixth conductive layers have a continuously inclined profile on their sidewalls in the first horizontal direction.

20. A semiconductor device, comprising: Lower interlayer insulation layer; Contact trenches are formed in the underlying interlayer insulation layer; A contact element disposed in the contact groove; A wiring barrier layer that contacts the upper surface of the contact element; A first conductive layer is in contact with the upper surface of the wiring barrier layer. The width of the first conductive layer in a first horizontal direction is greater than the width of the contact trench in the first horizontal direction. The first conductive layer extends in a second horizontal direction different from the first horizontal direction. The first conductive layer includes ruthenium (Ru). A second conductive layer is in contact with the upper surface of the first conductive layer, the second conductive layer comprising ruthenium nitride (RuN), and the second conductive layer extends in the second horizontal direction; A third conductive layer is in contact with the upper surface of the second conductive layer, the third conductive layer comprising ruthenium (Ru), and the third conductive layer extending in the second horizontal direction; A first upper interlayer insulating layer is disposed on the upper surface of the lower interlayer insulating layer. The first upper interlayer insulating layer is in contact with the sidewalls of the first conductive layer to the third conductive layer in the first horizontal direction. The upper surface of the first upper interlayer insulating layer and the upper surface of the third conductive layer are formed on the same plane. The second interlayer insulation layer is disposed on the upper surface of the first interlayer insulation layer; A via is disposed in the second upper interlayer insulating layer, and the via is in contact with the upper surface of the third conductive layer; as well as An upper wiring pattern is disposed in the second upper interlayer insulating layer. The upper wiring pattern contacts the upper surface of the via and is integrally formed with the via. The upper wiring pattern extends in the second horizontal direction. Wherein, the sidewalls of the first conductive layer to the third conductive layer that contact the first upper interlayer insulating layer in the first horizontal direction have a continuously inclined profile, and Wherein, the width of the upper surface of the third conductive layer in the first horizontal direction is smaller than the width of the upper surface of the first conductive layer in the first horizontal direction.

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