Three-dimensional integrated circuit, semiconductor device, and method of operating a three-dimensional integrated circuit

Abstract

A 3D integrated circuit includes: a first semiconductor die including: a first logic circuit; and a first interface circuit; a second semiconductor die including: a second logic circuit; and a second interface circuit; and an interconnect connected to the first semiconductor die and the second semiconductor die, wherein the first interface circuit includes: a transmission circuit connected to the interconnect; a first scan chain circuit that outputs first test data to the transmission circuit during a first test period; a first repair logic circuit configured to: set a first repair path that replaces a defective interconnect in the interconnect with a non-defective redundant interconnect based on defect information generated from a first test result from the first test data; and output input data to the first scan chain circuit via the first repair path; and a second scan chain circuit that outputs second test data to the first repair path during a second test period.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0054111 filed with the Korean Intellectual Property Office on April 24, 2025 and Korean Patent Application No. 10-2025-0151963 filed with the Korean Intellectual Property Office on October 20, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to semiconductor devices and methods for testing 3D integrated circuits and semiconductor devices. Background Technology

[0004] 3D integrated circuits consist of multiple semiconductor dies (or integrated circuits) stacked on top of each other. The semiconductor dies in a 3D integrated circuit are electrically connected to each other via interconnects to perform communication. In 3D integrated circuits, the process failure rate of interconnects is significantly higher than that of metal wiring in single-crystal silicon. Therefore, remediation schemes can be used for interface circuits within the semiconductor dies to detect defective interconnects through testing and replace defective interconnects with redundant, defect-free interconnects. Summary of the Invention

[0005] This disclosure may provide a three-dimensional (3D) integrated circuit, a semiconductor device, and a method for testing 3D integrated circuits, which is capable of detecting defects in interconnects and defects throughout the signal path, the entire signal path including a repair path for replacing defective interconnects with defect-free interconnects.

[0006] One or more embodiments of this disclosure may provide a 3D integrated circuit, comprising: a first semiconductor die including: a first logic circuit; and a first interface circuit; a second semiconductor die including: a second logic circuit; and a second interface circuit; and a plurality of interconnects connected to the first semiconductor die and the second semiconductor die, the plurality of interconnects being configured to transmit signals, wherein the first interface circuit includes: a plurality of transmitting circuits connected to the plurality of interconnects; a first scan chain circuit configured to output first test data to the plurality of transmitting circuits during a first test period; a first repair logic circuit configured to: set a first repair path based on defect information generated from a first test result from the first test data, the first repair path being configured to replace defective interconnects in the plurality of interconnects with defect-free redundant interconnects; and output input data to the first scan chain circuit along the first repair path; and a second scan chain circuit configured to output second test data to the first repair path during a second test period.

[0007] One or more embodiments of this disclosure may provide a semiconductor device including: a first semiconductor die including: a first interface circuit; and a first test controller; a second semiconductor die including: a second interface circuit; and a second test controller; and a plurality of interconnects connected to the first semiconductor die and the second semiconductor die, the plurality of interconnects being configured to transmit signals, wherein the first interface circuit includes: a first scan chain circuit configured to: receive first test data from the first test controller via the plurality of interconnects; and output the first test data; a first repair logic circuit configured to: set a first repair path based on a first test result from the first test data, the first repair path being configured to replace defective interconnects in the plurality of interconnects with defect-free redundant interconnects; and a second scan chain circuit configured to: receive second test data from the first test controller via the plurality of interconnects; detect defects in a signal path based on the second test data; and output the second test data, wherein the signal path includes: the first repair path; the first scan chain circuit; and an interconnect in the plurality of interconnects corresponding to the first repair path.

[0008] One or more embodiments of this disclosure may provide a 3D integrated circuit including a first semiconductor die and a second semiconductor die interconnected to each other via a plurality of interconnects. The method includes: performing a first test by transmitting first test data from a first scan chain circuit of the first semiconductor die to a second scan chain circuit of the second semiconductor die via a first test path including the plurality of interconnects; setting a repair path based on defect information generated by the result of the first test, the repair path including: a first repair logic circuit of the first semiconductor die; and a second repair logic circuit of the second semiconductor die, wherein the repair path is configured to replace defective interconnects in the plurality of interconnects with defect-free redundant interconnects; and performing a second test by transmitting second test data from a third scan chain circuit of the first semiconductor die to a fourth scan chain circuit of the second semiconductor die via a second test path, the second test path including the repair path and interconnects in the plurality of interconnects corresponding to the repair path. Attached Figure Description

[0009] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a semiconductor device according to one or more embodiments;

[0011] Figures 2A to 2C This is a diagram illustrating the interconnections according to an embodiment;

[0012] Figure 3 This is a block diagram illustrating a semiconductor device according to one or more embodiments;

[0013] Figure 4 This is a block diagram illustrating test operations of a semiconductor device according to one or more embodiments. Figure 5A This illustrates a first test path for a semiconductor device according to one or more embodiments. Figure 5B This illustrates a second test path for a semiconductor device according to one or more embodiments;

[0014] Figure 6 This illustrates the data path during normal operation of a semiconductor device according to one or more embodiments;

[0015] Figures 7A to 7G Test methods for semiconductor devices according to one or more embodiments are shown sequentially;

[0016] Figure 8A and Figure 8B Examples of first and second repair logic provided in a semiconductor device according to one or more embodiments are shown;

[0017] Figure 9A and Figure 9B The test method for the semiconductor device according to the comparative example is shown;

[0018] Figure 10 This is a block diagram illustrating a semiconductor device according to one or more embodiments;

[0019] Figure 11 This is a block diagram illustrating a semiconductor device according to one or more embodiments;

[0020] Figure 12 This is a block diagram illustrating a semiconductor device according to one or more embodiments;

[0021] Figure 13A , Figure 13B , Figure 13C and Figure 13D This is a structural diagram illustrating a semiconductor device according to an embodiment; and

[0022] Figure 14 This is a structural diagram illustrating an example of an electronic system according to one or more embodiments. Detailed Implementation

[0023] All embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude the possibility of being associated with one or more features of another example or another embodiment, whether also provided or not provided herein but consistent with the content of this disclosure.

[0024] It will be understood that when an element, component, layer, pattern, structure, region, etc., of a semiconductor device (collectively referred to below as "element") is described as being "above," "on top of," "above," "below," "below," "connected to," or "coupled to" another element of the semiconductor device, it may be directly above, above, above, below, below, connected to, or coupled to the other element, or intermediate elements may exist. Conversely, when an element of a semiconductor device is described as being "directly above," "directly above," "directly on," "directly below," "directly connected to," or "directly coupled to" another element of the semiconductor device, no intermediate elements exist.

[0025] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, when a statement such as “at least one of…” follows an element in a column, it modifies the entire column, not a single element in that column. For example, the statements “at least one of a, b, and c” and “at least one of a, b, or c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0026] It will also be understood that even if a step or operation in manufacturing an apparatus or structure is described as being performed after another step or operation, that step or operation may be performed after the other step or operation, unless the other step or operation is described as being performed after that step or operation.

[0027] The various embodiments and terminology used in this document are not intended to limit the technical features described herein to the particular embodiments, and should be understood to include various modifications, equivalents, or alternatives to the corresponding embodiments.

[0028] Similar reference numerals may be used for similar or related components in conjunction with the description in the accompanying drawings.

[0029] Unless otherwise explicitly stated in the relevant context, the singular form of the noun corresponding to an item may include one or more items.

[0030] The embodiments of this disclosure described in this specification and accompanying drawings are presented as specific examples only to explain the technical content of the embodiments according to this disclosure and to aid in understanding the embodiments of this disclosure, and are not intended to limit the scope of the embodiments of this disclosure. Therefore, the scope of one or more embodiments of this disclosure should be interpreted to cover all variations or modifications of the technical spirit derived from one or more embodiments of this disclosure other than those disclosed herein.

[0031] It should be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” “tertiary,” etc., may be used herein to describe various elements, the elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and a second element may be referred to as a first element. The term “and / or” includes a combination of multiple related items or any one of multiple related items.

[0032] When a component (e.g., a first component) is referred to as being “(functionally or communicatively) coupled” or “connected” to another component (e.g., a second component), the first component may be connected to the second component directly (e.g., wired), wirelessly, or via a third component.

[0033] In this disclosure, the terms “containing,” “including,” “comprising,” “having,” etc., are used to specify features, numbers, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0034] Furthermore, in this disclosure, "identical" means situations where the properties are similar to each other or similar within a certain range. Additionally, unless otherwise expressly indicated, stated, and / or shown, as used herein, the terms "same," "uniform," "equal," and / or "identical" mean "substantially identical," "substantially uniform," "substantially equal," "approximately identical," and / or "substantially the same." "Substantially identical" should be understood to include numerical values ​​within manufacturing tolerances, processing or handling tolerances, and / or differences within insignificant ranges such that the structure and function of the embodiments disclosed herein are not substantially altered, suppressed, or disrupted.

[0035] Unless otherwise stated, as used herein with respect to any plurality of components of a particular type, any two components of that type are considered “adjacent” or “nearby” to each other, provided that no other component of that type occupies the space between the two components. That is, if two components are not separated from each other by an intermediate component of that type, the two components are considered to be adjacent to each other.

[0036] Furthermore, while one or more embodiments may include the features disclosed herein, as well as additional features not specifically described, other embodiments may alternatively omit any undisclosed elements. For example, undisclosed elements may be completely omitted from one or more embodiments of this disclosure.

[0037] As used herein with reference to accompanying drawings, illustrations, graphs, and / or any other graphic depictions, the term "plan view" can refer to an orthogonal projection of at least a portion of a surface, area, object, structure, and / or any other feature from a location on a plane that is coplanar with or intersects with at least a portion of the feature. For example, a "plan view" (also known as a "top-down view" or "top view") can be a cross-sectional view taken from above one or more features. In such a plan view, portions of one or more features located above the plane shown in the plan view may be omitted to better illustrate portions of one or more features located below the plane.

[0038] As used herein, the terms “front (or forward),” “back (or rearward, backward, facing backward),” “up (or upper part, top, above),” “down (or lower part, bottom, below),” “left,” “right,” etc., may be defined with reference to the accompanying drawings and may not be intended to limit the shape and / or position of each component.

[0039] Figure 1 This is a block diagram illustrating a semiconductor device 1 according to one or more embodiments.

[0040] Reference Figure 1 The semiconductor device 1 may include a first semiconductor die 100, a second semiconductor die 200, and a plurality of interconnects 30. In one or more embodiments, the first semiconductor die 100 and the second semiconductor die 200 may be stacked in a vertical direction, and therefore, the semiconductor device 1 may be referred to as a three-dimensional (3D) integrated circuit.

[0041] The first semiconductor die 100 and the second semiconductor die 200 may include integrated circuits for performing certain functions, and may be referred to as logic dies, memory dies, analog dies, etc., depending on their functions. The first semiconductor die 100 may perform the same or different functions as the second semiconductor die 200. For example, when the first semiconductor die 100 and the second semiconductor die 200 are implemented as logic dies, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU) / artificial intelligence (AI) accelerator, a digital signal processor (DSP), a power management integrated circuit (PMIC), a memory controller, I / O interface circuits, security circuits, and on-chip memory may be implemented in the first semiconductor die 100 and / or the second semiconductor die 200.

[0042] The first semiconductor die 100 and the second semiconductor die 200 may be formed on silicon, silicon-on-insulator, or a compound semiconductor substrate. The first semiconductor die 100 and the second semiconductor die 200 may include a plurality of active elements and a plurality of passive devices, and each of the elements may be interconnected via a metal layer.

[0043] According to the manufacturing process of semiconductor device 1, the manufacturing process for forming the first semiconductor die 100 may be the same as or different from the manufacturing process for forming the second semiconductor die 200. The first semiconductor die 100 and the second semiconductor die 200 may be stacked on top of each other in the vertical direction based on a die-to-die stacking method, a die-to-wafer stacking method, or a wafer-to-wafer stacking method.

[0044] The multiple interconnects 30 may include structures for transmitting electrical signals between the first semiconductor die 100 and the second semiconductor die 200, and may be implemented as silicon vias (TSVs), microbumps, or hybrid bonding (e.g., bonding pads).

[0045] The plurality of interconnects 30 may include more interconnects than the number of signals (data) transmitted and received in parallel between the first semiconductor die 100 and the second semiconductor die 200 during normal operation of the semiconductor device 1. For example, when n signals (where n is an integer greater than or equal to 2) are transmitted and received in parallel (or simultaneously) between the first semiconductor die 100 and the second semiconductor die 200, the plurality of interconnects 30 may include m interconnects (where m is an integer greater than n), which includes n interconnects (hereinafter referred to as normal interconnects) and one or more redundant interconnects. Here, a normal interconnect refers to an interconnect that is essentially configured to transmit signals unless the interconnect itself is defective. A redundant interconnect refers to an interconnect that is provided to directly or indirectly (e.g., in a roundabout manner) replace a defective normal interconnect in the interconnect. Hereinafter, in this disclosure, "replacement" may mean either direct replacement or indirect replacement.

[0046] During the fabrication of semiconductor device 1, multiple interconnects 30 are subjected to numerous stress conditions, which can lead to various defects within the interconnects 30. For example, cracks may form in the material surrounding the TSV, causing a short circuit between the TSV and adjacent electrodes, or voids may form in the interconnects during the bonding process. Defective interconnects may fail to transmit signals correctly, and therefore, the reliability of all circuit operations may be reduced. Therefore, a repair scheme can be employed, thereby replacing defective normal interconnects with defect-free redundant interconnects.

[0047] The first semiconductor die 100 may include a first interface circuit 110 and a first logic circuit 120, and the second semiconductor die 200 may include a second interface circuit 210 and a second logic circuit 220. The first logic circuit 120 is a circuit that performs data processing operations (such as calculation, control, or determination) corresponding to certain functions supported by the first semiconductor die 100, and may include at least one of arithmetic logic circuits, control circuits, registers, multiplexers, sequential logic circuits, and combinational logic circuits. The second logic circuit 220 is a circuit that performs data processing operations (such as calculation, control, and determination) corresponding to certain functions supported by the second semiconductor die 200, and may include at least one of arithmetic logic circuits, control circuits, registers, multiplexers, sequential logic circuits, and combinational logic circuits. In one or more embodiments, the first logic circuit 120 and the second logic circuit 220 may be broadly defined as the remaining portion or a portion of the remaining portion of the first semiconductor die 100 and the second semiconductor die 200, excluding the first interface circuit 110 and the second interface circuit 210, respectively.

[0048] The first interface circuit 110 and the second interface circuit 210 can be configured to send and receive various signals between the first semiconductor die 100 and the second semiconductor die 200.

[0049] During normal operation mode (or normal operation period, also known as "non-test" mode or "non-test" period), the first interface circuit 110 and the second interface circuit 210 can send and receive signals (e.g., operation data) between the first logic circuit 120 and the second logic circuit 220.

[0050] During a test mode (or test period), the first interface circuit 110 and the second interface circuit 210 can be used to test for defects in the plurality of interconnects 30, and can also be used to test whether signals are correctly sent and received between the first interface circuit 110 and the second interface circuit 210. For example, the test can be performed during the manufacturing stage of the semiconductor device 1.

[0051] In normal operating mode, the first interface circuit 110 and the second interface circuit 210 operate based on a first clock signal (e.g., a function clock signal). In test mode, the first interface circuit 110 and the second interface circuit 210 operate based on a second clock signal (a test clock signal). The frequency of the first clock signal may differ from the frequency of the second clock signal. For example, the frequency of the first clock signal may be higher than the frequency of the second clock signal.

[0052] The first interface circuit 110 may include a first scan chain 11 (e.g., a first scan chain circuit), a first repair logic 12 (e.g., a first repair logic circuit), and a second scan chain 13 (e.g., a second scan chain circuit). In one or more embodiments, the first scan chain 11 may be located near the boundary of a first semiconductor die 100 near a plurality of interconnects 30, the first repair logic 12 may be connected between the first scan chain 11 and the second scan chain 13, and the second scan chain 13 may be electrically connected to the first logic circuit 120. In this document, any “scan chain” or “repair logic” may be understood to include circuits and / or circuit systems.

[0053] The first scan chain 11 and the second scan chain 13 may each include multiple flip-flops F / F. Each of the multiple flip-flops F / F can temporarily store and output 1 bit of data. The multiple flip-flops F / F can be connected in series to receive data sequentially or simultaneously, temporarily store it, and then output the data. The flip-flops F / F can be replaced by other storage elements such as latches and registers, and the flip-flops F / F or other storage elements may be referred to as scan units.

[0054] The number of flip-flops F / F in the first scan chain 11 can be greater than the number of flip-flops F / F in the second scan chain 13. For example, the first scan chain 11 may include a plurality of flip-flops F / F equal to the number of interconnects 30 (e.g., m flip-flops F / F), and the second scan chain 13 may include a plurality of flip-flops F / F equal to the number of signals transmitted and received in parallel between the first semiconductor die 100 and the second semiconductor die 200 (e.g., n flip-flops F / F).

[0055] The first scan chain 11 can be used for a first test to detect defective interconnects among the plurality of interconnects 30. Based on defect information generated according to the test results of the first test, the first repair logic 12 can perform repair by routing a signal path (specifically a repair path) between the first scan chain 11 and the second scan chain 13. According to the repair path set in the first repair logic 12, a defect-free redundant interconnect among the plurality of interconnects 30 can replace a defective normal interconnect. After the repair is performed (e.g., after the repair path is set in the first repair logic 12), the second scan chain 13 can be used for a second test to detect whether a defect occurs in the entire signal path (or data path) including the first repair logic 12, the first scan chain 11, and the plurality of interconnects 30.

[0056] The second interface circuit 210 may have a structure symmetrical with respect to the first interface circuit 110. The second interface circuit 210 may include a third scan chain 21, a second repair logic 22, and a fourth scan chain 23.

[0057] In one or more embodiments, the third scan chain 21 may be located near the boundary of the second semiconductor die 200 near the plurality of interconnects 30, the second repair logic 22 may be connected between the third scan chain 21 and the fourth scan chain 23, and the fourth scan chain 23 may be electrically connected to the second logic circuit 220.

[0058] The third scan chain 21 and the fourth scan chain 23 may each include multiple triggers F / F, and the number of triggers F / F in the third scan chain 21 may be greater than the number of triggers F / F in the fourth scan chain 23. For example, the number of triggers F / F in the third scan chain 21 may be equal to the number of triggers F / F in the first scan chain 11, and the number of triggers F / F in the fourth scan chain 23 may be equal to the number of triggers F / F in the second scan chain 13.

[0059] The third scan chain 21 can be used for a first test to detect defective interconnects among the multiple interconnects 30. The first test can be performed by sending first test data via a first test path including the first scan chain 11, the multiple interconnects 30 and the third scan chain 21.

[0060] Based on the defect information generated according to the test results of the first test, the second repair logic 22 can perform repair by routing the repair path between the third scan chain 21 and the fourth scan chain 23.

[0061] After the repair path is set in the second repair logic 22, the fourth scan chain 23 can be used for a second test to detect defects in the entire signal path, which includes multiple interconnects 30, the third scan chain 21, and the second repair logic 22.

[0062] Therefore, in the test mode of semiconductor device 1, before performing repair, a first test for detecting defects in multiple interconnects 30 can be performed using a first scan chain 11 and a third scan chain 21. Furthermore, the first repair logic 12 and the second repair logic 22 can perform repair based on defect information generated according to the test results of the first test. Additionally, after performing repair, a second test for detecting defects throughout the entire signal path can be performed using a second scan chain 13 and a fourth scan chain 23. The first test can be referred to as the pre-repair test, and the second test can be referred to as the post-repair test. See below for further details. Figures 4 to 7G The first test, the repair, and the second test are described in more detail.

[0063] As described above, the semiconductor device 1 according to one or more embodiments can perform a first test to detect defects present in a plurality of interconnects 30. The first test can be performed without being affected by the internal logic (e.g., first repair logic 12 and second repair logic 22) of the first interface circuit 110 and the second interface circuit 210, thus accurately detecting whether defects occur in the plurality of interconnects 30. Furthermore, since defects can also be detected in redundant interconnects, testability can be improved.

[0064] Furthermore, the semiconductor device 1 according to one or more embodiments can perform a second test to detect whether a defect occurs in the entire signal path, which includes not only the plurality of interconnects 30 but also the first repair logic 12 and the second repair logic 22. Therefore, the test coverage is expanded, and the operational reliability of the entire signal path, including the repair path, can be verified.

[0065] Figures 2A to 2C This is a diagram illustrating the interconnections according to an embodiment.

[0066] Reference Figure 2A The first semiconductor die 100_A and the second semiconductor die 200_A can be vertically stacked. The first semiconductor die 100_A may include a substrate SUB1 and a layer L1 formed by a back-end process (BEOL), and layer L1 may include an active element AC1 (e.g., a transistor, diode, optical device, etc.) formed by a front-end process (FEOL). The second semiconductor die 200_A may include a substrate SUB2 and a layer L2 formed by BEOL, and layer L2 may include an active element AC2 formed by FEOL.

[0067] The first semiconductor die 100_A and the second semiconductor die 200_A can be stacked in a face-to-face (F2F) configuration. Specifically, bonding pad 30A_1 connected to active component AC1 can be formed on the upper end of layer L1 of the first semiconductor die 100_A, and bonding pad 30A_2 connected to active component AC2 can be formed on the upper end of layer L2 of the second semiconductor die 200_A. Bonding pads 30A_1 and 30A_2 can then be bonded to each other. Therefore, interconnect 30A can include bonding pads 30A_1 and 30A_2.

[0068] Reference Figure 2B The first semiconductor die 100_B may include a substrate SUB1 having a through-silicon via (TSV) 33B and a layer L1 having an active element AC1 connected to the TSV 33B. The second semiconductor die 200_B may include a substrate SUB2 having a TSV 34B and a layer L2 having an active element AC2 connected to the TSV 34B.

[0069] The first semiconductor die 100_B and the second semiconductor die 200_B can be stacked in a back-to-back (B2B) configuration. A bonding pad 30B_1 connected to TSV 33B can be formed on the upper end of the substrate SUB1 of the first semiconductor die 100_B, and a bonding pad 30B_2 connected to TSV 34B can be formed on the upper end of the substrate SUB2 of the second semiconductor die 200_B. The bonding pads 30B_1 and 3B_2 can then be bonded to each other. Therefore, the interconnect 30B can include bonding pads 30B_1 and 30B_2, as well as TSVs 33b and 34B.

[0070] Reference Figure 2C The first semiconductor die 100_C may include a substrate SUB1 and a layer L1 having an active element AC1. The second semiconductor die 200_C may include a substrate SUB2 having a TSV 34C and a layer L2 having an active element AC2 connected to the TSV 34C.

[0071] The first semiconductor die 100_C and the second semiconductor die 200_C can be stacked in a face-to-back (F2B) configuration. A bonding pad 30C_1 connected to the active component AC1 can be formed on the upper end of layer L1 of the first semiconductor die 100_C, and a bonding pad 30C_2 connected to the TSV 34C can be formed on the upper end of the substrate SUB2 of the second semiconductor die 200_C. The bonding pads 30C_1 and 30C_2 can then be bonded to each other. Therefore, the interconnect 30C can include bonding pads 30C_1 and 30C_2 and the TSV 34C.

[0072] However, Figures 2A to 2C The interconnects 30A, 30B, and 30C shown are merely examples, and the embodiments are not limited thereto. The interconnects according to this disclosure can be implemented in various other forms.

[0073] Figure 3 This is a block diagram illustrating a semiconductor device 1a according to one or more embodiments.

[0074] Reference Figure 3 Semiconductor device 1a may include a first semiconductor die 100a, a second semiconductor die 200a, and a plurality of interconnects 30. The plurality of interconnects 30 may include first normal interconnects 31_1 to nth normal interconnects 31_n, and redundant interconnects 32_1 and 32_2. For ease of description, Figure 3The diagram shows redundant interconnects 32_1 and 32_2 arranged on one side of the first normal interconnects 31_1 to the nth normal interconnect 31_n, and the redundant interconnects 32_1 and 32_2 are adjacent to each other; however, the embodiment is not limited to this. Redundant interconnects 32_1 and 32_2 may be arranged on opposite sides of the first normal interconnects 31_1 to the nth normal interconnect 31_n, or they may be arranged between the first normal interconnects 31_1 to the nth normal interconnect 31_n, and the redundant interconnects 32_1 and 32_2 may not be adjacent to each other.

[0075] The first semiconductor die 100a may include a first interface circuit 110a, a first test controller 130, and a first non-volatile memory 140. The second semiconductor die 200a may include a second interface circuit 210a, a second test controller 230, and a second non-volatile memory 240. The first semiconductor die 100a and the second semiconductor die 200a also each include a first logic circuit 120 (see...). Figure 1 ) and second logic circuit 220 (see Figure 1 ).

[0076] In an embodiment, the first interface circuit 110a can send signals (data) to the second interface circuit 210a, and the second interface circuit 210a can receive data from the first interface circuit 110a.

[0077] The first interface circuit 110a may include a first scan chain 11, a first repair logic 12, a second scan chain 13, and multiple transmission circuits (e.g., first transmission circuit D1 to m-th transmission circuit Dm).

[0078] The first transmitting circuit D1 to the m-th transmitting circuit Dm may include the first transmitting circuit to the n-th transmitting circuit and redundant transmitting circuits, and may also be referred to hereinafter as the first transmitting circuit D1 to the n-th transmitting circuit to Dn and the redundant transmitting circuits Dm-1 and Dm. In one or more embodiments, the number of redundant transmitting circuits Dm-1 and Dm may be equal to the number of redundant interconnects 32_1 and 32_2.

[0079] The first transmitting circuit D1 to the m-th transmitting circuit Dm can transmit the input signal to the corresponding interconnect in the plurality of interconnects 30. In one or more embodiments, the first transmitting circuit D1 to the m-th transmitting circuit Dm can be implemented as a transmitting buffer.

[0080] In one or more embodiments, the first transmitting circuit D1 to the m-th transmitting circuit Dm can be connected one-to-one to a plurality of interconnects 30, and each transmitting circuit can transmit (or output) an input signal to a corresponding one of the plurality of interconnects 30. For example, the first transmitting circuit D1 to the n-th transmitting circuit Dn can be connected one-to-one to the first normal interconnects 31_1 to the n-th normal interconnects 31_n, while the redundant transmitting circuits Dm-1 and Dm can be connected one-to-one to the redundant interconnects 32_1 and 32_2.

[0081] The first scan chain 11 may include a plurality of first flip-flops F11 to F1m, and the number of first flip-flops F11 to F1m may be m. The plurality of first flip-flops F11 to F1m may include n first flip-flops and first redundant flip-flops, and may also be referred to hereinafter as n first flip-flops F11 to F1n and first redundant flip-flops F1m-1 and F1m. In one or more embodiments, the number of first redundant flip-flops F1m-1 and F1m may be equal to the number of redundant transmitting circuits Dm-1 and Dm. The plurality of first flip-flops F11 to F1m may be connected one-to-one to the first transmitting circuits D1 to the m-th transmitting circuit Dm. The plurality of first flip-flops F11 to F1m may temporarily store received data, and then output the data to the first transmitting circuits D1 to the m-th transmitting circuit Dm.

[0082] The second scan chain 13 may include multiple second flip-flops F21 to F2n, and the number of second flip-flops F21 to F2n may be n. The number of second flip-flops F21 to F2n may be less than the number of first flip-flops F11 to F1m. The multiple second flip-flops F21 to F2n may temporarily store the received data, and then output the data to the first repair logic 12.

[0083] The first repair logic 12 can output data received from the second scan chain 13 to the first scan chain 11. The first repair logic 12 can route signal paths between the first scan chain 11 and the second scan chain 13, and can output data (e.g., n bits of data) received from a plurality of second flip-flops F21 to F2n of the second scan chain 13 to the corresponding n first flip-flops F11 to F1m of a plurality of first flip-flops of the first scan chain 11.

[0084] For example, the first repair logic 12 can be implemented as one or more multiplexers (or demultiplexers), and based on the first selection signal, the multiplexer can select n first flip-flops to which data is to be sent from a plurality of first flip-flops F11 to F1m in the first scan chain 11.

[0085] The second interface circuit 210a may include multiple receiving circuits (e.g., first receiving circuit R1 to m-th receiving circuit Rm), a third scan chain 21, a second repair logic 22, and a fourth scan chain 23.

[0086] The first receiving circuit R1 to the m-th receiving circuit Rm may include the first to n-th receiving circuits and redundant receiving circuits, and may also be referred to hereinafter as the first receiving circuit R1 to the n-th receiving circuit Rn and the redundant receiving circuits Rm-1 and Rm. In one or more embodiments, the number of redundant receiving circuits Rm-1 and Rm may be equal to the number of redundant interconnects 32_1 and 32_2.

[0087] The first receiving circuit R1 to the m-th receiving circuit Rm can receive signals from corresponding interconnects among the plurality of interconnects 30. In one or more embodiments, the first receiving circuit R1 to the m-th receiving circuit Rm can be implemented as a receive buffer.

[0088] In one or more embodiments, the first receiving circuit R1 to the m-th receiving circuit Rm can be connected one-to-one to a plurality of interconnects 30, and each receiving circuit can receive data transmitted (or output) from a corresponding one of the plurality of interconnects 30. For example, the first receiving circuit R1 to the n-th receiving circuit Rn can be connected one-to-one to the first normal interconnects 31_1 to the n-th normal interconnects 31_n, and the redundant receiving circuits Rm-1 and Rm can be connected one-to-one to the redundant interconnects 32_1 and 32_2.

[0089] The third scan chain 21 may include multiple third flip-flops F31 to F3m, and the number of third flip-flops F31 to F3m may be m. The multiple third flip-flops F31 to F3m may include n third flip-flops and third redundant flip-flops, and may also be referred to hereinafter as n third flip-flops F31 to F3n and third redundant flip-flops F3m-1 and F3m. In one or more embodiments, the number of third redundant flip-flops F3m-1 and F3m may be equal to the number of redundant receiving circuits Rm-1 and Rm. The multiple third flip-flops F31 to F3m may be connected one-to-one to the first receiving circuit R1 to the m-th receiving circuit Rm. The multiple third flip-flops F31 to F3m may temporarily store data received from the first receiving circuit R1 to the m-th receiving circuit Rm, and then output the data to the second repair logic 22.

[0090] The fourth scan chain 23 may include multiple fourth flip-flops F41 to F4n, and the number of fourth flip-flops F41 to F4n may be n. The number of fourth flip-flops F41 to F4n may be less than the number of multiple third flip-flops F31 to F3m. The multiple fourth flip-flops F41 to F4n may temporarily store data received from the second repair logic 22 and then output the data.

[0091] The second repair logic 22 can output the data received from the third scan chain 21 to the fourth scan chain 23. The second repair logic 22 can route the signal path between the third scan chain 21 and the fourth scan chain 23, and can output the data (e.g., n bits of data) received from n third flip-flops (F31 to F3m) corresponding to the multiple fourth flip-flops F41 to F4n in the third scan chain 21 to multiple fourth flip-flops F41 to F4n.

[0092] For example, the second repair logic 22 can be implemented as one or more multiplexers (or demultiplexers), and based on the second selection signal, the multiplexer can select n third flip-flops to receive data from a plurality of third flip-flops F31 to F3m in the third scan chain 21.

[0093] The first test controller 130 and the second test controller 230 can perform tests in a test mode. The first test controller 130 can provide test data to the first interface circuit 110a, and the test data (or conversion data generated based on the test data) can be transmitted from the first interface circuit 110a to the second interface circuit 210a via multiple interconnects 30. The second test controller 230 can receive test data (or conversion data) from the second interface circuit 210a and generate (or analyze) test results by comparing the received test data with comparison data (e.g., a gold reference value or expected value).

[0094] For reference Figure 1 As described, a first test and a second test can be performed. Based on the test results of the first test, the second test controller 230 can detect defective interconnects among a plurality of interconnects 30 (e.g., first normal interconnects 31_1 to nth normal interconnects 31_n and redundant interconnects 32_1 and 32_2), and can generate defect information representing the defective interconnects. The first test controller 130 and the second test controller 230 can share the defect information. Subsequently, the first repair logic 12 and the second repair logic 22 can set up a repair path based on the defect information, and can perform a second test on the entire signal path including the repair path (e.g., the second test path). Furthermore, based on the test results of the second test, the second test controller 230 can detect whether a defect occurs in the entire signal path.

[0095] The first non-volatile memory 140 and the second non-volatile memory 240 can store defect information. In one or more embodiments, the first non-volatile memory 140 and the second non-volatile memory 240 can be implemented as one-time programmable (OTP) memories, and the defect information can be stored therein via OTP fuse. However, the embodiments are not limited to this, and the first non-volatile memory 140 and the second non-volatile memory 240 can be implemented as flash memory, ferroelectric random access memory (FeRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), phase-change memory (PCM), etc.

[0096] In the embodiments described herein, the first semiconductor die 100a operates as a driver for transmitting signals to the second semiconductor die 200a, and the second semiconductor die 200a operates as a receiver for receiving signals from the first semiconductor die 100a. However, the embodiments are not limited thereto, and the second semiconductor die 200a may operate as a driver while the first semiconductor die 100a operates as a receiver. Alternatively, the first semiconductor die 100a and the second semiconductor die 200a may each operate as both a driver and a receiver for communicating signals with each other.

[0097] Figure 4 This is a block diagram illustrating test operations of a semiconductor device according to one or more embodiments. Figure 5A A first test path for a semiconductor device 1a according to one or more embodiments is shown. Figure 5B A second test path for a semiconductor device 1a according to one or more embodiments is shown.

[0098] The test operation of the semiconductor device 1a can be performed during the manufacturing process and can be performed in the first interface circuit 110a and the second interface circuit 210a under the control of the first test controller 130 and the second test controller 230, respectively.

[0099] Reference Figure 4 and Figure 5A Semiconductor device 1a can perform a first test on a first test path including multiple interconnects 30 during a first test period (S110). Figure 5A In the test path, the element marked with a shading line can be included.

[0100] The first test controller 130 can provide the first test data TD1 to the first scan chain 11 of the first interface circuit 110a. The first test data TD1 can be transmitted from the first scan chain 11 to the third scan chain 21 via the first transmitting circuits D1 to the m-th transmitting circuits Dm (or referred to hereinafter as multiple transmitting circuits D1 to Dm), multiple interconnects 30, and the first receiving circuits R1 to the m-th receiving circuits Rm (or referred to hereinafter as multiple receiving circuits R1 to Rm). The third scan chain 21 can transmit the first received test data TD1R to the second test controller 230.

[0101] The second test controller 230 can generate a first test result (the test result of the first test) by comparing the first received test data TD1R with first comparison data. The first comparison data can be the same as the first test data TD1 or data predicted based on the first test data TD1. When there is no defect in the first test path, specifically in any of the plurality of interconnects 30, the first received test data TD1R can be the same as the first comparison data. When there is a defect in the first test path, specifically in any of the plurality of interconnects 30, the first received test data TD1R can be different from the first comparison data.

[0102] In one or more embodiments, the first test data TD1, the first receive test data TD1R, and the first comparison data may each include a number of bits equal to the number of interconnects 30 (e.g., m). The second test controller 230 can compare the m-bit first receive test data TD1R bit-by-bit with the m-bit first comparison data to identify defective (faulty) interconnects among the plurality of interconnects 30. The second test controller 230 can detect which bit(s)(e.g., one of "0" and "1") in the m bits between the first receive test data TD1R and the first comparison data differ, and can determine that the interconnect corresponding to the bit(s) whose bit(s) differ from each other in the first receive test data TD1R and the first comparison data is defective.

[0103] For example, when the bit value of the bit received through the nth normal interconnect 31_n and the redundant interconnect 32_2 in the m bits of the first received test data TD1R is different from the bit value of the corresponding bit in the first comparison data, the second test controller 230 can determine that the nth normal interconnect 31_n and the redundant interconnect 32_2 are defective.

[0104] The second test controller 230 can generate defect information representing defective interconnects among the multiple interconnects 30.

[0105] Semiconductor device 1a can set a repair path (S120) based on a first test result for replacing defective interconnects in a plurality of interconnects 30 with defect-free redundant interconnects. First repair logic 12 and second repair logic 22 can set the repair path based on defect information. First repair logic 12 can set a first repair path by setting the connection relationship between a plurality of second flip-flops F21 to F2n of the second scan chain 13 and a plurality of first flip-flops F11 to F1m of the first scan chain 11 based on defect information. Second repair logic 22 can set a second repair path by setting the connection relationship between a plurality of third flip-flops F31 to F3m of the third scan chain 21 and a plurality of fourth flip-flops F41 to F4n of the fourth scan chain 23 based on defect information.

[0106] For example, when the nth normal interconnect 31_n is defective, the first repair logic 12 and the second repair logic 22 can set up a repair path to replace the nth normal interconnect 31_n by using redundant interconnects 32_1 and 32_2. When the redundant interconnect 32_2 is defective, the first repair logic 12 and the second repair logic 22 can set up a repair path such that the defect-free redundant interconnect 32_1 replaces the defective nth normal interconnect 31_n.

[0107] Reference Figure 4 and Figure 5B Semiconductor device 1a can perform a second test on a second test path during a second test period (S130), the second test path including a repair path and an interconnect corresponding to the repair path among a plurality of interconnects 30. Figure 5B In the test path, the element marked with a shading line can be included in the second test path.

[0108] The first test controller 130 can provide the second test data TD2 to the second scan chain 13 of the first interface circuit 110a. The second test data TD2 can be sent from the second scan chain 13 to the fourth scan chain 23 via the first repair logic 12, the first scan chain 11, multiple transmitting circuits D1 to Dm, multiple interconnects 30, multiple receiving circuits R1 to Rm, the third scan chain 21, and the second repair logic 22. The fourth scan chain 23 can send the second received test data TD2R to the second test controller 230.

[0109] Specifically, the second test data TD2 can be obtained via the repair paths of the first repair logic 12 and the second repair logic 22, as well as the elements corresponding to the repair paths in the first scan chain 11, the plurality of transmitting circuits D1 to Dm, the plurality of interconnects 30, the plurality of receiving circuits R1 to Rm, and the third scan chain 21 (e.g., Figure 5BThe elements marked with shaded text are sent from the second scan chain 13 to the fourth scan chain 23. Defective nth normal interconnects 31_n and their corresponding elements are excluded from the transmission of the second test data TD2. In other words, the second test is not performed on defective nth normal interconnects 31_n and their corresponding elements.

[0110] The second test controller 230 generates a second test result (the test result of the second test) by comparing the second received test data TD2R with second comparison data. The second comparison data can be the same as the second test data TD2 or data predicted based on the second test data TD2. When there is no defect in the second test path, the second received test data TD2R can be the same as the second comparison data. When there is a defect in the second test path, the second received test data TD2R can be different from the second comparison data. Based on the comparison result, the second test controller 230 can determine whether there is a defect in the second test path. Therefore, it is possible to test whether the first repair logic 12 and the second repair logic 22 with the applied repair path and the multiple interconnects 30 operate normally, and thus, it is possible to confirm whether the first interface circuit 110a and the second interface circuit 210a operate stably.

[0111] Figure 6 The data path during normal operation of a semiconductor device 1a according to one or more embodiments is shown.

[0112] When based on reference Figure 4 and Figure 5B When the second test result described indicates that there are no defects in the second test path, the second test path can be used as a data path during normal operation of the semiconductor device 1a.

[0113] Reference Figure 6 During normal operation of semiconductor device 1a, the first interface circuit 110a of the first semiconductor die 100a can send data d1 to dn output from the first logic circuit 120 to the second semiconductor die 200a via multiple interconnects 30, and the second interface circuit 210a of the second semiconductor die 200a can send data d1 to dn received from the first semiconductor die 100a via multiple interconnects 30 to the second logic circuit 220.

[0114] For example, n data lines D1 to dn output from the first logic circuit 120 are sent to the second logic circuit 220 via multiple second flip-flops F21 to F2n in the second scan chain 13, the repair path (e.g., the first repair path) of the first repair logic 12, n first flip-flops among multiple first flip-flops F11 to F1m in the first scan chain 11, n transmitting circuits among multiple transmitting circuits D1 to Dm, n interconnects among multiple interconnects 30, n receiving circuits among multiple receiving circuits R1 to Rm, n third flip-flops among multiple third flip-flops F31 to F3m in the third scan chain 21, the repair path (e.g., the second repair path) of the second repair logic 22, and multiple fourth flip-flops F41 to F4n in the fourth scan chain 23. The n data lines d1 to dn can be sent simultaneously (or in parallel).

[0115] Figures 7A to 7G The test methods of semiconductor device 1a according to one or more embodiments are shown sequentially.

[0116] Specifically, Figures 7A to 7C This shows the operation of the first test performed during the first test period. Figure 7D The repair process is shown, and Figures 7E to 7G This shows the operation of the second test performed during the second test period.

[0117] See Figure 7A In the first scan chain 11 of the first interface circuit 110a, multiple first flip-flops F11 to F1m are connected in series. The first test controller 130 can provide the first test data TD1[m:1] to the first scan chain 11. The first test data TD1[m:1] can have m bits. The first test data TD1[m:1] is serially shifted into multiple first flip-flops F11 to F1m. The multiple first flip-flops F11 to F1m can temporarily store the first test data TD1[m:1].

[0118] refer to Figure 7B Multiple first flip-flops F11 to F1m can output first test data TD1[m:1]. The m-bit first test data TD1[m:1] can be output simultaneously (in parallel) to multiple transmitting circuits D1 to Dm. The multiple transmitting circuits D1 to Dm can send the first test data TD1[m:1] to multiple interconnects 30 (e.g., first normal interconnects 31_1 to nth normal interconnects 31_n and redundant interconnects 32_1 and 32_2).

[0119] The multiple receiving circuits R1 to Rm of the second interface circuit 210a can receive first received test data TD1R[m:1] based on first test data TD1[m:1] from multiple interconnects 30. The first received test data TD1R[m:1] may be the same as or different from the first test data TD1[m:1]. For example, when there is a defect in the multiple interconnects 30, the first received test data TD1R[m:1] may be different from the first test data TD1[m:1].

[0120] Multiple receiving circuits R1 to Rm can output the first received test data TD1R[m:1] to multiple third flip-flops F31 to F3m of the third scan chain 21. Therefore, the first test data TD1[m:1] can be sent from the multiple first flip-flops F11 to F1m of the first scan chain 11 to the multiple third flip-flops F31 to F3m of the third scan chain 21. The multiple third flip-flops F31 to F3m can temporarily store the first received test data TD1R[m:1].

[0121] Reference Figure 7C The multiple third flip-flops F31 to F3m of the third scan chain 21 can be connected in series, and the multiple third flip-flops F31 to F3m can be serially shifted out of the stored first receive test data TD1R[m:1], and the first receive test data TD1R[m:1] can be sent to the second test controller 230.

[0122] For reference Figure 5A The second test controller 230 can determine whether there is a defect in a plurality of interconnects 30 (e.g., a first test path) based on the first received test data TD1R[m:1], and can generate defect information representing defective interconnects (e.g., defective paths) in the plurality of interconnects 30 (e.g., the first interconnect 31_1 to the nth interconnect 31_n).

[0123] Reference Figure 7D The defect information DI can be stored in the first non-volatile memory 140 of the first semiconductor die 100a and the second non-volatile memory 240 of the second semiconductor die 200a. The first repair logic 12 can set a first repair path based on the defect information DI provided from the first non-volatile memory 140. The second repair logic 22 can set a second repair path based on the defect information DI provided from the second non-volatile memory 240.

[0124] In one or more embodiments, a first selection signal generated based on defect information DI can be stored in a first non-volatile memory 140, and a second selection signal generated based on defect information DI can be stored in a second non-volatile memory 240. First repair logic 12 can set a first repair path based on the first selection signal, and second repair logic 22 can set a second repair path based on the second selection signal.

[0125] The first repair logic 12 can connect the multiple second flip-flops F21 to F2n of the second scan chain 13 to the n first flip-flops F11 to F1m of the first scan chain 11 that correspond to the first repair path. The second repair logic 22 can connect the multiple third flip-flops F31 to F3m of the third scan chain 21 that correspond to the n third flip-flops F41 to F4n of the fourth scan chain 23 to the multiple fourth flip-flops F41 to F4n of the fourth scan chain 23.

[0126] For example, when the nth normal interconnect 31_n among multiple interconnects 30 is defective, the first repair logic 12 and the second repair logic 22 can set a first repair path and a second repair path, and the defect-free redundant interconnect among redundant interconnects 32_1 and 32_2 (e.g., redundant interconnect 32_1) can replace the nth normal interconnect 31_n. The first repair logic 12 can connect the second flip-flop F2n of the second scan chain 13 to the first flip-flop F1m-1 among the multiple first flip-flops F11 to F1m of the first scan chain 11 corresponding to the redundant interconnect 32_1, instead of connecting it to the first flip-flop F1n corresponding to the nth normal interconnect 31_n. The second repair logic 22 can connect the fourth flip-flop F4n of the fourth scan chain 23 to the third flip-flop F3m-1 among the multiple third flip-flops F31 to F3m of the third scan chain 21 corresponding to the redundant interconnect 32_1, instead of connecting it to the third flip-flop F3n corresponding to the nth normal interconnect 31_n.

[0127] Reference Figure 7E In the second scan chain 13 of the first interface circuit 110a, multiple second flip-flops F21 to F2n are connected in series. The first test controller 130 can provide the second test data TD2[n:1] to the second scan chain 13. The second test data TD2[n:1] can have n bits. The second test data TD2[n:1] is serially shifted into multiple second flip-flops F21 to F2n. The multiple second flip-flops F21 to F2n can temporarily store the second test data TD2[n:1].

[0128] refer to Figure 7FMultiple second flip-flops F21 to F2n can output second test data TD2[n:1]. The n-bit second test data TD2[n:1] can be output to the first repair logic 12 simultaneously (in parallel). The first repair logic 12 can output the second test data TD2[n:1] to the n first flip-flops F11, F12, ..., F1m-1 corresponding to the first repair path among the multiple first flip-flops F11 to F1m of the first scan chain 11 via the first repair path.

[0129] n first flip-flops F11, F12, ..., F1m-1 can temporarily store the second test data TD2[n:1] and output the second test data TD2[n:1] to the corresponding n transmitting circuits D1, D2, ..., Dm-1 among the multiple transmitting circuits D1 to Dm. The n transmitting circuits D1, D2, ..., Dm-1 can send the second test data TD2[n:1] to n defect-free interconnects 31_1, 31_2, ..., 32_1 among the multiple interconnects 30.

[0130] The n receiving circuits R1, R2, ..., Rm-1 of the multiple receiving circuits R1 to Rm of the second interface circuit 210a, corresponding to the n defect-free interconnects 31_1, 31_2, ..., 32_1, can receive second received test data TD2R[n:1] based on the second test data TD2[n:1]. The n receiving circuits R1, R2, ..., Rm-1 can output the second received test data TD2R[n:1] to the n corresponding third flip-flops F31, F32, ..., F3m-1 of the multiple third flip-flops F31 to F3m of the third scan chain 21. The n third flip-flops F31, F32, ..., F3m-1 can temporarily store the second received test data TD2R[n:1] and output the second received test data TD2R[n:1] to the second repair logic 22. The second repair logic 22 can simultaneously (in parallel) output the second receive test data TD2R[n:1] received via the second repair path to multiple fourth flip-flops F41 to F4n of the fourth scan chain 23. Therefore, the second test data TD2[n:1] can be sent from multiple second flip-flops F21 to F2n of the second scan chain 13 to multiple fourth flip-flops F41 to F4n of the fourth scan chain 23. The multiple fourth flip-flops F41 to F4n can temporarily store the second receive test data TD2R[n:1].

[0131] Reference Figure 7GThe multiple fourth flip-flops F41 to F4n of the fourth scan chain 23 can be connected in series, and the multiple fourth flip-flops F41 to F4n of the fourth scan chain 23 can be shifted to output the second received test data TD2R[n:1], and the second received test data TD2R[n:1] can be sent to the second test controller 230.

[0132] For reference Figure 5B The second test controller 230 can determine whether there is a defect in the data path (e.g., the second test path) from the second scan chain 13 to the fourth scan chain 23 based on the second received test data TD2R[n:1].

[0133] Figure 8A and Figure 8B Examples are shown of first repair logic 12a and 12b and second repair logic 22a and 22b provided in semiconductor device 1a according to one or more embodiments.

[0134] like Figure 3 As shown, multiple transmitting circuits D1 to Dm (refer to...) Figure 3 Connected between the first scan chain 11 and multiple interconnects 30, multiple receiving circuits R1 to Rm (refer to) Figure 3 It is connected between the third scan chain 21 and multiple interconnects 30.

[0135] refer to Figure 8A The first repair logic 12a and the second repair logic 22a can each be implemented by multiple multiplexers MX1 and MX2.

[0136] For ease of description, it can be assumed that the multiple interconnects 30 include first normal interconnects 31_1 to fifth normal interconnects 31_5 and redundant interconnects 32, the first scan chain 11 includes six first flip-flops F1, the second scan chain 13 includes five second flip-flops F2, the third scan chain 21 includes six third flip-flops F3, and the fourth scan chain 23 includes five fourth flip-flops F4.

[0137] The first repair logic 12a may include multiple multiplexers MX1 and a first decoder DEC1.

[0138] The first decoder DEC1 can decode the defect information DI and generate a first selection signal SEL1[4:1]. The bits of the first selection signal SEL1[4:1] can each be provided as a selection signal to the corresponding one of the multiplexers MX1.

[0139] Each of the multiplexers MX1 can receive two input data (or input signals) from two corresponding second flip-flops F2 of the second scan chain 13, and can output one of the two input data or no input data in response to a selection signal. Therefore, a repair path (e.g., a first repair path) can be set.

[0140] For example, when the third normal interconnect 31_3 is determined to be defective based on the first test result, the defect information DI can indicate that the third normal interconnect 31_3 is defective. In response to the first selection signal SEL1[4:1] generated based on the defect information DI, the multiple multiplexers MX1 of the first repair logic 12a can set the first repair path. Therefore, the first data d1 to the fifth data d5 output from the multiple second flip-flops F2 of the second scan chain 13 can be sent to the first normal interconnect 31_1, the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnect 32. Specifically, in response to the first selection signal SEL1[4:1], the multiple multiplexers MX1 in the first repair logic 12a can connect (e.g., in a one-to-one correspondence) the multiple second flip-flops F2 of the second scan chain 13 to the five first flip-flops F1 of the multiple first flip-flops F1 of the first scan chain 11 that correspond to the first normal interconnect 31_1, the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnect 32.

[0141] The second repair logic 22a may include multiple multiplexers MX2 and a second decoder DEC2.

[0142] The second decoder DEC2 can decode the defect information DI and generate a second selection signal SEL2[5:1]. Each bit of the second selection signal SEL2[5:1] can be provided as a selection signal to the corresponding one of the multiple multiplexers MX2.

[0143] Each of the multiplexers MX2 can receive two input data (or input signals) from two corresponding interconnects of the multiple interconnects 30, and can output one of the two input data in response to a selection signal. Therefore, a repair path (e.g., a second repair path) can be configured.

[0144] For example, in response to the second selection signal SEL2[5:1] generated based on defect information DI, the multiple multiplexers MX2 of the second repair logic 22a can set the second repair path. Therefore, the first data d1 to the fifth data d5 received from the first normal interconnect 31_1, the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnect 32 can be output to the multiple fourth flip-flops F4 of the fourth scan chain 23, respectively. Specifically, in response to the second selection signal SEL2[5:1], the multiple multiplexers MX2 in the second repair logic 22a can connect (e.g., in a one-to-one correspondence) the multiple fourth flip-flops F4 of the fourth scan chain 23 to the five third flip-flops F3 of the multiple third flip-flops F3 of the third scan chain 21 that correspond to the first normal interconnect 31_1, the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnect 32. Therefore, the redundant interconnect 32 can indirectly replace the third normal interconnect 31_3.

[0145] refer to Figure 8B The first repair logic 12b and the second repair logic 22b can each be implemented by multiple multiplexers MX1 and MX2.

[0146] For ease of description, it can be assumed that the plurality of interconnects 30 include first normal interconnects 31_1 to fifth normal interconnects 31_5 and redundant interconnects 32_1 and 32_2, the first scan chain 11 includes seven first flip-flops F1, the second scan chain 13 includes five second flip-flops F2, the third scan chain 21 includes seven third flip-flops F3, and the fourth scan chain 23 includes five fourth flip-flops F4. In one or more embodiments, the redundant interconnects 32_1 and 32_2 may be arranged on both sides of the first normal interconnects 31_1 to fifth normal interconnects 31_5, respectively.

[0147] The first repair logic 12b may include multiple multiplexers MX1 and a first decoder DEC1.

[0148] The first decoder DEC1 can decode the defect information DI and generate a first selection signal SEL1[5:1]. The bits of the first selection signal SEL1[5:1] can each be provided as a selection signal to the corresponding one of the multiple multiplexers MX1.

[0149] Each of the multiplexers MX1 can receive input data (or input signal) from a corresponding second flip-flop F2 among the multiple second flip-flops F2 in the second scan chain 13, and can output the input data to one of the corresponding three first flip-flops F1 based on a selection signal. Therefore, a repair path (e.g., a first repair path) can be set.

[0150] For example, when it is determined based on the first test results that the first normal interconnect 31_1 and the third normal interconnect 31_3 are defective, the defect information DI can indicate that the first normal interconnect 31_1 and the third normal interconnect 31_3 are defective.

[0151] In response to the first selection signal SEL1[5:1] generated based on defect information DI, the multiple multiplexers MX1 of the first repair logic 12b can set the first repair path. Therefore, the first data d1 to the fifth data d5 output from the multiple second flip-flops F2 of the second scan chain 13 can be sent to the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnects 32_1 and 32_2. Specifically, in response to the first selection signal SEL1[5:1], the multiple multiplexers MX1 in the first repair logic 12b can connect (e.g., in a one-to-one correspondence) the multiple second flip-flops F2 of the second scan chain 13 to the five first flip-flops F1 of the multiple first flip-flops F1 of the first scan chain 11 that correspond to the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnects 32_1 and 32_2.

[0152] The second repair logic 22b may include multiple multiplexers MX2 and a second decoder DEC2.

[0153] The second decoder DEC2 can decode the defect information DI and generate a second selection signal SEL2[5:1]. Each bit of the second selection signal SEL2[5:1] can be provided as a selection signal to the corresponding one of the multiple multiplexers MX2.

[0154] Each of the multiplexers MX2 can receive three input data (or input signals) from three corresponding third flip-flops F3 of the third scan chain 21, and can output one of the three input data in response to a selection signal. Therefore, a repair path (e.g., a second repair path) can be configured.

[0155] For example, in response to the second selection signal SEL2[5:1] generated based on defect information DI, the multiple multiplexers MX2 of the second repair logic 22b can set the second repair path. Therefore, the first data d1 to the fifth data d5 received from the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnects 32_1 and 32_2 can be output to the multiple fourth flip-flops F4 of the fourth scan chain 23, respectively. Specifically, in response to the second selection signal SEL2[5:1], the multiple multiplexers MX2 in the second repair logic 22b can connect (e.g., in a one-to-one correspondence) the multiple fourth flip-flops F4 of the fourth scan chain 23 to the five third flip-flops F3 of the multiple third flip-flops F3 of the third scan chain 21 that correspond to the second normal interconnect 31_2, the fourth normal interconnect 31_4, the fifth normal interconnect 31_5, and the redundant interconnects 32_1 and 32_2. Therefore, redundant interconnect 32_1 can directly replace the first normal interconnect 31_1, and redundant interconnect 32_2 can indirectly replace the third normal interconnect 31_3.

[0156] The above has been referred to Figure 8A and Figure 8B Examples of first repair logic 12a and 12b and second repair logic 22a and 22b provided in semiconductor device 1a according to one or more embodiments are described. However, the embodiments are not limited thereto, and the first repair logic 12a and 12b and the second repair logic 22a and 22b can be implemented in various other ways.

[0157] Figure 9A and 9B The test method for semiconductor device 1' according to the comparative example is shown.

[0158] refer to Figure 9A and 9B According to the comparative example, the semiconductor device 1' may include a first semiconductor die 300, a second semiconductor die 400 and a plurality of interconnects 30, and the plurality of interconnects 30 may transmit signals between the first semiconductor die 300 and the second semiconductor die 400.

[0159] The first semiconductor die 300 may include a first interface circuit 310 and a first test controller 330, and the second semiconductor die 400 may include a second interface circuit 410 and a second test controller 430. The first semiconductor die 300 and the second semiconductor die 400 may also include a first logic circuit and a second logic circuit, respectively.

[0160] The first interface circuit 310 may include a first scan chain 311, a first repair logic 312, and multiple transmitting circuits D1 to Dm; the second interface circuit 410 may include a second scan chain 411, a second repair logic 412, and multiple receiving circuits R1 to Rm.

[0161] The first scan chain 311 may include a plurality of first flip-flops F51 to F5n, and the first repair logic 312 may connect the plurality of first flip-flops F51 to F5n of the first scan chain 311 to a plurality of transmitting circuits D1 to Dm.

[0162] The second scan chain 411 may include a plurality of second flip-flops F61 to F6n, and the second repair logic 412 may connect a plurality of receiving circuits R1 to Rm to the plurality of second flip-flops F61 to F6n of the second scan chain 411.

[0163] refer to Figure 9A The first repair logic 312 can essentially connect the multiple first flip-flops F51 to F5n of the first scan chain 311 to the first transmitting circuit D1 to the nth transmitting circuit Dn in a one-to-one correspondence. The second repair logic 412 can essentially connect the first receiving circuit R1 to the nth receiving circuit Rn to the multiple second flip-flops F61 to F6n of the second scan chain 411 in a one-to-one correspondence.

[0164] The first test controller 330 can provide test data TD[n:1] to the first scan chain 311. The test data TD[n:1] can be sent to the second scan chain 411 via the first repair logic 312, the first transmitting circuit D1 to the nth transmitting circuit Dn, the first normal interconnect 31_1 to the nth normal interconnect 31_n, the first receiving circuit R1 to the nth receiving circuit Rn, and the second repair logic 412. The second scan chain 411 can send the received test data TDR[n:1] to the second test controller 430.

[0165] Based on the test results, defective interconnects among the first normal interconnects 31_1 to the nth normal interconnects 31_n can be detected, and the defect information can be stored in a non-volatile memory provided in each of the first interface circuit 310 and the second interface circuit 410.

[0166] The first repair logic 312 and the second repair logic 412 can set repair paths (e.g., first repair path and second repair path) based on defect information. Therefore, redundant interconnects 32_1 and 32_2 can replace defective normal interconnects.

[0167] refer to Figure 9BThe first repair logic 312 and the second repair logic 412 can set the repair path, and the redundant interconnect 32_1 can replace the defective nth normal interconnect 31_n. However, the redundant interconnect 32_1 may also be defective. (Refer to...) Figure 9A In the described test, since the test data TD[n:1] is transmitted via the first normal interconnect 31_1 to the nth normal interconnect 31_n, defects in redundant interconnects 32_1 and 32_2 may not be detected. Therefore, even if the first repair logic 312 and the second repair logic 412 have set up repair paths, the data may still fail to be transmitted normally due to the defect in the redundant interconnect 32_1 that replaces the defective nth normal interconnect 31_n.

[0168] Therefore, after setting the repair path and performing the test again, when it is determined that the redundant interconnect 32_1 is defective, the defect information can be generated again and stored in the non-volatile memory provided in each of the first interface circuit 310 and the second interface circuit 410.

[0169] As described above, in the semiconductor device 1' according to the comparative example, when a defect exists in the repair path, the defect information indicating the defect in the repair path is stored again, the repair path is reset, and the test is performed again. Therefore, the test can be performed repeatedly. In the worst case where all k redundant interconnects (k is an integer greater than or equal to 2) are defective, k+1 tests can be performed, including the initial test, which may significantly increase the test time. Furthermore, it is difficult to clearly distinguish whether the defect detected by the test is caused by a defect in the interconnect or by a defect in the first repair logic 312 and the second repair logic 412.

[0170] However, as described above, in the semiconductor devices 1 and 1a according to the embodiments, a first test is performed on a first test path that includes a plurality of interconnects 30 but does not include the first repair logic 12 and the second repair logic 22 before the repair path is set. Therefore, it is possible to accurately detect whether a defect occurs in the plurality of interconnects 30, and it is also possible to detect whether a defect occurs in redundant interconnects.

[0171] After setting up the repair path based on the defect information, a second test is performed on the entire signal path, which includes not only multiple interconnects 30 but also the first repair logic 12 and the second repair logic 22. Therefore, the presence or absence of defects in the entire signal path can be detected, and the operational reliability of the repair path can be verified.

[0172] Furthermore, in semiconductor devices 1 and 1a according to the embodiments, since a total of two tests are performed, namely a first test (pre-repair test) and a second test (post-repair test) before setting the repair path, the test time can be reduced.

[0173] Figure 10 This is a block diagram illustrating a semiconductor device 1b according to one or more embodiments.

[0174] Reference Figure 10 The semiconductor device 1b may include a first semiconductor die 100b, a second semiconductor die 200b, a plurality of first interconnects 30_1, and a plurality of second interconnects 30_2. In one or more embodiments, the semiconductor device 1b is a 3D integrated circuit, and the first semiconductor die 100b and the second semiconductor die 200b may be stacked on top of each other in the vertical direction. The plurality of first interconnects 30_1 and the plurality of second interconnects 30_2 may each include normal interconnects and redundant interconnects.

[0175] The first semiconductor die 100b may include a first interface circuit 110b, a first test controller 130, and a first non-volatile memory 140, and the second semiconductor die 200b may include a second interface circuit 210b, a second test controller 230, and a second non-volatile memory 240. The first semiconductor die 100b may also include a first logic circuit connected to the first interface circuit 110b, and the second semiconductor die 200b may also include a second logic circuit connected to the second interface circuit 210b.

[0176] The first interface circuit 110b may include a first unit circuit 110b_1 and a second unit circuit 110b_2. The first unit circuit 110b_1 and the second unit circuit 110b_2 may have the same structure and respectively include first scan chains 11_1 and 11_2, first repair logic 12_1 and 12_2, second scan chains 13_1 and 13_2, and multiple transmitting circuits 14_1 and 14_2. The multiple transmitting circuits 14_1 of the first unit circuit 110b_1 may be connected to multiple first interconnects 30_1, and the multiple transmitting circuits 14_2 of the second unit circuit 110b_2 may be connected to multiple second interconnects 30_2.

[0177] The second interface circuit 210b may include a third unit circuit 210b_1 and a fourth unit circuit 210b_2. The third unit circuit 210b_1 and the fourth unit circuit 210b_2 may have the same structure and include third scan chains 21_1 and 21_2, second repair logic 22_1 and 22_2, fourth scan chains 23_1 and 23_2, and multiple receiving circuits 24_1 and 24_2. The multiple receiving circuits 24_1 of the third unit circuit 210b_1 may be connected to multiple first interconnects 30_1, and the multiple receiving circuits 24_2 of the fourth unit circuit 210b_2 may be connected to multiple second interconnects 30_2.

[0178] here, Figure 10The first interface circuit 110b and the second interface circuit 210b are shown to each include two unit circuits, but this is for ease of description. The first interface circuit 110b and the second interface circuit 210b may each include three or more unit circuits.

[0179] During the first test period, multiple flip-flops F / F in the first scan chains 11_1 and 11_2 of the first unit circuit 110b_1 and the second unit circuit 110b_2 can be connected in series, and the first test data TD1 received from the first test controller 130 can be serially shifted to the multiple flip-flops F / F in the first scan chains 11_1 and 11_2.

[0180] The first scan chain 11_2 of the second unit circuit 110b_2 can receive the lower half of the bits of the first test data TD1 shifted therein from the first scan chain 11_1 of the first unit circuit 110b_1. The lower half of the bits in the first test data TD1 can be temporarily stored in the first scan chain 11_2 of the second unit circuit 110b_2, and the upper half of the bits in the first test data TD1 can be temporarily stored in the first scan chain 11_1 of the first unit circuit 110b_1.

[0181] The first test data TD1 can be sent via transmitting circuits 14_1 and 14_2, multiple first interconnects 30_1 and multiple second interconnects 30_2, and receiving circuits 24_1 and 24_2 to multiple flip-flops F / F in the third scan chains 21_1 and 21_2 as the first received test data TD1R.

[0182] The lower half of the bits in the first received test data TD1R can be temporarily stored in the third scan chain 21_2 of the fourth unit circuit 210b_2, and the upper half of the bits can be temporarily stored in the third scan chain 21_1 of the third unit circuit 210b_1.

[0183] Multiple flip-flops F / F in the third scan chains 21_1 and 21_2 of the third unit circuit 210b_1 and the fourth unit circuit 210b_2 can be connected in series, and the first received test data TD1R can be serially shifted out from the multiple flip-flops F / F in the third scan chains 21_1 and 21_2 and sent to the second test controller 230.

[0184] Defect information based on the test results of the first test is stored in the first non-volatile memory 140 and the second non-volatile memory 240. Furthermore, the first repair logics 12_1 and 12_2 of the first unit circuit 110b_1 and the second unit circuit 110b_2 can set a first repair path based on the defect information from the first non-volatile memory 140, and the second repair logics 22_1 and 22_2 of the third unit circuit 210b_1 and the fourth unit circuit 210b_2 can set a second repair path based on the defect information from the second non-volatile memory 240.

[0185] Subsequently, during the second test period, multiple flip-flops F / F in the second scan chains 13_1 and 13_2 of the first unit circuit 110b_1 and the second unit circuit 110b_2 can be connected in series, and the second test data TD2 received from the first test controller 130 can be serially shifted to the multiple flip-flops F / F in the second scan chains 13_1 and 13_2.

[0186] The second test data TD2 can be sent via the first repair logic 12_1 and 12_2, the first scan chains 11_1 and 12_1, the transmitting circuits 14_1 and 14_2, the multiple first interconnects 30_1 and the multiple second interconnects 30_2, the receiving circuits 24_1 and 24_2, the third scan chains 21_1 and 22_1, and the second repair logic 22_1 and 22_2 to multiple flip-flops F / F in the fourth scan chains 23_1 and 23_2 as the second received test data TD2R.

[0187] Multiple flip-flops F / F of the fourth scan chains 23_1 and 23_2 are connected in series, and the second received test data TD2R can be serially removed from the multiple flip-flops F / F of the fourth scan chains 23_1 and 23_2 and sent to the second test controller 230.

[0188] As described above, the first interface circuit 110b and the second interface circuit 210b can be implemented as multiple unit circuits with the same structure, and these unit circuits are repeatedly arranged. Therefore, test data can be easily generated, and testing efficiency and automation of interface circuit design can be improved.

[0189] Figure 11 This is a block diagram illustrating a semiconductor device 1c according to one or more embodiments.

[0190] Reference Figure 11The semiconductor device 1c may include a first semiconductor die 100c, a second semiconductor die 200c, a plurality of first interconnects 30_1, and a plurality of second interconnects 30_2. In one or more embodiments, the semiconductor device 1c is a 3D integrated circuit, and the first semiconductor die 100c and the second semiconductor die 200c may be stacked on top of each other in the vertical direction. The plurality of first interconnects 30_1 and the plurality of second interconnects 30_2 may each include normal interconnects and redundant interconnects.

[0191] The first semiconductor die 100c may include a first interface circuit 110c and a first test controller 130c, and the second semiconductor die 200c may include a second interface circuit 210c and a second test controller 230c. The first semiconductor die 100c may also include a first logic circuit connected to the first interface circuit 110c and a first non-volatile memory for storing defect information, and the second semiconductor die 200c may also include a second logic circuit connected to the second interface circuit 210c and a second non-volatile memory for storing defect information.

[0192] The first interface circuit 110c may include a transmitting interface circuit 10_1 and a receiving interface circuit 20_2, and the second interface circuit 210c may include a receiving interface circuit 20_1 and a transmitting interface circuit 10_2.

[0193] The transmitting interface circuit 10_1 of the first interface circuit 110c and the receiving interface circuit 20_1 of the second interface circuit 210c (hereinafter referred to as "the first transmitting / receiving interface circuit pair 10_1 and 20_1") are responsible for transmitting signals (data) from the first semiconductor die 100c to the second semiconductor die 200c. The transmitting interface circuit 10_2 of the second interface circuit 210c and the receiving interface circuit 20_2 of the first interface circuit 110c (hereinafter referred to as "the second transmitting / receiving interface circuit pair 10_2 and 20_2") are responsible for transmitting signals from the second semiconductor die 200c to the first semiconductor die 100c. Therefore, the first semiconductor die 100c and the second semiconductor die 200c can exchange data with each other.

[0194] The transmitting interface circuits 10_1 and 10_2 may include first scan chains 11_1 and 11_2, first repair logic 12_1 and 12_2, second scan chains 13_1 and 13_2, and multiple transmitting circuits 14_1 and 14_2. The receiving interface circuits 20_1 and 20_2 may include third scan chains 21_1 and 21_2, second repair logic 22_1 and 22_2, fourth scan chains 23_1 and 23_2, and multiple receiving circuits 24_1 and 24_2.

[0195] In the embodiments, the transmitting interface circuits 10_1 and 10_2 and the receiving interface circuits 20_1 and 20_2 may each include multiple unit circuits with the same structure, as shown in the reference. Figure 10 As described.

[0196] The transmitting interface circuits 10_1 and 10_2 can be connected with Figure 3 The first interface circuit 110a operates in the same or similar manner, and the receiving interface circuits 20_1 and 20_2 can operate in the same manner as... Figure 3 The second interface circuit 210a operates in the same or similar manner.

[0197] The first test controller 130c and the second test controller 230c can control the first interface circuit 110c and the second interface circuit 210c to perform tests in test mode. The first test controller 130c and the second test controller 230c can respectively provide test data to the transmitting interface circuits 10_1 and 10_2, and receive test data from the receiving interface circuits 20_1 and 20_2 to determine (analyze) the test results. The operation and reference of the first test controller 130c and the second test controller 230c are as follows: Figure 3 , Figure 5A , Figure 5B , Figure 7A and Figure 7G The operations described are the same or similar.

[0198] Figure 11 The diagram illustrates that first transmit / receive interface pairs 10_1 and 20_1 are connected to a plurality of first interconnects 30_1, and second transmit / receive interface pairs 10_2 and 20_2 are connected to a plurality of second interconnects 30_2. Therefore, the first transmit / receive interface pairs 10_1 and 20_1 and the second transmit / receive interface pairs 10_2 and 20_2 can be connected to different interconnects. However, the embodiments are not limited to this, and the first transmit / receive interface pairs 10_1 and 20_1 and the second transmit / receive interface pairs 10_2 and 20_2 can also share multiple interconnects.

[0199] Figure 12 This is a block diagram illustrating a semiconductor device 1d according to one or more embodiments.

[0200] Reference Figure 12The semiconductor device 1d may include a first semiconductor die 100d, a second semiconductor die 200d, a third semiconductor die 300d, a plurality of first interconnects 30_1, and a plurality of second interconnects 30_2. The plurality of first interconnects 30_1 may be connected between the first semiconductor die 100d and the second semiconductor die 200d, and the plurality of second interconnects 30_2 may be connected between the second semiconductor die 200d and the third semiconductor die 300d. The plurality of first interconnects 30_1 and the plurality of second interconnects 30_2 may each include normal interconnects and redundant interconnects.

[0201] In one or more embodiments, the first semiconductor die 100d, the second semiconductor die 200d, and the third semiconductor die 300d may be stacked on top of each other in the vertical direction. In one or more embodiments, the first semiconductor die 100d and the second semiconductor die 200d may be stacked in the vertical direction, the second semiconductor die 200d and the third semiconductor die 300d may be stacked in the vertical direction, and the first semiconductor die 100d and the third semiconductor die 300d may be at the same horizontal level in the vertical direction. The semiconductor device 1d may be referred to as a 3D integrated circuit.

[0202] The first semiconductor die 100d may include a first interface circuit 110d and a first logic circuit 120d; the second semiconductor die 200d may include a second interface circuit 210d, a second logic circuit 220d, and a third interface circuit 250d; and the third semiconductor die 300d may include a fourth interface circuit 310d and a third logic circuit 320d. The first semiconductor die 100d, the second semiconductor die 200d, and the third semiconductor die 300d may each further include a test controller and a non-volatile memory for storing defect information.

[0203] The first interface circuit 110d and the second interface circuit 210d can be responsible for sending and receiving signals (data) between the first semiconductor die 100d and the second semiconductor die 200d, and the third interface circuit 250d and the fourth interface circuit 310d can be responsible for sending and receiving signals (data) between the second semiconductor die 200d and the third semiconductor die 300d.

[0204] refer to Figure 1 , Figure 3 , Figure 10 and Figure 11 The first interface circuits 110, 110a, 110b and 110c and the second interface circuits 210, 210a, 210b and 210c described can be applied to the first interface circuit 110d and the second interface circuit 210d, and can also be applied to the third interface circuit 250d and the fourth interface circuit 310d.

[0205] Figure 13A , Figure 13B , Figure 13C and Figure 13D This is a structural diagram illustrating semiconductor devices 1000a, 1000b, 1000c and 1000d according to embodiments.

[0206] Reference Figure 13A The semiconductor device 1000a may include a first semiconductor die (die 1) 1100 and a second semiconductor die (die 2) 1200, and the die 1 1100 and the die 2 1200 may be stacked on top of each other in the vertical direction.

[0207] As described above, die 1 1100 and die 2 1200 can be electrically connected to each other via multiple interconnects implemented as TSVs, microbumps, hybrid bonding, etc. Die 2 1200 can be connected to package substrate 1400 (or interposer) via bumps (BPs). Bumps (BPs) can each be implemented as, for example, solder bumps, flip chip bumps, or microbumps.

[0208] Reference Figure 13B and Figure 13C Semiconductor devices 1000b and 1000c may each include die 1 1100, die 2 1200, and die 3 1300. In one or more embodiments, reference is made to... Figure 12 The first semiconductor die 100d, the second semiconductor die 200d, and the third semiconductor die 300d described can each be implemented as die 1 1100, die 2 1200, and die 3 1300, respectively.

[0209] Reference Figure 13B Die 1 (1100) and die 3 (1300) can be stacked on die 2 (1200). See reference... Figure 13C Die 1 1100, die 2 1200 and die 3 1300 can be stacked on top of each other in the vertical direction.

[0210] Die 1 1100 and die 2 1200 can be electrically connected to each other via multiple interconnects, and die 2 1200 and die 3 1300 can be electrically connected to each other via multiple interconnects. Die 2 1200 can be connected to package substrate 1400 (or interposer) via bump BP.

[0211] Reference Figure 13D Die 1 110 and die 2 1200 can be stacked on interposer 1500 and electrically connected to each other via interposer 1500.

[0212] Die 1 1100 and die 2 1200 may be connected to interposer 1500 via bumps (e.g., microbumps, flip chip bumps, etc.) or hybrid bonding. Die 1 1100 and die 2 1200 may be electrically connected to each other via TSVs, metal lines, vias, or active elements (e.g., buffers, switches, multiplexers, etc.) within interposer 1500. At least one of the TSVs, metal lines, vias, and active elements within interposer 1500 may form an interconnect together with a hybrid bonding or bump connecting die 1 1100 and die 2 1200 to interposer 1500.

[0213] Figure 14 This is a structural diagram illustrating an example of an electronic system 2000 according to one or more embodiments.

[0214] Reference Figure 14 The electronic system 2000 may include a host 2100, multiple high-bandwidth memories (HBMs) 2200, an interposer 2300, and a packaging substrate 2400.

[0215] The host 2100 can correspond to various other semiconductor devices requesting memory access. The host 2100 can be implemented as a 3D integrated circuit according to the embodiments described above. The host 2100 may include two or more vertically stacked semiconductor dies, and the semiconductor dies may be electrically connected to each other via multiple interconnects. The interface circuitry in each semiconductor die may include two independent scan chains for verifying the interface between the semiconductor dies, and a first test (pre-repair test) and a second test (post-repair test) can be performed on two test circuits based on the two scan chains. Therefore, defects in the multiple interconnects themselves and defects in the entire signal path (data path) including the interface circuitry can be detected.

[0216] The CPU, GPU, NPU / AI accelerator, DSP, PMIC, memory controller, I / O interface circuitry, security circuitry, and on-chip memory can be implemented in the semiconductor die of host 2100. For example, circuitry with high operating speeds (such as the CPU, GPU, and NPU / AI accelerator) can be integrated on the upper semiconductor die (e.g., a semiconductor die located relatively far from the interposer 2300), and other circuitry can be integrated on the lower semiconductor die (e.g., a semiconductor die located relatively close to the interposer 2300).

[0217] The HBM 2200 may include a plurality of semiconductor dies 2211 to 2215, and the plurality of semiconductor dies 2211 to 2215 may be electrically connected to each other via a plurality of interconnects.

[0218] The host 2100 and HBM 2200 can be mounted on the interposer 2300, and the interposer 2300 can be mounted on the package substrate 2400. The interposer 2300 can be implemented in various other forms, such as a silicon-based (TSV) interposer, a printed circuit board (PCB) based organic interposer, or as a non-TSV embedded multi-die interconnect bridge (EMIB) type interposer. Conductive devices (such as solder balls 2500) can be mounted on the underside of the package substrate 2400.

[0219] One or more embodiments of this disclosure can provide a 3D integrated circuit, comprising: a first semiconductor die including a first interface circuit and a first test controller; a second semiconductor die including a second interface circuit and a second test controller; and a plurality of interconnects connected between the first semiconductor die and the second semiconductor die and configured to transmit signals, wherein the first interface circuit includes a first unit circuit. The first unit circuit includes: a first scan chain configured to receive first test data for performing a first test from the first test controller and output the first test data during a first test period; a first repair logic configured to set a first repair path based on defect information generated from the test results of the first test to replace defective interconnects among the plurality of interconnects with defect-free redundant interconnects; and a second scan chain configured to receive second test data for performing a second test from the first test controller and output the second test data during a second test period after setting the first repair path.

[0220] In one or more embodiments, the first interface circuit may further include a second unit circuit, wherein the second unit circuit includes: a third scan chain configured to receive first test data from the first scan link and output the first test data during a first test period; a second repair logic configured to set a second repair path based on defect information; and a fourth scan chain configured to receive second test data from the second scan link and output the second test data during a second test period after the second repair path is set.

[0221] In one or more embodiments, a defect-free redundant interconnect among a plurality of interconnects can replace a defective interconnect along a first repair path of a first repair logic and a second repair path of a second repair logic.

[0222] In one or more embodiments, the first scan chain may include m first scan units (where m is an integer greater than or equal to 3), and the third scan chain may include m third scan units. During a first test period, the m first scan units of the first scan chain and the m third scan units of the third scan chain may be connected in series, and the first test data may be shifted into the m first scan units and the m third scan units.

[0223] In one or more embodiments, during a first test period, multiple bits of the first test data stored in the first scan chain and the third scan chain can be sent in parallel to multiple interconnects.

[0224] In one or more embodiments, the second scan chain may include n second scan units (where n is an integer greater than or equal to 2), and the fourth scan chain may include n fourth scan units. During the second test period, the n second scan units of the second scan chain and the n fourth scan units of the fourth scan chain may be connected in series, and the second test data may be serially shifted into the n second scan units and the n fourth scan units.

[0225] In one or more embodiments, during the second test period, multiple bits of the second test data stored in the second scan chain and the fourth scan chain can be output in parallel through the first repair path of the first repair logic and the second repair path of the second repair logic.

[0226] In one or more embodiments, the second interface circuit may include a third unit circuit and a fourth unit circuit. The third unit circuit may include: a fifth scan chain configured to move first test data received from the first semiconductor die to a second test controller during a first test period; third repair logic configured to set a third repair path based on defect information; and a sixth scan chain configured to move second test data received from the first semiconductor die to the second test controller during a second test period after the third repair path is set. The fourth unit circuit may include: a seventh scan chain configured to move first test data received from the first semiconductor die to a fifth scan chain during a first test period; fourth repair logic configured to set a fourth repair path based on defect information; and an eighth scan chain configured to move second test data received from the first semiconductor die to the sixth scan chain during a second test period after the fourth repair path is set.

[0227] One or more embodiments may provide a semiconductor device wherein a plurality of interconnects includes n interconnects (where n is an integer greater than or equal to 2) and mn redundant interconnects (where m is an integer greater than n), a first scan chain circuit includes m flip-flops, and a second scan chain circuit includes n flip-flops.

[0228] One or more embodiments may provide a semiconductor device, wherein the first test data includes m bits and the second test data includes n bits.

[0229] One or more embodiments may provide a semiconductor device, wherein the first semiconductor die further includes a first test controller configured to: provide first test data to a first scan chain circuit during a first test period; and provide second test data to a second scan chain circuit during a second test period.

[0230] One or more embodiments may provide a semiconductor device wherein a second scan chain circuit is configured to: receive second test data from a first test controller and output the second test data to a first repair logic circuit during a second test period; and receive operation data from the first logic circuit and output the operation data to the first repair logic circuit during a normal operation period.

[0231] One or more embodiments may provide a semiconductor device, wherein a second interface circuit of a second semiconductor die includes: a plurality of interconnected receiving circuits; wherein a first scan chain circuit is configured to: output first test data received from a first test controller to a plurality of transmitting circuits during a first test period; and output second test data or operation data received from a first repair logic circuit to n receiving circuits (where n is an integer greater than or equal to 2) of the plurality of receiving circuits during a second test period and a normal operation period.

[0232] One or more embodiments may provide a semiconductor device in which a first repair logic circuit includes a plurality of multiplexers, and the plurality of multiplexers are configured to selectively connect a plurality of second flip-flops of a second scan chain circuit to a plurality of first flip-flops of a first scan chain circuit based on defect information.

[0233] One or more embodiments may provide a semiconductor device wherein a second interface circuit of a second semiconductor die includes: a plurality of receiver circuits connected to a plurality of interconnected circuits; a third scan chain circuit configured to receive signals from the plurality of receiver circuits; a second repair logic circuit configured to: set a second repair path based on defect information; and output data input from the third scan chain circuit along the second repair path; and a fourth scan chain circuit configured to receive the data from the second repair logic circuit.

[0234] One or more embodiments may provide a semiconductor device wherein a third scan chain circuit is configured to: receive first test data from a plurality of receiving circuits during a first test period; and receive second test data or operation data from n receiving circuits among the plurality of receiving circuits corresponding to a second repair path during a second test period and a normal operation period.

[0235] One or more embodiments may provide a semiconductor device wherein a fourth scan chain circuit is configured to: receive second test data from a second repair logic circuit during a second test period; and receive operation data from the second repair logic circuit and send the operation data to the second logic circuit during a normal operation period.

[0236] One or more embodiments may provide a semiconductor device, wherein the second semiconductor die further includes a second test controller configured to: during a first test period: receive first test data from a third scan chain circuit; and generate defect information by comparing the first test data with first comparison data; and during a second test period: receive second test data from a fourth scan chain circuit; and generate a test result by comparing the second test data with second comparison data.

[0237] One or more embodiments may provide a semiconductor device, wherein the first semiconductor die further includes: a first non-volatile memory configured to store defect information; and the second semiconductor die further includes a second non-volatile memory configured to store defect information.

[0238] One or more embodiments may provide a semiconductor device in which a plurality of interconnects include n interconnects (where n is an integer greater than or equal to 2) and mn redundant interconnects (where m is an integer greater than n), a first test data including m bits, and a second test data including n bits.

[0239] One or more embodiments may provide a semiconductor device wherein the second interface circuit includes: a third scan chain circuit configured to send first test data to a second test controller; a second repair logic circuit configured to set a second repair path based on the first test result; and a fourth scan chain circuit configured to send the second test data received via the third scan chain circuit and the second repair logic circuit to the second test controller.

[0240] One or more embodiments may provide a semiconductor device wherein a first scan chain circuit and a third scan chain circuit each include m scan units (where m is an integer greater than or equal to 3), wherein a second scan chain circuit and a fourth scan chain circuit each include n scan units (where n is an integer less than m), and wherein the scan units are configured to store and output 1 bit of data.

[0241] One or more embodiments may provide a semiconductor device in which a first semiconductor die and a second semiconductor die are stacked in a vertical direction.

[0242] One or more embodiments may provide a method in which a first scan chain circuit is connected to a third scan chain circuit via a first repair logic circuit, and a second scan chain circuit is connected to a fourth scan chain circuit via a second repair logic circuit.

[0243] One or more embodiments may provide a method in which a first test includes: a plurality of first scan units connected in series with a first scan chain circuit; shifting first test data into the plurality of first scan units; and outputting the first test data from the plurality of first scan units to a plurality of interconnects; and wherein a second test includes: a plurality of third scan units connected in series with a third scan chain circuit; shifting second test data into the plurality of third scan units; and outputting the second test data from the plurality of third scan units to a first repair logic circuit.

[0244] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional integrated circuit, comprising: The first semiconductor die includes: First logic circuit; and First interface circuit; The second semiconductor die includes: Second logic circuit; and Second interface circuit; and Multiple interconnects are connected between the first semiconductor die and the second semiconductor die, and the multiple interconnects are configured to transmit signals. The first interface circuit includes: Multiple transmitting circuits are connected to the multiple interconnects; A first scan chain circuit is configured to output first test data to the plurality of transmitting circuits during a first test period; The first repair logic circuit is configured as follows: Based on defect information generated from the first test results derived from the first test data, a first repair path is established, configured to replace defective interconnects among a plurality of interconnects with defect-free redundant interconnects; and The input data is output to the first scan chain circuit via the first repair path; and The second scan chain circuit is configured to output the second test data to the first repair path during the second test period.

2. The 3D integrated circuit according to claim 1, wherein the plurality of interconnects comprises n interconnects and mn redundant interconnects, where n is an integer greater than or equal to 2, and m is an integer greater than n. The first scan chain circuit includes m flip-flops, and The second scan chain circuit includes n flip-flops.

3. The 3D integrated circuit according to claim 2, wherein the first test data comprises m bits, and The second test data consists of n bits.

4. The 3D integrated circuit according to claim 1, wherein the first semiconductor die further includes a first test controller, the first test controller being configured to: During the first test period, the first test data is provided to the first scan chain circuit; and The second test data is provided to the second scan chain circuit during the second test period.

5. The 3D integrated circuit according to claim 1, wherein the second scan chain circuit is configured as follows: During the second test period, the second test data is received from the first test controller, and The second test data is output to the first repair logic circuit; and During normal operation periods, operation data is received from the first logic circuit, and The operation data is output to the first repair logic circuit.

6. The 3D integrated circuit according to claim 5, The first scan chain circuit is configured as follows: During the first test period, the first test data received from the first test controller is output to the plurality of transmitting circuits; and During the second test period and the normal operation period, the second test data or the operation data received from the first repair logic circuit is output to n transmission circuits among the plurality of transmission circuits corresponding to the first repair path, where n is an integer greater than or equal to 2.

7. The 3D integrated circuit according to claim 1, wherein the first repair logic circuit comprises a plurality of multiplexers, and The multiplexers are configured to selectively connect multiple second flip-flops of the second scan chain circuit to multiple first flip-flops of the first scan chain circuit based on the defect information.

8. The 3D integrated circuit according to claim 1, wherein the second interface circuit of the second semiconductor die comprises: Multiple receiving circuits connected to the plurality of interconnected circuits; The third scan chain circuit is configured to receive signals from the plurality of receiving circuits; The second repair logic circuit is configured as follows: A second repair path is set based on the defect information; and Output the data input from the third scan chain circuit along the second repair path; and The fourth scan chain circuit is configured to receive the data from the second repair logic circuit.

9. The 3D integrated circuit of claim 8, wherein the third scan chain circuit is configured as follows: During the first test period, the first test data is received from the plurality of receiving circuits; and During the second test period and the normal operation period, the second test data or operation data is received from n receiving circuits of the plurality of receiving circuits that correspond to the second repair path.

10. The 3D integrated circuit of claim 9, wherein the fourth scan chain circuit is configured as follows: During the second test period, the second test data is received from the second repair logic circuit; and During the normal operation period, the operation data is received from the second repair logic circuit and the operation data is sent to the second logic circuit.

11. The 3D integrated circuit of claim 10, wherein the second semiconductor die further comprises a second test controller, the second test controller being configured to: During the first test period: Receive the first test data from the third scan chain circuit; and The defect information is generated by comparing the first test data with the first comparison data; and During the second test period: Receive the second test data from the fourth scan chain circuit; and Test results are generated by comparing the second test data with the second comparison data.

12. The 3D integrated circuit of claim 1, wherein the first semiconductor die further comprises a first non-volatile memory configured to store the defect information; and The second semiconductor die further includes a second non-volatile memory configured to store the defect information.

13. A semiconductor device, comprising: The first semiconductor die includes: First interface circuit; and First test controller; The second semiconductor die includes: Second interface circuit; and Second test controller; and Multiple interconnects are connected to the first semiconductor die and the second semiconductor die, and the multiple interconnects are configured to transmit signals. The first interface circuit includes: The first scan chain circuit is configured as follows: Receive first test data from the first test controller; and Output the first test data; The first repair logic circuit is configured as follows: Based on the first test result from the first test data, a first repair path is set, which is configured to replace the defective interconnects among the plurality of interconnects with defect-free redundant interconnects; and The second scan chain circuit is configured as follows: Receive second test data from the first test controller; Defects in the signal path were detected based on the second test data; and Output the second test data. The signal path includes: First repair path; The first scan chain circuit; and The interconnection among the plurality of interconnections that corresponds to the first repair path.

14. The semiconductor device of claim 13, wherein the plurality of interconnects comprises n interconnects and mn redundant interconnects, wherein n is an integer greater than or equal to 2, and m is an integer greater than n. The first test data includes m bits, and The second test data consists of n bits.

15. The semiconductor device of claim 13, wherein the second interface circuit comprises: The third scan chain circuit is configured to send the first test data received via the plurality of interconnects to the second test controller; The second repair logic circuit is configured to set a second repair path based on the first test result; and The fourth scan chain circuit is configured to send the second test data received via the plurality of interconnects to the second test controller, the third scan chain circuit, and the second repair logic circuit.

16. The semiconductor device of claim 15, wherein the first scan chain circuit and the third scan chain circuit each comprise m scan units, where m is an integer greater than or equal to 3. The second scan chain circuit and the fourth scan chain circuit each include n scan units, where n is an integer less than m, and The scanning unit is configured to store and output 1 bit of data.

17. The semiconductor device of claim 13, wherein the first semiconductor die and the second semiconductor die are stacked in a vertical direction.

18. A method for testing a three-dimensional 3D integrated circuit, the 3D integrated circuit comprising a first semiconductor die and a second semiconductor die interconnected by a plurality of interconnects, the method comprising: The first test is performed by sending first test data from the first scan chain circuit of the first semiconductor die to the second scan chain circuit of the second semiconductor die via a first test path including the plurality of interconnections. A repair path is set based on the defect information generated from the results of the first test, and the repair path includes: The first repair logic circuit of the first semiconductor die; and The second repair logic circuit of the second semiconductor die, The repair path is configured to replace defective interconnects among the plurality of interconnects with defect-free redundant interconnects; and The second test is performed by sending second test data from the third scan chain circuit of the first semiconductor die to the fourth scan chain circuit of the second semiconductor die via a second test path, the second test path including the repair path and the interconnects corresponding to the repair path among the plurality of interconnects.

19. The method of claim 18, wherein the first scan chain circuit is connected to the third scan chain circuit via the first repair logic circuit, and The second scan chain circuit is connected to the fourth scan chain circuit via the second repair logic circuit.

20. The method of claim 18, wherein the first test comprises: Multiple first scan units are connected in series in the first scan chain circuit; The first test data is shifted to the plurality of first scanning units; and The first test data is output from the plurality of first scanning units to the plurality of interconnects; and The second test includes: Multiple third scan units are connected in series in the third scan chain circuit; The second test data is shifted to the plurality of third scanning units; and The second test data is output from the plurality of third scanning units to the first repair logic circuit.

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