Digital isolator film layer structure and method of making same

Abstract

The application discloses a digital isolator film layer structure and a manufacturing method thereof. The digital isolator film layer structure comprises a UTM Cu layer, a SION layer and a SIN layer arranged in sequence from bottom to top, and further comprises a polymer buffer dispersion layer formed on the top of the SIN layer, which is used for reducing polymer aggregation, avoiding direct contact of the SIN layer with an etching environment and a copper layer, and preventing the generation of chelate CuxNyFz. The polymer buffer dispersion layer is etched first when etching, and can buffer and disperse the polymer generated in the etching process of the SIN layer, so that the polymer aggregation is reduced. Meanwhile, the SIN layer is prevented from directly contacting the etching environment and the copper layer, the generation of chelate CuxNyFz is prevented, and defects can be avoided without additional wet cleaning.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a digital isolator film structure and its fabrication method. Background Technology

[0002] Digital isolators, as key components in the semiconductor field for signal isolation and withstand voltage protection, employ a composite stacked structure of silicon oxynitride (SION) and silicon nitride (SIN) in their core RV layer (isolation layer) to meet insulation performance requirements under high-voltage conditions and significantly improve overall withstand voltage levels. The stacking order of this composite structure from the substrate upwards is as follows: bottom UTM Cu layer (bottom copper interconnect layer), middle SION layer (silicon oxynitride insulating layer), and top SIN layer (silicon nitride withstand voltage layer). The SIN layer possesses excellent insulation and withstand voltage characteristics and is the core functional layer ensuring the high-voltage stability of the isolator.

[0003] In existing manufacturing processes, when dry etching is performed on the aforementioned RV layer composite film to form a preset circuit pattern, the top SIN film layer is designed to be relatively thick to meet voltage withstand requirements. This results in a vigorous etching reaction that generates a large amount of highly adhesive polymer byproducts, with high polymer aggregation and a heavy build-up. When the etching process reaches the point of exposing the underlying UTM Cu layer (exposed copper), fluoride and nitrogen ions in the etching environment readily react with copper ions to form copper-nitrogen-fluorine chelates (CuxNyFz). These chelates are chemically stable and have extremely strong adhesion; even with multiple cleanings using conventional wet cleaning processes, it is difficult to completely remove them from the film surface. The residual polymers and chelates form permanent defects on the chip surface, not only damaging the integrity of the film structure and affecting normal circuit conduction, but also significantly reducing chip production yield, weakening the long-term stability and reliability of the digital isolator, and shortening the device's lifespan.

[0004] The existing technology exhibits RV layer film stacking morphology, post-etching polymer residue, and chelate formation defect states. Observation of low-magnification optical micrographs of the chip surface reveals large areas of polymer residue. Defects manifest as irregular protrusions and impurity spots formed by polymer accumulation, indicating a dense polymer adhesion on the film surface. These polymer residue defects are difficult to eliminate under current processes. (Reference...) Figure 2 As shown. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is that during the etching of the isolation layer film of existing digital isolators, the polymer generated by the etching of the top SIN film layer is heavy, and after the copper is exposed, it forms a difficult-to-remove chelate, resulting in chip defects, low yield and low reliability.

[0007] To solve the above-mentioned technical problems, the present invention provides a digital isolator film layer structure, comprising, from bottom to top, a UTM Cu layer, a SION layer, and a SIN layer, characterized in that it further comprises: A polymer buffer dispersion layer is formed on top of the SIN layer. It is used to reduce polymer aggregation, prevent the SIN layer from directly contacting the etching environment and the copper layer, and prevent the formation of the chelate CuxNyFz.

[0008] Optionally, the structure of the digital isolator membrane can be further improved, with the polymer buffer dispersion layer being a SiO2 membrane.

[0009] This invention provides a method for fabricating a digital isolator membrane structure, comprising the following steps: 1) Prepare a UTM Cu layer, a SION layer, and a SIN layer sequentially, and prepare a polymer buffer dispersion layer on top of the SIN layer to form a composite film structure; The polymer buffer dispersion layer is used to reduce polymer aggregation, prevent the SIN layer from directly contacting the etching environment and the copper layer, and prevent the formation of the chelate CuxNyFz. 2) Photoresist is coated on the surface of the polymer buffer dispersion layer, and then exposed and developed to form a preset pattern; 3) Etch the polymer buffer dispersion layer, SIN layer, and SION layer sequentially according to the preset pattern until the UTM Cu layer is exposed; 4) Remove the photoresist to complete the digital isolator film layer.

[0010] Optionally, the method for fabricating the digital isolator membrane structure can be further improved, wherein the polymer buffer dispersion layer is a SiO2 membrane.

[0011] Optionally, the method for fabricating the digital isolator film structure can be further improved by using a dry etching process in step 3).

[0012] Based on the above technical solution, the working principle of the present invention is explained as follows: The present invention adds an additional SiO2 film layer on top of the original SIN layer as a polymer buffer and dispersion layer, thereby changing the etching process sequence. During dry etching, the upper SiO2 film is etched first. SiO2 reacts mildly during etching, its products are volatile, and it does not readily form heavy polymers. Therefore, it acts as a buffer, disperser, and barrier: Firstly, the SiO2 film pre-consumes the etching reaction energy, reducing the intensity of the reaction during the etching of the underlying SIN layer and significantly reducing the total amount of polymer generated during SIN layer etching, thus preventing the local accumulation and deposition of polymers. Secondly, the SiO2 film continuously covers and protects the surface of the SIN layer during etching, preventing the SIN layer from being directly exposed to the high-energy, high-fluorine etching environment, reducing the strong erosion of the SIN layer by fluorine- and nitrogen-containing reactive particles. More importantly, even when etched near the bottom, the SiO2 film effectively isolates the SIN layer from the underlying UTM Cu layer, preventing the nitrogen- and fluorine-containing reactive species generated during SIN layer etching from directly contacting and reacting with the copper layer, fundamentally preventing the formation of the copper-nitrogen-fluorine chelate CuxNyFz. Therefore, the etched film surface is basically free of polymer residue and chelate adhesion, eliminating the need for additional wet cleaning steps to avoid defects and achieving a clean and smooth etched surface.

[0013] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects. 1) This invention can effectively suppress the generation and residue of polymers during the SIN layer etching process, eliminate the surface defects caused by the chelate CuxNyFz from the root of the process, significantly improve chip yield, and reduce scrap and rework caused by defects.

[0014] 2) This invention eliminates the need for multiple wet cleaning steps required in conventional processes to remove polymers and chelates, simplifying the overall process flow, shortening the production cycle, and reducing equipment occupation, chemical consumption, and labor costs.

[0015] 3) This invention can avoid the negative impact of residual polymers and chelates on the film structure, insulation performance and circuit contact reliability, thereby greatly improving the withstand voltage stability and long-term working reliability of digital isolators, extending the service life of devices and reducing the risk of failure. Attached Figure Description

[0016] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0017] Figure 1 This is a schematic diagram of the existing technology process.

[0018] Figure 2 This is a schematic diagram of surface defects of a film observed using an optical microscope with existing technology.

[0019] Figure 3 This is a schematic diagram of the process of this invention.

[0020] Figure 4 This is a schematic diagram of the film surface observed by an optical microscope according to the present invention. Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0022] First embodiment; This invention provides a method for fabricating a digital isolator film layer, comprising a UTM Cu layer, a SION layer, a SIN layer and a SiO2 film layer stacked sequentially from bottom to top; Among them, the UTM Cu layer is the bottom conductive layer; the SION layer is located above the UTM Cu layer to help improve the isolation withstand voltage; the SIN layer is located above the SION layer and is the withstand voltage core layer; the SiO2 film layer is located on top of the SIN layer, with a thickness adapted to the etching requirements of the SIN layer, and is used to buffer the etching polymer and prevent the formation of chelates.

[0023] Second embodiment; As shown in Figure 3, the present invention provides a method for fabricating a digital isolator membrane structure, comprising the following steps: 1) Film preparation: On a semiconductor substrate, a UTM Cu layer, a SION layer, and a SIN layer are prepared sequentially by a deposition process, and then a SiO2 film is deposited on top of the SIN layer; 2) Photolithography: Photoresist (PR) is uniformly coated on the surface of the SiO2 film. After drying, it is exposed and developed to form a preset pattern that matches the target etching area on the photoresist layer. 3) Step-by-step etching: A dry etching process is adopted, using the photoresist pattern as a mask. First, the SiO2 film layer is etched, and then the SIN layer and SION layer are etched down sequentially until the underlying UTM Cu layer is exposed. 4) Photoresist removal: The residual photoresist is removed using a photoresist removal process to complete the etching of the digital isolator film layer.

[0024] As shown in Figure 4, the surface of the membrane layer prepared using the present invention is free of polymer residue and chelate defects.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0026] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A digital isolator membrane structure, comprising a UTM Cu layer, a SION layer, and a SIN layer arranged sequentially from bottom to top, characterized in that, Also includes: A polymer buffer dispersion layer is formed on top of the SIN layer. It is used to reduce polymer aggregation, prevent the SIN layer from directly contacting the etching environment and the copper layer, and prevent the formation of the chelate CuxNyFz.

2. The digital isolator membrane structure as described in claim 1, characterized in that: The polymer buffer dispersion layer is a SiO2 film.

3. A method for fabricating a digital isolator membrane structure, characterized in that, Includes the following steps: 1) Prepare a UTM Cu layer, a SION layer, and a SIN layer sequentially, and prepare a polymer buffer dispersion layer on top of the SIN layer to form a composite film structure; The polymer buffer dispersion layer is used to reduce polymer aggregation, prevent the SIN layer from directly contacting the etching environment and the copper layer, and prevent the formation of the chelate CuxNyFz. 2) Photoresist is coated on the surface of the polymer buffer dispersion layer, and then exposed and developed to form a preset pattern; 3) Etch the polymer buffer dispersion layer, SIN layer, and SION layer sequentially according to the preset pattern until the UTM Cu layer is exposed; 4) Remove the photoresist to complete the digital isolator film layer.

4. The method for fabricating the digital isolator membrane structure as described in claim 3, characterized in that: The polymer buffer dispersion layer is a SiO2 film layer.

5. The method for fabricating the digital isolator membrane structure as described in claim 3, characterized in that: In step 3), a dry etching process is used for etching.

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