A board-level fan-out package structure and a preparation method thereof

Abstract

The application provides a board-level fan-out packaging structure and a preparation method, which greatly suppresses electromagnetic crosstalk between power and small-signal chips, and constructs a short-range low-resistance heat dissipation channel; meanwhile, high integration, structural reliability and mass production economy are considered. It comprises a high-thermal-conductivity copper plate layer, a plastic sealing layer, a redistribution layer and an external lead-out structure which are sequentially stacked from bottom to top; it also comprises a chip assembly, the chip assembly contains at least one high-power chip and at least one small-signal chip; the high-thermal-conductivity copper plate layer is a packaging heat dissipation and electromagnetic shielding base, the surface of which is integrally formed with multiple independent accommodating cavities through an etching process, and adjacent accommodating cavities are separated by an integral metal isolation wall; at least one chip is arranged in each group of accommodating cavities, and the high-power chip and the small-signal chip are arranged in different accommodating cavities.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device packaging, specifically to a board-level fan-out packaging structure. The invention also provides a method for preparing the board-level system-level packaging structure. Background Technology

[0002] With the continuous improvement of power density and control precision requirements for power modules in fields such as new energy vehicles, photovoltaic inverters, and data center power supplies, board-level fan-out packaging uses a large-area square panel as the process carrier substrate, which can break through the wafer size bottleneck. The single batch chip capacity, substrate area utilization and I / O density are significantly improved, and it has become the core technology route for the next generation of high-power heterogeneous integrated packaging.

[0003] However, current conventional board-level fan-out packages present significant electromagnetic compatibility and signal integrity issues in high-power-density integration scenarios. The high dV / dt and dI / dt noise generated during the high-frequency switching of power chips can crosstalk to adjacent small-signal control chips through near-field electric field coupling, magnetic field coupling, and common-medium conduction, causing control signal distortion or even false triggering. Existing solutions mostly rely on increasing chip spacing and surface-mount shielding films to suppress crosstalk. The former directly sacrifices package integration, while the latter requires additional processes and has limited shielding effectiveness, making it difficult to balance high integration with high electromagnetic isolation performance.

[0004] In addition, existing board-level packaging has several technical shortcomings: First, insufficient heat dissipation capacity. Traditional packaging often uses thin copper layers or ordinary substrates as heat dissipation bases, with the power chip completely encapsulated inside the molding compound. This results in long heat dissipation paths and high thermal resistance, making it difficult to withstand the high heat flux density of high-power devices. Second, high cost of multilayer interconnects. Existing vertical stacking solutions generally rely on TSV (Through Silicon Via) technology, which involves complex processes such as deep hole etching, insulating deposition, and electroplating filling, leading to high equipment investment and process costs. Third, difficulty in controlling warpage of large-size substrates. Stress concentration in thick molding layers can easily cause substrate warpage, resulting in yield problems such as photolithography misalignment and interconnect structure cracking, which restricts the large-scale deployment of board-level packaging. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a board-level fan-out packaging structure that significantly suppresses electromagnetic crosstalk between power and small-signal chips and constructs a short-range, low-resistance heat dissipation channel; while also achieving high integration, structural reliability, and mass production economy.

[0006] A board-level fan-out packaging structure is characterized in that it comprises, from bottom to top, a high thermal conductivity copper plate layer, a molding layer, a redistribution layer and an external lead-out structure. It also includes a chip assembly, which contains at least one high-power chip and at least one small-signal chip; The high thermal conductivity copper plate layer is a packaged heat dissipation and electromagnetic shielding substrate. Its surface is integrally formed with multiple independent receiving cavities through an etching process. Adjacent receiving cavities are separated by an integral metal isolation wall. Each set of receiving cavities contains at least one chip, with high-power chips and small signal chips placed in different receiving cavities.

[0007] Its further features are: Preferably, only one chip is placed in each set of receiving cavities to ensure sufficient and reliable electromagnetic isolation; The metal isolation wall forms a Faraday cage shielding structure through a grounding design, further enhancing the electromagnetic isolation effect; The top surface of the metal isolation wall is slightly lower than the active surface pad of the tallest chip in the chip assembly to avoid the risk of short circuit caused by metal debris in the subsequent planarization process. The high-power chip is a power or radio frequency semiconductor chip that performs power transmission and power conversion functions, and is suitable for high voltage, high current, and high frequency operating conditions. Typical components of the high-power chip include SiC and GaN transistors, power management chips, and radio frequency power chips. The small signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions. The non-active surfaces of all chips are bonded to a high thermal conductivity copper plate layer, and the active surfaces are facing upwards. The molding compound fully encapsulates the chip assembly and the metal isolation wall. The molding compound has molded vias of different heights, and the interior of the molded vias is filled to form conductive interconnect pillars. The lower end of the conductive interconnect pillar is electrically connected to the active surface pad of the corresponding chip, and the upper end of the conductive interconnect pillar is electrically connected to the redistribution layer. The redistribution layer is disposed on the flat top surface of the molding compound. The redistribution layer includes at least one layer of alternately stacked metal circuit layers and insulating passivation layers. The redistribution layer is used to realize signal fan-out and power distribution of all chips. The above the redistribution layer is provided with pads, a metal layer under the bumps, or a conductive solder ball structure to achieve external electrical interconnection of the package.

[0008] A method for fabricating a board-level fan-out package structure is characterized by: firstly preparing a high thermal conductivity copper plate layer with a receiving cavity; then mounting corresponding chips at preset positions on the bottom surface of the corresponding receiving cavity; then performing a molding process to form a molding layer; then processing molded vias of the corresponding chips on the molding layer; then obtaining corresponding conductive interconnect pillars within the molded vias; then preparing a redistribution layer on the top surface of the molding layer; then performing a post-packaging process on the redistribution layer to obtain an outwardly protruding connection structure; and finally performing board-level dicing to obtain a single independent finished packaged device.

[0009] Its further features are: It includes the following steps: S1 substrate preparation: A square temporary glass panel is selected as a temporary process carrier. A temporary bonding adhesive layer is coated on the surface of the square temporary glass panel, and then a high thermal conductivity copper plate layer is laid on the entire surface. S2 isolation cavity etching: The high thermal conductivity copper plate layer is deeply etched using photolithography + wet etching process to form at least two independent cavities, with adjacent cavities separated by an integrated metal isolation wall. The S3 chip assembly is mounted by using a high thermal conductivity bonding adhesive layer to mount the non-active surfaces of high-power chips and small signal chips to preset positions on the bottom surface of the corresponding receiving cavity. The two types of chips are arranged in separate cavities, and the active surfaces are both set upwards. The S4 molding layer is prepared and planarized by using a vacuum hot pressing process to press a solid epoxy molding film, which is then cured at high temperature to form a molding layer, achieving embedded full encapsulation of high-power chips, small-signal chips and metal isolation walls; the top surface of the molding layer is planarized by chemical mechanical polishing to achieve the preset thickness. The S5 conductive interconnect pillars are fabricated using ultraviolet laser drilling technology. Molded vias of different depths are processed at the positions of different chip pads in the molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, the vias are filled by copper electroplating to form the corresponding conductive interconnect pillars, which lead out the electrical signals of the high-power chip and the small signal chip respectively. S6 Redistribution layer fabrication: A redistribution layer is fabricated on the flattened top surface of the molding compound to complete the signal fan-out and power distribution of all chips; the redistribution layer includes at least one layer of alternately stacked metal circuit layer and insulating passivation layer to realize the lateral transmission of signals and electrical energy and inter-layer interconnection. The S7 back-end packaging process completes the preparation of the top insulating passivation layer and the under-bump metal layer; then the entire substrate is flipped over, and the square temporary glass panel is peeled off using a debonding process to remove the residual temporary bonding adhesive layer on the surface; conductive solder balls are prepared in the under-bump metal layer area using a ball-planting process; finally, a board-level cutting process is used to diced the components to obtain individual finished packaged devices.

[0010] Its further characteristic is: It also includes an optoelectronic integration extension step. In the mounting process of step S3, optoelectronic modules 830 are arranged outside the accommodating cavity at the edge of the plastic encapsulation layer or in an independent accommodating cavity. The optoelectronic modules and the internal rewiring lines complete signal matching connection. While retaining the original power and signal electrical transmission functions, an optical signal transmission channel is added to realize electro-optical hybrid integration, which is suitable for high-frequency power device scenarios that require high-speed optical interconnection.

[0011] This invention effectively solves a series of technical problems in traditional high-power fan-out packaging, such as severe electromagnetic crosstalk, insufficient heat dissipation, low substrate area utilization, high cost of multilayer interconnection process, and low yield of warpage on large-size substrates.

[0012] In terms of electromagnetic isolation, the design of copper-based integrated isolation cavity and grounding shield can improve the high-frequency electromagnetic crosstalk suppression capability between chips by more than 8 dB. The power circuit and signal circuit achieve physical and electromagnetic dual isolation, significantly improving signal integrity and EMC performance, and adapting to the application requirements of high-precision control scenarios. In terms of heat dissipation and reliability, the structure of directly attaching a high thermal conductivity copper plate to the back of the chip can reduce the steady-state thermal resistance of the package junction to 0.8~1.2℃ / W, which can meet the heat dissipation requirements of third-generation semiconductor devices of 500V / 20A level; the copper-based composite rigid support structure can reduce the warpage of the 510×515mm large board by more than 30% compared with the traditional solution, effectively improving the process yield. In terms of mass production economics, the TMV (Through-Via Molded Via) vertical interconnection is abandoned in favor of TSV process, combined with micro CMP planarization solution, which greatly reduces the process cost of multi-layer integration; large-area board-level process can increase the substrate area utilization rate to more than 95%, significantly reduce the packaging cost of a single chip, and is fully compatible with existing board-level mass production lines, which has good industrial application value. In addition, this architecture can be flexibly expanded to integrate heterogeneous devices such as optoelectronic modules, realize electro-optical hybrid interconnection, and adapt to application scenarios of high-frequency and high-speed power modules. Attached Figure Description

[0013] Figure 1 This is a structural schematic diagram of a specific embodiment of the present invention, and also a schematic diagram of step S7 of the preparation method; Figure 2 This is a schematic diagram of the structure of a specific embodiment two of the present invention; Figure 3 This is a schematic diagram of step S1 of the preparation method of the present invention; Figure 4 This is a schematic diagram of step S2 in the preparation method of the present invention: Figure 5 This is a schematic diagram of step S3 in the preparation method of the present invention; Figure 6 This is a schematic diagram of step S4 in the preparation method of the present invention; Figure 7 This is a schematic diagram of step S5 in the preparation method of the present invention; Figure 8 This is a schematic diagram of step S6 in the preparation method of the present invention. Detailed Implementation

[0014] A board-level fan-out packaging structure, see Figure 1 and Figure 2 It includes a high thermal conductivity copper plate layer 210, a molding layer 400, a redistribution layer 600 and an external lead-out structure stacked from bottom to top; It also includes a chip assembly, which contains at least one high-power chip and at least one small-signal chip; The high thermal conductivity copper plate layer 210 is the heat dissipation and electromagnetic shielding substrate of the package. Its surface is integrally formed with multiple independent receiving cavities through an etching process. Adjacent receiving cavities are separated by an integral metal isolation wall 220. Each set of receiving cavities contains at least one chip, with high-power chips and small signal chips placed in different receiving cavities.

[0015] In practice, only one chip is placed in each cavity to ensure sufficient and reliable electromagnetic isolation.

[0016] The metal isolation wall 220 forms a Faraday cage shielding structure through grounding design, further enhancing the electromagnetic isolation effect; The top surface of the metal isolation wall 220 is slightly lower than the active surface pad of the tallest chip in the chip assembly to avoid the risk of short circuit caused by metal debris in the subsequent planarization process; High-power chips are power or radio frequency semiconductor chips that perform power transmission and conversion functions. They are suitable for high-voltage, high-current, and high-frequency operating conditions. Typical high-power chip devices include SiC and GaN transistors, power management chips, and radio frequency power chips. Small-signal chips are digital or analog semiconductor chips that perform signal acquisition, logic operations, and data storage functions. The non-active surfaces of all chips are bonded to a high thermal conductivity copper plate layer, and the active surfaces are facing upwards. The molding compound 400 fully encapsulates the chip assembly and the metal isolation wall 220. Molded vias of different heights are formed inside the molding compound 400, and conductive interconnect pillars are formed inside the molded vias. The lower end of the conductive interconnect pillar is electrically connected to the active surface pad of the corresponding chip, and the upper end of the conductive interconnect pillar is electrically connected to the redistribution layer 600. The redistribution layer 600 is disposed on the flat top surface of the molding layer. The redistribution layer includes at least one layer of alternately stacked metal circuit layers and insulating passivation layers. The redistribution layer is used to realize signal fan-out and power distribution of all chips. Pads, bump under metal layers, or conductive solder ball structures are arranged above the redistribution layer 600 to achieve external electrical interconnection of the package.

[0017] In specific embodiments one and two, the chip assembly includes a high-power chip 310 and a small-signal chip 320. The upper surface of the high thermal conductivity copper plate layer 210 is etched to form two independent receiving cavities. The two receiving cavities are separated by an integrated metal isolation wall 220. The high-power chip 310 is provided with a first conductive interconnect post 510, and the small-signal chip 320 is provided with a second conductive interconnect post 520. Conductive solder balls 700 are arranged above the redistribution layer 600 to achieve external electrical interconnection of the package.

[0018] In the second specific embodiment, an optoelectronic module 830 is arranged outside the accommodating cavity at the edge of the plastic encapsulation layer 400 or inside an independent accommodating cavity. The optoelectronic module 830 completes signal matching connection with the internal rewiring line. While retaining the original power and signal electrical transmission functions, an optical signal transmission channel is added to realize electro-optical hybrid integration. It is suitable for high-frequency power device scenarios that require high-speed optical interconnection. The optoelectronic module 830 is an optoelectronic chip or an optical fiber interface component.

[0019] The fabrication method of the board-level fan-out packaging structure corresponding to Specific Embodiment 1 is as follows: See Figure 1 , Figures 3-8 It includes the following steps: S1 Substrate preparation: A square temporary glass panel 100 is selected as a temporary process carrier. A temporary bonding adhesive layer 110 is coated on the surface of the square temporary glass panel 100, and then a high thermal conductivity copper plate layer 210 is laid on the entire surface. The copper plate is patterned by photolithography and wet etching process to form a patterned high thermal conductivity copper plate layer covering the encapsulation area. The square temporary glass panel 100 is a glass carrier plate with a size of 510mm×515mm; the temporary bonding adhesive layer 110 is a high-temperature resistant UV bonding adhesive or laser-dissociated bonding adhesive, which can withstand subsequent high-temperature processes; the high thermal conductivity copper plate layer is an oxygen-free copper plate with a thickness of 150~350μm, which takes into account both heat dissipation performance and etching processability. S2 Isolation cavity etching: The patterned high thermal conductivity copper plate layer is deeply etched using photolithography + wet etching process to form two independent cavities. The adjacent cavities are separated by an integrated metal isolation wall 220. The size of the cavity is adapted to the shape of the corresponding chip. The horizontal dimension of the cavity is 20~50μm larger than the chip on each side. The width of the metal isolation wall is 50~100μm, and the height is slightly lower than the active surface pad of the tallest chip in the chip assembly. After etching, the remaining thickness of the copper plate at the bottom of the cavity is not less than 50μm to ensure the continuity of the heat dissipation conduction path of high-power chips. S3 chip assembly mounting: Through the high thermal conductivity bonding adhesive layer 301, the non-active surfaces of the high power chip 310 (thicker) and the small signal chip 320 (thinner) are respectively mounted on the bottom preset positions of the corresponding receiving cavity. The two types of chips are arranged in separate cavities, with the active surfaces facing upwards. The high thermal conductivity bonding adhesive layer 301 is a high thermal conductivity permanent bonding adhesive with a thickness of 1~5μm; the thickness of the high power chip 310 is 150~350μm, and the thickness difference between the two types of chips is ≤80μm to avoid poor molding or poor through-hole electroplating consistency due to excessive thickness difference. S4 Molding layer preparation and planarization: A solid epoxy molding film is pressed together using a vacuum hot pressing process and cured at high temperature to form molding layer 400, realizing the embedded full encapsulation of high-power chip 310, small signal chip 320 and metal isolation wall 220; Chemical mechanical polishing (CMP) process is used to grind and planarize the top surface of molding layer 400 to achieve the preset thickness; The preset thickness is: the vertical spacing between the top surface of the molding compound and the top active pads of the high-power chip 310 is 10~20μm to avoid grinding damage to the active area of ​​the chip; The S5 conductive interconnect pillars are fabricated using ultraviolet laser drilling technology. Through-hole (TMV) of different depths are processed at the positions of different chip pads in the molding layer 400. After preparing a Ti / Cu seed layer by physical vapor deposition (PVD), the through-holes are filled by copper electroplating to form the first conductive interconnect pillar 510 (deeper) and the second conductive interconnect pillar 520 (shallower), which respectively lead out the electrical signals of the high-power chip 310 and the small-signal chip 320. If there is overflow or unevenness on the surface of the encapsulation layer after electroplating and filling, it can be flattened by fine grinding process. S6 redistribution layer fabrication: Redistribution layer 600 is fabricated on the flattened top surface of molding layer 400 to complete signal fan-out and power distribution for all chips; redistribution layer 600 includes at least one layer of alternately stacked metal circuit layer and insulating passivation layer to realize lateral transmission of signals and power and interlayer interconnection. The S7 back-end packaging process completes the preparation of the top insulating passivation layer and the under-bump metal layer (UBM); the entire substrate is flipped over, and the square temporary glass panel 100 is peeled off using a debonding process to remove the temporary bonding adhesive layer 110 remaining on the surface; conductive solder balls 700 are prepared in the under-bump metal layer area using a ball-planting process; finally, a board-level cutting process is used to diced the components to obtain individual finished packaged devices.

[0020] In the second specific embodiment, during the mounting process in step S3, the photoelectric module 830 can be placed outside the receiving cavity at the edge of the plastic seal layer or inside an independent receiving cavity.

[0021] Its innovative points are as follows: 1. Copper-based integrated cavity electromagnetic isolation architecture: The surface of a high thermal conductivity copper plate is integrally etched to form an independent housing cavity and a metal isolation wall, realizing the physical partitioning of power chips and small signal chips; the metal isolation wall can be grounded to form a Faraday cage shielding structure, blocking the near-field electromagnetic coupling path, greatly reducing high-frequency switching crosstalk, and significantly improving EMC performance without sacrificing integration.

[0022] 2. Chip-to-Chip Composite Heat Dissipation and Anti-Warp Structure: The entire non-active surface of the chip is directly bonded to a high thermal conductivity copper plate layer without any molding compound or insulating substrate in between, creating a short-range, low-resistance heat dissipation channel and effectively improving the package's heat dissipation capacity. At the same time, the high thermal conductivity copper plate layer and the metal isolation wall embedded in the molding layer form a composite rigid support structure, effectively suppressing molding stress warpage of large-size substrates and improving process yield.

[0023] 3. Low-cost TMV vertical interconnect solution: It adopts solid epoxy molding film layered vacuum hot pressing molding, and obtains a high flatness surface by relying on the uniform flow characteristics of the molding film. Only a small amount of CMP polishing is required to meet the redistribution layer preparation requirements, reducing process time and cost; vertical interconnect is realized by molding through-hole (TMV) without the need for high-cost TSV silicon through-hole process, and is fully compatible with conventional fan-out packaging process.

[0024] 4-board-level pre-processing and post-debonding process: The entire process uses a square temporary glass panel as a rigid support. After the molding, via preparation, redistribution layer and passivation layer are completed, the temporary panel is debonded and peeled off to expose the high thermal conductivity copper plate layer. This ensures the structural rigidity and alignment accuracy of the entire process, and avoids the bottom surface of the copper plate being etched, oxidized or damaged during the process.

[0025] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0026] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A board-level fan-out packaging structure, characterized in that: It includes a high thermal conductivity copper plate layer, a molding layer, a redistribution layer and an external lead-out structure stacked from bottom to top; It also includes a chip assembly, which contains at least one high-power chip and at least one small-signal chip; The high thermal conductivity copper plate layer is a packaged heat dissipation and electromagnetic shielding substrate. Its surface is integrally formed with multiple independent receiving cavities through an etching process. Adjacent receiving cavities are separated by an integral metal isolation wall. Each set of receiving cavities contains at least one chip, with high-power chips and small signal chips placed in different receiving cavities.

2. The board-level fan-out packaging structure according to claim 1, characterized in that: Only one chip is placed inside each of the cavities.

3. The board-level fan-out packaging structure according to claim 1, characterized in that: The metal isolation wall forms a Faraday cage shielding structure through a grounding design.

4. The board-level fan-out packaging structure according to claim 1, characterized in that: The top surface of the metal isolation wall is slightly lower than the active surface pad of the tallest chip in the chip assembly.

5. The board-level fan-out packaging structure according to claim 1, characterized in that: The high-power chip is a power or radio frequency semiconductor chip that performs power transmission and conversion functions, and is suitable for high-voltage, high-current, and high-frequency operating conditions. Typical components of the high-power chip include SiC and GaN transistors, power management chips, and radio frequency power chips. The small-signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions. The non-active surfaces of all chips are bonded to a high thermal conductivity copper plate layer, and the active surfaces are facing upwards.

6. The board-level fan-out packaging structure according to claim 1, characterized in that: The molding compound fully encapsulates the chip assembly and the metal isolation wall. The molding compound has molded vias of different heights, and the interior of the molded vias is filled to form conductive interconnect pillars. The lower end of the conductive interconnect pillar is electrically connected to the active surface pad of the corresponding chip, and the upper end of the conductive interconnect pillar is electrically connected to the redistribution layer.

7. The board-level fan-out packaging structure according to claim 1, characterized in that: The redistribution layer is disposed on the flat top surface of the molding compound. The redistribution layer includes at least one layer of alternately stacked metal circuit layers and insulating passivation layers. The redistribution layer is used to realize signal fan-out and power distribution for all chips.

8. The board-level fan-out packaging structure according to claim 1, characterized in that: The above the redistribution layer is provided with pads, a metal layer under the bumps, or a conductive solder ball structure to achieve external electrical interconnection of the package.

9. A method for fabricating a board-level fan-out package structure, used to manufacture a board-level fan-out package structure as described in any one of claims 1 to 8, characterized in that: The process involves pre-fabricating a high thermal conductivity copper plate layer with a receiving cavity, then mounting the corresponding chips onto the bottom surface of the corresponding receiving cavity at preset positions, followed by molding to form a molding layer, then processing the molding layer to obtain the corresponding chip through-holes, then obtaining the corresponding conductive interconnect pillars within the molding through-holes, then preparing a redistribution layer on the top surface of the molding layer, and then performing post-packaging processes on the redistribution layer to obtain an externally protruding connection structure, followed by board-level dicing to obtain a single independent finished packaged device.

10. The method for fabricating a board-level fan-out packaging structure according to claim 9, characterized in that, It includes the following steps: S1 substrate preparation: A square temporary glass panel is selected as a temporary process carrier. A temporary bonding adhesive layer is coated on the surface of the square temporary glass panel, and then a high thermal conductivity copper plate layer is laid on the entire surface. S2 isolation cavity etching: The high thermal conductivity copper plate layer is deeply etched using photolithography + wet etching process to form at least two independent cavities, with adjacent cavities separated by an integrated metal isolation wall. The S3 chip assembly uses a high thermal conductivity bonding adhesive layer to mount the non-active surfaces of high-power chips and small-signal chips onto preset positions on the bottom surface of the corresponding receiving cavity. The two types of chips are arranged in separate cavities, and the active surfaces are both facing upwards. The S4 molding layer is prepared and planarized by using a vacuum hot pressing process to press a solid epoxy molding film, which is then cured at high temperature to form a molding layer, achieving embedded full encapsulation of high-power chips, small-signal chips and metal isolation walls; the top surface of the molding layer is planarized by chemical mechanical polishing to achieve the preset thickness. The S5 conductive interconnect pillars are fabricated using ultraviolet laser drilling technology. Molded vias of different depths are processed at the positions of different chip pads in the molding layer. After preparing a Ti / Cu seed layer by physical vapor deposition, the vias are filled by copper electroplating to form the corresponding conductive interconnect pillars, which lead out the electrical signals of the high-power chip and the small signal chip respectively. S6 Redistribution layer fabrication: A redistribution layer is fabricated on the flattened top surface of the molding compound to complete the signal fan-out and power distribution of all chips; the redistribution layer includes at least one layer of alternately stacked metal circuit layer and insulating passivation layer to realize the lateral transmission of signals and electrical energy and inter-layer interconnection. The S7 back-end packaging process completes the preparation of the top insulating passivation layer and the metal layer under the bumps; then the entire substrate is flipped over, and the square temporary glass panel is peeled off using a debonding process to remove the residual temporary bonding adhesive layer on the surface. Conductive solder balls are prepared in the metal layer region under the bumps using a ball-planting process; finally, a board-level dicing process is used to slice the components into individual finished packaged devices.

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