A high heat dissipation package method and structure for stacked integration

Abstract

The application relates to a high-heat-dissipation packaging method and structure for stacked integration, which comprises the following steps: mounting a heterogeneous chip and a TSV chip on a temporary bonding plate, performing plastic packaging by using resin plastic packaging material to form a resin-based reconstitution wafer, wherein the heterogeneous chip is loaded in a copper heat dissipation shell; the resin-based reconstitution wafer is taken off by using a debonding technology, and re-wiring is made on the front surface of the resin-based reconstitution wafer; the back surface of the resin-based reconstitution wafer is thinned until the copper column of the TSV chip is exposed; re-wiring is made on the back surface of the resin-based reconstitution wafer; ball mounting, reflow and dicing are performed on the front re-wiring layer to form a single-chip packaging body; a plurality of single-chip packaging bodies are inverted and stacked, and underfilling is performed to form a final stacked packaging body. The application solves the problems of internal heat accumulation and low heat dissipation efficiency of the existing three-dimensional stacked packaging.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology for integrated circuits, and in particular to a high heat dissipation packaging method and structure for stacked integration. Background Technology

[0002] With the ever-increasing demand for data processing speed and bandwidth in fields such as artificial intelligence and high-performance computing, high-bandwidth memory (HBM) has achieved breakthroughs in both storage density and data transmission efficiency through its three-dimensional stacking architecture, becoming a core storage solution for high-end chips. To further improve memory capacity and bandwidth, the number of HBM stacking layers is evolving from 12 to 16 layers and beyond. However, the vertical stacking structure also brings severe thermal management challenges. Due to the tight bonding of multiple chips and the limitation of heat conduction paths to the vertical direction, heat easily accumulates inside the stack, forming hot spots. The mismatch in thermal expansion coefficients of heterogeneous materials such as silicon, copper, and dielectrics leads to a sharp increase in internal thermal resistance after the number of stacking layers exceeds 12. In some scenarios, the chip junction temperature even exceeds 140°C, far exceeding the safe operating threshold of 95~105°C for electronic components. This heat accumulation not only directly causes chip performance degradation and data transmission errors but also accelerates failure mechanisms such as electromigration and interlayer stripping, severely shortening product lifespan and significantly reducing HBM stacking yield, thus hindering the commercialization of ultra-high-layer HBM.

[0003] Therefore, in view of the problem of internal heat accumulation in multi-layer HBM stacks, this invention urgently needs to propose a high heat dissipation packaging method and structure for stacked integration to solve the above-mentioned technical problems. Summary of the Invention

[0004] The purpose of this invention is to provide a high-heat-dissipation packaging method and structure for stacked integration, so as to solve the problems of heat accumulation and low heat dissipation efficiency in existing three-dimensional stacked packaging.

[0005] To address the aforementioned technical problems, this invention provides a high-heat-dissipation packaging method for stacked integration, comprising: A resin-based reconstructed wafer is formed by mounting a heterogeneous chip and a TSV chip onto a temporary bonding board and then encapsulating them with a resin molding compound; wherein the heterogeneous chip is mounted inside a copper heat sink. The resin-based reconstructed wafer is removed using debonding technology, and rewiring is fabricated on the front side of the resin-based reconstructed wafer to form a front rewiring layer. The back side of the resin-based reconstructed wafer is thinned until the copper pillars of the TSV chip are exposed. A back-side rewiring layer is formed by rewiring the back side of the resin-based reconstructed wafer. A single-chip package is formed by balling, reflowing, and dicing on the front redistribution layer. The final stacked package is formed by flip-chip stacking of several of the single-chip packages and underfilling.

[0006] Preferably, the copper heat sink includes: a shell, a heat-conducting cavity, and capillary sidewall heat pipes; the heterogeneous chip is loaded inside the shell, and thermally conductive adhesive is filled between the heterogeneous chip and the shell to form a single chip unit that can be mounted; the heat-conducting cavity is equally spaced inside the four sides of the shell, and capillary sidewall heat pipes are arranged on the inner wall of the heat-conducting cavity, and the surface of the capillary sidewall heat pipes also includes several equally spaced serrated cones.

[0007] Preferably, the heat-conducting cavity has a rectangular cross-section, and the copper layer of the copper heat sink on the side away from the heterogeneous chip is thicker.

[0008] Preferably, the thermally conductive adhesive includes silicone thermally conductive curing adhesive, epoxy resin curing adhesive, nano-silver low-temperature sintering adhesive, or die-bonding solder paste.

[0009] Preferably, the thickness of the resin-based reconstructed wafer is 500μm to 900μm.

[0010] Preferably, both the formation of the front redistribution layer and the formation of the back redistribution layer are performed using a multi-layer redistribution process, wherein the multi-layer redistribution process employs a redistribution process in which passivation layers and metal layers are overlapped multiple times; wherein the thickness of the metal layers is not less than 3 μm and the thickness of the passivation layers is not less than 5 μm.

[0011] Preferably, before thinning the back side of the resin-based reconstructed wafer, the method further includes: providing temporary bonding protection on the front side of the resin-based reconstructed wafer; When thinning the back side of the resin-based reconstructed wafer, the process includes: coarse thinning to quickly remove the resin molding compound from the back side; and fine thinning to precisely thin to the target thickness that exposes the TSV chip.

[0012] Preferably, the ball placement process is used to form solder ball bumps, the solder ball bumps including cylindrical bumps or spherical bumps, and the flux used in the ball placement process includes organic flux, inorganic flux or resin-based flux.

[0013] Preferably, the underfilling process includes capillary underfilling and corner filling, and the underfill adhesive used includes epoxy resin-based underfill adhesive or modified epoxy-based underfill adhesive.

[0014] The present invention also provides a high heat dissipation packaging structure for stacked integration, which is prepared using a high heat dissipation packaging method for stacked integration as described above.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention directly embeds a copper heat sink structure with capillary sidewall heat pipes into the three-dimensional stacked package. By utilizing the rewiring technology on the upper surface of the heat sink and the flip-chip structure, the heat sink is in contact with the front of the chip, forming a direct heat dissipation channel, which greatly reduces thermal resistance. By encapsulating the chip on all five sides, the area of ​​the heat-conducting surface is greatly increased. The heat from the chip can be quickly conducted to the side of the package through the copper layer of the heat sink and the capillary sidewall heat pipes. This is a direct and efficient active heat dissipation method, realizing multi-dimensional and multi-scale thermal management of the three-dimensional packaging system.

[0016] 2. This invention can significantly widen the heat conduction path and reduce the thermal resistance in the vertical direction by embedding a copper heat sink, thereby greatly improving the heat dissipation efficiency in the horizontal direction. At the same time, the rigid structure of the copper heat sink can also enhance the mechanical stability of the HBM stack and alleviate the risk of interlayer delamination caused by the difference in thermal expansion coefficient. Without increasing the overall thickness of the stack or affecting the data transmission bandwidth, it achieves a dual improvement in heat dissipation efficiency and structural reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the heterogeneous chip with built-in heat sink and the TSV chip assembly provided by the present invention.

[0018] Figure 2 This is a schematic diagram of wafer reconstruction after being encapsulated with molding compound, provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the debonding and removal of temporary bonded carrier provided by the present invention.

[0020] Figure 4 This is a schematic diagram of the wafer-level front-side redistribution provided by the present invention.

[0021] Figure 5 This is a schematic diagram of the reconstructed wafer thinning method provided by the present invention.

[0022] Figure 6 This is a schematic diagram of the rewiring of the back side of the reconstructed wafer provided by the present invention.

[0023] Figure 7 This is a schematic diagram of wafer-level ball-mounting provided by the present invention.

[0024] Figure 8 This is a schematic diagram of the individual chip packages provided by the present invention.

[0025] Figure 9 This is a schematic diagram of the inverted stacking provided by the present invention.

[0026] Figure 10This is an external schematic diagram of the three-dimensional packaged body provided by the present invention.

[0027] Figure 11 This is a cross-sectional schematic diagram of the copper heat sink for mounting chips provided by the present invention.

[0028] Figure 12 This is a schematic diagram of the capillary sidewall heat pipe provided by the present invention.

[0029] Figure 13 This is a cross-sectional schematic diagram of a copper heat sink shell with equally spaced heat-conducting cavities provided by the present invention.

[0030] Figure 14 This is an external schematic diagram of the single-layer resin-based reconstructed wafer provided by the present invention.

[0031] In the diagram: 111-Copper heat sink, 112-Capillary sidewall heat pipe, 113-Thermal conductive adhesive, 114-Heterogeneous chip, 115-Temporary bonding carrier, 116-TSV chip, 117-Resin molding compound, 118-Front redistribution layer, 119-Back redistribution layer, 120-Solder ball bumps, 121-Bottom filler. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] like Figures 1 to 14 As shown, this embodiment of the invention specifically provides a high heat dissipation packaging method for stacked integration, which includes the following steps: The system provides a heterogeneous chip 114, a TSV chip 116, a resin molding compound 117, a copper heat sink 111 with capillary sidewall heat pipes 112, thermally conductive adhesive 113, and a temporary bonding carrier 115; the heterogeneous chip 114 is fixed onto the copper heat sink 111 with thermally conductive adhesive 113 to form a single chip unit that can be mounted. like Figure 1 As shown, various chips are mounted onto a carrier board with a temporary bonding film attached using a die mounter, thus forming a temporary bonding carrier board 115; like Figure 2 As shown, resin molding compound 117 is used for overmolding to form a resin-based reconstructed wafer; as Figure 3 As shown, the resin-based reconstructed wafer was removed using debonding technology; like Figure 4 As shown, a redistribution operation is performed on the front side of the resin-based reconstructed wafer to form a front redistribution layer 118; like Figure 5 As shown, a thinning operation is performed on the back side of the resin-based reconstructed wafer using a special grinding wheel to thin the back side of the copper heat sink 111 and expose the surface copper pillars of the TSV chip 116. like Figure 6 As shown, the front side of the resin-based reconstructed wafer is temporarily bonded and protected, and a rewiring operation is performed on the back side of the resin-based reconstructed wafer to form a back rewiring layer 119, thereby completing the fabrication of a double-sided wiring wafer. like Figure 7 As shown, using wafer-level ball-mounting technology, ball reflow and dicing are performed on the front side of the resin-based reconstructed wafer to form a single chip package, such as... Figure 8 As shown; like Figure 9 and Figure 10 As shown, the individual chip packages are flip-chip stacked and underfilled with underfill adhesive 121 to complete the final stacked package.

[0034] like Figure 11 , Figure 12 and Figure 13 As shown, in a preferred embodiment of the present invention, the copper heat sink 111 includes: a shell, a heat-conducting cavity, and capillary sidewall heat pipes 112; the heterogeneous chip 114 is loaded inside the shell, and thermally conductive adhesive 113 is filled between the heterogeneous chip 114 and the shell to form a single-chip unit that can be mounted; the heat-conducting cavity is evenly spaced inside the four sides of the shell, and the capillary sidewall heat pipes 112 are arranged on the inner wall of the heat-conducting cavity, and the surface of the capillary sidewall heat pipes 112 also includes several equally spaced serrated cones. The cross-section of the heat-conducting cavity is rectangular, and the copper layer of the copper heat sink 111 on the side away from the heterogeneous chip 114 is thicker.

[0035] The thermally conductive adhesive 113 includes silicone thermally conductive curing adhesive, epoxy resin curing adhesive, nano-silver low-temperature sintering adhesive, or die-bonding solder paste.

[0036] The thickness of the resin-based reconstructed wafer is 500μm~900μm.

[0037] The formation of the front redistribution layer 118 and the formation of the back redistribution layer 119 are both carried out using a multi-layer redistribution process, which employs a redistribution process in which passivation layers and metal layers are overlapped multiple times; wherein the thickness of the metal layers is not less than 3 μm and the thickness of the passivation layers is not less than 5 μm.

[0038] When performing back-side thinning, the resin molding material 117 on the back side is first removed quickly through coarse thinning, and then the target thickness of the TSV chip 116 is precisely reduced through fine thinning. The ball placement process is described to form solder ball bumps 120, which include columnar bumps or ball bumps. The flux used in the ball placement process includes organic flux, inorganic flux, or resin-based flux.

[0039] The underfilling process includes capillary underfilling and corner filling, and the underfill adhesive 121 used includes epoxy resin type underfill adhesive or modified epoxy type underfill adhesive.

[0040] In summary, this invention embeds a copper heat sink within the stack body, with both ends of the copper heat sink longitudinally penetrating the stack body and protruding from the surface of the stack body, such as... Figure 10 and Figure 14 As shown, the copper heat sink is connected to the back of the chip on one side by thermally conductive adhesive, and to the front of the upper chip on the other side by stacking. Utilizing the excellent thermal conductivity of copper, the heat generated during the operation of the multi-layer chip is quickly conducted out and evenly diffused to the heat sink formed by the entire copper heat sink. The heat is then transferred to the outer surface of the package through the capillary sidewall heat pipes on the heat sink. Fins and other heat dissipation structures can be further welded to the outside of the heat sink. Compared with the traditional solution that relies on the thermal conductivity of the silicon chip itself, the embedded copper heat sink can significantly widen the heat conduction path, reduce the thermal resistance in the vertical direction, and greatly improve the heat dissipation efficiency in the horizontal direction. At the same time, the rigid structure of the copper heat sink can also enhance the mechanical stability of the HBM stack and mitigate the risk of interlayer delamination caused by the difference in thermal expansion coefficients. Without increasing the overall thickness of the stack or affecting the data transmission bandwidth, it achieves a dual improvement in heat dissipation efficiency and structural reliability.

[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-heat-dissipation packaging method for stacked integration, characterized in that, include: A resin-based reconstructed wafer is formed by mounting a heterogeneous chip and a TSV chip onto a temporary bonding board and then encapsulating them with a resin molding compound; wherein the heterogeneous chip is mounted inside a copper heat sink. The resin-based reconstructed wafer is removed using debonding technology, and rewiring is fabricated on the front side of the resin-based reconstructed wafer to form a front rewiring layer. The back side of the resin-based reconstructed wafer is thinned until the copper pillars of the TSV chip are exposed. A back-side rewiring layer is formed by rewiring the back side of the resin-based reconstructed wafer. A single-chip package is formed by balling, reflowing, and dicing on the front redistribution layer. The final stacked package is formed by flip-chip stacking of several of the single-chip packages and underfilling.

2. The high heat dissipation packaging method for stacked integration as described in claim 1, characterized in that, The copper heat sink includes: a shell, a heat-conducting cavity, and capillary sidewall heat pipes; the heterogeneous chip is loaded inside the shell, and thermally conductive adhesive is filled between the heterogeneous chip and the shell to form a single chip unit that can be mounted; the heat-conducting cavity is equally spaced inside the four sides of the shell, and capillary sidewall heat pipes are arranged on the inner wall of the heat-conducting cavity, and the surface of the capillary sidewall heat pipes also includes several equally spaced serrated cones.

3. The high heat dissipation packaging method for stacked integration as described in claim 2, characterized in that, The heat-conducting cavity has a rectangular cross-section, and the copper layer of the copper heat sink is thicker on the side away from the heterogeneous chip.

4. A high-heat-dissipation packaging method for stacked integration as described in claim 2, characterized in that, The thermally conductive adhesive includes silicone thermally conductive curing adhesive, epoxy resin curing adhesive, nano-silver low-temperature sintering adhesive, or die-bonding solder paste.

5. A high-heat-dissipation packaging method for stacked integration as described in claim 1, characterized in that, The thickness of the resin-based reconstructed wafer is 500μm~900μm.

6. A high-heat-dissipation packaging method for stacked integration as described in claim 1, characterized in that, The formation of the front redistribution layer and the formation of the back redistribution layer both employ a multi-layer redistribution process, which uses a redistribution process that involves multiple overlaps of passivation layers and metal layers; wherein the thickness of each metal layer is not less than 3 μm, and the thickness of each passivation layer is not less than 5 μm.

7. A high-heat-dissipation packaging method for stacked integration as described in claim 1, characterized in that, Before thinning the back side of the resin-based reconstructed wafer, the method further includes: providing temporary bonding protection on the front side of the resin-based reconstructed wafer; When thinning the back side of the resin-based reconstructed wafer, the process includes: coarse thinning to quickly remove the resin molding compound from the back side; and fine thinning to precisely thin to the target thickness that exposes the TSV chip.

8. A high-heat-dissipation packaging method for stacked integration as described in claim 1, characterized in that, The ball placement process is described to form solder ball bumps, which include cylindrical bumps or spherical bumps. The flux used in the ball placement process includes organic flux, inorganic flux, or resin-based flux.

9. A high-heat-dissipation packaging method for stacked integration as described in claim 1, characterized in that, The underfilling process includes capillary underfilling and corner filling, and the underfill adhesive used includes epoxy resin-based underfill adhesive or modified epoxy-based underfill adhesive.

10. A high-heat-dissipation packaging structure for stacked integration, characterized in that, It is prepared using a high heat dissipation packaging method for stacked integration as described in any one of claims 1 to 9.

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