Middle active heat dissipation layer structure, machine learning collaborative control method and preparation method

Abstract

The application discloses a middle active heat dissipation layer structure, a machine learning collaborative control method and a preparation method. The structure comprises a first logic chip layer, a first bonding interconnection layer, a middle active heat dissipation layer, a second bonding interconnection layer and a second logic chip layer which are stacked and bonded in sequence. The middle active heat dissipation layer has a first heat receiving surface, a second heat receiving surface, a micro-channel network, a local reinforced cooling area and an electric interconnection avoiding area. The cooling medium can receive the heat of the upper and lower chips at the same time, and the space conflict between the flow channel and the vertical electric interconnection passage is avoided. The machine learning collaborative control method predicts future hot spots and outputs the flow regulation instructions corresponding to the branch valves according to the temperature of the local reinforced cooling area, the flow and pressure drop of the branch flow channel, the power consumption distribution of the upper and lower chips and the valve state, so as to realize bidirectional near-source cooling, partitioned accurate heat dissipation and reliable protection of the vertical interconnection.

Description

Technical Field

[0001] This invention relates to the fields of three-dimensional integrated packaging, logic chip thermal management, microfluidic cooling, package-level sensing, machine learning thermal control, and advanced electronic packaging reliability technology. Specifically, it relates to a centrally located active heat dissipation layer structure for vertically stacked multilayer logic chip packaging, a high-power logic chip packaging device, and a machine learning collaborative control method and preparation method. Background Technology

[0002] As the power density of AI computing, graphics computing, network switching processing, and high-performance logic control chips continues to rise, the heat flux density within a single logic chip has increased significantly. In two-dimensional packaging, heat sinks are typically placed on top of the chip, allowing heat to be conducted to an external cold plate or heatsink along a short path. However, in multi-layer vertically stacked logic chip packages, the internal logic chips are far from the external heatsink, and heat must pass through bonding layers, dielectric layers, vertical interconnect layers, and external packaging layers before it can be dissipated, easily leading to high-temperature hotspots in the central stack area. Relying solely on a top heatsink or bottom heat dissipation path is insufficient to meet the thermal management requirements of two high-power logic chips operating simultaneously.

[0003] In existing technologies, some 3D stacked chips employ microchannels, microfluidics, or heat-dissipating metal layers for active heat dissipation. Other solutions attempt to shorten the heat dissipation path by setting microfluidic channels between chip layers. These solutions demonstrate that intermediate cooling or embedded microchannels are not entirely unfamiliar concepts. However, existing solutions typically emphasize the presence of the cooling layer or the formation of fluid pathways, without fully addressing three packaging-level contradictions: First, the cooling layer located in the middle of the stack needs to simultaneously receive heat from the logic chips on both sides, rather than just dissipating heat from a single chip or a single die; second, there is space competition between the microchannel network and vertical electrical interconnects, hybrid bonding pads, and redistribution vias. Without dedicated avoidance structures, this can easily lead to electrical interconnect interruptions, cooling medium leakage, or electrochemical corrosion; third, the hot spots of the upper and lower logic chips migrate with workload, and uniform liquid supply or fixed flow distribution can result in insufficient cooling in hot spots while wasting pumping power in low-load areas.

[0004] Furthermore, existing intelligent flow distribution methods mostly focus on overall temperature field or pump speed regulation as the control object, and are generally based on a "sensor acquisition - machine learning prediction - actuator regulation" process, lacking a one-to-one correspondence with the internal physical structure of the package. For the central heat dissipation layer of multi-layer logic chips, if the machine learning model cannot be directly bound to local enhanced cooling areas, branch channels, electrical interconnect avoidance areas, and branch valves, it is difficult to demonstrate its technical contribution to a specific package structure. Therefore, a packaging solution is needed that unifies the central bidirectional heating structure, the partitioned enhanced cooling structure, the electrical interconnect avoidance structure, and machine learning predictive control, so that the heat dissipation layer is not only located at the center of the stack, but also can perform near-source, partitioned, and proactive cooling of hot spots of the upper and lower logic chips without compromising the reliability of the vertical interconnect. Summary of the Invention

[0005] The purpose of this invention is to address the problems existing in the prior art by providing a centrally located active heat dissipation layer structure, a machine learning collaborative control method, and a fabrication method for vertically stacked multilayer logic chips. This addresses the issues of long internal chip heat dissipation paths, mutual coupling of hot spots between upper and lower chips, spatial conflicts between microchannels and vertical electrical interconnects, lack of forward-looking flow distribution, and high pumping power consumption in existing vertically stacked multilayer logic chips.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, a centrally located active heat dissipation layer structure is provided for vertically stacked packaging of multi-layer logic chips. The multi-layer logic chip includes at least a first logic chip layer, a first bonding interconnect layer, a centrally located active heat dissipation layer, a second bonding interconnect layer, and a second logic chip layer, which are stacked and bonded sequentially. The centrally located active heat dissipation layer has a first heat-receiving surface facing the first logic chip layer and a second heat-receiving surface facing the second logic chip layer, so that the cooling medium entering the centrally located active heat dissipation layer simultaneously receives heat from the first logic chip and the second logic chip. The centrally located active heat dissipation layer is provided with a microfluidic network, at least one locally enhanced cooling area corresponding to the hot spot projection areas of the first logic chip and the second logic chip, and an electrical interconnection avoidance area spatially isolated from the vertical electrical interconnection path.

[0007] Furthermore, the centrally located active heat dissipation layer includes a substrate, a cooling medium inlet, and a cooling medium outlet. The microchannel network is disposed inside the substrate and connects the cooling medium inlet and the cooling medium outlet. The centrally located active heat dissipation layer also includes a sealing and isolation structure, which is disposed at at least one of the following locations: the periphery of the microchannel network, the boundary of the electrical interconnection avoidance area, the cooling medium inlet, and the cooling medium outlet.

[0008] Furthermore, when the hot spot projection area of ​​the first logic chip layer coincides with the hot spot projection area of ​​the second logic chip layer, the local enhanced cooling area is disposed in the overlapping hot spot projection area; when the hot spot projection areas partially overlap, a high-density enhanced cooling structure is disposed in the partially overlapping area, and branch channels are disposed in the non-overlapping areas respectively; when the hot spot projection areas do not overlap, at least two independent local enhanced cooling areas are disposed.

[0009] Furthermore, the localized enhanced cooling zone is connected to a branch flow channel or branch valve with independently adjustable flow rate, and the branch flow channel or branch valve corresponds one-to-one or in groups to one or more localized enhanced cooling zones.

[0010] Furthermore, the electrical interconnection avoidance zone is a channelless solid area, an insulating isolation wall, a metal barrier layer, a dielectric sealing ring, or a combination thereof arranged around the vertical electrical interconnection path, so that the microchannel network can reconverge after bypassing or diverting around the electrical interconnection avoidance zone.

[0011] Furthermore, the substrate material of the central active heat dissipation layer is one or more of silicon, glass, silicon carbide, aluminum nitride, silicon nitride, diamond composite material, copper, molybdenum-copper composite material, or high thermal conductivity composite substrate material; the first logic chip layer and the second logic chip layer are respectively at least one of central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), artificial intelligence accelerator, network processor, digital signal processor (DSP), or high power logic control chip.

[0012] Secondly, a machine learning collaborative control method is provided for a centrally located active heat dissipation layer structure in a vertically stacked package of multi-layer logic chips, comprising the following steps: The temperature of each local enhanced cooling zone, the flow rate and pressure drop of the corresponding branch flow channel, the power consumption distribution of the first logic chip layer and the second logic chip layer, and the branch valve status are collected to obtain the collected data. After synchronizing the data with time and assigning regional numbers, it is input into a machine learning prediction model. The machine learning prediction model outputs predicted hot spot temperatures and branch valve opening commands corresponding to each local enhanced cooling zone, based on the thermal-fluid coupling characteristics of the local enhanced cooling zone, branch flow channels, and electrical interconnection avoidance zone within the central active heat dissipation layer.

[0013] Furthermore, the training samples of the machine learning prediction model include at least one of thermal-fluid-structure interaction simulation data, packaged prototype test data, and online operation data. The training samples are labeled with region number, hot spot location, peak temperature, temperature difference between the first logic chip layer and the second logic chip layer, pressure drop of the branch channel, pumping power consumption, and adjacent temperature of the vertical electrical interconnect. The machine learning prediction model uses the peak temperature, the temperature difference, and the pressure drop as optimization objectives, and the maximum allowable pressure drop of the branch channel and the allowable temperature of the vertical electrical interconnect as constraints.

[0014] Furthermore, the prediction time of the machine learning prediction model is at least one time within 10 milliseconds to 10 seconds after the current sampling time, and the output control quantity of the machine learning prediction model includes the branch valve opening percentage, the target branch flow rate, the pump speed increment, or the backup flow channel switching command.

[0015] Thirdly, a method for fabricating a centrally located active heat dissipation layer structure for vertically stacked packaging of multilayer logic chips is provided, comprising the following steps: Based on the hot spot projection areas and vertical electrical interconnect path positions of the first logic chip layer and the second logic chip layer, the flow channel-avoidance cooperative layout of the central active heat dissipation layer is generated; According to the flow channel-avoidance collaborative layout, a microflow network, a locally enhanced cooling zone, and an electrical interconnection avoidance zone are fabricated in the substrate of the centrally located active heat dissipation layer; a sealed isolation structure and a sensing unit are formed; the centrally located active heat dissipation layer is aligned and bonded to the first logic chip layer and the second logic chip layer respectively; and the cooling medium path, the vertical electrical interconnect path, and the sensing unit are subjected to electro-thermal-fluid joint testing.

[0016] The microchannel network and the electrical interconnection avoidance area are defined by the same mask. Etching, laser processing, micromilling or sacrificial layer release are performed in the channel region, while solid material is retained or an insulating filling area is formed in the electrical interconnection avoidance area.

[0017] The bonding includes thermo-press bonding, wafer-level bonding, hybrid bonding, metal diffusion bonding, anodic bonding, or cryogenic dielectric bonding, wherein the vertical electrical interconnect path falls within the electrical interconnect avoidance zone during bonding.

[0018] The combined electro-thermal-fluidity test includes cooling channel withstand voltage test, leakage test, flow channel pressure drop test, vertical electrical interconnect continuity test, insulation reliability test, thermal response test, and thermal cycling reliability test.

[0019] Fourthly, a high-power logic chip packaging device is also provided, including the centrally located active heat dissipation layer structure described above. The packaging device can be an artificial intelligence computing package, a server processor package, a graphics computing package, a network switching processing package, or a high-power logic control package.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The central active heat dissipation layer structure for vertical stacking packaging of multi-layer logic chips is designed as a bidirectional heat receiving component with both a first heat receiving surface and a second heat receiving surface, so that the cooling medium can simultaneously receive heat from the upper first logic chip and the lower second logic chip within a single central layer; at the same time, a local enhanced cooling zone and an electrical interconnection avoidance zone are set within the central layer, so that heat dissipation resources and vertical interconnection space are configured collaboratively within the same physical layer; 2. The collaborative design of the electrical interconnection avoidance zone and the local enhanced cooling zone solves the spatial conflict between the microfluidic network and the vertical electrical interconnection path, reducing the risk of leakage, short circuit and corrosion; 3. The sensing unit, machine learning prediction model and branch valve constitute a closed loop of perception, prediction and execution, which can dynamically adjust the zone flow according to the future hot spot migration trend. Attached Figure Description

[0021] Figure 1 This is a schematic cross-sectional view of the five-layer logic chip vertical stacked package structure of the present invention, showing the relative positions between the first logic chip layer, the first bonding interconnect layer, the central active heat dissipation layer, the second bonding interconnect layer, and the second logic chip layer, as well as the path of the heat flow from the top and bottom to converge towards the central active heat dissipation layer; Figure 2 This is a schematic diagram of the functional zoning and flow channel layout of the active heat dissipation layer in this invention, showing the planar relationship of the cooling medium inlet, outlet, main flow channel, local enhanced cooling zone, electrical interconnection avoidance zone, and branch valves; Figure 3 This is a schematic diagram of the hot spot projection relationship between the upper and lower logic chips and the arrangement rules of the local enhanced cooling area of ​​the present invention, showing three cases: hot spot projection overlap, partial overlap, and complete non-overlap. Figure 4 This is a schematic diagram of the closed-loop machine learning collaborative thermal state prediction and zoned flow control of the present invention, showing the correspondence between sensor acquisition, feature construction, hotspot prediction, control output and physical branch valve execution; Figure 5 This is a schematic diagram of the process for fabricating the active heat dissipation layer, five-layer stacking and bonding, and electro-thermal-fluid joint testing in this invention.

[0022] In the diagram: 1. First logic chip layer; 2. First bonding interconnect layer; 3. Central active heat dissipation layer; 4. Second bonding interconnect layer; 5. Second logic chip layer; 301. Microfluidic network; 302. Cooling medium inlet; 303. Local enhanced cooling zone; 304. Cooling medium outlet; 305. Electrical interconnect avoidance zone. Detailed Implementation

[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In the description of this invention, it should be noted that the terms "middle," "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Example 1: A center-mounted active heat dissipation layer structure is provided for vertical stacking packaging of multi-layer logic chips, such as... Figure 1 As shown, the multilayer logic chip includes at least a first logic chip layer 1, a first bonding interconnect layer 2, a central active heat dissipation layer 3, a second bonding interconnect layer 4, and a second logic chip layer 5, which are stacked and bonded in sequence. The central active heat dissipation layer 3 has a first heat-receiving surface facing the first logic chip layer 1 and a second heat-receiving surface facing the second logic chip layer 5, so that the cooling medium entering the central active heat dissipation layer 3 simultaneously receives heat from the first logic chip layer 1 and the second logic chip layer 5. The central active heat dissipation layer 3 is provided with a microfluidic network 301, a local enhanced cooling area 303 corresponding to at least one hot spot projection area of ​​the first logic chip layer 1 and the second logic chip layer 5, and an electrical interconnection avoidance area 305 that is spatially isolated from the vertical electrical interconnection path.

[0026] The central active heat dissipation layer structure for vertical stacking of multi-layer logic chips is not simply a cooling channel sandwiched between two chip layers. Instead, the central active heat dissipation layer 3 is designed as a bidirectional heat receiving component with both a first heat receiving surface and a second heat receiving surface, so that the cooling medium can simultaneously receive heat from the upper first logic chip layer 1 and the lower second logic chip layer 5 within a single central layer. At the same time, a local enhanced cooling zone 303 and an electrical interconnection avoidance zone 305 are set within the central layer, so that the heat dissipation resources and the vertical interconnection space are configured collaboratively within the same physical layer.

[0027] Compared with the traditional top cold plate, this centrally located active heat dissipation layer structure significantly shortens the heat conduction path between the hot spot at the center of the stack and the cooling medium; compared with a simple heat-conducting intermediate layer, it can actively carry heat out of the package through fluid, rather than passively diffusing it inside the package.

[0028] The key to this centrally located active cooling layer structure lies in aligning the localized enhanced cooling zones with the hotspot projection areas of the upper and lower logic chips. The hotspot projection area refers to the vertical or near-vertical projection of high-power computing units, cache arrays, on-chip networks, power management areas, or high-speed interface areas in the first or second logic chip layer onto the centrally located active cooling layer plane. When the upper and lower hotspot projections overlap (i.e., when the hotspot projection areas of the first and second logic chip layers overlap), a localized enhanced cooling zone is set in the overlapping hotspot projection area, allowing this zone to serve both hotspots simultaneously. When the upper and lower hotspot projections partially overlap, an enhanced cooling structure with a higher heat transfer area density is set in the partially overlapping area, and independent branch channels are arranged in the non-overlapping areas. When the upper and lower hotspot projections do not overlap at all, two or more independent localized enhanced cooling zones are set, and liquid is supplied separately through different branch valves. Through these rules, the structure of this invention can adapt to the actual conditions of hotspot asymmetry, dynamic migration, and time-varying loads in multi-layer logic chips.

[0029] This structure also includes an electrical interconnect avoidance zone 305 within the centrally located active heat dissipation layer. This avoidance zone 305 is formed around copper pillars, through-silicon vias (TSVs), redistribution vias, hybrid bonding pad arrays, or other vertical electrical interconnect pathways. It can be a channelless solid region, an insulating isolation wall, a metal barrier layer, a dielectric sealing ring, or a combination thereof. The microchannel network branches and bypasses the avoidance zone as it approaches, then rejoins downstream, ensuring continuous fluid flow while preventing cooling medium from intruding into the electrical interconnect pathways. For hotspots located near densely populated electrical interconnect areas, this invention can provide a locally enhanced cooling zone or a heat diffusion enhancement layer near the avoidance zone to laterally transfer heat from areas where channels cannot be placed to adjacent areas where channels can be placed. This ensures the reliability of vertical interconnects while avoiding heat dissipation gaps caused by avoiding electrical interconnects.

[0030] Furthermore, the centrally located active heat dissipation layer 3 also includes a substrate, a cooling medium inlet 302, and a cooling medium outlet 304. The microchannel network 301 is disposed inside the substrate and connects the cooling medium inlet 302 and the cooling medium outlet 304. The centrally located active heat dissipation layer 3 also includes a sealing and isolation structure, which is disposed at at least one of the following locations: the periphery of the microchannel network, the boundary of the electrical interconnection avoidance area, the cooling medium inlet, and the cooling medium outlet.

[0031] For cooling media with a high risk of conductivity, the sealing and isolation structure includes inner and outer double sealing rings and a leakage detection electrode located between the double sealing rings.

[0032] Furthermore, the local enhanced cooling zone 303 is connected to a branch channel or branch valve with independently adjustable flow rate, and the branch channel or branch valve corresponds one-to-one or in groups to one or more local enhanced cooling zones.

[0033] In some embodiments, the localized enhanced cooling zone is composed of a branched flow channel densification zone, parallel branched flow channels, serpentine zigzag flow channels, turbulence column array, micro-needle rib array, locally deepened flow channels, locally narrowed flow channels, or combinations thereof, and the heat transfer area density of the localized enhanced cooling zone is higher than that of the ordinary flow channel zone.

[0034] Furthermore, the central active heat dissipation layer 3 integrates at least two of the following: a temperature sensing unit, a pressure sensing unit, a flow sensing unit, and a leakage detection unit, and at least one temperature sensing unit is arranged around the local enhanced cooling zone or the electrical interconnection avoidance zone.

[0035] Furthermore, the substrate material of the central active heat dissipation layer 3 is one or more of silicon, glass, silicon carbide, aluminum nitride, silicon nitride, diamond composite material, copper, molybdenum copper composite material, or high thermal conductivity composite substrate material.

[0036] The first logic chip layer and the second logic chip layer are respectively at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), an artificial intelligence accelerator, a network processor, a digital signal processor (DSP), or a high-power logic control chip.

[0037] In this embodiment, the first logic chip layer 1 can be a GPU, CPU, NPU, AI accelerator, network processor, or digital signal processor; the second logic chip layer 5 can be a high-power logic chip that is the same as or of a different type as the first logic chip layer; the first bonding interconnect layer 2 and the second bonding interconnect layer 4 can include microbumps, copper pillars, hybrid bonding pads, redistribution vias, or low-temperature metal diffusion bonding structures, used to realize electrical connections, mechanical connections, and local heat conduction between the upper and lower logic chips and the central active heat dissipation layer.

[0038] The heat generated by the first logic chip layer 1 is transferred to the first heated surface via the first bonding interconnect layer 2, and the heat generated by the second logic chip layer 5 is transferred to the second heated surface via the second bonding interconnect layer 4. The microfluidic network 301 is disposed between the two heated surfaces. The cooling medium enters through the cooling medium inlet 302, passes through the main flow channel, branch flow channels, and localized enhanced cooling zone 303, and exits through the cooling medium outlet 304. Because the cooling medium is located between the upper and lower logic chips, heat can be carried away without passing through the entire stack, making it particularly suitable for solving the high-temperature hotspot problem in the central region of multi-layer logic chip stacks.

[0039] like Figure 2As shown, the planar structure of the centrally located active heat dissipation layer 3 includes a general flow channel region, a locally enhanced cooling region 303, an electrical interconnect avoidance region 305, branch flow channels, branch valves, a cooling medium inlet 302, and a cooling medium outlet 304. The general flow channel region is used to maintain the overall flow of cooling medium; the locally enhanced cooling region 303 is used to correspond to the hot spot projection areas of the upper and lower logic chips; the electrical interconnect avoidance region 305 is used to accommodate copper pillars, bonding pillars, through-silicon vias (TSVs), redistribution vias, or hybrid bonding pad arrays. When the microchannels approach the electrical interconnect avoidance region 305, they can split into two or more branches to bypass the physical avoidance region and then rejoin. For high-density vertical electrical interconnect arrays, the electrical interconnect avoidance region can form a strip-shaped physical region; for distributed vertical interconnect arrays, the electrical interconnect avoidance region can form multiple island-shaped physical regions.

[0040] In a specific parameter window, the thickness of the centrally located active heat dissipation layer 3 can be from 50 micrometers to 800 micrometers, preferably from 100 micrometers to 500 micrometers; the microchannel width can be from 20 micrometers to 300 micrometers, the microchannel depth can be from 20 micrometers to 300 micrometers, and the spacing between ordinary channels can be from 50 micrometers to 600 micrometers. The spacing between channels in the locally enhanced cooling zone is smaller than that in the ordinary channel zone, or parallel branch microchannels, serpentine flow channels, micro-needle ribs, turbulence column arrays, locally deepened channels, or locally narrowed channels are used to make its heat transfer area density higher than that of the ordinary channel zone. For packages requiring lower voltage drop, parallel branch microchannels can be used; for hot spots with extremely high local heat flux density, micro-needle ribs or turbulence column arrays can be used; for hot spots with small area but high power consumption density, serpentine flow channels can be used to increase local residence time.

[0041] like Figure 3 As shown, this embodiment determines the local enhanced cooling zone based on the hotspot projection relationship between the upper and lower logic chips. If the hotspot projections of the first logic chip layer 1 and the second logic chip layer 5 are substantially overlapping, a single local enhanced cooling zone is set in the common projection area, which simultaneously receives heat from both the upper and lower sides. If the hotspot projections on both sides partially overlap, a higher density of microchannels or micro-needles is arranged in the overlapping area, and branch channels are arranged in the non-overlapping areas on both sides to avoid insufficient heat dissipation on the other side due to arrangement based only on one side's hotspot. If the hotspot projections on both sides do not overlap at all, two or more local enhanced cooling zones are set in the central active heat dissipation layer, each enhanced cooling zone is supplied with liquid by an independent branch channel and controlled by a corresponding branch valve. This arrangement rule enables the present invention to adapt to various heterogeneous or homogeneous high-power logic stacks such as dual GPUs, GPU+NPU, and CPU+AI accelerators.

[0042] The electrical interconnect clearance area 305 is a key structural feature that distinguishes this invention from a simple microchannel cooling layer. Vertical electrical interconnect paths need to transmit high-speed signals, power, and ground return between upper and lower logic chips; they cannot be interrupted by the flow channels or exposed to the cooling medium. Therefore, this invention defines the electrical interconnect clearance area simultaneously during the flow channel layout design phase, spatially isolating the microchannel network 301 from the vertical electrical interconnect paths. The electrical interconnect clearance area can be a flow channelless solid silicon region, a glass solid region, a ceramic solid region, an insulating medium-filled region, a metal barrier layer enclosure region, or a sealing ring enclosure region. A safety distance is reserved between the edge of the clearance area and the flow channels; this safety distance can be set from 5 micrometers to 200 micrometers depending on the type of cooling medium, operating pressure, and bonding precision.

[0043] When a hot spot is located near an electrical interconnect avoidance zone, since open flow channels are not suitable within the avoidance zone, this invention can provide a heat diffusion enhancement layer above, below, or adjacent to the avoidance zone. The heat diffusion enhancement layer can be a copper, diamond, silicon carbide, aluminum nitride, graphene composite layer, or other high thermal conductivity material layer, used to laterally guide heat from the avoidance zone to an adjacent locally enhanced cooling zone. In this way, the electrical interconnect avoidance zone ensures electrical reliability, while the locally enhanced cooling zone and the heat diffusion enhancement layer compensate for the cooling gap caused by the avoidance zone. This structure embodies the technical concept of "co-design of heat dissipation structure and electrical interconnect structure."

[0044] The sealing and isolation structure can be located at the periphery of the microchannel network, the cooling medium inlet 302, the cooling medium outlet 304, and the boundary of the electrical interconnection avoidance zone 305. The sealing and isolation structure can employ silicon-silicon bonded sealing rings, glass sealing rings, metal sealing rings, polymer sealing rings, dielectric bonded rings, or multi-layer composite sealing structures, with a width ranging from 20 micrometers to 500 micrometers. For dielectric coolants, a single-layer sealing ring can be used; for deionized water or other cooling media with a risk of conductivity, double-layer sealing rings can be used, with a leakage detection electrode placed between the double-layer sealing rings. Once the leakage detection electrode detects an impedance abnormality, the control system can close the corresponding branch valve, reduce the pump speed, or trigger the encapsulation protection strategy.

[0045] The arrangement of sensing units should serve zonal control and reliability monitoring. Temperature sensing units can employ thin-film metal resistors, diode temperature sensors, CMOS-compatible temperature sensing units, or thermocouple thin-film structures. Inlet temperature sensors are used to obtain the initial temperature of the cooling medium, outlet temperature sensors are used to estimate instantaneous heat transfer, temperature sensors in locally enhanced cooling zones are used to determine hotspot trends, and temperature sensors near electrical interconnect clearance zones are used to evaluate the thermal reliability of vertical interconnects. Pressure sensing units can be arranged at the inlet, outlet, middle section of the main flow channel, and inlet of critical branch flow channels. Flow sensing units can be arranged at the intersection of the main flow channel and branch flow channels. Flow sensing units can employ thermal flow detection, differential pressure flow detection, or micro vortex flow detection.

[0046] Actuators can include micropumps, proportional valves, MEMS microvalves, zoned valves, bypass valves, or backup flow channel switching valves. Each localized enhanced cooling zone can correspond to a branch valve, or multiple adjacent enhanced cooling zones can share a valve group. The control strategy is not to simply increase the total flow rate, but to adjust the valve opening of the corresponding branch based on future hotspot predictions. If the temperature of a certain localized enhanced cooling zone will rise in the future but the pressure drop is still within the allowable range, the valve opening of that branch will be increased first; if the pressure drop of the corresponding branch is close to the upper limit, the thermal load can be reduced through bypass valves, backup flow channels, or chip task migration.

[0047] Example 2: A machine learning collaborative control method is provided for a centrally located active heat dissipation layer structure for vertically stacked packaging of multi-layer logic chips.

[0048] Combination Figure 4 As shown, the machine learning collaborative control method includes the following steps: The temperature of each local enhanced cooling zone, the flow rate and pressure drop of the corresponding branch flow channel, the power consumption distribution of the first logic chip layer and the second logic chip layer, and the branch valve status are collected to obtain the collected data. After synchronizing the data with time and assigning regional numbers, it is input into a machine learning prediction model. The machine learning prediction model outputs predicted hot spot temperatures and branch valve opening commands corresponding to each local enhanced cooling zone, based on the thermal-fluid coupling characteristics of the local enhanced cooling zone, branch flow channels, and electrical interconnection avoidance zone within the central active heat dissipation layer.

[0049] This machine learning-based collaborative control method is not a general temperature field prediction algorithm, but rather establishes a prediction and control relationship based on the specific physical structure within the centrally located active heat dissipation layer. Through this control method, the system can proactively allocate flow before hotspots actually exceed thresholds, rather than passively increasing the total pump speed after the temperature exceeds limits.

[0050] Furthermore, the training samples of the machine learning prediction model include at least one of thermal-fluid-structure interaction simulation data, packaged prototype test data, and online operation data. The training samples are labeled with region number, hot spot location, peak temperature, temperature difference between the first logic chip layer and the second logic chip layer, pressure drop of the branch channel, pumping power consumption, and adjacent temperature of the vertical electrical interconnect. The machine learning prediction model uses the peak temperature, the temperature difference, and the pressure drop as optimization objectives, and the maximum allowable pressure drop of the branch channel and the allowable temperature of the vertical electrical interconnect as constraints.

[0051] Furthermore, the prediction time of the machine learning prediction model is at least one time within 10 milliseconds to 10 seconds after the current sampling time, and the output control quantity of the machine learning prediction model includes the branch valve opening percentage, the target branch flow rate, the pump speed increment, or the backup flow channel switching command.

[0052] While implementing the aforementioned machine learning collaborative control method, a machine learning collaborative control system is also provided. The system includes a data acquisition module, a feature construction module, a prediction model, a control decision module, and an actuator. The data acquisition module acquires the temperatures of the first logic chip layer, the second logic chip layer, the local enhanced cooling zone, the inlet temperature, the outlet temperature, branch flow rate, channel pressure drop, branch valve opening, chip power consumption distribution, and historical task load. The feature construction module synchronizes the data from different sampling sources in time and spatially aligns them according to the local enhanced cooling zone number. The prediction model can employ Long Short-Term Memory (LSTM) networks, gated recurrent units (GRUs), temporal convolutional networks, graph neural networks, random forests, gradient boosting trees, or lightweight neural networks. Its output corresponds to specific local enhanced cooling zones and branch valves, rather than simply outputting an abstract temperature field.

[0053] When training machine learning prediction models, thermal-fluid-structure interaction (TFS) simulation data, packaged prototype test data, and online runtime data can be used. Each training sample can include the power consumption diagram of the upper and lower chips at a certain moment, the temperature of each local enhanced cooling zone, the flow rate of each branch, the inlet-outlet temperature difference, pressure drop, valve opening, and the peak temperature at the next prediction moment. Sample labels can also include hotspot location, hotspot migration direction, bonding interface thermal stress, and adjacent temperature of vertical electrical interconnects. Model training objectives can include peak temperature prediction error, upper and lower chip temperature difference prediction error, flow channel pressure drop prediction error, and valve opening control error. By using physical partition numbers and valve numbers as inputs or embedding features, the model can learn the correspondence of "which specific branch valve should be adjusted when the temperature of a certain area rises."

[0054] In one exemplary control flow, the sampling period is 1 millisecond to 100 milliseconds, and the prediction time domain is 10 milliseconds to 10 seconds. The system first determines whether the future hot spot temperature exceeds a preset temperature threshold. If the hot spot temperature is expected to exceed the threshold and the corresponding branch voltage drop is below the upper limit, the opening of the corresponding branch valve is increased and the pump speed is appropriately increased. If the hot spot temperature is expected to exceed the threshold but the voltage drop is close to the upper limit, task migration, chip frequency reduction, backup flow channel switching, or local power limiting are triggered. If multiple local enhanced cooling zones heat up simultaneously, the controller performs multi-target allocation based on the peak temperature, the temperature difference between the upper and lower chips, and the pumping power consumption to avoid excessive voltage drop caused by all branch valves being fully open at the same time.

[0055] Example 3: A method for fabricating a centrally located active heat dissipation layer structure for vertical stacking packaging of multilayer logic chips.

[0056] Combination Figure 5 As shown, the preparation method includes the following steps: S1: Generate the flow channel-avoidance cooperative layout of the central active heat dissipation layer based on the power consumption distribution, hot spot projection area, vertical electrical interconnect path location and package external interface location of the first logic chip layer and the second logic chip layer; S2: Based on the flow channel-avoidance cooperative layout, a microflow channel network, a locally enhanced cooling zone, and an electrical interconnection avoidance zone are processed in the substrate of the central active heat dissipation layer; S3: Forming a sealed isolation structure and sensing unit; S4: Align and bond the central active heat dissipation layer to the first logic chip layer and the second logic chip layer respectively; S5: Perform electro-thermal-fluid joint testing on the cooling medium path, vertical electrical interconnect path, and sensing unit.

[0057] The flow channel-avoidance collaborative layout simultaneously marks the general flow channel area, the local enhanced cooling area, the electrical interconnection avoidance area, the sealing isolation area, the inlet and outlet positions, and the sensor unit position. Subsequently, a centrally located active heat dissipation layer 3 is fabricated on silicon, glass, silicon carbide, aluminum nitride, diamond composite material, or copper substrate.

[0058] The microfluidic network 301 can be formed using deep reactive ion etching, wet etching, laser processing, micromilling, sacrificial layer release, metal additive manufacturing, or wafer bonding. If a silicon-based active heat dissipation layer is used, the flow channel region and the electrical interconnect avoidance region can be defined within the same mask: the flow channel region is etched to form channels, while the electrical interconnect avoidance region retains solid silicon or is subsequently filled with insulating material. If a metal or ceramic substrate is used, the microfluidic channels can be formed using laser processing, micromilling, or additive manufacturing, with solid columnar or strip-shaped regions reserved at the vertical interconnect locations. After processing, a sealed isolation structure is formed, and temperature, pressure, and flow sensing units are fabricated at predetermined locations.

[0059] During bonding, the first logic chip layer 1, the central active heat dissipation layer 3, and the second logic chip layer 5 are precisely aligned so that the vertical electrical interconnect path falls within the electrical interconnect avoidance area 307, and the locally enhanced cooling area 303 corresponds to the hot spot projection area of ​​the upper and lower logic chips. Bonding methods can include thermocompression bonding, hybrid bonding, wafer-level bonding, metal diffusion bonding, anodic bonding, or cryogenic dielectric bonding. The bonding temperature, pressure, and atmosphere are determined based on the material system. For example, the silicon-based central active heat dissipation layer and the silicon-based logic chip can be bonded using cryogenic dielectric bonding or hybrid bonding; the metal substrate heat dissipation layer can be bonded using metal diffusion bonding or solder-assisted bonding; and the glass central layer can be bonded using anodic bonding or cryogenic adhesion.

[0060] After the packaged sample is completed, a cooling channel withstand pressure test should be performed under unpowered conditions. The test pressure can be 1.2 to 3 times higher than the normal operating pressure. Following this, liquid tightness and electrical insulation tests should be performed to confirm that the cooling medium has not entered the electrical interconnect area. Afterward, continuity, contact resistance, and high-frequency signal integrity tests should be performed on the vertical electrical interconnect path; thermal response tests should be performed on the locally reinforced cooling area; and calibration tests should be performed on the sensing unit. In the thermal cycling reliability test, the package structure is cycled between low temperature, room temperature, and high operating temperature, and the vertical electrical interconnect resistance, sealing structure leakage signal, and sensor output drift are monitored. If the electrical interconnect resistance changes or the leakage signal exceeds the threshold, the electrical interconnect clearance area size, sealing ring width, or channel spacing can be adjusted in reverse according to the location.

[0061] In a dual-GPU / NPU vertical stacked package embodiment, the first logic chip layer 1 is a GPU chip, the second logic chip layer 5 is an NPU chip, and the central active heat dissipation layer 3 adopts a silicon-based microfluidic structure. The hot spot projection on the GPU side is located in the area slightly to the left of the chip center, and the hot spot projection on the NPU side is located in the area slightly to the right of the chip center. Therefore, the central active heat dissipation layer is provided with two local enhanced cooling zones. The first local enhanced cooling zone adopts a serpentine flow channel to increase the local residence time, and the second local enhanced cooling zone adopts a parallel branched microfluidic channel to reduce the voltage drop. A strip-shaped electrical interconnection avoidance area is provided between the two local enhanced cooling zones to prevent the power pillars and high-speed signal channels from communicating with the microfluidic channels when passing through the central active heat dissipation layer.

[0062] During operation, when the GPU load increases while the NPU load decreases, the machine learning prediction model predicts that the region will heat up within the next 100 milliseconds based on the temperature of the GPU-side local enhanced cooling zone, GPU power consumption distribution, and historical hotspot migration trends. The control module then increases the opening of the valves in the first local enhanced cooling zone branch while decreasing the opening of the valves in the second local enhanced cooling zone branch to reduce unnecessary pumping power consumption. When the NPU load subsequently increases, the system further increases the flow rate of the second branch based on the prediction results. Compared to uniform flow distribution, this embodiment can reduce the temperature of local hotspots and decrease the temperature difference between the upper and lower chips while maintaining a relatively constant total flow rate.

[0063] In another embodiment, the hotspot projections of the first logic chip layer 1 and the second logic chip layer 2 substantially overlap. In this case, the centrally located active heat dissipation layer sets a high-density micro-needle fin enhanced cooling zone in the common hotspot projection area. The cooling medium enters this zone through multiple parallel branches to enhance the heat transfer capacity at the convergence point of the bidirectional heat flow. Multiple temperature sensing units are arranged around this enhanced cooling zone to sense the temperature rise caused by the upper and lower heat flow, respectively. A machine learning control model infers the heat load distribution between the upper and lower chips based on the inlet-outlet temperature difference, local temperature gradient, and branch flow rate, and adjusts the flow rate without significantly increasing the voltage drop.

[0064] In another embodiment, a high-density vertical electrical interconnect array is located near the hotspot projection area. To prevent flow channels from traversing this interconnect array, a centrally located active heat dissipation layer is configured with island-shaped electrical interconnect clearance zones, and a surrounding localized enhanced cooling zone is formed around these island-shaped clearance zones. The cooling medium flows around the outer periphery of the island-shaped clearance zones, resulting in a high heat transfer area density around the hotspot area. Simultaneously, a thin layer of highly thermally conductive material is placed below the island-shaped clearance zones to laterally diffuse the heat from the center of the clearance zones to the surrounding flow channels. This embodiment illustrates that the present invention does not simply sacrifice heat dissipation to ensure electrical interconnection, but rather resolves the spatial conflict between the clearance zones and the enhanced cooling zones through their cooperation.

[0065] The industrial implementation of this invention is compatible with existing wafer-level processing, chip-level bonding, microfluidic packaging, and advanced packaging testing processes. For mass production, the central active heat dissipation layer can be processed as a separate wafer, with flow channels, clearance areas, sealing rings, and sensing units completed at the wafer level; subsequently, it is bonded to logic chip wafers or diced chips. For high-end low-volume packaging, the central layer can also be processed and assembled at the single-chip level. This invention is applicable to server processors, AI computing chips, graphics computing chips, network switching chips, high-power logic control chips, and other packaged devices requiring near-source active heat dissipation within a vertically stacked structure.

[0066] To further illustrate the superiority of this centrally located active heat dissipation layer structure and machine learning-based collaborative control method, an exemplary simulation or prototype test is provided. Under the conditions of a total logic chip power consumption of 600W, a cooling medium inlet temperature of 25 degrees Celsius, and a constant total flow rate, the peak temperature at the stack center of a traditional top-heat dissipation structure is approximately 96 degrees Celsius, and the peak temperature of a typical uniform centrally located microchannel structure is approximately 78 degrees Celsius. However, after adopting the bidirectional heating, zoned enhanced cooling, and hotspot prediction flow distribution of this invention, the peak temperature can be reduced to approximately 64 degrees Celsius (as shown in Table 1). Under non-uniform load migration conditions, compared with uniform flow distribution, the local hotspot temperature fluctuation amplitude of this invention can be reduced from approximately 18 degrees Celsius to approximately 7 degrees Celsius, and the pumping power consumption can be reduced by approximately 12% to 25%. In thermal cycling reliability testing, after setting an electrical interconnect avoidance zone and a double sealing ring, the vertical interconnect resistance change rate can be controlled within approximately 1.5%, while the risk of electrical interconnect anomalies is significantly increased in the flow channel crossing scheme without an avoidance zone. The above data are exemplary data to illustrate the technical effects. The actual values ​​can be adjusted according to chip power consumption, channel size, cooling medium and packaging materials, and do not constitute a limitation on the scope of protection of the claims.

[0067] Table 1: Exemplary Comparison Data

[0068] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A centrally located active heat dissipation layer structure for vertically stacked packaging of multi-layer logic chips, characterized in that: The multilayer logic chip includes at least a first logic chip layer, a first bonding interconnect layer, a central active heat dissipation layer, a second bonding interconnect layer, and a second logic chip layer, which are stacked and bonded sequentially. The central active heat dissipation layer has a first heat-receiving surface facing the first logic chip layer and a second heat-receiving surface facing the second logic chip layer, so that the cooling medium entering the central active heat dissipation layer simultaneously receives heat from the first logic chip layer and the second logic chip layer. The central active heat dissipation layer is provided with a microfluidic network, at least one locally enhanced cooling area corresponding to the hot spot projection area of ​​the first logic chip layer and the second logic chip layer, and an electrical interconnection avoidance area that is spatially isolated from the vertical electrical interconnection path.

2. The centrally located active heat dissipation layer structure according to claim 1, characterized in that, The centrally located active heat dissipation layer includes a substrate, a cooling medium inlet, and a cooling medium outlet. The microchannel network is disposed inside the substrate and connects the cooling medium inlet and the cooling medium outlet. The centrally located active heat dissipation layer also includes a sealing and isolation structure, which is disposed at at least one of the following locations: the periphery of the microchannel network, the boundary of the electrical interconnection avoidance area, the cooling medium inlet, and the cooling medium outlet.

3. The centrally located active heat dissipation layer structure according to claim 1, characterized in that, When the hot spot projection area of ​​the first logic chip layer coincides with the hot spot projection area of ​​the second logic chip layer, the local enhanced cooling area is set in the overlapping hot spot projection area; when the hot spot projection areas partially overlap, a high-density enhanced cooling structure is set in the partially overlapping area, and branch channels are set in the non-overlapping areas respectively; when the hot spot projection areas do not overlap, at least two independent local enhanced cooling areas are set.

4. The centrally located active heat dissipation layer structure according to claim 3, characterized in that, The localized enhanced cooling zone is connected to a branch channel or branch valve with independently adjustable flow rate, and the branch channel or branch valve corresponds one-to-one or in groups to one or more localized enhanced cooling zones.

5. The centrally located active heat dissipation layer structure according to claim 1, characterized in that, The electrical interconnection avoidance zone is a channelless solid area, an insulating isolation wall, a metal barrier layer, a dielectric sealing ring, or a combination thereof arranged around the vertical electrical interconnection path, so that the microchannel network can reconverge after bypassing or diverting around the electrical interconnection avoidance zone.

6. The centrally located active heat dissipation layer structure according to claim 1, characterized in that, The substrate material of the central active heat dissipation layer is one or more of silicon, glass, silicon carbide, aluminum nitride, silicon nitride, diamond composite material, copper, molybdenum copper composite material, or high thermal conductivity composite substrate material; the first logic chip layer and the second logic chip layer are respectively at least one of central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), artificial intelligence accelerator, network processor, digital signal processor (DSP), or high power logic control chip.

7. The machine learning collaborative control method for the centrally located active heat dissipation layer structure according to any one of claims 1 to 6, characterized in that, Includes the following steps: The temperature of each local enhanced cooling zone, the flow rate and pressure drop of the corresponding branch flow channel, the power consumption distribution of the first logic chip layer and the second logic chip layer, and the branch valve status are collected to obtain the collected data. After synchronizing the data with time and assigning regional numbers, it is input into a machine learning prediction model. The machine learning prediction model outputs predicted hot spot temperatures and branch valve opening commands corresponding to each local enhanced cooling zone, based on the thermal-fluid coupling characteristics of the local enhanced cooling zone, branch flow channels, and electrical interconnection avoidance zone within the central active heat dissipation layer.

8. The machine learning collaborative control method for the centrally located active heat dissipation layer structure according to claim 7, characterized in that, The training samples of the machine learning prediction model include at least one of thermal-fluid-structure interaction simulation data, packaged prototype test data, and online operation data. The training samples are labeled with region number, hot spot location, peak temperature, temperature difference between the first logic chip layer and the second logic chip layer, pressure drop of the branch channel, pumping power consumption, and adjacent temperature of the vertical electrical interconnect. The machine learning prediction model uses the peak temperature, the temperature difference, and the pressure drop as optimization objectives, and the maximum allowable pressure drop of the branch channel and the allowable temperature of the vertical electrical interconnect as constraints.

9. The machine learning collaborative control method for the centrally located active heat dissipation layer structure according to claim 7, characterized in that, The prediction time of the machine learning prediction model is at least one moment within 10 milliseconds to 10 seconds after the current sampling time, and the output control quantity of the machine learning prediction model includes the branch valve opening percentage, the target branch flow rate, the pump speed increment, or the backup flow channel switching command.

10. The method for preparing the centrally located active heat dissipation layer structure according to any one of claims 1 to 6, characterized in that, Includes the following steps: Based on the hot spot projection areas and vertical electrical interconnect path positions of the first logic chip layer and the second logic chip layer, the flow channel-avoidance cooperative layout of the central active heat dissipation layer is generated; According to the channel-avoidance cooperative layout, a microchannel network, a locally enhanced cooling zone, and an electrical interconnection avoidance zone are fabricated in the substrate of the central active heat dissipation layer; a sealed isolation structure and a sensing unit are formed; the central active heat dissipation layer is aligned and bonded to the first logic chip layer and the second logic chip layer, respectively. The cooling medium path, vertical electrical interconnect path, and sensing unit were subjected to combined electro-thermal-fluid testing.

Images