Packaging structure and method of manufacturing the same

Abstract

The present disclosure relates to a packaging structure and a preparation method thereof, the packaging structure comprising: a metal substrate comprising an integrally arranged metal base and a metal protruding structure, the metal base being provided with at least two chip mounting areas, the metal protruding structure being arranged between two adjacent chip mounting areas; a chip mounted on the chip mounting area; a package covering the metal substrate and the chip, at least part of the metal protruding structure being configured to be in communication with the outside through the package. In this way, by integrally arranging the metal protruding structure and the metal base, electromagnetic shielding and heat dissipation can be integrated, the metal protruding structure is configured to be in communication with the outside through the package, for example, the metal protruding structure can be connected with a heat dissipation member outside, so that the metal base and the heat dissipation member outside jointly dissipate heat, improving the heat dissipation efficiency, in addition, the integrally arranged metal protruding structure and the metal base can simplify the structure and reduce the packaging steps, thereby reducing the packaging cost and improving the packaging efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of chip board-level packaging technology, specifically to a packaging structure and its fabrication method. Background Technology

[0002] In panel-level packaging, the integration density of semiconductor devices is increasing, leading to electromagnetic interference between multiple adjacent semiconductor devices. Simultaneously, as semiconductor device dimensions shrink, more computations are performed in a smaller space, resulting in increased heat generation. In related technologies, heat dissipation and shielding in panel-level packaged semiconductor devices are typically separate units, leading to problems such as numerous packaging steps, high packaging costs, and bottlenecks in heat dissipation and shielding. Summary of the Invention

[0003] The purpose of this disclosure is to provide a packaging structure and a method for fabricating the same. The packaging structure is integrally formed by a metal substrate and a metal protrusion structure, which can reduce the thickness and cost of the packaging, while also improving the heat dissipation and shielding effect, so as to at least partially solve the problems in the related art.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a packaging structure, comprising: A metal substrate includes an integrally formed metal substrate and a metal protrusion structure, wherein at least two chip mounting areas are provided on the metal substrate, and the metal protrusion structure is disposed between two adjacent chip mounting areas; A chip, mounted in the chip mounting area; and A package covering the metal substrate and the chip, wherein at least a portion of the metal protrusions are configured to communicate with the outside through the package.

[0005] Optionally, the thickness D of the metal substrate satisfies that D≥80um.

[0006] Optionally, the metal protrusion structure is constructed as a metal retaining wall; or The metal protrusion structure is constructed as a plurality of metal pillars spaced apart along a first direction.

[0007] Optionally, the top surface of the package is provided with a first through hole communicating with the metal protrusion structure, and a plurality of second through holes communicating with the chip electrodes.

[0008] Optionally, the packaging structure further includes a redistribution layer located on the top surface of the package. The first ground wire in the redistribution layer is connected to the metal protrusion structure through the first metal filling the first through hole. The second ground line and signal line in the redistribution layer are connected to the ground electrode and signal electrode of the chip respectively through the second metal filled in the corresponding second via.

[0009] Optionally, bumps are provided on the signal lines of the redistribution layer, and the bumps are used to form the I / O interface of the chip.

[0010] Optionally, the first grounding wire and the second grounding wire are connected to each other.

[0011] A second aspect of this disclosure provides a method for preparing an encapsulation structure, comprising: A metal substrate is prepared, wherein the metal substrate includes a metal substrate and a metal bump structure, the metal substrate has at least two chip mounting regions, and the metal bump structure is disposed between two adjacent chip mounting regions; The chip is mounted in the chip mounting area; A package is covered laterally on the metal substrate and above the metal substrate and the chip, and at least a portion of the metal protrusion structure is configured to connect to the outside through the package.

[0012] Optionally, the fabrication of the metal substrate includes: Provide the main metal plate; Multiple sub-regions are etched into the main metal plate; A metal substrate is formed by etching in each sub-region and by electroplating at predetermined locations on the metal substrate to form a metal protrusion structure, thereby forming a metal substrate.

[0013] Optionally, the method further includes: A first through hole is made on the top surface of the package. A second through-hole is formed on the top surface of the package body by filling the first through-hole with a first metal connection to the metal protrusion structure. The chip is connected by filling the second through hole with a second metal.

[0014] Optionally, the method further includes: A redistribution layer is provided on the top surface of the package. The first ground wire of the redistribution layer is connected to the metal protrusion structure through the first metal in the first through hole; The first ground line and signal line of the redistribution layer are connected to the ground electrode and signal electrode of the chip respectively through the second metal of the corresponding second via.

[0015] Optionally, the package covering the metal substrate and the chip includes: The main metal plate after the chip is mounted is then encapsulated in plastic. Cut the molded body along a preset trajectory to form multiple encapsulation structures.

[0016] The above technical solution involves a packaging structure comprising a metal substrate, a chip, and a package body. The metal substrate includes an integrally formed metal substrate and a metal bump structure. The metal substrate has at least two chip mounting areas, each mounting a chip. The metal bump structure is positioned between two adjacent chip mounting areas. The package body covers the metal substrate and the chip, and at least a portion of the metal bump structure is configured to penetrate the package body and connect to the outside. Thus, through the integrally formed metal bump structure and metal substrate, the metal bump structure primarily serves for electromagnetic shielding, while the metal substrate primarily serves for heat dissipation, integrating electromagnetic shielding and heat dissipation. The metal bump structure can also connect to the outside; for example, it can connect to an external heat sink, allowing the metal substrate and the external heat sink to share heat dissipation, improving heat dissipation efficiency. Furthermore, the integrally formed metal bump structure and metal substrate simplify the structure and reduce packaging steps, thereby reducing packaging costs and improving packaging efficiency.

[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the accompanying drawings...

[0019] Figure 1 This is a cross-sectional schematic diagram of the packaging structure provided in an exemplary embodiment of this disclosure.

[0020] Figure 2 This is a top view of a metal substrate provided in an exemplary embodiment of this disclosure.

[0021] Figure 3 This is a top view of a metal substrate provided in an exemplary embodiment of this disclosure.

[0022] Figure 4 This is a flowchart of the preparation method of the packaging structure provided in the exemplary embodiments of this disclosure.

[0023] Figures 5-9 This is a schematic diagram illustrating the fabrication process of the encapsulation structure in a rational embodiment of the present disclosure.

[0024] Explanation of reference numerals in the attached figures 1-Metal substrate; 11-Metal substrate; 12-Metal bump structure; 13-Chip mounting area; 2-Chip; 3-Package; 31-First through-hole; 32-Second through-hole; 4-Redistribution layer; 41A-First ground line; 41B-Second ground line; 42-Signal line; 43-Bump; 5-Thermal conductive adhesive; 6-Main metal plate; 7-Sub-region. Detailed Implementation

[0025] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0026] In this disclosure, unless otherwise stated, directional terms such as “inner” and “outer” refer to the inner and outer parts of a specific structural outline; terms such as “first” and “second” are used only to distinguish one element from another and do not have any sequential or important meaning.

[0027] Furthermore, "comprising" and its variations are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". Definitions of other terms will be given in the following description.

[0028] The terms “a” and “a plurality” used in this disclosure are illustrative and not restrictive, and those skilled in the art should understand that they should be understood as “one or more” unless otherwise expressly indicated in the context.

[0029] In this disclosure, directional terms are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or a specific orientation structure and operation, and therefore should not be construed as a limitation of this disclosure, which is not limited in this respect.

[0030] In the description of this disclosure, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "connect," "link," and "install" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0031] The inventors discovered that in panel-level packaging, the integration density of semiconductor devices is increasing, leading to electromagnetic interference between multiple adjacent semiconductor devices. Simultaneously, as semiconductor device dimensions shrink, more computations are performed in a smaller space, resulting in increased heat generation. In related technologies, heat dissipation and shielding in panel-level packaged semiconductor devices are typically separate units, leading to problems such as numerous packaging steps, high packaging costs, and bottlenecks in heat dissipation and shielding.

[0032] To solve the above technical problems, such as Figures 1 to 3 As shown, in a first aspect, this disclosure provides a packaging structure, including: a metal substrate 1, a chip 2, and a package 3, wherein the metal substrate 1 includes an integrally disposed metal substrate 11 and a metal protrusion structure 12, the metal substrate 11 is provided with at least two chip mounting regions 13, and the metal protrusion structure 12 is disposed between two adjacent chip mounting regions 13; the chip 2 is mounted on the chip mounting region 13; the package 3 covers the metal substrate 1 and the chip 2, and at least a portion of the metal protrusion structure 12 is configured to be able to pass through the package 3 and communicate with the outside.

[0033] The above technical solution includes a packaging structure comprising a metal substrate 1, a chip 2, and a package body 3. The metal substrate 1 includes a metal substrate 11 and a metal protrusion structure 12. The metal substrate 11 has at least two chip mounting areas 13, and a chip 2 is mounted on each chip mounting area 13. The metal protrusion structure 12 is disposed between two adjacent chip mounting areas 13. The package body 3 covers the side of the metal substrate 1 and the top of the metal substrate 1 and the chip 2. A first through hole 31 communicating with the metal protrusion structure 12 is provided on the top surface of the package body 3 so that the metal protrusion structure 12 can be connected to an external heat sink through the first metal filled in the first through hole 31. The integrated metal bump structure 12 and metal substrate 11 combine electromagnetic shielding and heat dissipation. The metal bump structure 12 is also connected to an external heat sink via a first through-hole 31, allowing the metal substrate 11 and the external heat sink to share heat dissipation. The design of a large, vertically penetrating heat conduction path with conduction both vertically and horizontally improves heat dissipation efficiency. Furthermore, the integrated metal bump structure 12 and metal substrate 11 simplify the structure and reduce packaging steps, thereby lowering packaging costs and improving packaging efficiency. Of course, the integrated design of the metal bump structure 12 and metal substrate 11 also enhances the overall mechanical strength of the metal substrate 1.

[0034] Meanwhile, the metal substrate 11 and the metal bump structure 12 can also shield signal interference from above and between the chips, providing comprehensive shielding for the surrounded chip 2, effectively reducing electromagnetic interference and improving the performance and reliability of the chip 2.

[0035] In some possible implementations, the thickness D of the metal substrate 11 satisfies D≥80µm. In this embodiment, by replacing the composite material substrate commonly used in traditional packaging structures with the metal substrate 11, the substrate thickness can be reduced; and due to the metal substrate 11, the lower limit of the original composite substrate thickness can be lowered to 80µm, thereby significantly reducing the overall thickness of the packaging structure, providing integration space for wiring and other devices, and improving integration density. Furthermore, the thinner metal substrate 11 can also reduce the vertical heat conduction path, lower the overall thermal resistance, and allow heat to be dissipated quickly, thereby improving heat dissipation capacity.

[0036] In some possible implementations, the metal bump structure 12 is constructed as a metal barrier; or the metal bump structure 12 is constructed as a plurality of metal pillars spaced apart along a first direction. Thus, by constructing the metal bump structure 12 as a metal barrier or a plurality of metal pillars, electromagnetic shielding can be formed between two adjacent chips 2, reducing electromagnetic interference between the two adjacent chips 2. For example, the metal substrate 11 can be a copper plate, and the metal bump structure 12 can be constructed as a copper barrier of the same material as the metal substrate 11, wherein the copper barrier extends along the gap between two adjacent chip mounting areas 13, and both ends of the copper barrier extend to the outside of the chip 2, thereby reducing electromagnetic interference between the two chips 2 through the arrangement of the copper barrier. It is understood that the aforementioned copper barrier can be grown vertically upwards at a predetermined position on the metal substrate 11, directly forming a continuous solid copper barrier.

[0037] It is understood that the copper material of the metal substrate 11 and the metal protrusion structure 12 described above is illustrative. In other embodiments, the metal substrate 11 and the metal protrusion structure 12 can also be made of other metal materials, such as aluminum alloy, copper alloy, etc. Of course, the fact that the metal substrate 11 and the metal protrusion structure 12 are made of the same material is also illustrative. In other embodiments, the materials of the two can also be different. For example, the metal substrate 11 can be an aluminum alloy, and the metal protrusion structure 12 can be a copper alloy.

[0038] It is understood that the above-described metal protrusion structure 12, constructed as a copper retaining wall, is illustrative. In other embodiments, the metal protrusion structure 12 may also be constructed as a plurality of copper pillars spaced apart along a first direction. The first direction can be referenced to the direction of the gap between the two chip mounting areas 13. Figure 3 In the X direction, multiple copper pillars can be formed at preset positions on the metal substrate 11 by electroplating. The multiple copper pillars can be arranged at equal intervals along the gap between the two chip mounting areas 13. Thus, by setting multiple copper pillars, a shield can also be formed between the two chips 2, reducing electromagnetic interference between the two chips 2.

[0039] Of course, in some other possible implementations, the metal substrate 1 can also be formed by casting with a mold, that is, the shape of the metal substrate 1 is formed in the mold, and the metal substrate 1 is formed after casting and demolding. In this case, the metal substrate 11 and the metal protrusion structure 12 in the metal substrate 1 are integrally formed.

[0040] Of course, the metal substrate 1 can also be etched on a large piece of metal according to a preset step so that the metal substrate 11 and the metal protrusion structure 12 are integrally formed.

[0041] Since the packaging structure is board-level packaging, a large-area main metal plate 6 is typically required. Multiple electrically isolated sub-regions 7 are etched onto the main metal plate 6, and a metal substrate 11 is etched onto each sub-region 7. Metal protrusion structures 12 are then electroplated onto the metal substrate 11, thereby forming a metal substrate 1 within the sub-region 7. It should be noted that the main metal plate 6 can be divided into multiple electrically isolated sub-regions 7 by etching. That is, unwanted metal areas are etched away, creating isolation trenches or grooves. The overall shape of the main metal plate 6 remains a single plate, facilitating overall transfer and movement. Individual sub-regions 7 can be further etched to form the required metal substrate 11, and metal protrusion structures 12 can be electroplated onto the metal substrate 11. Chip mounting areas 13 are also formed on the metal substrate 11, and the chip 2 is mounted on the chip mounting area 13. Because the sub-regions 7 are isolated by trenches, thermal expansion and contraction stress is released according to each individual sub-region 7, resulting in minimal overall warpage of the main metal plate 6.

[0042] It is understandable that the aforementioned main metal plate 6 can be equally divided into multiple sub-regions 7, for example... Figure 2 As shown, the main metal plate 6 can be divided into 12 sub-regions 7, thereby enabling the simultaneous formation of 12 metal substrates 1. After panel-level packaging and cutting, 12 single-chip package structures can be formed.

[0043] In some possible implementations, such as Figure 1As shown, to facilitate the connection of chip 2 and metal bump structure 12 with external devices or circuits, the top surface of package 3 is provided with a first through hole 31 communicating with metal bump structure 12 and multiple second through holes 32 communicating with the electrodes of chip 2. A first metal is filled into the first through hole 31 to facilitate the connection of metal bump structure 12 with external devices or circuits. The first through hole 31 can be laser-drilled to expose the metal bump structure 12. The first metal filling in the first through hole 31 facilitates the connection of the metal bump structure 12 with external devices or circuits. For example, the metal bump structure 12 can be connected to an auxiliary heat sink through the first metal filling in the first through hole 31. The auxiliary heat sink can be, for example, a metal layer located on package 3, thereby achieving heat dissipation of the bottom metal substrate 11 of the package structure and the auxiliary heat sink on the upper part of package 3. Of course, the above-mentioned device can also be an external grounding wire. The metal protrusion structure 12 is connected to the external grounding wire through the first metal filled in the first through hole 31, which can also form a shield above the chip 2, thereby forming a shielding layer formed by the metal substrate 11, the metal protrusion structure 12 and the external grounding wire, which improves the electromagnetic shielding effect.

[0044] It is understood that the above-described structure, which establishes the metal protrusion structure 12 by starting the first through hole 31 at a preset position on the package 3 above the metal protrusion structure 12 to achieve external communication, is illustrative. In other embodiments, the metal protrusion structure 12 can also be connected to the outside through other structures. For example, in the vertical direction, the height of the metal protrusion structure 12 is higher than the height of the chip 2. After the package 3 is packaged, the package 3 can be thinned at a preset position until the metal protrusion structure 12 is exposed. Thus, the exposed metal protrusion structure 12 can pass through the package 3 to connect to external devices or ground wires.

[0045] Of course, the thickness of the package 3 in the vertical direction can also be controlled. For example, the metal substrate 11 and the chip 2 can be packaged with a thinner package thickness, so that part of the metal protrusion structure 12 is exposed, while the chip 2 is encapsulated.

[0046] Of course, there are multiple second vias 32, each corresponding to a ground interface, signal interface, and power interface of chip 2. By filling the second vias 32 with a second metal, the ground interface, signal interface, and power interface of chip 2 can be connected to external devices or circuits. That is, at least some of the second vias 32 are connected to the ground interface of chip 2 after being filled with the second metal, at least some are connected to the signal interface of chip 2 after being filled with the second metal, and at least some are connected to the power interface of chip 2 after being filled with the second metal. For example, a device can be directly mounted to chip 2 through the metal filling in the second via 32. This device can be a resistor, capacitor, or another chip.

[0047] In some possible implementations, such as Figure 1 As shown, the packaging structure also includes a redistribution layer 4, which is located on the top surface of the package 3. The first ground wire 41A of the redistribution layer 4 is connected to the metal protrusion structure 12 through the first through-hole 31 filled with metal. For example, the redistribution layer 4 is located on the top surface of the package 3. With the top surface of the package 3 as the base, after the chip 2 and the metal substrate 1 are encapsulated, the top surface of the package 3 needs to be polished flat. An insulating resin is then laminated or coated on the entire top surface of the polished package 3 to provide an insulating base for the redistribution layer 4. The location of the traces is opened by photolithography. Copper is deposited and electroplated in the opened area to form copper traces and pads. This copper trace is the redistribution layer 4 on the top surface of the package 3. After the redistribution layer 4 is completed, an insulating layer can be covered on top. Of course, it is necessary to open windows to expose copper at the locations of the ball-planting and interconnection pads so that the redistribution layer 4 can be electrically connected to external electrical components. To facilitate the connection between the first ground line 41A of the redistribution layer 4 and the metal bump structure 12, a first through-hole 31 is formed at a predetermined position on the top surface of the package 3. The first through-hole 31 can be laser-drilled to expose the metal bump structure 12. The first through-hole 31 is filled with a first metal to connect the metal bump structure 12 and the first ground line 41A of the redistribution layer 4, thereby connecting the redistribution layer 4 to the metal substrate 11 through the metal bump structure 12 and achieving grounding of the redistribution layer 4. In addition, the heat generated by the chip 2 can be dissipated through the metal substrate 11 and conducted to the redistribution layer 4 through the metal bump structure 12, achieving auxiliary heat dissipation. Compared with the chip 2, heat can be dissipated in both the top and bottom directions, thereby further improving the heat dissipation capacity.

[0048] It is understandable that the first metal filling the first through hole 31 can be electroplated and integrally formed with the redistribution layer 4 simultaneously, or the first metal filling the first through hole 31 can be distributed and formed with the redistribution layer 4.

[0049] In some possible implementations, to facilitate the electrode lead-out of chip 2, the second ground line 41B, signal line 42, and power line of the redistribution layer 4 are connected to the ground electrode, signal electrode, and power electrode of chip 2 respectively through the filling of the corresponding second vias 32 with second metal. Thus, by opening multiple second vias 32 on the package 3 above the front side of chip 2 and filling the second vias 32 with second metal, the electrodes of chip 2 can be led upwards to the top redistribution layer 4, completing the vertical interconnection and fan-out of signals, power, and ground, saving bottom-layer wiring space; simultaneously, the top redistribution layer 4 can also serve as an electromagnetic shield and auxiliary heat dissipation structure, adaptable to high-density pins and chip 2 stacking integration.

[0050] It is understood that the filling of the second metal in the second through hole 32 can be set with reference to the filling of the first metal in the first through hole 31. That is, the filling of the second metal in the second through hole 32 can be electroplated and integrally formed with the redistribution layer 4 at the same time, or the filling of the second metal in the second through hole 32 can be distributed and formed with the redistribution layer 4.

[0051] Of course, there can be multiple first ground wires 41A and multiple second ground wires 41B, and multiple first ground wires 41A and multiple second ground wires 41B are connected to each other, so that after the first ground wires 41A and the second ground wires 41B are connected, they are connected to the metal substrate 11 through the metal protrusion structure 12, thereby facilitating heat conduction to the metal substrate 11 for heat dissipation.

[0052] In some possible implementations, bumps 43 are provided on the signal lines 42 of the redistribution layer 4. The bumps 43 are used to form the I / O interface leads of the chip 2. The bumps 43 can be solder balls or copper pillars, and the device can be directly mounted to the package structure through the bumps 43.

[0053] It is understood that the redistribution layer 4 of the above-mentioned packaging structure can be rearranged and generated on a single packaging structure, or it can be generated on the top surface of the main metal plate 6 after the main metal plate 6 is molded and before the single packaging structure is formed, by generating the redistribution layer 4 corresponding to each packaging structure according to a preset route, and then cutting the main metal plate 6 to form multiple packaging structures with redistribution layers 4.

[0054] Of course, in some possible implementations, such as Figure 1As shown, to facilitate the fixing of chip 2 onto the preset chip mounting area 13, the packaging structure also includes thermally conductive adhesive 5. Thermally conductive adhesive 5 is disposed on the chip mounting area 13, and the back side of chip 2 is fixed to the chip mounting area 13 by the thermally conductive adhesive 5. Thus, when chip 2 generates heat during operation, the thermal conductivity of the thermally conductive adhesive 5 can be used to directly transfer heat to the metal substrate 11 for dissipation. It is understood that the thickness of the aforementioned thermally conductive adhesive 5 can be adjusted according to the specific type of chip 2, and this disclosure does not impose specific limitations.

[0055] It is understood that the types of chips 2 installed in the two chip mounting areas 13 can be the same or different. In this embodiment, the type of chip 2 can be selected according to the specific operating conditions.

[0056] The second aspect of this disclosure, such as Figures 4 to 9 As shown, a method for fabricating a packaging structure is provided, comprising: S10. Prepare a metal substrate 1, wherein the metal substrate 1 includes a metal substrate 11 and a metal protrusion structure 12, the metal substrate 11 is provided with at least two chip mounting regions 13, and the metal protrusion structure 12 is disposed between two adjacent chip mounting regions 13. S20. Install chip 2 in chip mounting area 13; S30. A package 3 is covered on the side of the metal substrate 1 and above the metal substrate 1 and the chip 2, and at least part of the metal protrusion structure 12 passes through the package 3 and communicates with the outside.

[0057] Through the above technical solution, the packaging structure preparation method provided in this embodiment prepares a metal substrate 1. The metal substrate 1 may include an integrally formed metal substrate 11 and a metal protrusion structure 12. A chip mounting area 13 is provided on the metal substrate 11, and the metal protrusion structure 12 is disposed between two adjacent chip mounting areas 13. A chip 2 is mounted on each chip mounting area 13. By covering the metal substrate 1 and the chip 2 with a package body 3, at least a portion of the packaged metal protrusion structure 12 can pass through the package body 3 and communicate with the outside, so as to complete the preparation of the packaging structure. Thus, the above steps facilitate the formation of an integrally integrated metal substrate 11 and metal protrusion structure 12. The packaged metal protrusion structure 12 can also communicate with the outside through the package body 3, thereby integrating heat dissipation and electromagnetic shielding. That is, the metal protrusion structure 12 can shield electromagnetic interference between the two chips 2, and can also integrate heat dissipation with the metal substrate 11 to improve heat dissipation capacity. In addition, the metal protrusion structure 12 can also be connected to external devices, which can be auxiliary heat dissipation components or grounding wires. By connecting the metal protrusion structure 12 to external devices, multiple paths can be formed for simultaneous heat dissipation or shielding, thereby improving both shielding effect and heat dissipation efficiency. Furthermore, the integrally integrated metal substrate 11 and metal protrusion structure 12 can simplify the structure and reduce packaging steps, thereby reducing the packaging cost and improving the efficiency of packaging structure preparation.

[0058] In this metal substrate 1, the metal substrate 11 can be a copper plate, and the metal protrusion structure 12 can be a copper barrier made of the same material as the metal substrate 11. A continuous solid copper barrier is directly formed by vertical electroplating at a predetermined position on the metal substrate 11.

[0059] Of course, such as Figure 5 As shown, the aforementioned metal protrusion structure 12 can also be a plurality of copper pillars spaced apart along the first direction. The plurality of copper pillars can also be directly formed on the metal substrate 11 by an upward vertical electroplating growth method. In addition, the metal substrate 1 can also be etched on a large piece of metal according to a predetermined step so that the metal substrate 11 and the metal protrusion structure 12 are integrally formed.

[0060] Of course, in some possible embodiments, the metal substrate 1 can also be formed by mold casting, that is, the shape of the metal substrate 1 is formed in a mold, and the metal substrate 1 is formed after demolding by casting metal. In addition, the metal substrate 1 can also be formed by etching a large copper plate according to a predetermined step, so that the metal substrate 11 and the metal protrusion structure 12 are integrally formed.

[0061] In some possible embodiments, the fabrication of the metal substrate 1 includes: Provide main metal plate 6; The main metal plate 6 is etched into multiple sub-regions 7; A metal substrate 11 is etched within each sub-region 7, and a metal protrusion structure 12 is electroplated at a predetermined position on the metal substrate 11, thus forming multiple metal substrates 1 on the main metal plate 6. The main metal plate 6 can be a large copper plate. The main metal plate 6 is divided into multiple electrically isolated sub-regions 7 by etching; that is, unwanted metal areas are etched away, creating isolation grooves or trenches. The overall shape of the main metal plate 6 remains a single sheet, facilitating its transfer. However, the internal metal of each sub-region 7 is separated by trenches, forming multiple electrically isolated sub-regions 7. A metal substrate 11 is etched within each sub-region 7, and a metal protrusion structure 12 is electroplated at a predetermined position on the metal substrate 11, thereby forming multiple metal substrates 1 on the main metal plate 6. Because stress is released according to individual sub-regions 7, the overall warpage of the main metal plate 6 can be reduced.

[0062] In some possible implementations, a corresponding chip 2 is mounted on the chip mounting area 13 on the metal substrate 11 of each metal substrate 1 on the main metal plate 6, and then encapsulated using a panel-level molding process or a dry film molding process. Multiple package structures are formed by cutting the encapsulated body along a preset trajectory. At this time, a covering package 3 is formed on the sides of each metal substrate 1, above the metal substrate 1, and above the chip 2. In this way, the production efficiency of the package structure can be improved through a panel-level packaging process.

[0063] like Figure 5 As shown, in a sub-region 7, there is a cross-sectional schematic diagram of a metal substrate 11 and a metal protrusion structure 12. Two chip mounting regions 13 are provided on the metal substrate 11, and a metal protrusion structure 12 is formed by electroplating at a predetermined position between the two chip mounting regions 13, thereby forming a metal substrate 1.

[0064] like Figure 6 As shown, where, Figure 6 In order to be in Figure 5 The diagram illustrates the subsequent steps of the fabrication process based on the prepared metal substrate 1. Chips 2 are mounted in each chip mounting area 13 on the metal substrate 1, and the back side of each chip 2 can be attached to the corresponding chip mounting area 13 by thermally conductive adhesive 5.

[0065] like Figure 7 As shown, where, Figure 7 yes Figure 6The diagram illustrates the subsequent steps in the fabrication process based on the metal substrate 1 after the chip 2 is mounted. After each metal substrate 1 on the main metal plate 6 with the chip 2 mounted is mounted by a panel-level molding process or a dry film molding process, the molding body is cut along a preset trajectory to form multiple package structures. At this time, in a sub-region 7, a package body 3 is formed on the side of the metal substrate 11 and above the metal substrate 11 and above the chip 2.

[0066] Of course, it is understandable that after the metal substrate 11 and the chip 2 above it are encapsulated, the package body 3 above the metal bump structure 12 can be thinned through a thinning process, so that part of the metal bump structure 12 is exposed. That is, during the manufacturing process of the metal bump structure 12, the height of the metal bump structure 12 in the vertical direction is higher than that of the chip 2. Therefore, after encapsulation, the pre-set thickness can be reduced to allow part of the metal bump structure 12 to be exposed, so as to facilitate the connection between the metal bump structure 12 and the outside.

[0067] In addition, in some other possible embodiments, a hole can be made in the package 3 above the metal bump structure 12. That is, the height of the metal bump structure 12 in the vertical direction is flush with the chip 2 during the manufacturing process. In this case, in order to allow part of the metal bump structure 12 to be exposed so as to facilitate connection with the outside, a hole can be made at a preset position of the package 3 above the metal bump structure 12. The metal bump structure 12 is exposed by making the hole.

[0068] Of course, in some other possible implementations, the height of the package 3 can also be controlled. For example, by designing the height of the package 3, some of the metal protrusion structure 12 can be exposed, while the chip 2 is fully packaged.

[0069] It is understood that the above-mentioned encapsulation body 3 formed above the metal substrate 11 and above the chip 2 may also include encapsulation body 3 on the side of the metal substrate 11, so that the metal substrate 11 can be encapsulated laterally by the encapsulation body 3, preventing dust, moisture and other substances from entering the encapsulation from the side and improving the stability of the encapsulation body.

[0070] like Figure 8 As shown, Figure 8 for Figure 7The diagram illustrates the subsequent steps in the fabrication process of the metal substrate 1 after molding the chip 2. The fabrication method of the package structure further includes: opening a first through-hole 31 on the top surface of the package 3, and filling the first through-hole 31 with a first metal, so that the metal protrusion structure 12 can be connected to an external device through the first metal filling the first through-hole 31. The first through-hole 31 can be laser-drilled to expose the metal protrusion structure 12. The first metal filling the first through-hole 31 facilitates the connection of the metal protrusion structure 12 to an external device. For example, the device can be an auxiliary heat sink, and the metal protrusion structure 12 can be connected to the auxiliary heat sink through the first metal filling the first through-hole 31, thereby achieving heat dissipation of the bottom metal substrate 11 of the package structure and the auxiliary heat sink on the top of the package 3. Alternatively, the device can be an auxiliary shielding component, and the metal protrusion structure 12 can be connected to the auxiliary shielding component through the first metal filling the first through-hole 31, thus forming a shield above the chip 2, forming a shielding layer composed of the metal substrate 11, the metal protrusion structure 12, and the auxiliary shielding component, improving the electromagnetic shielding effect.

[0071] In some possible implementations, a second through-hole 32 is formed on the top surface of the package 3, and the second through-hole 32 is filled with a second metal to connect the chip 2 to external devices. The second through-hole 32 can be laser-drilled with reference to the first through-hole 31. There are multiple second through-holes 32, each corresponding to a ground interface, signal interface, and power interface of the chip 2. That is, at least some of the second through-holes 32 are used to connect to the ground interface of the chip 2, at least some are used to connect to the signal interface of the chip 2, and at least some are used to connect to the power interface of the chip 2. The second metal filling the second through-hole 32 enables the connection of the chip 2's ground interface, signal interface, and power interface to external devices or circuits. For example, a device can be directly mounted to the chip 2 through the second metal filling the second through-hole 32. The device can be a resistor, capacitor, or another chip.

[0072] like Figure 9 As shown, Figure 9 for Figure 8 The diagram illustrates the subsequent fabrication process after the opening step is completed. A redistribution layer 4 is provided on the top surface of the package 3. The first ground wire 41A of the redistribution layer 4 is connected to the metal protrusion structure 12 through the first metal filled in the first through hole 31. The second ground wire 41B, signal wire 42 and power wire of the redistribution layer 4 are connected to the ground electrode, signal electrode and power electrode of the chip 2 through the second metal filled in the corresponding second through holes, respectively.

[0073] The redistribution layer 4 is located on the top surface of the package 3. With the top surface of the package 3 as the base, after the chip 2 and the metal substrate 1 are encapsulated, the top surface of the package 3 needs to be polished flat. An insulating resin is then laminated or coated on the entire top surface of the polished package 3 to provide an insulating base for the redistribution layer 4. The location of the wiring is opened by photolithography, and copper is deposited and electroplated in the opened area to form copper wiring and pads. This copper wiring is the redistribution layer 4 on the top surface of the package 3. After the redistribution layer 4 is completed, an insulating layer can be covered on top. Of course, it is necessary to open windows to expose copper at the locations of the ball-planting and interconnection pads so that the redistribution layer 4 can be electrically connected to external electrical components. To facilitate the connection between the first ground line 41A of the redistribution layer 4 and the metal bump structure 12, a first through-hole 31 is formed at a predetermined position on the top surface of the package 3. The first through-hole 31 can be laser-drilled to expose the metal bump structure 12. A first metal is filled in the first through-hole 31 to connect the metal bump structure 12 and the first ground line 41A of the redistribution layer 4, thereby connecting the redistribution layer 4 to the metal substrate 11 through the metal bump structure 12 and achieving grounding of the redistribution layer 4. In addition, the heat generated by the chip 2 can be dissipated through the metal substrate 11 and conducted to the redistribution layer 4 through the metal bump structure 12 to achieve auxiliary heat dissipation, thereby further improving the heat dissipation capacity.

[0074] It is understandable that the first metal filling the first through hole 31 can be electroplated and integrally formed with the redistribution layer 4 simultaneously, or the first metal filling the first through hole 31 can be distributed and formed with the redistribution layer 4.

[0075] Furthermore, by opening multiple second vias 32 on the package 3 above the front side of the chip 2 and filling the second vias 32 with a second metal, the electrodes of the chip 2 can be led upward to the top redistribution layer 4, completing the vertical interconnection and fan-out of signals, power, and ground, saving bottom-layer wiring space; at the same time, the top redistribution layer 4 can also serve as an electromagnetic shield and auxiliary heat dissipation structure, adapting to high-density pins and chip 2 stacking integration.

[0076] It is understood that the second metal filled in the second through hole 32 can be set with reference to the first metal filled in the first through hole 31. That is, the second metal filled in the second through hole 32 can be electroplated and integrally formed with the redistribution layer 4 at the same time, or the second metal filled in the second through hole 32 can be distributed and formed with the redistribution layer 4.

[0077] It is understood that the redistribution layer 4 of the above-mentioned packaging structure can be rearranged and generated on a single packaging structure, or it can be generated on the top surface of the main metal plate 6 after the main metal plate 6 is molded and before the single packaging structure is formed, by generating the redistribution layer 4 corresponding to each packaging structure according to a preset route, and then cutting the main metal plate 6 to form multiple packaging structures with redistribution layers 4.

[0078] In some specific embodiments, a metal substrate 1 is first prepared. The main metal plate 6 is etched into multiple electrically isolated sub-regions 7. A metal substrate 11 is etched within each sub-region 7, and a metal protrusion structure 12 is electroplated at a predetermined position on the metal substrate 11, thereby forming multiple metal substrates 1 on the main metal plate 6. After the metal substrate 1 is prepared, a chip 2 is mounted on each metal substrate 1. That is, the back side of each chip 2 can be attached to the corresponding chip mounting area 13 using thermally conductive adhesive 5, thus completing the chip 2 mounting on the metal substrate 1. The metal substrate 1 after chip 2 mounting is encapsulated. This can be done using a panel-level encapsulation process or a dry film encapsulation process. That is, encapsulation is performed on the sides of each metal substrate 1, above the metal substrate 1, and above the chip 2, forming an encapsulation covering the sides of the metal substrate 1, above the metal substrate 1, and above the chip 2. After completing the molding process, a redistribution layer 4 is prepared at the corresponding package body 3. During the preparation of the redistribution layer 4, a first via 31 and a second via 32 need to be laser-drilled in the package body 3 to expose the electrodes corresponding to the metal protrusion structure 12 and the chip 2. Then, a redistribution layer 4 corresponding to each package structure is generated on the top surface of the package body 3 according to a preset route. During the preparation of the redistribution layer 4, a first metal is filled in the first via 31 and a second metal is filled in the second via 32 so that the first ground line 41A in the redistribution layer 4 is connected to the metal protrusion structure 12, the second ground line 41B and the ground electrode of the chip 2. The signal line 42 and the power line of the redistribution layer 4 are connected to the signal electrode and the power electrode of the chip 2, respectively. After the redistribution layer 4 is completed, the main metal plate 6 after molding is laser-cut to form multiple package structures with redistribution layers 4.

[0079] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0080] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0081] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A packaging structure, characterized in that, include: A metal substrate includes an integrally formed metal substrate and a metal protrusion structure, wherein at least two chip mounting areas are provided on the metal substrate, and the metal protrusion structure is disposed between two adjacent chip mounting areas; A chip is mounted in the chip mounting area; and A package covering the metal substrate and the chip, wherein at least a portion of the metal protrusion structure is configured to communicate with the outside through the package.

2. The packaging structure according to claim 1, characterized in that, The thickness D of the metal substrate satisfies D≥80um.

3. The packaging structure according to claim 1, characterized in that, The metal protrusion structure is constructed as a metal retaining wall; or The metal protrusion structure is constructed as a plurality of metal pillars spaced apart along a first direction.

4. The packaging structure according to claim 1, characterized in that, The top surface of the package is provided with a first through hole communicating with the metal protrusion structure, and a plurality of second through holes communicating with the chip electrodes.

5. The packaging structure according to claim 4, characterized in that, The packaging structure further includes a redistribution layer located on the top surface of the package. The first ground wire in the redistribution layer is connected to the metal protrusion structure through the first metal filling the first through hole. The second ground line and signal line in the redistribution layer are connected to the ground electrode and signal electrode of the chip through the second metal filled in the corresponding second via.

6. The packaging structure according to claim 5, characterized in that, The signal lines of the redistribution layer are provided with bumps, which are used to form the I / O interface of the chip.

7. The packaging structure according to claim 5, characterized in that, The first grounding wire and the second grounding wire are connected to each other.

8. A method for preparing a packaging structure, characterized in that, include: A metal substrate is prepared, wherein the metal substrate includes a metal substrate and a metal bump structure, the metal substrate has at least two chip mounting regions, and the metal bump structure is disposed between two adjacent chip mounting regions; The chip is mounted in the chip mounting area; An encapsulation is covered over the metal substrate and the chip, and at least a portion of the metal protrusion structure is configured to connect to the outside through the encapsulation.

9. The method for preparing the packaging structure according to claim 8, characterized in that, The preparation of the metal substrate includes: Provide the main metal plate; The main metal plate is etched into multiple sub-regions; A metal substrate is formed by etching in each sub-region and by electroplating at predetermined locations on the metal substrate to form a metal protrusion structure, thereby forming a metal substrate.

10. The method for preparing the packaging structure according to claim 8, characterized in that, The method further includes: A first through hole is made on the top surface of the package. The first metal connection structure is filled into the first through hole; A second through hole is made on the top surface of the package. The chip is connected by filling the second through hole with a second metal.

11. The method for preparing the packaging structure according to claim 10, characterized in that, The method further includes: A redistribution layer is provided on the top surface of the package. The first ground wire of the redistribution layer is connected to the metal protrusion structure through the first metal in the first through hole; The second ground line and signal line of the redistribution layer are connected to the ground electrode and signal electrode of the chip respectively through the second metal in the corresponding second via.

12. The method for preparing the packaging structure according to claim 9, characterized in that, The encapsulation covering the metal substrate and the chip includes: The main metal plate after the chip is mounted is then encapsulated in plastic. Cut the molded body along a preset trajectory to form multiple encapsulation structures.

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