Chip-level all-solid-state unidirectional heat rectifying heat dissipation architecture and preparation method thereof

Abstract

The application discloses a kind of chip-level all-solid-state unidirectional heat rectification heat dissipation framework and preparation method thereof, belong to super high power chip solid-state heat management field.The heat dissipation framework includes three functional layers of atomic level direct surface contact in turn layering and along the vertical direction of chip heat emitting surface: thermoelectric active heat pumping layer, anisotropic phase change heat storage layer and super high thermal conductivity uniform heating layer;Limit interface thermal resistance control is realized by atomic level direct surface contact between three functional layers.The application can realize heat self-chip upward unidirectional orderly transport by vertically constructing three all-solid-state functional layers including thermoelectric active heat pumping layer, anisotropic phase change heat storage layer and super high thermal conductivity uniform heating layer on chip upper surface, fundamentally eliminates heat bidirectional backflow loss problem in traditional double-sided parallel heat dissipation framework.

Description

Technical Field

[0001] This invention relates to the field of chip thermal management technology, and more specifically to a chip-level all-solid-state unidirectional thermal rectification heat dissipation architecture and its fabrication method. In particular, it relates to an all-solid-state chip heat dissipation architecture based on the unidirectional thermal rectification effect, which adopts a vertically cascaded three-level functional layer of thermoelectric-phase change-heat homogenization and related fabrication methods. Background Technology

[0002] With the exponential increase in computing power for large-scale AI models, the local heat flux density of chips has exceeded 1000W / cm². However, existing heat dissipation methods all have the following drawbacks:

[0003] 1. Air cooling has a heat dissipation capacity that is limited by the physical upper limit of the thermal conductivity of air, and cannot effectively suppress instantaneous kilowatt-level heat spikes; 2. Liquid cooling relies on circulation pipelines, coolant and pumping systems. Long-term operation may lead to reliability issues such as leakage, electrochemical corrosion and low-temperature freezing blockage. In addition, it has poor compatibility with standard CMOS wafer processes. 3. Single phase change heat dissipation: Single phase change material layers are mostly ultra-thin thermal pads, which do not have independent large-capacity heat storage capacity. Under continuous high power conditions, there is a problem of energy storage saturation failure. 4. Thermoelectric-phase change composite heat dissipation: This method usually uses heat dissipation units arranged on both sides of the chip and a horizontally split parallel heat path topology, which has the fundamental defect of bidirectional heat return. In addition, existing composite heat dissipation solutions mostly use discrete block thermoelectric pillars, which cannot achieve uniform cooling across the entire chip area. Furthermore, discrete block thermoelectric coolers have the problem of heat accumulation at the hot end, and are prone to cooling failure without a large-capacity thermal buffer layer. In addition, the current reliance on mechanical assembly connections between functional layers easily introduces a large amount of additional thermal resistance, making it difficult to achieve wafer-level integrated mass production.

[0004] Therefore, overcoming the above-mentioned defects is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above problems, this invention innovatively proposes a chip-level all-solid-state unidirectional thermal rectification heat dissipation architecture and its fabrication method, aiming to provide a single-sided vertical three-level functional layer cascaded heat dissipation architecture based on the unidirectional thermal rectification effect.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, embodiments of the present invention provide a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture, comprising three functional layers stacked sequentially along the vertical direction of the chip's heat-generating surface and in direct atomic-level surface contact: The first stage, a thermoelectric active pumping layer, is used to actively pump chip heat upward in the vertical direction based on the Peltier effect using a highly oriented Bi2Te3-based micron array thin film. The second stage, an anisotropic phase change thermal storage layer, is used to construct directional phonon transport channels using vertically oriented reduced graphene oxide aerogel composite phase change materials, suppressing heat backflow downwards and simultaneously performing phase change thermal storage. The third level, an ultra-high thermal conductivity heat dissipation layer, is used to unidirectionally dissipate the received heat to the external environment based on the single-crystal diamond-graphene composite structure.

[0007] The three functional layers work together to construct a global irreversible unidirectional solid-state heat flow field pointing from the chip to the external environment, thereby achieving a unidirectional thermal rectification effect.

[0008] Preferably, the highly oriented Bi2Te3-based micron array film includes thermoelectric arms with alternating N-type Se-doped Bi2Te3 films and P-type SbBi0.5Sb1.5Te3 films, wherein the thermoelectric arms fully cover the heating surface of the chip.

[0009] Preferably, electrodes are disposed above and below the thermoelectric arm for connection to a temperature control system; the temperature control system is used to perform graded control of the thermoelectric active pump heat layer according to the real-time temperature of the chip, the steps of which include: When the real-time temperature of the chip is lower than the first threshold, the thermoelectric active pump heat layer is de-energized, and passive heat dissipation is only achieved by the anisotropic phase change heat storage layer and the ultra-high thermal conductivity heat dissipation layer. When the real-time temperature of the chip is between the first threshold and the second threshold, the operating current of the thermoelectric active pump thermal layer increases linearly with temperature; the second threshold is greater than the first threshold. When the real-time temperature of the chip reaches or exceeds the second threshold, the thermoelectric active pump heat layer operates at rated full load, and the phase change heat storage layer releases its heat storage capacity simultaneously.

[0010] Preferably, the temperature control system has a built-in temperature prediction model for predicting future temperatures based on the chip's real-time temperature sequence. When the future temperature reaches or exceeds a second threshold, the thermoelectric active pump heat layer operates at its rated full load, and the phase change heat storage layer releases its heat storage capacity simultaneously.

[0011] Preferably, the vertically oriented reduced graphene oxide aerogel composite phase change material is a mixed cured product of modified paraffin and vertically oriented reduced graphene oxide aerogel, wherein the modified paraffin and the vertically oriented reduced graphene oxide aerogel are bonded by intermolecular hydrogen bonds.

[0012] Preferably, the single-crystal diamond-graphene composite structure uses MPCVD single-crystal diamond sheets as a substrate, with a vertically oriented graphene film hot-pressed onto the surface.

[0013] Secondly, embodiments of the present invention provide a method for fabricating a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture, the steps of which include: S1: Deposit an insulating layer on the top surface of the chip stack; S2: Deposit a patterned bottom electrode on the insulating layer; S3: The N-type and P-type thermoelectric thin films are alternately deposited using the PLD method, and in-situ annealing and secondary annealing are performed during and after the deposition process to form a thermoelectric arm array. S4: Deposit a top-layer series electrode above the thermoelectric arm array to achieve series connection of the thermoelectric arms; S5: Build a frame above the thermoelectric active pump heat layer, vacuum inject the mixed system of molten phase change material and vertically oriented reduced graphene oxide aerogel into the frame, cool and solidify it and then seal it to form an anisotropic phase change heat storage layer. S6: The ultra-high thermal conductivity heat spreader is hot-pressed to the top surface of the anisotropic phase change heat storage layer through a thermally conductive adhesive layer to form an atomically close contact interface.

[0014] Preferably, the vertically oriented reduced graphene oxide aerogel is prepared by the following steps: The graphene oxide dispersion was placed in a liquid nitrogen bath and frozen vertically. After complete freezing, it was freeze-dried under vacuum to obtain vertically oriented graphene oxide aerogel. The vertically oriented graphene oxide aerogel was placed in a hydrothermal reactor, and a reducing agent was added for chemical reduction to obtain vertically oriented reduced graphene oxide aerogel. The vertically oriented reduced graphene oxide aerogel was immersed in an alkaline solution for hydroxylation treatment to obtain hydroxylated vertically oriented reduced graphene oxide aerogel.

[0015] Preferably, the ultra-high thermal conductivity heat spreader is prepared by the following steps: Single-crystal diamond wafers were homoepitaxially grown on seed crystals using the MPCVD method. A vertically oriented graphene film was grown on the surface of the single-crystal diamond sheet using the ECVD method to obtain a composite heat exchanger.

[0016] This invention provides a chip-level all-solid-state unidirectional thermal rectification heat dissipation architecture and its fabrication method. The heat dissipation architecture is completely free of fluid channels, liquid cooling media, and fluid pumping circulation components, making it a 100% all-solid-state heat dissipation architecture. The three functional layers work together to construct a globally unique irreversible unidirectional vertical series solid-state thermal path. Relying on the unidirectional thermal rectification effect, heat is transported unidirectionally and orderly from the chip upwards without any heat loss due to downward backflow.

[0017] Compared with the prior art, the beneficial effects of this application include at least the following: 1. Construct a 100% all-solid-state, single-sided vertical three-level functional layer cascaded heat dissipation architecture, with no fluid, no pumping, zero leakage and corrosion risk, which can completely avoid all fluid sealing-related patent barriers of liquid cooling technology. 2. Provides a two-step annealed highly oriented Bi2Te3-based micron array thermoelectric thin film to achieve active and uniform heat pumping across the entire heating surface of the chip; 3. Based on hydroxylated vertically oriented graphene aerogel composite phase change material, a solid reverse heat flow barrier is constructed to achieve synergistic optimization of ultra-high latent heat storage and anisotropic thermal conductivity; specifically, its vertical orientation design and the unidirectional heat pumping direction of the thermoelectric active pumping layer work together to achieve unidirectional heat transport. 4. Wafer-level in-situ layer-by-layer integration fabrication process, with in-situ growth throughout the entire process, compatible with CMOS production lines, significantly improves packaging yield, and enables integrated manufacturing of heat dissipation structure and chip; and the total thermal resistance of the three-level atomic bonding interface is ≤0.2K / W, which is more than 65% lower than the existing mechanical assembly structure.

[0018] In addition, this application proposes a heat transfer theory of "unidirectional thermal rectification effect" and constructs a complete mathematical model of solid-state irreversible series heat flow, thereby fundamentally helping to solve the problem of heat return loss in existing parallel split architecture.

[0019] This invention is applicable to long-term dynamic thermal management scenarios for AI training chips, graphics processors, and 3D stacked chips with ultra-high heat flux density of 1000W / cm². Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture provided in an embodiment of the present invention; Figure 2 This is a top view of the N / P alternating micrometer thermoelectric arm array provided in an embodiment of the present invention; Figure 3 The temperature-current variation curve is provided in the three-level control system of this invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] This invention discloses a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture and its fabrication method. The architecture includes three vertically stacked all-solid-state functional layers: thermoelectric, phase change, and heat homogenization. The thermoelectric active heat pumping layer utilizes the Peltier effect to actively pump heat upwards from the chip. The vertically oriented graphene framework in the anisotropic phase change heat storage layer constructs directional phonon transport channels, with a thermal conductivity in the vertical direction much greater than that in the lateral and reverse directions, suppressing heat backflow. The top ultra-high thermal conductivity heat homogenization layer dissipates heat unidirectionally to the external environment. All three layers are indispensable and work together to construct a globally irreversible unidirectional solid-state heat flow field.

[0024] The following is a description through specific embodiments.

[0025] Example 1: Unlike existing chips with dual-sided heat dissipation units and built-in microfluidic parallel heat dissipation architectures, this invention only sets three levels of all-solid-state functional layers sequentially along the vertical direction on the chip's heat-generating surface, and these three levels of all-solid-state functional layers are in direct atomic-level surface contact. For example... Figure 1 As shown.

[0026] In some implementations, a thermoelectric active heat pumping layer is used to actively pump chip heat upwards in the vertical direction based on the Peltier effect using a highly oriented Bi₂Te₃-based microarray thin film; wherein, the highly oriented Bi₂Te₃-based microarray thin film includes thermoelectric arms with alternating N-type Se-doped Bi₂Te₃ thin films and P-type Sb-doped Bi₀.₅Sb₁.₅Te₃ thin films, exemplarily, such as... Figure 2 As shown, the thermoelectric arms are arranged in a 200μm × 200μm array with an array spacing of 100μm and a film thickness of 10~100μm, fully covering the chip's heating surface to achieve no cooling dead zones. In this embodiment, the carrier mobility is ≥130cm²V. - ¹s - ¹, The average ZT at room temperature is ≥1.43.

[0027] In some preferred embodiments, electrodes are disposed above and below the thermoelectric arm for connection to a temperature control system; the temperature control system is used to perform graded control on the thermoelectric active pumping heat layer according to the real-time temperature of the chip. In this embodiment, a millisecond-level micro thermocouple is implanted inside the chip and integrated with the temperature control system in a single package to collect the chip temperature, with a response time of <10ms.

[0028] Furthermore, such as Figure 3 As shown, the hierarchical control steps include: When the real-time temperature of the chip is lower than the first threshold, the thermoelectric active pump heat layer is de-energized, and passive heat dissipation is only achieved by the anisotropic phase change heat storage layer and the ultra-high thermal conductivity heat dissipation layer. When the real-time temperature of the chip is between the first threshold and the second threshold, the operating current of the thermoelectric active pump thermal layer increases linearly with temperature, with a rated current of 5A. When the real-time temperature of the chip reaches or exceeds the second threshold, the thermoelectric active pump heat layer operates at the rated full load, and the phase change heat storage layer releases its heat storage capacity to reduce the peak; when the temperature drops below the first threshold, it automatically switches back to the first level.

[0029] The second threshold is greater than the first threshold; preferably, the first threshold is 65°C and the second threshold is 80°C.

[0030] Furthermore, in some optional implementations, the temperature control system incorporates a temperature prediction model based on chip computing power time-series data, preferably a long short-term memory neural network architecture, to predict future temperatures based on the chip's real-time temperature sequence and anticipate heat flow impacts in advance. When the future temperature reaches or exceeds a second threshold, the thermoelectric active pump heat layer operates at its rated full load, and the phase change heat storage layer simultaneously releases its heat storage capacity.

[0031] The intelligent control process in this invention can effectively improve the chip temperature drop rate. Comparative data from some experiments are as follows: No intelligent control: peak temperature 87.5℃, overshoot 22.5℃, settling time 280ms; The solution of this invention has the following characteristics: peak temperature of 73.2℃, overshoot of 8.2℃, settling time of 120ms, peak temperature reduction of 16.3%, and overshoot reduction of 63.6%. Therefore, this application can significantly reduce settling time and overshoot, thereby improving temperature drop efficiency.

[0032] In some implementations, an anisotropic phase change thermal storage layer is used to construct directional phonon transport channels using a vertically oriented reduced graphene oxide aerogel composite phase change material, suppressing downward heat recirculation and simultaneously performing phase change thermal storage. The vertically oriented reduced graphene oxide aerogel composite phase change material is a mixed cured product of modified paraffin and vertically oriented reduced graphene oxide aerogel, with the modified paraffin and the vertically oriented reduced graphene oxide aerogel bonded by intermolecular hydrogen bonds to compensate for latent heat loss during phase change. Further, the mass ratio of modified paraffin to the vertically oriented reduced graphene oxide aerogel is 6:4 to 9:1, preferably 8:2. At this ratio, the phase change temperature is 60°C, the latent heat of phase change is 320 J / g, the vertical thermal conductivity is 789 W / (m·K), and the thermal rectification ratio is ≥2.6; the layer thickness is 200 μm, and the leakage after 3600 melt-solidification thermal cycles is <0.3 wt%. As a preferred option, the vertically oriented reduced graphene oxide aerogel can be replaced with a vertically oriented boron nitride aerogel, while still forming an 8:2 hydrogen bond composite with the modified paraffin. In this case, the thermal rectification ratio is ≥2.0, the temperature resistance is improved, and it is suitable for military-grade high-temperature computing chips, while the rest of the structure remains unchanged.

[0033] In some implementations, an ultra-high thermal conductivity vapor chamber is used to unidirectionally dissipate received heat to the external environment based on a single-crystal diamond-graphene composite structure. The single-crystal diamond-graphene composite structure uses an MPCVD single-crystal diamond sheet as a substrate with a thermal conductivity ≥2000 W / (m·K). A vertically oriented graphene film is hot-pressed onto the surface, and the bottom surface is atomically hot-pressed to the top surface of the phase change layer using 5μm nano-silver thermally conductive adhesive at 80°C and 0.5MPa. In an optional embodiment, to reduce costs, the vapor chamber is replaced with a 1mm single-crystal silicon carbide sheet, with a vertically oriented graphene film grown by ECVD, and the substrate has a thermal conductivity ≥800 W / (m·K). m - ¹, the remaining thermoelectric and phase change layer parameters are completely consistent with those of Example 1; adapted to low-to-mid-range cost-sensitive GPU computing chips.

[0034] In this embodiment, the three functional layers are in direct surface contact with each other, with a total thickness of 450μm and a total interface thermal resistance of ≤0.2K / W. By collaboratively constructing a global irreversible unidirectional solid-state heat flow field pointing from the chip to the external environment, a unidirectional thermal rectification effect can be achieved.

[0035] Example 2: This invention further provides a method for fabricating a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture, the steps of which include: S1: Using a chip stack as a substrate, an insulating layer is deposited on its top surface. For example, a 1μm Si3N4 insulating layer is deposited in situ using PECVD as the substrate for thermoelectric thin film growth. Deposition parameters include: deposition temperature 250~300℃, substrate temperature 300℃, RF power 200W, reactant gas flow rate of SiH4 20sccm, NH3 flow rate of 10sccm, and N2 flow rate of 100sccm, operating pressure of 50Pa, and deposition time of 30min. The surface roughness Ra of the deposited insulating layer is ≤0.5nm to meet the requirements of subsequent thin film growth.

[0036] S2: Deposit a patterned bottom electrode on the insulating layer; exemplary, a 2μm high-purity Cu bottom electrode is deposited by magnetron sputtering, with the following sputtering parameters: sputtering power 100~200W, preferably 150W, argon pressure 0.3~0.6Pa, preferably 0.05Pa, Cu target purity 99.999%, and background vacuum 5×10⁻⁶. -4 Pa, working gas Ar flow rate 30 sccm, deposition rate 0.5 nm / s.

[0037] After deposition, the Cu layer is patterned into an array of electrodes using a standard photolithography process. The electrode size is 300μm×300μm with a spacing of 100μm.

[0038] S3: This application employs the PLD method to alternately deposit N-type and P-type thermoelectric thin films. By combining the in-situ simultaneous heat preservation and vacuum secondary annealing coupling process of PLD deposition, the thermoelectric figure of merit of the Bi2Te3 thin film can be significantly improved. In some embodiments, N-type thin film target: Se-doped Bi2Te3 target, Se doping molar ratio 5%, target diameter 50 mm, purity 99.99%; P-type thin film target: Sb-doped Bi0.5Sb1.5Te3 target, purity 99.99%; Deposition parameters: KrF excimer laser, wavelength 248nm, laser energy density 2~3J / cm², preferably 2.5J / cm², pulse frequency 10Hz, target-substrate distance 50mm, substrate temperature 250℃; Deposition sequence: N and P layers were deposited alternately, with a deposition time of 5 min per layer, a deposition rate of 0.1~0.5 nm / s, a single layer thickness of about 2 μm, and a total of 5 NP pairs were deposited, with a total thickness of 20 μm; Simultaneous in-situ annealing at 250℃ for 1 hour was performed during deposition under an Ar protective atmosphere. After deposition, the wafer was transferred to a vacuum annealing furnace for secondary annealing at 320~360℃. Annealing parameters: Vacuum degree ≤1×10⁻⁶ - ³Pa, preferably 8×10 -4Pa was used to enhance the preferred crystal orientation of the thin film (00l), and the temperature was increased to 340°C at a rate of 5°C / min, held for 50 min, and then cooled to room temperature in the furnace to obtain a thermoelectric arm array with full chip coverage.

[0039] S4: Sputter and deposit a flat, unmodified Cu top-layer series electrode above the thermoelectric arm array to achieve series connection of the thermoelectric arms; Preferably, after the thermoelectric active pump thermal layer is fabricated, the following performance tests are performed sequentially: The Seebeck coefficients of N-type thin films and P-type thin films were determined using a Seebeck coefficient tester. The conductivity of N-type and P-type thin films was determined using the four-probe method. The thermal conductivity of N-type and P-type thin films was determined using the laser flare method. The average ZT values ​​of room temperature N-type and P-type films were calculated.

[0040] S5: Further, a 200μm ultrathin frame is built above the thermoelectric active pump heat layer. The frame and the thermoelectric active pump heat layer are sealed with epoxy resin. The molten phase change material, i.e., the mixture of modified paraffin and vertically oriented reduced graphene oxide aerogel, is then vacuum-injected into the frame at 80°C. The injection parameters are preferably a vacuum degree of 0.1MPa and an injection rate of 0.5mL / min. After cooling and solidification, the frame is sealed to form an anisotropic phase change heat storage layer.

[0041] In a preferred embodiment, the vertically oriented reduced graphene oxide aerogel is prepared by the following steps: Preparation of graphene oxide dispersion: 100 mg of graphene oxide powder was dispersed in 50 mL of deionized water and ultrasonically dispersed for 2 h until completely dispersed, with a concentration of 2 mg / mL; Vertical orientation treatment: The graphene oxide dispersion was placed in a liquid nitrogen bath and frozen vertically at a freezing rate of 1℃ / min until completely frozen. Then, it was freeze-dried under vacuum for 48h to obtain vertically oriented graphene oxide aerogel. Chemical reduction: The vertically oriented graphene oxide aerogel was placed in a hydrothermal reactor, and ascorbic acid reducing agent (graphene oxide:ascorbic acid mass ratio 1:2) was added for chemical reduction. The reaction was carried out at 90°C for 6 hours to obtain vertically oriented reduced graphene oxide aerogel. Hydroxylation treatment: Vertically oriented reduced graphene oxide aerogel was immersed in 0.1M NaOH solution and treated at 60℃ for 4h. It was then washed with deionized water until neutral and freeze-dried to obtain hydroxylated vertically oriented reduced graphene oxide aerogel.

[0042] In a preferred embodiment, the preparation steps of the hydrogen-bonded composite phase change material are as follows: Modified paraffin (melting point 60℃) and hydroxylated vertically oriented reduced graphene oxide aerogel were weighed at a mass ratio of 8:2. The paraffin wax was melted in an 80°C constant temperature oil bath, and then hydroxylated graphene aerogel was added. The mixture was magnetically stirred for 2 hours (500 rpm) to allow the molten paraffin wax to fully penetrate the three-dimensional channels of the aerogel, and to form intermolecular hydrogen bonds between the paraffin wax molecules and the hydroxylated graphene. The composite system was degassed in an 80℃ vacuum drying oven for 30 minutes to remove air bubbles trapped during the composite process.

[0043] In a preferred embodiment, the two are mixed in a ratio of 8:2, stirred at 80°C for 2 hours to form a hydrogen-bonded composite system, and vacuum-injected into the enclosure in a molten state. The phase change temperature range is 50~80°C. After 3600 melt-solidification thermal cycles, the leakage is <0.3wt%. The system is degassed to remove air bubbles, and after cooling and solidification, the sides are sealed with epoxy resin.

[0044] This embodiment solves the industry problem of leakage during hot and cold cycles of phase change materials by binding paraffin and graphene framework through intermolecular hydrogen bonds.

[0045] Preferably, after production is completed, the following performance tests are performed: The heating rate, phase transition temperature, and latent heat of phase transition were determined by differential scanning calorimetry (DSC). The thermal conductivity in the vertical and horizontal directions was determined using a thermal constant analyzer. Thermal cycling stability was tested using a thermal cycling test chamber: 3600 melt-solidification cycles were performed between 25 and 80°C, with each cycle lasting 60 minutes (30 minutes of heating up + 30 minutes of cooling down). The mass loss rate was measured after 3600 cycles.

[0046] S6: The ultra-high thermal conductivity heat spreader is hot-pressed to the top surface of the anisotropic phase change heat storage layer through a thermally conductive adhesive layer to form an atomically close contact interface.

[0047] In this embodiment, the ultra-high thermal conductivity heat spreader is prepared through the following steps: Single-crystal diamond wafers were homoepitaxially grown on high-temperature and high-pressure synthetic diamond seed crystals using MPCVD. The growth parameters were: microwave power 5kW, working pressure 15kPa, CH4 / H2 flow ratio 5%, substrate temperature 850℃, growth rate 5μm / h, and growth time 200h, resulting in single-crystal diamond wafers with a thickness of 1mm. The wafers were polished on both sides to a surface roughness Ra≤10nm and then laser-cut to chip-matching dimensions. Vertically oriented graphene films were grown on the surface of the single-crystal diamond wafer using the ECVD method. The growth parameters were: substrate temperature 750℃, CH4 flow rate 50 sccm, H2 flow rate 200 sccm, RF power 300W, and growth time 30 min. Three vertically oriented graphene films were grown (each layer grew for 10 min). The thickness of the vertically oriented graphene films was approximately 1 μm, and the vertical orientation degree was measured by Raman spectroscopy with an I2D / IG ratio ≥ 0.8. Finally, a composite heat sink was obtained.

[0048] Furthermore, the thermally conductive adhesive layer uses nano-silver thermally conductive adhesive. The nano-silver thermally conductive adhesive (silver particle size 50nm, solid content 70%) is uniformly coated on the bottom surface of the diamond-graphene composite heat exchanger plate with a coating thickness of 5μm. The heat exchanger plate coated with nano-silver thermally conductive adhesive is placed on the top surface of the phase change heat storage layer and hot-pressed at 80℃ and 0.5MPa pressure for 2h. After hot pressing, it is naturally cooled to room temperature, and the nano-silver thermally conductive adhesive is completely cured, forming an atomically close bonding interface.

[0049] After preparation, the following performance tests were performed sequentially: The thermal conductivity of the diamond matrix was determined using the laser flare method. The surface thermal reflection method was used to determine the interfacial thermal resistance of the heat exchanger-phase change layer and the total interfacial thermal resistance of the three functional layers (chip-thermoelectric active pumping heat layer, thermoelectric active pumping heat layer-phase change layer, phase change layer-heat exchanger).

[0050] In this embodiment, the layers are in direct atomic-level surface contact without any intermediate components, and the total interfacial thermal resistance is ≤0.2K / W.

[0051] To further optimize the above technical solution, this application constructs a corresponding heat transfer mathematical model to simulate the heat dissipation effect, and optimizes the parameters of the above all-solid-state unidirectional heat dissipation architecture based on the simulation results; wherein the heat transfer mathematical model includes: 1. The active pumping thermal coupling equation for thermoelectric thin films is applicable to the heat transfer description of micron-scale thin-film thermoelectric arrays;

[0052] In the formula, This indicates the pumping heat power per unit area of ​​the thermoelectric thin film. This represents the average Seebeck coefficient of the thin film. This indicates the operating DC current of the thermoelectric arm. This represents the average thermodynamic temperature of the thin film at both the hot and cold ends. This represents the equivalent thermal conductivity of a micron-thin film. Indicates the temperature difference between the hot and cold ends of the thermoelectric layer. Indicates the thickness of a single-layer thermoelectric thin film. This represents the equivalent resistance of a single N / P thermoelectric arm.

[0053] 2. Unidirectional thermal storage coupling equations for anisotropic phase change layers

[0054] in, This represents the overall density of hydrogen-bonded composite phase change materials. This indicates the specific heat capacity at constant pressure of the composite material. This represents the rate of change of temperature over time. Indicates the anisotropic thermal conductivity in a vertical orientation. Represents the spatial temperature gradient. Indicates the latent heat of phase transition. This indicates the rate of change of the liquid phase fraction.

[0055] 3. Cascaded Interface Thermal Resistance Optimization Model

[0056] In the formula, This represents the total interfacial thermal resistance of the three-layer series connection. This indicates the thermal resistance between the chip and the thermoelectric layer. This indicates the thermal resistance at the interface between the thermoelectric layer and the phase change layer. This indicates the thermal resistance between the phase change layer and the diamond heat exchanger.

[0057] Any content or technical means not mentioned in the embodiments of this invention can be obtained by referring to the prior art. This disclosure does not limit the scope of the invention and therefore will not be elaborated further.

[0058] Compared with existing technologies, the single-sided vertical three-level functional layer cascaded all-solid-state architecture in this application is fluid-free, pump-free, and leak-free; the two-step annealed PLD highly oriented Bi2Te3 film provides full coverage without blind spots; the vertically oriented rGO aerogel-paraffin hydrogen bond composite phase change material utilizes intermolecular hydrogen bonding to compensate for the latent heat loss of the phase change, with a latent heat ≥320J / g and a vertical thermal conductivity ≥780W / (m·K); the single-crystal diamond-graphene composite heat sink is integrated in situ with the thermoelectric and phase change three-layer wafer at the wafer level, with a substrate thermal conductivity ≥2000W / (m·K).

[0059] The invention is a 100% solid-state architecture, completely avoiding all technical barriers of the liquid cooling patent pool, and can be directly mass-produced at the wafer level.

[0060] The embodiments of the present invention have been described in detail above, and the principles and implementation methods of the present invention have been explained. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, computer software program products, or electronic devices, etc. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0061] It should be noted that the word "comprising" does not exclude the presence of components or steps not listed in the claims. The words "a" or "an" preceding a component do not exclude the presence of a plurality of such components. This invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer.

[0062] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0063] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture, characterized in that, This includes three functional layers stacked sequentially along the vertical direction of the chip's heat-generating surface and in direct atomic-level surface contact: The first stage, a thermoelectric active pumping layer, is used to actively pump chip heat upward in the vertical direction based on the Peltier effect using a highly oriented Bi2Te3-based micron array thin film. The second stage, an anisotropic phase change thermal storage layer, is used to construct directional phonon transport channels using vertically oriented reduced graphene oxide aerogel composite phase change materials, suppressing heat backflow downwards and simultaneously performing phase change thermal storage. The third level, an ultra-high thermal conductivity heat dissipation layer, is used to unidirectionally dissipate the received heat to the external environment based on the single-crystal diamond-graphene composite structure.

2. The chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 1, characterized in that, The highly oriented Bi2Te3-based micron array film includes thermoelectric arms with alternating N-type Se-doped Bi2Te3 films and P-type Sb-doped Bi0.5Sb1.5Te3 films, which fully cover the chip's heating surface.

3. The chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 2, characterized in that, Electrodes are provided above and below the thermoelectric arm for connection to the temperature control system; The temperature control system is used to perform graded control on the thermoelectric active pump heat layer based on the real-time temperature of the chip, and the steps include: When the real-time temperature of the chip is lower than the first threshold, the thermoelectric active pump heat layer is de-energized, and passive heat dissipation is only achieved by the anisotropic phase change heat storage layer and the ultra-high thermal conductivity heat dissipation layer. When the real-time temperature of the chip is between the first threshold and the second threshold, the operating current of the thermoelectric active pump thermal layer increases linearly with temperature; the second threshold is greater than the first threshold. When the real-time temperature of the chip reaches or exceeds the second threshold, the thermoelectric active pump heat layer operates at the rated full load, and the anisotropic phase change heat storage layer releases its heat storage capacity simultaneously.

4. The chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 1, characterized in that, The temperature control system has a built-in temperature prediction model to predict future temperatures based on the chip's real-time temperature sequence. When the future temperature reaches or exceeds a second threshold, the thermoelectric active pump heat layer operates at its rated full load, and the anisotropic phase change heat storage layer releases its heat storage capacity simultaneously.

5. The chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 1, characterized in that, The vertically oriented reduced graphene oxide aerogel composite phase change material is a mixed cured product of modified paraffin and vertically oriented reduced graphene oxide aerogel, wherein the modified paraffin and the vertically oriented reduced graphene oxide aerogel are bonded together by intermolecular hydrogen bonds.

6. The chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 1, characterized in that, The single-crystal diamond-graphene composite structure uses MPCVD single-crystal diamond sheets as a substrate, with a vertically oriented graphene film hot-pressed onto the surface.

7. A method for fabricating a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture, comprising the following steps: S1: Deposit an insulating layer on the top surface of the chip stack; S2: Deposit a patterned bottom electrode on the insulating layer; S3: The N-type and P-type thermoelectric thin films are alternately deposited using the PLD method, and in-situ annealing and secondary annealing are performed during and after the deposition process to form a thermoelectric arm array. S4: Deposit a top-layer series electrode above the thermoelectric arm array to achieve series connection of the thermoelectric arms; S5: Build a frame above the thermoelectric active pump heat layer, vacuum inject the mixed system of molten phase change material and vertically oriented reduced graphene oxide aerogel into the frame, cool and solidify it and then seal it to form an anisotropic phase change heat storage layer. S6: The ultra-high thermal conductivity heat spreader is hot-pressed to the top surface of the anisotropic phase change heat storage layer through a thermally conductive adhesive layer to form an atomically close contact interface.

8. The method for fabricating a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 7, characterized in that, The vertically oriented reduced graphene oxide aerogel is prepared through the following steps: The graphene oxide dispersion was placed in a liquid nitrogen bath and frozen vertically. After complete freezing, it was freeze-dried under vacuum to obtain vertically oriented graphene oxide aerogel. The vertically oriented graphene oxide aerogel was placed in a hydrothermal reactor, and a reducing agent was added for chemical reduction to obtain vertically oriented reduced graphene oxide aerogel. The vertically oriented reduced graphene oxide aerogel was immersed in an alkaline solution for hydroxylation treatment to obtain hydroxylated vertically oriented reduced graphene oxide aerogel.

9. The method for fabricating a chip-level all-solid-state unidirectional thermal rectification and heat dissipation architecture as described in claim 7, characterized in that, The ultra-high thermal conductivity heat spreader is prepared through the following steps: Single-crystal diamond wafers were homoepitaxially grown on seed crystals using the MPCVD method. A vertically oriented graphene film was grown on the surface of the single-crystal diamond sheet using the ECVD method to obtain a composite heat exchanger.

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