Chip heat spreader, electronic device, and method of manufacturing a chip heat spreader

Abstract

The application discloses a chip heat sink, an electronic device and a manufacturing method of the chip heat sink, and relates to the technical field of chip heat dissipation. The chip heat sink comprises a manifold, a plurality of fins and a baffle, a connecting surface of the manifold is provided with a cooling groove, the plurality of fins extend in a direction away from the manifold, heat dissipation spaces are formed between adjacent fins, the baffle is connected with the manifold and the fins respectively, the baffle is provided with a slit opposite to the cooling groove, the cooling groove is communicated with the heat dissipation spaces through the slit, the slit comprises a wide section and a narrow section, the wide section is arranged at a high-temperature area of a chip, and the opening size of the wide section is greater than that of the narrow section. The flow of the cooling liquid is distributed through the manifold, the contact area is increased through the fins, the heat exchange capacity of convection is improved, and the heat dissipation requirement of a high-power chip is met. In addition, the cooling liquid is distributed in different areas through the slit, the distribution of the cooling efficiency is more flexible and accurate, the high-temperature heat dissipation requirement is met through efficient cooling of the hotspot area of the chip, the temperature difference of the chip is reduced, the thermal stress is reduced, and the reliability of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a chip heat sink, an electronic device, and a method for manufacturing the chip heat sink. Background Technology

[0002] With the continuous improvement of chip computing power, the power density of chips has increased dramatically, and the heat flux density of local hot spots has exceeded 900W / cm². 2 Research indicates that high temperatures account for up to 55% of all electronic device failures. The heat dissipation efficiency of chips is crucial to the performance of electrical devices. If the heat from a chip cannot be dissipated in time, it can accumulate into hot spots, increasing internal thermal stress, leading to decreased chip performance and stability, and even failure. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art or related technologies.

[0004] The first aspect of this application proposes a chip heat sink, which includes: a manifold, multiple fins, and a baffle. The manifold has a cooling groove on its connecting surface. The multiple fins extend in a direction away from the manifold, and a heat dissipation space is formed between adjacent fins. The baffle is connected to the manifold and the fins respectively. The baffle has a slit opposite to the cooling groove. The cooling groove communicates with the heat dissipation space through the slit. The slit includes a wide section and a narrow section. The wide section is used to be located in the high-temperature area of ​​the chip, and the opening size of the wide section is larger than the opening size of the narrow section.

[0005] In some of the technical solutions provided in this application, the cooling tank includes: an inlet tank and an outlet tank. The inlet tank is used to connect to the inlet pipe, and the outlet tank is used to connect to the outlet pipe. The inlet tank and the outlet tank are connected through a heat dissipation space.

[0006] In some of the technical solutions provided in this application, the cooling tank extends along the first direction, and multiple water inlet tanks and multiple water outlet tanks are alternately arranged along the second direction, with the first direction and the second direction intersecting.

[0007] In some of the technical solutions provided in this application, there are multiple chips, and multiple wide segments are used to correspond one-to-one with each chip.

[0008] In some of the technical solutions provided in this application, multiple fins form multiple rows and columns, with adjacent rows of fins arranged in a staggered manner.

[0009] In some of the technical solutions provided in this application, the row spacing of multiple fins is the same, and the column spacing of multiple fins is the same.

[0010] In some of the technical solutions provided in this application, the two ends of the fins are respectively provided with sharp corners.

[0011] In some of the technical solutions provided in this application, the chip heat sink further includes: a heat dissipation substrate, which includes a stacked diamond layer, a titanium layer and a metal layer, the metal layer being connected to the end of the fin away from the manifold, and the diamond layer being used to connect the chip.

[0012] The second aspect of the technical solution of this application proposes an electronic device, which includes: a chip and any one of the above-mentioned chip heat sinks, wherein the chip heat sink is connected to the chip.

[0013] The third aspect of this application provides a method for manufacturing a chip heat sink, used to manufacture any of the aforementioned chip heat sinks, the method comprising: Multiple fins are fabricated on a heat dissipation substrate, and heat dissipation space is formed between adjacent fins; Manifolds are manufactured, and cooling grooves are engraved on the connecting surfaces of the manifolds. A baffle is manufactured, and slits are etched on the baffle. The slits include a wide section and a narrow section. The wide section is used to be located in the high-temperature region of the chip, and the opening size of the wide section is larger than that of the narrow section. Connect the manifold and the baffle. The baffle blocks part of the opening of the cooling tank, and the slit is opposite to the cooling tank. Connect the baffle and fins to allow the cooling slot to connect with the heat dissipation space through the slit.

[0014] Compared with related technologies, the present invention has at least the following beneficial effects: The coolant flow is distributed through a manifold, and the fins increase the contact area, improving convective heat transfer and meeting the heat dissipation requirements of high-power chips. Furthermore, the coolant is distributed in zones through slits, allowing for more flexible and precise distribution of cooling efficiency. This enables highly efficient cooling of hot spots on the chip, meeting high-temperature heat dissipation needs, reducing chip temperature differences, lowering thermal stress, and improving chip reliability. Attached Figure Description

[0015] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of some embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the structure of a chip heat sink according to one embodiment of this application; Figure 2 A schematic diagram of the structure of a chip according to one embodiment of this application; Figure 3 A schematic diagram of the structure of a baffle according to one embodiment of this application; Figure 4 for Figure 3 Liquid velocity distribution at different locations in the slit of the baffle; Figure 5 A diagram showing the relationship between slit velocity and heat transfer coefficient in one embodiment of this application is provided. Figure 6 A schematic diagram of the structure of a fin in one embodiment of this application; Figure 7 This is a schematic diagram illustrating a method for manufacturing a chip heat sink according to an embodiment of this application.

[0016] in, Figures 1 to 7 The correspondence between the reference numerals and component names in the attached drawings is as follows: 100. Manifold; 110. Cooling tank; 111. Inlet tank; 112. Outlet tank; 200. Fins; 210. Heat dissipation space; 220. Sharp corner; 300. Baffle; 310. Slit; 311. Wide section; 312. Narrow section; 400. Heat dissipation substrate; 410. Diamond layer; 420. Titanium layer; 430. Metal layer; 20. Chip; 21. Memory chip; 22. Logic chip; 23. High-temperature area. Detailed Implementation

[0017] To better understand the above technical solutions, the technical solutions of the embodiments of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0018] The first aspect of this application provides a chip heat sink, such as... Figure 1 , Figure 2 and Figure 3 As shown, the chip heat sink includes: a manifold 100, multiple fins 200 and a baffle 300. The connecting surface of the manifold 100 is provided with a cooling groove 110. The multiple fins 200 extend in a direction away from the manifold 100, and a heat dissipation space 210 is formed between adjacent fins 200. The baffle 300 is connected to the manifold 100 and the fins 200 respectively. The baffle 300 is provided with a slit 310 opposite to the cooling groove 110. The cooling groove 110 communicates with the heat dissipation space 210 through the slit 310. The slit 310 includes a wide section 311 and a narrow section 312. The wide section 311 is used to be located in the high temperature region 23 of the chip 20. The opening size of the wide section 311 is larger than the opening size of the narrow section 312.

[0019] In this embodiment, a chip heat sink is used to dissipate heat from the chip 20. The chip 20 can be a high-power, high-computing-power chip 20. The core of the chip 20 is usually concentrated in the central region inside the chip 20, which makes the center of the chip 20 a hot spot, while the temperature around it is lower, resulting in a large temperature difference. The central region of the chip 20 forms a high-temperature region 23, and the temperature of the high-temperature region 23 is higher than the normal temperature.

[0020] The bottom surface of the manifold 100 can be a connecting surface, and the connecting surface has a cooling groove 110 extending in a straight line, which is used to hold cooling water. Multiple fins 200 are spaced apart below the manifold 100. Each fin 200 extends vertically downwards in a direction away from the manifold 100. Adjacent fins 200 maintain a distance and form a heat dissipation space 210. The fins 200 increase the heat exchange area of ​​the coolant and improve the convective heat transfer capacity. A baffle 300 is provided between the manifold 100 and the fins 200. The manifold 100, fins 200, and baffle 300 are all made of copper. The upper and lower end faces of the baffle 300 are connected to the manifold 100 and the fins 200, respectively. A slit 310 is provided at the position opposite to the cooling tank 110 on the baffle 300. The extension direction of the slit 310 is the same as that of the cooling tank 110, so that the baffle 300 covers part of the opening of the cooling tank 110. The slit 310 connects the cooling tank 110 and the heat dissipation space 210, allowing cooling water to flow between the cooling tank 110 and the heat dissipation space 210. The manifold 100 is responsible for distributing the flow of the upper layer of coolant, making the flow of coolant more uniform. The fins 200 form the lower layer of cooling microchannels, and the slit 310 of the baffle 300 precisely distributes coolant to the cooling microchannels.

[0021] The opening size of slit 310 changes during its extension. Figure 3 In the diagram, D represents the opening size of slit 310. Slit 310 is divided into a wide segment 311 and a narrow segment 312 based on its opening size. For example, the opening size of the wide segment 311 is 0.6 mm to 0.8 mm, and the opening size of the narrow segment 312 is 0.05 mm to 0.15 mm. For instance, the opening size of the wide segment 311 is 0.7 mm, and the opening size of the narrow segment 312 is 0.1 mm. The chip heat sink adjusts the flow rate and quality of the upper coolant entering the lower microchannel by controlling the size of the slit 310, thereby configuring the heat dissipation capacity at different locations. The coolant flow cross-sectional area is larger at the wide segment 311. Figure 4 The horizontal axis represents the distance of the test point from the center point along the extension direction of the slit 310, and the vertical axis represents the cooling water velocity at the test point. The cooling water velocity is greater in the wider opening of the slit 310. Figure 5The horizontal axis represents the flow velocity in slit 310. A faster flow velocity results in a higher convective heat transfer coefficient. Slit 310 controls the coolant flow velocity by adjusting the width of its opening, allowing the chip heat sink to rationally allocate heat dissipation performance across different areas based on heat flux density. The high-temperature region 23, with its relatively high heat flux density, is contrasted with the wider opening of 311. Higher liquid flow velocities are provided at the hot spots of chip 20 to increase heat transfer capacity. Coolant flow velocities are lower in the relatively low-temperature regions to reduce the temperature difference of chip 20. Simulation experiments show that, with an overall coolant flow velocity of 1 L / min, the chip heat sink of this application, compared to traditional heat sinks, can control the maximum temperature of chip 20 below 95℃, and reduce the temperature difference of chip 20 from 18℃ to 11℃.

[0022] The coolant flow is distributed through the manifold 100, and the fins 200 increase the contact area, improving convective heat transfer capacity and meeting the heat dissipation requirements of the high-power chip 20. Furthermore, the coolant is distributed in zones through the slits 310, making the distribution of cooling efficiency more flexible and accurate. This allows for efficient cooling of hot spots in the chip 20, meeting high-temperature heat dissipation requirements, reducing temperature differences in the chip 20, reducing thermal stress, and improving the reliability of the chip 20.

[0023] In some embodiments provided in this application, such as Figure 1 As shown, the cooling tank 110 includes an inlet tank 111 and an outlet tank 112. The inlet tank 111 is used to connect the inlet water pipe, and the outlet tank 112 is used to connect the outlet water pipe. The inlet tank 111 and the outlet tank 112 are connected through the heat dissipation space 210.

[0024] In this embodiment, the inlet tank 111 collects the input coolant. After the coolant enters the inlet tank 111, it flows into the heat dissipation space 210 below through the slit 310, and then flows into the outlet tank 112 above through the slit 310. The outlet tank 112 collects the high-temperature coolant after heat exchange, forming a complete circulating water path to ensure continuous circulation and heat dissipation of the coolant.

[0025] In some embodiments provided in this application, such as Figure 1 As shown, the cooling tank 110 extends along the first direction, and multiple water inlet tanks 111 and multiple water outlet tanks 112 are alternately arranged along the second direction, with the first direction and the second direction intersecting.

[0026] In this embodiment, Figure 2In the diagram, the arrow at position X points to the first direction, and the arrow at position Y points to the second direction. The first and second directions can be perpendicular to each other. Cooling tanks 110 extend and are spaced apart in different directions, forming an array arrangement that expands the cooling coverage. Inlet tanks 111 and outlet tanks 112 are arranged alternately along the second direction, achieving multi-channel staggered liquid supply. The coolant forms reciprocating convection within the heat dissipation space 210, extending the heat exchange path of the coolant and improving the heat dissipation effect.

[0027] For example, there are 4 inlet tanks 111 and 3 outlet tanks 112.

[0028] In some embodiments provided in this application, such as Figure 2 As shown, there are multiple chips 20, and multiple wide segments 311 are used to correspond one-to-one with each chip 20.

[0029] In this embodiment, the heat-generating area of ​​any chip 20 is individually matched with the width 311 of the slit 310, so that each chip 20 can obtain sufficient coolant, which greatly improves the temperature uniformity of multiple chips 20 and avoids performance degradation and aging problems caused by excessive temperature difference between chips 20.

[0030] For example, chip 20 includes logic chip 22 and memory chip 21. There are two chips 20 and two wide segments 311. The two chips 20 are symmetrically arranged. The high temperature region 23 is located at the center of chip 20. The two wide segments 311 are symmetrically arranged.

[0031] In some embodiments provided in this application, such as Figure 6 As shown, multiple fins 200 form multiple rows and columns, with adjacent rows of fins 200 arranged in a staggered manner.

[0032] In this embodiment, the multi-row and multi-column arrangement of the fins 200 allows the heat dissipation space 210 to extend in different directions. The coolant flowing out of the inlet tank 111 can flow laterally to the bottom of the adjacent outlet tank 112 and enter the outlet tank 112 through the slit 310, thereby allowing the coolant to flow between adjacent cooling tanks 110. Furthermore, the staggered cross-shaped structure of the fins 200 forces the coolant to repeatedly change direction and continuously generate eddies during flow, continuously disrupting the fluid thermal boundary layer, significantly improving the convective heat transfer coefficient, extending the residence time of the coolant in the heat dissipation space 210, and fully absorbing the heat from the chip 20 conducted by the fins 200.

[0033] In some embodiments provided in this application, the row spacing of the plurality of fins 200 is the same, and the column spacing of the plurality of fins 200 is the same.

[0034] In this embodiment, the standardized, equally spaced array of fins 200 improves the dispersion and uniformity of the heat dissipation space 210, making the coolant distribution among the fins 200 more dispersed and uniform. Furthermore, the standardized array reduces the difficulty of processing and shaping the fins 200, resulting in better consistency in mold and etching processes, and lower mass production costs.

[0035] In some embodiments provided in this application, such as Figure 6 As shown, the two ends of the fin 200 are respectively provided with sharp corners 220.

[0036] In this embodiment, the pointed end 220 of the fin 200 reduces the resistance to the flow of cooling water, increases the flow velocity of the cooling water, and enhances the heat exchange effect. Furthermore, the tip of the pointed end 220 is located on the center line of the distance between the two adjacent fins 200 in the adjacent column, which improves the regularity of the microchannel.

[0037] In some embodiments provided in this application, such as Figure 1 As shown, the chip heat sink also includes a heat sink substrate 400, which includes a stacked diamond layer 410, a titanium layer 420 and a metal layer 430. The metal layer 430 is connected to the end of the fin 200 away from the manifold 100, and the diamond layer 410 is used to connect the chip 20.

[0038] In this embodiment, fins 200 are disposed on the top surface of a heat dissipation substrate 400, which provides a mounting and heat dissipation base for the fins 200. The heat dissipation substrate 400 is formed by stacking a diamond layer 410, a titanium layer 420, and a metal layer 430. The diamond layer 410 has a high thermal conductivity, enabling rapid lateral temperature equalization of the heat generated by the chip 20 and eliminating tiny hot spots on the surface of the chip 20. The titanium layer 420 has good toughness and solderability, serving as a transition layer to buffer the difference in thermal expansion coefficients between the diamond and metal layers 430, suppressing interlayer cracking and delamination under high-temperature conditions. The metal layer 430 can be a copper layer, which is stably connected to the fins 200, rapidly conducting heat from the substrate to the fins 200. This three-layer composite structure balances ultra-high thermal conductivity, structural strength, and thermal expansion matching.

[0039] A second aspect of this application provides an electronic device, which includes a chip 20 and any one of the chip heat sinks, wherein the chip heat sink is connected to the chip 20.

[0040] In this embodiment, the electronic device can be a high-computing-power three-dimensional integrated circuit. It should be noted that since the electronic device includes the chip heat sink provided in any of the above embodiments, it has all the beneficial technical effects of the chip heat sink. To avoid repetition, it will not be described in detail here.

[0041] A third aspect of this application provides a method for manufacturing a chip heat sink, used to manufacture any of the aforementioned chip heat sinks, such as... Figure 7 As shown, the manufacturing method includes: Step 1: Fabricate multiple fins on the heat dissipation substrate, forming heat dissipation spaces between adjacent fins; Step 2: Manifold manufacturing, with cooling grooves carved into the connecting surfaces of the manifold; Step 3: Fabricate a baffle and etch slits on the baffle. The slits include a wide section and a narrow section. The wide section is used to be located in the high-temperature area of ​​the chip, and the opening size of the wide section is larger than that of the narrow section. Step 4: Connect the manifold and the baffle. The baffle covers part of the opening of the cooling tank, and the slit is opposite to the cooling tank. Step 5: Connect the baffle and fins to allow the cooling slot to connect with the heat dissipation space through the slit.

[0042] In this embodiment, the operator manufactures the chip heat sink according to the design scheme. Manufacturing step 1 specifically includes: sputtering a titanium layer onto a diamond layer; the titanium layer reacts with the diamond layer to form titanium carbide, providing extremely strong adhesion. The operator then grows a copper layer in situ on the titanium layer, serving as a seed layer for subsequent electroplating of fins (i.e., copper pillars) and protecting the titanium layer from oxidation. The operator spin-coates photoresist onto the copper layer, exposes the fin fabrication area through exposure and development, and sequentially electroplats fins and solder in this area before removing the photoresist, thus fabricating multiple spacer fins on the heat sink substrate, creating heat dissipation spaces between adjacent fins.

[0043] The workers also manufacture the manifolds, using a CNC engraving machine to carve cooling grooves onto the manifold connection surfaces and applying solder to these surfaces. They also etch slit structures into the baffle, consisting of connected wide and narrow sections; the wide sections are used to locate high-temperature areas on the chip. Steps 1, 2, and 3 can be performed simultaneously or sequentially.

[0044] Workers weld the baffle to the connection surface of the manifold, with the baffle partially blocking the opening of the cooling trough, and the slit facing the cooling trough. Then, the baffle and fins are welded to allow the cooling trough to connect with the heat dissipation space through the slit.

[0045] The coolant flow is distributed through a manifold, and the fins increase the contact area, improving convective heat transfer and meeting the heat dissipation requirements of high-power chips. Furthermore, the coolant is distributed in zones through slits, allowing for more flexible and precise distribution of cooling efficiency. This enables highly efficient cooling of hot spots on the chip, meeting high-temperature heat dissipation needs, reducing chip temperature differences, lowering thermal stress, and improving chip reliability.

[0046] The design steps for a chip heat sink are as follows: The staff builds a chip model, determines the specific size of the chip and the location of each core, cache, and interface, sets the power corresponding to each location of the chip, and adopts an equivalent method for smaller or more complex structures. The thermal conductivity is equivalent to a uniform cuboid equivalent layer. The equivalent layer includes three-dimensional stacked structures, redistribution layers, active silicon layers, hybrid bonding layers, and microbumps, which have a significant impact on the thermal simulation results.

[0047] Staff constructed a chip model and performed thermal simulations on the two-chip stacked package. They set the thermal conductivity of each structure, configured the ambient temperature and convective heat transfer coefficient, divided the mesh size, and refined the mesh for finer structures. Through thermal simulation, they identified hotspot areas within the chip, obtained key values ​​such as the maximum temperature and temperature difference between the logic and memory chips, and determined the heat dissipation performance requirements for different areas. Based on the thermal simulation results, staff determined the dimensions of the chip heatsink. The length and width of the heatsink are the same as the chip. Figure 5 Determine the specific dimensions of the slit to balance the heat dissipation capacity of the hot spot area and the surrounding area.

[0048] In this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise explicitly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0049] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0051] The above are merely some embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A chip heat sink, characterized in that, include: The manifold has a cooling groove on its connecting surface; Multiple fins extend in a direction away from the manifold, and heat dissipation space is formed between adjacent fins; A baffle is connected to the manifold and the fins respectively. The baffle has a slit opposite to the cooling tank. The cooling tank communicates with the heat dissipation space through the slit. The slit includes a wide section and a narrow section. The wide section is used to be located in the high-temperature area of ​​the chip. The opening size of the wide section is larger than the opening size of the narrow section.

2. The chip heat sink according to claim 1, characterized in that, The cooling tank includes: Water inlet tank, used to connect the water inlet pipe; The water outlet tank is used to connect the water outlet pipe, and the water inlet tank and the water outlet tank are connected through the heat dissipation space.

3. The chip heat sink according to claim 2, characterized in that, The cooling tank extends along a first direction, and a plurality of water inlet tanks and a plurality of water outlet tanks are alternately arranged along a second direction, wherein the first direction and the second direction intersect.

4. The chip heat sink according to any one of claims 1 to 3, characterized in that, The number of chips is multiple, and the multiple wide segments are used to correspond one-to-one with each chip.

5. The chip heat sink according to any one of claims 1 to 3, characterized in that, The fins are arranged in multiple rows and columns, with adjacent rows of fins staggered.

6. The chip heat sink according to claim 5, characterized in that, The row spacing of the multiple fins is the same, and the column spacing of the multiple fins is the same.

7. The chip heat sink according to any one of claims 1 to 3, characterized in that, The fins are provided with sharp corners at both ends.

8. The chip heat sink according to any one of claims 1 to 3, characterized in that, Also includes: A heat dissipation substrate, comprising a stacked diamond layer, a titanium layer, and a metal layer, wherein the metal layer is connected to the end of the fin facing away from the manifold, and the diamond layer is used to connect the chip.

9. An electronic device, characterized in that, include: chip; The chip heat sink as described in any one of claims 1 to 8, wherein the chip heat sink is connected to the chip.

10. A method for manufacturing a chip heat sink, characterized in that, The method for manufacturing a chip heat sink as described in any one of claims 1 to 8 comprises: Multiple fins are fabricated on a heat dissipation substrate, and heat dissipation spaces are formed between adjacent fins; Manifolds are manufactured, and cooling grooves are engraved on the connecting surfaces of the manifolds. A baffle is manufactured, and a slit is etched on the baffle. The slit includes a wide section and a narrow section. The wide section is used to be located in a high-temperature region of the chip, and the opening size of the wide section is larger than the opening size of the narrow section. The manifold and the baffle are connected, the baffle partially obstructing the opening of the cooling tank, and the slit is opposite to the cooling tank. The baffle and the fins are connected so that the cooling groove communicates with the heat dissipation space through the slit.

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