Integrated circuit layout for reducing electromagnetic interference

Abstract

This application relates to an integrated circuit layout for reducing electromagnetic interference. An example circuit (100) can include a packaged integrated circuit (IC) (102) having opposing first and second sides (104, 106). The first side (104) of the packaged IC (102) can include a first ground terminal (112), a second ground terminal (114), and an input voltage terminal (116). The input voltage terminal (116) can be positioned substantially equidistant between the first and second ground terminals (112, 114) along the first side (104) of the packaged IC (102).

Description

Technical Field

[0001] This specification relates to an integrated circuit layout for reducing electromagnetic interference. Background Technology

[0002] Power switches are used in a variety of applications to control power supply. As an example, a controller can provide an input pulse-width modulation (PWM) signal to a driver circuit configured to provide a drive signal to an output stage (e.g., one or more transistors). The output stage may contain one or more transistors. In some circuit configurations, noise can be introduced at the input of the driver circuit, such as from parasitic effects or other sources, which can distort the input PWM signal. Such distortion can lead to damage to the drive signal. Summary of the Invention

[0003] One described example relates to a circuit comprising a packaged integrated circuit (IC) having opposing first and second sides. The first side of the packaged IC may include a first ground terminal, a second ground terminal, and an input voltage terminal. The input voltage terminal may be positioned substantially equidistantly along the first side of the packaged IC between the first ground terminal and the second ground terminal.

[0004] Another example relates to a circuit comprising a packaged integrated circuit (IC) having a package body having opposing first and second sides, and a converter circuit on a substrate within the package body. The first side of the package body may include a first ground terminal, a second ground terminal, and a first input voltage terminal. The first input voltage terminal may be positioned substantially equidistantly between the first and second ground terminals along the first side of the package body. The second side of the package body may include a third ground terminal, a fourth ground terminal, and a second input voltage terminal. The second input voltage terminal may be located between the third and fourth ground terminals along the second side of the package body, and the first ground terminal, the second ground terminal, and the first input voltage terminal are spatially symmetrical with respect to the third ground terminal, the fourth ground terminal, and the second input voltage terminal, respectively. The converter circuit has a first converter input, a second converter input, and a converter output. The first converter input may be coupled to the first and second input voltage terminals, the second converter input may be coupled to at least one of the first, second, third, or fourth ground terminals, and the converter output may be coupled to an output terminal along one side of the package body.

[0005] Another described example relates to a power converter circuit comprising a packaged integrated circuit (IC) and an arrangement of a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The packaged integrated circuit (IC) comprises a package body having opposing first and second sides. The packaged IC includes a first ground terminal, a second ground terminal, and a first input voltage terminal along the first side of the package body. The first input voltage terminal is positioned substantially equidistantly between the first ground terminal and the second ground terminal. The packaged IC also includes a third ground terminal, a fourth ground terminal, and a second input voltage terminal along the second side of the package body. The second input voltage terminal is positioned substantially equidistantly between the third ground terminal and the fourth ground terminal, and the first ground terminal, the second ground terminal, and the first input voltage terminal are spatially symmetrical with respect to the third ground terminal, the fourth ground terminal, and the second input voltage terminal, respectively. The packaged IC may also include a bridging circuit on a substrate within the packaged IC, wherein the bridging circuit includes a first power input, a ground input, and an output. The first power input may be coupled to the first input voltage terminal and the second input voltage terminal, and the ground input may be coupled to at least one of the first ground terminal, the second ground terminal, the third ground terminal, or the fourth ground terminal. The output of the bridge circuit can be coupled to the output terminal of the packaged IC along the corresponding side of the package body. A first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to a first ground terminal, and the second terminal of the first capacitor is coupled to a first input voltage terminal. A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to a second ground terminal, and the second terminal of the second capacitor is coupled to the first input voltage terminal. A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to a third ground terminal, and the second terminal of the third capacitor is coupled to a second input voltage terminal. A fourth capacitor has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to a fourth ground terminal, and the second terminal of the fourth capacitor is coupled to a second input voltage terminal. Attached Figure Description

[0006] Figure 1 These are circuit diagrams and block diagrams depicting example circuit systems configured to reduce electromagnetic interference.

[0007] Figure 2 This is a circuit diagram and block diagram depicting another example circuit system configured to reduce electromagnetic interference.

[0008] Figure 3 This is a schematic plan view showing an example printed circuit board containing a circuit system configured to reduce electromagnetic interference.

[0009] Figure 4This is a schematic plan view showing another example of a printed circuit board containing a circuit system configured to reduce electromagnetic interference.

[0010] Figure 5 This is a plan view showing a portion of yet another example printed circuit board.

[0011] Figure 6 The packaged IC implemented in an example power converter circuit is depicted.

[0012] Figure 7 A packaged IC implemented in another example power converter circuit is depicted.

[0013] Figure 8 This is a graph showing the comparison of input impedance with frequency. Detailed Implementation

[0014] This specification relates to circuits and systems configured to reduce electromagnetic interference, such as those used in power converter circuits.

[0015] The examples described herein include packaged integrated circuits (ICs) with opposing sides. As used herein, a packaged IC can refer to a single-chip or multi-chip package, a system-in-package (SIP), and / or a system-on-a-chip (SOC). One or both sides of a packaged IC include an arrangement of terminals (e.g., pins or pads of conductive material such as copper and / or alloys thereof) spatially positioned relative to each other to reduce electromagnetic interference. For example, a first side of a packaged IC includes a first ground terminal and a second ground terminal, as well as an input voltage terminal. The voltage terminal is positioned substantially equidistantly along the first side of the packaged IC between the first and second ground terminals to define a layout that may be referred to as a single-butterfly layout. In other examples that may be referred to herein as a double-butterfly layout, the second side of the packaged IC opposite to the first side includes a third ground terminal and a fourth ground terminal, as well as another input voltage terminal positioned substantially equidistantly along the second side between the third and fourth ground terminals.

[0016] Both configurations (e.g., a single-butterfly layout or a dual-butterfly layout) reduce (or eliminate) the electromagnetic field across the horizontal axis of the packaged IC, which extends through opposing first and second sides of the packaged IC. The dual-butterfly layout reduces (or eliminates) the electromagnetic field across the horizontal axis of the packaged IC as well as through the vertical axis extending through the packaged IC perpendicular to the horizontal axis. For example, this further reduces electromagnetic interference associated with the power connection of the IC converter.

[0017] In some instances, a first input capacitor and a second input capacitor are placed on one or both of the first and second sides of the packaged IC. For example, the first input capacitor is coupled between an input terminal and a first ground terminal, and the second input capacitor is coupled between an input terminal and a second ground terminal. This arrangement of capacitors may be referred to herein as a mirror configuration, which can be configured to have a lower parasitic inductance than existing methods. The reduced parasitic inductance translates to lower parasitic inductance in the input loop (e.g., supply voltage to ground) of the circuit system implementing the packaged IC (e.g., a power converter). Lower parasitic inductance can also enable faster switching of the internal switches (e.g., transistors) of the packaged IC by allowing a higher dI / dt for a given induced voltage.

[0018] Additionally, in instances where the packaged IC and input capacitors with a single-butterfly or dual-butterfly layout are configured as a power converter (e.g., a DC-DC converter), the total power (e.g., current) to the high-side and low-side power transistors can be directed along parallel paths, which reduces the total input impedance because the resistive and capacitive input paths are branched (e.g., separated). This makes the overall configuration of the resulting circuit's power supply voltage-to-ground system layout more compact. The ground-to-power supply voltage-to-ground configurations of the single-butterfly and dual-butterfly layouts described herein also allow for efficient use of 3-terminal capacitors, as they can be directly coupled to the IC's input pins to implement the first and second capacitors in a mirror capacitor configuration along one or more sides of the packaged IC.

[0019] Figure 1 This is a circuit diagram and block diagram depicting an example circuit system 100. System 100 includes a packaged IC 102 having opposing first sides 104 and second sides 106, the first and second sides being spaced apart from each other by another pair of opposing sides 108 and 110. The first side 104 of packaged IC 102 includes a first ground terminal 112, a second ground terminal 114, and an input voltage terminal 116. Figure 1 In one example, the input voltage terminal 116 is located substantially equidistantly along side 104 between the first ground terminal 112 and the second ground terminal 114. In the examples herein, each terminal of the packaged IC 102 may be implemented as a single pin or grouped into pin blocks for corresponding connections (e.g., for ground and / or voltage connections).

[0020] Package IC 102 includes one or more circuits 120, which may be formed on one or more substrates housed within a package body defining the package IC. In some examples described herein, one or more circuits 120 include power converter circuitry configured to convert a voltage at input voltage terminal 116 into an output voltage available at output terminal 166 of the package IC. The power converter may be a DC-DC buck, boost, buck-boost, or other converter topology. Alternatively, one or more circuits 120 may include other types of circuitry for performing other functions.

[0021] exist Figure 1 In one example, circuit 120 is depicted as a power converter comprising a first half-bridge circuit 122 and a second half-bridge circuit 124 arranged in parallel. Controller 126 has outputs 128 and 130 coupled to respective inputs of each of the half-bridge circuits 122 and 124. Half-bridge circuit 122 includes transistors (e.g., FETs, such as power FETs) 132 and 134 coupled in series between a first ground terminal 112 and an input voltage terminal 116. Transistor 132 includes a first current terminal 136 (e.g., drain), a second current terminal 138 (e.g., source), and a control input 140 (e.g., gate), wherein the first current terminal 136 is coupled to the output 148 of circuit 120 (e.g., a switching node). The second current terminal 138 may be coupled to the first ground terminal 112, and the control input 140 may be coupled to the output 130 of controller 126. Transistor 134 includes a first current terminal 142 (e.g., drain), a second current terminal 144 (e.g., source), and a control input 146 (e.g., gate). The first current terminal 142 is coupled to an input voltage terminal 116. The second current terminal 144 is coupled to the first current terminal 136 of transistor 132, and the first current terminal is also coupled to an output 148. The control input 140 is coupled to the output 128 of controller 126.

[0022] The half-bridge circuit 124 includes transistors (e.g., FETs, such as power FETs) 150 and 152 series coupled between a second ground terminal 114 and an input voltage terminal 116. Transistor 150 includes a first current terminal 154 (e.g., drain), a second current terminal 156 (e.g., source), and a control input 158 ​​(e.g., gate), wherein the first current terminal 154 is coupled to an output 148, the second current terminal 156 is coupled to the input voltage terminal 116, and the control input 140 is coupled to the output 128 of controller 126. Transistor 152 includes a first current terminal 160 (e.g., drain), a second current terminal 162 (e.g., source), and a control input 164 (e.g., gate). The first current terminal 160 is coupled to the second ground terminal 114. The second current terminal 162 is coupled to the output 148, which is also coupled to terminal 154 of transistor 150. The control input 164 is coupled to the output 130 of controller 126.

[0023] Although transistors 132, 134, 150, and 152 are in Figure 1 In this example, it is shown as a FET, but in other examples, the transistor can be implemented as other types of transistors, such as bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, etc. For Figure 1 For the purposes of the example circuit system 100, package IC 102 also includes an output terminal 166 shown on side 106, another ground terminal 168 on side 110, and sensing terminals 170 and 172 on the same side 104 as terminals 112, 114, and 116. In other instances, package IC may include other numbers and arrangements of terminals. Each of the ground terminals 112, 114, and 168 may be coupled to a ground terminal of package IC 102 (e.g., common IC ground).

[0024] System 100 can be implemented on a printed circuit board (PCB or other substrate) as shown in Figure 174, the PCB including the arrangement of circuit paths (e.g., conductive traces, wires) and board ground 176 (e.g., a ground plane). Board ground 176 can be coupled to a first ground terminal 112 and a second ground terminal 114 via corresponding circuit paths (e.g., traces or wires), each circuit path having a corresponding parasitic inductance (L_PAR1 and L_PAR2). Voltage terminal 178 can also be coupled to the input voltage terminal 116 of packaged IC 102 via a corresponding parasitic inductance (L_PAR3). The various parasitic inductances can be the same or different, depending on their relative lengths and cross-sectional dimensions. Furthermore, each of the parasitic inductances L_PAR1, L_PAR2, and L_PAR3 can represent the sum of all parasitic inductances between the respective terminals of capacitors C1 and C2 and the power switch on package IC 102 (or other circuitry coupled to the terminals), such as the equivalent series inductance (ESL) of the capacitors, parasitic wiring of PCB connections, and package inductance (e.g., bond wires and / or package connections of any wiring).

[0025] exist Figure 1 In one example, system 100 includes a first capacitor C1 coupled between a circuit board ground 176 and a voltage terminal 178. A second capacitor C2 is coupled between a second ground terminal 114 and a voltage terminal 178. For example, C1 and C2 define corresponding input capacitors, where C1 = C2. The voltage terminal 178 can be coupled to the output of a power source (e.g., another power converter, such as a voltage regulator, battery structure) to receive a DC voltage. Figure 1 The configuration of system 100 shown on PCB 174 in the example can be considered a single butterfly layout because terminals 112 and 114, along with capacitors C1 and C2, are arranged symmetrically (e.g., in a mirror configuration) about the horizontal axis A1 extending through the input voltage terminal 116 and the sides 104 and 106 of package IC 102. Such a configuration reduces (or eliminates) electromagnetic interference across the horizontal axis A1 at the voltage input of IC 102 (e.g., due to voltage supply connections). Parasitic impedance at the input is also reduced compared to many existing designs. The mirror arrangement of capacitors C1 and C2 further results in lower parasitic impedance. Reduced parasitic inductance allows for a higher di / dt for a given induced voltage, which further enables faster switching of the switches (e.g., transistors) of circuit 120.

[0026] System 100 may also include output circuitry (e.g., a load) 180, which may be implemented on or outside of PCB 174 via appropriate connections. The output circuitry includes inputs coupled to ground terminal 168 and output terminal 166. Output circuitry 180 may also be coupled to terminals 170 and 172 to provide feedback to controller 126 representing operating parameters (e.g., voltage, current, etc.). Inductor L1 may be coupled between output 148 of circuit 120 and output circuitry 180. Inductor L1 may be implemented on packaged IC 102, such as coupled between output 148 of circuit 120 and output terminal 166 (as shown), or inductor L1 may be external to packaged IC. In one example, a sensed voltage for output circuitry 180 is provided at terminals 170 and 172. Controller 126 may be configured to control circuitry 120 in response to feedback signals provided at terminals 170 and 172. For example, the controller is configured to control circuit 120 in response to feedback signals received from output circuit 180 at terminals 170 and 172, for example by providing control signals at outputs 128 and 130 to corresponding control inputs 140, 146, 158 and 164.

[0027] Figure 2 This is a circuit diagram and block diagram depicting another example circuit system 200. Figure 2 The circuit system is an alternative layout that can be implemented to further reduce electromagnetic interference. Although Figure 1 The layout in the example system has symmetry about the horizontal axis A1, but Figure 2 Example system 200 has a layout exhibiting symmetry about a horizontal axis A2 and about a vertical axis A3, the vertical axis A3 extending orthogonally through the packaged IC to the horizontal axis A2. When compared with... Figure 1 Compared to the single butterfly layout, Figure 2 The layout shown in the example can be referred to as a double butterfly layout in this article.

[0028] The circuit system 200 includes a packaged IC 202 defining a package body having first and second opposing sides 204 and 206 spaced apart from each other by third and fourth opposing sides 208 and 210. Figure 2In the illustrated orientation, axis A2 extends through sides 204 and 206, and another axis A3, orthogonal and coplanar with axis A2, extends through other sides 208 and 210. Package IC 202 includes a first ground terminal 212, a second ground terminal 214, and a first input voltage terminal 216 along the first side 204. Package IC 202 also includes a third ground terminal 218, a fourth ground terminal 220, and a second input voltage terminal 222 along the second side 206 of the package body. Voltage terminal 216 may be positioned substantially equidistantly between ground terminals 212 and 214, and voltage terminal 222 may be positioned substantially equidistantly between ground terminals 218 and 220 along their respective sides. Figure 2 As shown in the example, the circuit system 200 includes a PCB 224 having a surface for mounting the packaged IC 202 and other circuit systems.

[0029] PCB 224 includes the arrangement of circuit paths (e.g., conductive traces, wires) and board ground 226 (e.g., a ground plane). Board ground 226 can be coupled to ground terminals 212, 214, 218, and 220 via corresponding circuit paths (e.g., traces or wires), each circuit path having a corresponding parasitic inductance, shown as L_PAR4 and L_PAR5, L_PAR6 and L_PAR7. Voltage terminals 228 and 230 can also be coupled to corresponding input voltage terminals 216 and 222 via corresponding parasitic inductances L_PAR8 and L_PAR9. Although shown as separate terminals 228 and 230, such terminals can be implemented as a common coupler to an input voltage source (not shown), which can be implemented on PCB 224 or externally to the PCB. The various parasitic inductances can be the same or different, and can represent the sum of the associated parasitic inductances associated with each corresponding circuit path (e.g., traces, ESL of capacitors, parasitic wiring and package inductance of PCB connections).

[0030] exist Figure 2In this example, circuit system 200 also includes input capacitors C3, C4, C5, and C6. C3 is coupled between ground terminal 212 and voltage terminal 216, such that the path between the terminal of C3 and the associated circuit system in IC 202 includes corresponding parasitic inductances L_PAR4 and L_PAR8. C4 is coupled between ground terminal 214 and voltage terminal 216, such that the path between the terminal of C4 and the associated circuit system in IC 202 includes corresponding parasitic inductances L_PAR5 and L_PAR8. On the other side of the package body, C5 is coupled between ground terminal 218 and voltage terminal 222, and C6 is coupled between ground terminal 220 and voltage terminal 222. The path between the terminal of each of C5 and C6 and the associated circuit system in IC 202 also includes corresponding parasitic inductances denoted as L_PAR4, L_PAR5, and L_PAR9. In some instances, capacitors C3 and C4 are implemented by three-terminal capacitors and / or capacitors C5 and C6 are implemented by another three-terminal capacitor.

[0031] Package IC 202 includes one or more circuits 232, which may be formed on one or more substrates housed within a package body defining the package IC. In some examples described herein, the one or more circuits 232 include a power converter circuit system configured to convert the voltage at input voltage terminals 228 and 230 into an output voltage at output terminal 234 of package IC 202. Figure 2 In this example, the output terminal is on side 208, but in other examples it may be located on one or more other sides 204, 208, 210, and 212 of the packaged IC. The power converter may be a DC-DC buck, boost, buck-boost, or other converter topology. Alternatively, the one or more circuits 232 may include other types of circuitry for performing other functions.

[0032] exist Figure 2 In this example, circuit 232 is depicted as a power converter, comprising a first bridge circuit 236 and a second bridge circuit 238 arranged in parallel between input voltage terminals 216, 222 and output terminal 234. Each of bridge circuits 236 and 238 can be considered to have two half-bridge circuits, each half-bridge circuit being connected in parallel with respect to… Figure 1 The half-bridge circuit is configured similarly to the one described above. Thus, each bridge circuit 236 and 238 may include an arrangement of transistors (e.g., FETs, such as power FETs) coupled between corresponding terminals of the package IC 202, for example... Figure 2As shown in the diagram. As another example, the packaged IC may include internal electrical connections (e.g., on-die wiring and / or bonding wires) configured to electrically couple voltage terminal 216 to terminal 222, terminal 212 to terminal 218, and terminal 214 to terminal 220. Figure 2 In the dual-butterfly example, each of the bridging circuits 236 and 238 is configured as a corresponding full-bridge circuit, wherein each bridging circuit includes corresponding switching output terminals (e.g., switching nodes) 240 and 242 coupled to the output terminal 234.

[0033] The controller 244 has outputs 246, 248, 250, and 252 that are coupled to a corresponding control input (e.g., coupled to the gate of a corresponding transistor) of each of the bridge circuits 236 and 238. Figure 2 In one example, output 246 is coupled to the control input of the first pair of high-side transistors in each of bridge circuits 236 and 238, and output 248 is coupled to the control input of the other pair of high-side transistors in the bridge circuit. Other outputs 250 and 252 are each coupled to a corresponding pair of low-side transistors in each of bridge circuits 236 and 238. In other examples, a separate controller output can be coupled to the control input (e.g., the gate) of each of the corresponding transistors in circuit 232 to achieve its independent control.

[0034] exist Figure 2In the example shown, package IC 202 also includes another ground terminal 256 on side 210, and sensing terminals 258 and 260 on the same side 204 as terminals 212, 214, and 216. In other examples, package IC 202 may include other numbers and / or arrangements of terminals. Each of ground terminals 212, 214, 218, 220, and 256 may be coupled to a ground terminal of package IC 202 (e.g., common IC ground). System 200 may also include output circuitry (e.g., including output capacitors and / or loads) 262, which may be implemented on PCB 224 or externally via one or more corresponding connections. Output circuitry 262 includes inputs coupled to ground terminal 256 and output terminal 234. Output circuitry 262 may also be coupled to terminals 258 and 260 to provide feedback to corresponding inputs of controller 244 representing operating parameters (e.g., voltage, current, etc.). Inductor L2 may be coupled between output 148 of circuit 232 and output circuit 180. Inductor L1 may be implemented on packaged IC 102, such as coupled between outputs 240, 242 of circuit 232 and output terminal 234 (as shown), or in other instances, inductor L2 may be external to packaged IC. In one instance, a sensed voltage potential for output circuit 262 is provided at terminals 258 and 260. Controller 244 may be configured to control circuit 232 in response to feedback signals provided at terminals 258 and 260. For example, controller 244 may be configured to control circuit 232 in response to feedback signals received from output circuit 180 at terminals 258 and 260, for example, by providing control signals (e.g., pulse signals) to the respective control inputs of bridge circuits 236 and 238 at outputs 246, 248, 250, and 252. Advantageously, because electromagnetic interference along both sides 204 and 206 of the packaged IC is reduced (or eliminated) due to the double-butterfly arrangement of the terminals and circuitry, the input signals listed at terminals 258 and 260 can be more accurate than the measured signals. Therefore, controller 244 can operate circuit 232 with a faster switching rate and improved performance compared to many existing methods.

[0035] Figure 3 and Figure 4 This is a schematic plan view showing a portion of an example PCB containing a circuit system configured to reduce electromagnetic interference. Figure 3 Describing for similar Figure 1 This is an example of a single butterfly layout PCB 300. Therefore, Figure 3 The description can also be found here. Figure 1 In some aspects. Figure 3PCB 300 includes a packaged IC 302 mounted on the surface of the PCB. Packaged IC 302 includes ground terminals 304 and 306 and input terminals 308 along a respective side 310 of the IC. Input terminals 308 are located approximately midway between ground terminals 304 and 306. Respective traces (or other forms of connection) 312 and 314 of PCB 300 are coupled to each ground terminal 304 and 306 and extend away from each ground terminal 304 and 306. A voltage trace (or other form of connection) 316 is coupled to input terminal 308. Trace 316 may extend along or within PCB 300 away from input terminal 308, generally parallel to traces 312 and 314 and spaced apart midway between traces 312 and 314 (also extending from the respective terminals), providing a ground-supply voltage-ground configuration along side 310.

[0036] An axis (e.g., a horizontal axis) A4 extends through input terminal 308 and trace 316, the trace showing a symmetrical line around the input voltage path for a ground-supply voltage-ground configuration. The PCB also includes capacitors 326 and 328, wherein on each side of axis A4, a capacitor is coupled between trace 312 (coupled to ground terminal 304) and input trace 316 (coupled to terminal 308), and capacitor 328 is coupled between ground trace 314 (coupled to ground terminal 306) and input trace 316 (coupled to terminal 308). The capacitors may also be implemented using a single three-terminal capacitor.

[0037] Therefore, the ground-supply voltage-ground configuration along side 310 provides a parallel path for the current to the circuitry of package IC 302. This reduces or cancels out electromagnetic interference (EMI) caused by signals (e.g., current) through parasitic inductance along each parallel path. Furthermore, by reducing EMI, the ground-supply voltage-ground configuration achieves a more compact configuration. For example, the package IC includes terminals 318 and 320, which are positioned along the same side 310 and adjacent to terminal 306. In other instances, terminals 318 and 320 may be positioned adjacent to another ground terminal 304 (e.g., below) (see example...). Figure 1 The PCB includes corresponding traces (or other forms of connection) 322 and 324 coupled to terminals 318 and 320. Because the ground-supply voltage-ground configuration reduces interference, the information (e.g., signal measurements) provided at terminals 318 and 320 via traces 322 and 324, respectively, is still visible even when... Figure 3 The compact design shown also achieves increased accuracy compared to many existing systems.

[0038] Figure 4 The example depicts a similar Figure 2This is an example of a circuit system on a PCB 400 with a dual-butterfly layout. Therefore, Figure 4 The description can also be found here. Figure 2 In some aspects. Figure 4 PCB 400 includes a packaged IC 402 mounted on the surface of the PCB. Packaged IC 402 includes ground terminals 404 and 406 and input terminals 408 along a respective side 410 of the IC. Input terminals 408 are located approximately midway between ground terminals 404 and 406 on side 410. Figure 4 In the dual-butterfly layout, package IC 402 also includes ground terminals 412 and 414 and another input terminal 416 along the opposite side 418. Input terminal 416 is located approximately midway between ground terminals 412 and 414 on side 418. Thus, the ground terminals and input terminals 404-408 and 412-416 along each respective side 410 and 418 of package IC have a ground-voltage source-ground configuration. As a further example, axis (e.g., horizontal axis) A5 extends through input terminals 408 and 416, traces 428 and 434, which represent a first line of symmetry for the input voltage path at each opposite side of package IC 402. Another axis (e.g., vertical axis) A6 extends through opposite sides 420 and 422 of package IC 402, for example, at a midway point between opposite sides 410 and 418, and may also be orthogonal and coplanar with axis A5. The intersection point between axes A5 and A6 shown at 436 defines the central symmetry point of package IC 402. Therefore, the double-butterfly configuration of the circuitry on PCB 400 has multidimensional symmetry about the central symmetry point 436.

[0039] like Figure 4As shown in the example, traces 424, 426, 428, 430, 432, and 434 are coupled to each of the corresponding terminals 404, 406, 408, 412, 414, and 416. Each of traces 424, 426, and 428 (e.g., defining a first set of traces) may extend outward and away from side 410, and traces 430, 432, and 434 (e.g., defining a second set of traces) may extend outward and away from the other side 418. Traces 424, 426, and 428 in the first set of traces may be arranged parallel to each other at least along a portion of their coupling to terminals 404, 406, and 408. Similarly, traces 430, 432, and 434 in the second set of traces may be arranged parallel to each other at least along a portion of their coupling to terminals 412, 414, and 416. Traces 424, 426, 430, and 432 define corresponding ground connections, and traces 428 and 434 define corresponding input voltage traces, thereby providing corresponding parallel input connections with a ground-supply voltage-ground configuration along each side of package IC 402. In addition to the symmetry of the ground-supply voltage-ground configuration along each corresponding side of package IC 402, the dual-butterfly configuration also exhibits symmetry between the sides of the package body along axis A6.

[0040] PCB 400 may also include a first pair of capacitors 438 and 440 coupled to input connection traces 424, 426 and 428 at side 410, and a second pair of capacitors 442 and 444 coupled to input connection traces 430, 432 and 434 at opposite side 418. In some instances, capacitors 438 and 442 may be positioned symmetrically on opposite sides of axis A5 with respect to the respective capacitors 440 and 444.

[0041] As described herein, the dual-butterfly layout, including ground-supply voltage-to-ground input connections along opposite sides 410 and 418 of package IC 402, provides parallel paths for input current to each side of the package IC. As schematically shown by arrows 446 and 448, electromagnetic interference induced by the current signal through parasitic inductance from the ground-supply voltage-to-ground input connection along side 410 of the package IC can be reduced (or canceled) from each other. Similarly, as schematically shown by arrows 450 and 452, electromagnetic interference induced by the current signal through parasitic inductance from the ground-supply voltage-to-ground input connection along side 420 of the package IC can be reduced (or canceled) from each other. Furthermore, by reducing electromagnetic interference, a more compact circuit configuration can be achieved with the ground-supply voltage-to-ground connections on one or both sides of 410 and 418.

[0042] exist Figure 4In one example, package IC 402 includes terminals 454 and 456, which are positioned along the same side 410 and adjacent to terminal 404. PCB 400 includes corresponding traces (or other forms of connection) 458 and 460 coupled to terminals 454 and 456. In other examples, terminals 454 and 456 may be located near (e.g., below or directly below) another ground terminal 304 on side 410 (see example...). Figure 2 Alternatively, terminals (not shown) may be similarly located above or below (e.g., adjacent to) terminals 412 or 414 on the other side 418 of package IC 402. Electromagnetic interference is reduced due to the ground-supply voltage-ground connection on both sides, allowing terminals carrying sensitive information to be located closer to terminals 404, 406, 408, 412, 414, and 416 than in many existing configurations.

[0043] Figure 5 An example of a packaged IC 500 implemented in circuit 502, such as a power converter circuit, is depicted. Figure 5 In this example, package IC 500 includes leads arranged along the inner periphery of the package body at or near the side edge of the package body, consisting of pins or pads (e.g., numbered 1 to 34). Package IC 500 also includes an arrangement of thermal pads (e.g., numbered 35 to 37) distributed along the central portion of the package body. The pins and pads may be exposed on the bottom side (and / or sidewalls) of package IC 500 for contacting corresponding pads on a PCB (not shown).

[0044] exist Figure 5 In one example, circuit 502 includes a dual-butterfly configuration having ground-supply voltage-ground input connections 504 and 506 along opposite sides of package IC 500. The dual-butterfly configuration can be implemented according to the examples described herein, including... Figure 2 and 4 .therefore, Figure 5 The description can be found here. Figure 2And / or 4. In short, input capacitor C7 is coupled between ground terminal 508 (e.g., pin 29) and input voltage terminal 510 (e.g., pins 30 and 31), and another input capacitor C8 is coupled between another ground terminal 512 (e.g., pin 32) and input voltage terminal 510 to define a ground-supply voltage-ground input connection 504. Another ground-supply voltage-ground input connection 506 includes input capacitor C9 coupled between ground terminal 514 (e.g., pin 13) and input voltage terminal 516 (e.g., pins 12 and 11), and another input capacitor C10 coupled between another ground terminal 518 (e.g., pin 10) and input voltage terminal 516. In some instances, the input terminals may be a single conductive block. Each pin may be a single pin or grouped into pin blocks for the corresponding connection (e.g., for ground and / or input voltage connections).

[0045] Circuit 502 also includes an input power supply 520 having an output coupled to each of input voltage terminals 510 and 516, which are also coupled to an intermediate node between each corresponding capacitor pair C7-C8 and C9-C10. Input power supply 520 may be a DC-DC converter and an AC-DC converter, or other power supply configured to provide a DC input voltage to the input voltage terminals 510 and 516 of packaged IC 500. Other types of input power supplies may be used in other embodiments.

[0046] Circuit 502 also includes output circuit 522 having inputs 524 and 526 coupled to corresponding terminals 528 and 530 of packaged IC 500. In one example, terminal 528 is an output terminal that can be coupled to the output of one or more bridge circuits (e.g., switching node outputs 148, 240, 242). Terminal 530 is the ground of packaged IC 500 (e.g., power ground terminal (PGND)), which can be coupled to ground terminals 508, 512, 514, and 518 via internal wiring of the IC. Output circuit 522 may also have outputs 532 and 534 coupled to corresponding terminals 536 and 538 of packaged IC 500. The output circuit may also include inductor L3, output capacitor COUT, and load 540. The load may include load capacitance (e.g., inherent to the load), represented as CLOAD across first load input 542 and second load input 544. Figure 5 In this example, inductor L3 is external to package IC 500 and coupled between terminal 528 and the first load input 542. Output capacitor COUT is coupled in parallel with load capacitor CLOAD between load inputs 542 and 544.

[0047] The circuitry of packaged IC 500 can be configured to provide an output voltage VOUT across load inputs 542 and 544. For example, terminals 536 and 538 of packaged IC 500 are implemented as sensing terminals configured to receive a signal (e.g., voltage potential) representing VOUT received at load 540, in order to provide feedback for the circuitry (e.g., circuits 120, 232) controlling packaged IC 500. As described herein, the ground-supply-ground input connection 504 results in reduced electromagnetic interference and lower impedance (e.g., lower parasitic inductance). As a result of reduced interference, the feedback signal at terminals 536 and 538 provides a more accurate representation of the signal measurement (e.g., VOUT). Additionally, the reduced impedance allows for a larger di / dt at the input voltage, which further enables faster switching within the packaged IC.

[0048] Figure 6 Another example of a packaged IC 600 implemented in circuit 602, such as a power converter circuit, is depicted. Circuit 602 includes components 608 and 610 along opposite sides of packaged IC 600. Figure 5 The circuit 502 is basically the same as the ground-supply voltage-ground input connection of 604 and 606. Figure 6 Examples and Figure 5 The difference in the power converter circuit is that the inductor L3 is implemented inside the package IC 600 (rather than outside) (see example). Figure 2 The inductor L2), and because of the inclusion of this internal inductor, the output circuit 612 can be coupled to the IC in different ways.

[0049] For example, output circuit 612 has inputs 614 and 616 coupled to corresponding terminals 618 and 620 of packaged IC 600. Figure 6 In one example, terminals 618 and 620 are on opposite sides 622 and 624 (e.g., top and bottom sides) of package IC 600. In other examples, each of the terminals may be located on any of the sides 608, 610, 622, and 624, contained on the same or different sides of the package body.

[0050] In the first example, packaged IC 600 includes one or more bridging circuits (see example...). Figure 1An internal inductor implemented on the same die as the power converter circuitry of (or 2) the power converter circuitry, wherein the inductor is coupled between terminal 618 and the output switching terminals of the one or more bridge circuits (e.g., switching node outputs 148, 240, 242). In a second example, the internal inductor may be implemented within a packaged IC outside the die containing the power converter circuitry, for example, coupled between the output switching terminals of the die (or another packaged IC) and terminal 618 of the packaged IC (e.g., SOC). In each of the first and second examples, output terminal 618 may define an output voltage terminal (e.g., shown as pad 21) to provide an output voltage VOUT. Output terminal 620 may be a power ground terminal (e.g., PGND) of packaged IC 600, which may be coupled (e.g., through internal wiring of the packaged IC) to other ground terminals of the IC.

[0051] Output circuit 612 may also include a load 626 having load inputs 628 and 630. Load 626 may include a load capacitance (e.g., inherent to the load), represented as a CLOAD across the first load input 628 and the second load input 630. An output capacitor COUT is coupled in parallel with the load capacitance CLOAD between load inputs 628 and 630, which are further coupled to (or define) corresponding inputs 614 and 616 of output circuit 612. Output circuit 612 may also include outputs 632 and 634 coupled to corresponding terminals 636 and 638 of package IC 600.

[0052] Circuit 602 may also include an input power supply 640 having outputs coupled to respective input voltage terminals 642 and 644, which are also coupled to an intermediate node between each respective pair of input capacitors. Input power supply 640 may be a DC-DC converter and an AC-DC converter, or other power supplies as described herein.

[0053] As another example, the circuitry of packaged IC 600 can be configured to provide an output voltage VOUT across load inputs 628 and 630. Terminals 636 and 638 of packaged IC 600 can be implemented as sensing terminals configured to receive a signal (e.g., voltage potential) representing VOUT received at load 626, providing feedback during operation for the circuitry controlling packaged IC 600 (e.g., circuits 120, 232). As described herein, the ground-supply voltage-ground input connections 604 and 606 at opposite sides 608 and 610 result in reduced electromagnetic interference and lower impedance (e.g., lower parasitic inductance). As a result of reduced interference, the feedback signal at terminals 636 and 638 provides a more accurate representation of the signal measurement (e.g., VOUT). Additionally, the reduced impedance at the input path allows for a higher di / dt at the input voltage, which further enables faster switching within the packaged IC.

[0054] Figure 7 This is a plan view showing a portion (or at least a portion) of another example circuit 700 implemented on PCB 702. Circuit 700 has a dual-butterfly configuration and therefore provides Figure 2 , 4 Another example of circuits 5 and 6. Therefore, Figure 7 The description can also be found in the following references. Figure 2 , 4 Some aspects of 5 and 6.

[0055] Circuit 700 includes a packaged IC 704 mounted to the surface of a PCB and corresponding ground-supply voltage-ground input connections 706 and 708 along opposite sides 710 and 712 of the packaged IC 704. The packaged IC 704 may contain a power converter circuitry and / or other types of circuitry receiving an input voltage VIN from a power source, which may reside on the PCB or be coupled to the PCB via one or more connections. Each of the ground-supply voltage-ground input connections 706 and 708 may be symmetrical about each other about orthogonal axes A7 and A8. For example, ground-supply voltage-ground input connection 706 includes a pair of input capacitors 714 and 716 (e.g., capacitors 438, 440, C7, C8), wherein capacitor 714 is coupled between a first ground terminal 717 (shown below the capacitor) and a voltage input trace 718. Another capacitor 716 is coupled between a second ground terminal 719 (shown below the capacitor 716) and a voltage input trace 716. Another ground-supply voltage-ground input connection 708 includes a pair of input capacitors 720 and 722 (e.g., capacitors 442, 444, C9, C10). Capacitor 720 is coupled between a first ground 723 (shown below the capacitor) and voltage input trace 724. Capacitor 722 is coupled between a second ground 725 (shown below the capacitor 722) and voltage input trace 724. Each of the corresponding terminals and traces 717, 718, 719, 723, 724, and 725 can be coupled to the corresponding pin (or pad) of the packaged IC via the trace and / or other conductive elements routed through one or more layers of PCB 702.

[0056] exist Figure 7 In some examples, the circuit also includes a corresponding output capacitor (e.g., Figure 5 and 6 The output capacitors 730 and 732 (COUT) can be coupled across one or more loads suitable for coupling to the input (not shown – see example). Figure 5 and 6 The loads 540 and 626 in the data and their associated connections.

[0057] Figure 8 Figure 800 shows the input impedance as a function of frequency for two different power converter circuits, plots 802 and 804. Plot 802 shows the impedance of a power circuit with a ground-supply voltage-ground layout in a dual-butterfly configuration, as described herein (e.g., Figure 2 , 4(5, 6). Another graph, 804, is for an existing design that does not include a ground-supply voltage-ground layout in a single-butterfly or dual-butterfly configuration. The graph comparison shows the reduced input impedance of the circuit and system described herein compared to existing designs. The resulting reduced impedance enables a more compact system layout. The symmetry of the ground-supply voltage-ground layout also reduces (or eliminates) electromagnetic interference along each side of the IC and between opposite sides. Another benefit of this configuration is lower parasitic inductance, which allows for higher di / dt at the voltage input for faster transistor switching compared to existing methods.

[0058] In this specification, the numerical designations “first,” “second,” etc., do not necessarily correspond to the same names in the claims herein. Spatial relative terms such as “top,” “bottom,” “above,” “below,” “under,” “near,” “farthest,” etc., are used herein to describe the relationship between one element or feature depicted in the figures and another element or feature. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms may also cover different orientations of the device in use or operation. For example, if the device in the figures is inverted, an element described as “below” other elements or features would be oriented as “above” other elements or features.

[0059] Additionally, the term "coupling" may encompass connections, communication, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is directly coupled to device B; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is indirectly coupled to device B through intermediate component C, and therefore device B is controlled by device A via the control signal generated by device A.

[0060] Furthermore, in this specification, a device "configured to" perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programming and / or hardwiring) to perform a function and / or may be configured (or reconfigurable) by the user after manufacturing to perform a function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device or combinations thereof. Additionally, circuits or devices described herein as containing certain components may alternatively be configured to couple to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor wafer and / or integrated circuit (IC) package) and may be configured to couple to at least some passive elements and / or sources at manufacturing time or after manufacturing, for example, by an end user and / or a third party, to form the described structure.

[0061] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A circuit comprising: Packaged integrated circuit IC, which has a first side and a second side opposite to each other. The first side of the packaged IC includes a first ground terminal, a second ground terminal, and an input voltage terminal, wherein the input voltage terminal is positioned substantially equidistantly between the first ground terminal and the second ground terminal along the first side of the packaged IC.

2. The circuit according to claim 1, further comprising: A printed circuit board (PCB) having a surface, wherein a packaged IC is mounted to the surface of the PCB, the PCB comprising: A first trace having a proximal end coupled to the first ground terminal and extending from the proximal end of the first trace away from the packaged IC; A second trace having a proximal end coupled to the second ground terminal and extending from the proximal end of the second trace away from the packaged IC; and A third trace has a proximal end coupled to the input voltage terminal and extends from the proximal end of the third trace away from the package IC; A first capacitor, coupled between the first ground terminal and the input voltage terminal; and A second capacitor is coupled between the second ground terminal and the input voltage terminal.

3. The circuit according to claim 1, wherein: The input voltage terminal is the first input voltage terminal. The second side of the packaged IC includes a third ground terminal, a fourth ground terminal, and a second input voltage terminal. The second input voltage terminal is located along the second side of the packaged IC between the third ground terminal and the fourth ground terminal, and The first grounding terminal, the second grounding terminal, and the first input voltage terminal are spatially symmetrically arranged relative to the third grounding terminal, the fourth grounding terminal, and the second input voltage terminal, respectively.

4. The circuit according to claim 3, further comprising: A printed circuit board (PCB) having a surface, wherein a packaged IC is mounted to the surface of the PCB, the PCB comprising: A first trace having a proximal end coupled to the first ground terminal and extending from the proximal end of the first trace away from the packaged IC; A second trace has a proximal end coupled to the second ground terminal and extends from the proximal end of the second trace away from the packaged IC; A third trace having a proximal end coupled to the third ground terminal and extending from the proximal end of the third trace away from the package IC; and A fourth trace having a proximal end coupled to the fourth ground terminal and extending from the proximal end of the fourth trace away from the packaged IC.

5. The circuit of claim 4, wherein the PCB further comprises: A fifth trace having a proximal end coupled to the first input voltage terminal and extending from the proximal end of the fifth trace away from the package IC; as well as A sixth trace having a proximal end coupled to the second input voltage terminal and extending from the proximal end of the sixth trace away from the packaged IC.

6. The circuit according to claim 5, wherein: At least the proximal portion of the fifth trace extends longitudinally between the corresponding proximal portions of the first and second traces, and At least the proximal portion of the sixth trace extends longitudinally between the corresponding proximal portions of the third and fourth traces.

7. The circuit according to claim 6, further comprising: A first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the proximal portion of the first trace, and the second terminal of the first capacitor is coupled to the proximal portion of the fifth trace; A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the proximal portion of the second trace, and the second terminal of the second capacitor is coupled to the proximal portion of the fifth trace; A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the proximal portion of the third trace, and the second terminal of the third capacitor is coupled to the proximal portion of the sixth trace; as well as A fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the proximal portion of the fourth trace, and the second terminal of the fourth capacitor is coupled to the proximal portion of the sixth trace.

8. The circuit according to claim 7, wherein: The IC package has opposing third and fourth sides extending between the first and second sides. The IC package has a first axis extending through the first side and the second side and through the fifth trace and the sixth trace. The IC package has a second axis that extends through the third and fourth sides at a midpoint between the first and second sides, wherein the first and second axes are orthogonal to each other. The first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are arranged symmetrically on the PCB with respect to the first axis and the second axis.

9. The circuit according to claim 7, wherein: The first capacitor and the second capacitor define a first three-terminal capacitor, wherein the second terminal of the first capacitor and the second terminal of the second capacitor are the same terminal of the first three-terminal capacitor. The third capacitor and the fourth capacitor define a second three-terminal capacitor, wherein the second terminal of the third capacitor and the second terminal of the fourth capacitor are the same terminal of the second three-terminal capacitor.

10. The circuit of claim 1, wherein the packaged IC includes a power converter circuit configured to convert a voltage at the input voltage terminal to an output voltage at the output terminal of the packaged IC.

11. The circuit of claim 10, wherein the first side of the packaged IC includes a first sensing terminal and a second sensing terminal, one side of the packaged IC includes an output voltage terminal and a third ground terminal, and the circuit further includes: A capacitor having a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to the output voltage terminal and the second capacitor terminal is coupled to the third ground terminal; as well as A load having a first load input and a second load input, wherein the first load input is coupled to a first capacitor terminal and the second load input is coupled to a second capacitor terminal, a first sensing terminal is coupled to the first load input and the second sensing terminal is coupled to the second load input.

12. The circuit of claim 1, wherein the packaged IC comprises: Output voltage terminals are located on the corresponding side of the packaged IC; as well as A bridging circuit is provided on a substrate within the packaged IC, wherein the bridging circuit includes a power input, a ground input, and an output, the power input being coupled to the input voltage terminal, and the ground input being coupled to each of a first ground terminal and a second ground terminal; as well as An inductor coupled between the output of the bridge circuit and the output voltage terminal.

13. A circuit comprising: A packaged integrated circuit (IC) includes a package body having opposing first and second sides, and a converter circuit on a substrate within the package body. The first side of the package body includes a first ground terminal, a second ground terminal, and a first input voltage terminal, wherein the first input voltage terminal is positioned substantially equidistantly between the first ground terminal and the second ground terminal along the first side of the package body. The second side of the package body includes a third ground terminal, a fourth ground terminal, and a second input voltage terminal. The second input voltage terminal is located between the third ground terminal and the fourth ground terminal along the second side of the package body. The first ground terminal, the second ground terminal, and the first input voltage terminal are spatially symmetrical with respect to the third ground terminal, the fourth ground terminal, and the second input voltage terminal, respectively. The converter circuit has a first converter input, a second converter input, and a converter output, wherein the first converter input is coupled to a first input voltage terminal and a second input voltage terminal, the second converter input is coupled to at least one of a first ground terminal, a second ground terminal, a third ground terminal, or a fourth ground terminal, and the converter output is coupled to an output terminal along one side of the package body.

14. The circuit of claim 13, wherein the first side of the package body includes a first sensing terminal and a second sensing terminal, and the circuit further includes: A capacitor having a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to the output terminal and the second capacitor terminal is coupled to a corresponding ground terminal of the package body; as well as A load having a first load input and a second load input, wherein the first load input is coupled to a first capacitor terminal and the second load input is coupled to a second capacitor terminal, a first sensing terminal is coupled to the first load input and the second sensing terminal is coupled to the second load input.

15. The circuit of claim 13, further comprising: A printed circuit board (PCB) having a surface, wherein a packaged IC is mounted to the surface of the PCB, the PCB comprising: A first trace having a proximal end coupled to the first ground terminal and extending from the proximal end of the first trace away from the first side of the package body; A second trace having a proximal end coupled to the second ground terminal and extending from the proximal end of the second trace away from the first side of the package body; A third trace having a proximal end coupled to the third ground terminal and extending from the proximal end of the third trace away from the second side of the package body; A fourth trace having a proximal end coupled to the fourth ground terminal and extending from the proximal end of the fourth trace away from the second side of the package body; A fifth trace having a proximal end coupled to the first input voltage terminal and extending from the proximal end of the fifth trace away from the first side of the package body; and A sixth trace having a proximal end coupled to the second input voltage terminal and extending from the proximal end of the sixth trace away from the second side of the package body. The fifth trace has at least a proximal portion extending longitudinally between the respective proximal portions of the first and second traces, and The sixth trace extends longitudinally between the respective proximal portions of the third and fourth traces.

16. The circuit of claim 15, further comprising: A first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the proximal portion of the first trace, and the second terminal of the first capacitor is coupled to the proximal portion of the fifth trace; A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the proximal portion of the second trace, and the second terminal of the second capacitor is coupled to the proximal portion of the fifth trace; A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the proximal portion of the third trace, and the second terminal of the third capacitor is coupled to the proximal portion of the sixth trace; as well as A fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the proximal portion of the fourth trace, and the second terminal of the fourth capacitor is coupled to the proximal portion of the sixth trace.

17. The circuit according to claim 16, wherein: The encapsulation body has opposing third and fourth sides extending between the first and second sides. The packaging body has a first axis that extends through the first side and the second side and through the fifth trace and the sixth trace. The packaging body has a second axis that extends through the third and fourth sides at a midpoint between the first and second sides, wherein the first and second axes are orthogonal to each other. The first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are arranged symmetrically on the PCB with respect to the first axis and the second axis.

18. The circuit according to claim 17, wherein: The first capacitor and the second capacitor define a first three-terminal capacitor, wherein the second terminal of the first capacitor and the second terminal of the second capacitor are the same terminal of the first three-terminal capacitor. The third capacitor and the fourth capacitor define a second three-terminal capacitor, wherein the second terminal of the third capacitor and the second terminal of the fourth capacitor are the same terminal of the second three-terminal capacitor.

19. A power converter circuit, comprising: Packaged integrated circuits (ICs), which include: The encapsulation body has a first side and a second side that are opposite to each other; Along the first side of the package body, there are a first ground terminal, a second ground terminal, and a first input voltage terminal, wherein the first input voltage terminal is positioned substantially equidistantly between the first ground terminal and the second ground terminal; A third ground terminal, a fourth ground terminal, and a second input voltage terminal are located along the second side of the package body, wherein the second input voltage terminal is positioned substantially equidistantly between the third ground terminal and the fourth ground terminal, and the first ground terminal, the second ground terminal, and the first input voltage terminal are spatially symmetrical with respect to the third ground terminal, the fourth ground terminal, and the second input voltage terminal, respectively; and A bridging circuit is provided on a substrate within the packaged IC, wherein the bridging circuit includes a first power input, a ground input, and an output, the first power input being coupled to a first input voltage terminal and a second input voltage terminal, the ground input being coupled to at least one of a first ground terminal, a second ground terminal, a third ground terminal, or a fourth ground terminal, and the output of the bridging circuit being coupled to an output terminal of the packaged IC along a respective side of the package body. A first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first ground terminal, and the second terminal of the first capacitor is coupled to the first input voltage terminal. A second capacitor has a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the second ground terminal, and the second terminal of the second capacitor is coupled to the first input voltage terminal; A third capacitor has a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third ground terminal, and the second terminal of the third capacitor is coupled to the second input voltage terminal; and A fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the fourth ground terminal, and the second terminal of the fourth capacitor is coupled to the second input voltage terminal.

20. The power converter circuit of claim 19, further comprising: A printed circuit board (PCB) having a surface, wherein a packaged IC is mounted to the surface of the PCB, the PCB comprising: A first trace having a proximal end coupled to the first ground terminal and extending from the proximal end of the first trace away from the packaged IC; A second trace has a proximal end coupled to the second ground terminal and extends from the proximal end of the second trace away from the packaged IC; A third trace has a proximal end coupled to the first input voltage terminal and extends from the proximal end of the third trace away from the first side of the package body, wherein the first terminal of the first capacitor is coupled to the proximal portion of the first trace, the second terminal of the first capacitor is coupled to the proximal portion of the third trace, the first terminal of the second capacitor is coupled to the proximal portion of the second trace, and the second terminal of the second capacitor is coupled to the proximal portion of the third trace. A fourth trace having a proximal end coupled to the third ground terminal and extending from the proximal end of the fourth trace away from the packaged IC; A fifth trace having a proximal end coupled to the fourth ground terminal and extending from the proximal end of the fifth trace away from the packaged IC; and A sixth trace having a proximal end coupled to the second input voltage terminal and extending from the proximal end of the sixth trace away from the second side of the package body, wherein the first terminal of the third capacitor is coupled to the proximal portion of the fourth trace, the second terminal of the third capacitor is coupled to the proximal portion of the sixth trace, and the first terminal of the fourth capacitor is coupled to the proximal portion of the fifth trace, and the second terminal of the fourth capacitor is coupled to the proximal portion of the sixth trace.

21. The power converter circuit according to claim 19, wherein: The encapsulation body has opposing third and fourth sides extending between the first and second sides. The packaging body has a first axis that extends through the first side and the second side and through the third trace and the sixth trace. The IC package has a second axis that extends through the third and fourth sides at a midpoint between the first and second sides. The first axis and the second axis are orthogonal to each other, and The first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are arranged symmetrically with respect to the first axis and the second axis.

22. The power converter circuit according to claim 19, wherein: The first capacitor and the second capacitor define a first three-terminal capacitor, wherein the second terminal of the first capacitor and the second terminal of the second capacitor are the same terminal of the first three-terminal capacitor. The third capacitor and the fourth capacitor define a second three-terminal capacitor, wherein the second terminal of the third capacitor and the second terminal of the fourth capacitor are the same terminal of the second three-terminal capacitor.

23. The power converter circuit of claim 19, wherein the first side of the package body includes a first sensing terminal and a second sensing terminal, and the power converter circuit further includes: A fifth capacitor having a first terminal and a second terminal, wherein the first terminal of the fifth capacitor is coupled to the output terminal, and the second terminal of the fifth capacitor is coupled to a corresponding ground terminal of the package body; as well as A load having a first load input and a second load input, wherein the first load input is coupled to the first terminal of the fifth capacitor and the second load input is coupled to the second terminal of the fifth capacitor, the first sensing terminal is coupled to the first load input and the second sensing terminal is coupled to the second load input.

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