Multilayer ceramic substrate integrated assembly packaging method and multilayer ceramic substrate package

Abstract

The application relates to the field of three-dimensional packaging technology of electronic circuits, and discloses a multilayer ceramic substrate integrated assembly packaging method and a multilayer ceramic substrate package, which comprises the following steps: providing at least two ceramic substrates, each of the ceramic substrates is formed with a through hole; filling conductive material in each through hole, and making the end surface of the conductive material flush with the surface of the corresponding ceramic substrate; forming a conductive pattern on the surface of each ceramic substrate through a thin film process; and making the conductive pattern cover the port of the through hole to form an airtight seal; forming a solder layer on the surface of each ceramic substrate to be welded, and the melting points of at least part of the solder layers are different from each other; stacking each ceramic substrate along the thickness direction, and welding layer by layer according to the order from high to low of the melting points; wherein the welding temperature of the current welding layer is lower than the melting point of the solder of the welded layer. The three-dimensional stacked packaging with high reliability and high airtightness between multilayer substrates is realized.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional packaging technology for electronic circuits, and in particular to an integrated assembly and packaging method for multilayer ceramic substrates and a multilayer ceramic substrate package. Background Technology

[0002] As electronic devices evolve towards miniaturization, higher frequencies, and higher reliability, 3D packaging technology has become a key path to overcome the bottlenecks of planar integration. Currently, multilayer packaging mainly employs two types of implementation schemes: One type is the through-hole stacking scheme based on silicon substrates. This scheme utilizes the fine processing capabilities of silicon semiconductors, etching through-holes and electroplating copper to achieve interconnection between the upper and lower layers, and then forming a multilayer structure through wafer bonding. However, silicon, as a semiconductor material, has a high dielectric constant (approximately 11.9), which easily leads to severe parasitic capacitance and signal delay under high-frequency conditions. Furthermore, wafer-level processing carries the process risk of batch loss due to single-sheet scrap, resulting in a long overall development cycle and high cost.

[0003] Another type is the multilayer co-fired scheme represented by high-temperature co-fired ceramics (HTCC) or low-temperature co-fired ceramics (LTCC). This scheme involves stacking layers of green ceramic tapes with printed circuitry and then co-firing them under pressure to form a three-dimensional ceramic substrate and achieve the embedding of some passive devices. However, due to limitations in screen printing precision and sintering shrinkage deformation, the linewidth and spacing of the conductors between layers can usually only reach about 150μm, which is difficult to meet the requirements of high-density interconnection, and it is also difficult to control the dimensional consistency of the substrate after sintering.

[0004] Furthermore, Chinese invention patent application CN121308737A discloses a high-reliability miniature solid-state relay and its manufacturing method, specifically a solid-state relay manufacturing method using an LTCC substrate, electroplating for via filling, and AuSn eutectic bonding. This solution still falls under the category of planar packaging for mounting devices on a single-layer substrate, and does not involve the vertical stacking assembly of multiple independent ceramic substrates, nor does it solve the temperature gradient control problem in the multi-layer stacking and soldering process. Moreover, the electroplating for via filling and thick-film printing processes used are also difficult to simultaneously meet the requirements of ultra-high precision circuitry and the airtightness at both ends of the vias.

[0005] In summary, existing 3D packaging solutions have limitations in terms of dielectric properties, process yield, wiring accuracy, stacking flexibility, and hermetic reliability. There is an urgent need for a new multilayer substrate assembly and packaging method that can comprehensively take into account the above-mentioned performance. Summary of the Invention

[0006] The technical problem that this invention aims to solve is: how to provide a multilayer ceramic substrate assembly and packaging method that combines high-precision patterns, low-loss media, flexible stacking, and reliable airtightness.

[0007] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for integrated assembly and packaging of multilayer ceramic substrates, comprising the following steps: At least two ceramic substrates are provided, each of which has a through hole; Each of the through holes is filled with conductive material, and the end face of the conductive material is flush with the surface of the corresponding ceramic substrate. Conductive patterns are formed on the surface of each of the ceramic substrates using a thin-film process; and the conductive patterns are made to cover the port of the through hole to form an airtight opening; Solder layers are formed on the surfaces to be soldered of at least one of the two adjacent ceramic substrates, and at least a portion of the solder layers have different melting points; The ceramic substrates are stacked along the thickness direction and welded layer by layer in order of decreasing melting point; wherein the welding temperature of the current welding layer is lower than the melting point of the solder of the previously welded layers.

[0008] Furthermore, filling each of the through holes with conductive material specifically includes: The conductive paste is drawn in and filled into each of the through holes by vacuum suction, and then cured. Excess conductive paste that overflows onto the surface of the corresponding ceramic substrate is removed by mechanical polishing, so that the end face of the conductive material is flush with the surface of the corresponding ceramic substrate.

[0009] Furthermore, the conductive material is conductive silver paste.

[0010] Furthermore, the thin film process includes photolithography and film deposition processes; the minimum linewidth and / or line spacing of the conductive pattern is less than or equal to 20 μm.

[0011] Furthermore, at least a portion of the solder layer is selected from at least two of AuSn18, AuSn20, and AuSn21 to form a stepped melting point gradient.

[0012] Furthermore, the layer-by-layer welding adopts a welding process with a peak temperature of 290~350℃ and a holding time of 25~40s to form an intermetallic compound layer at the welding interface, thereby inhibiting the transfer of heat to the welded layers; and pressure is maintained throughout the welding process to ensure tight adhesion between the layers.

[0013] Furthermore, the solder layer is prefabricated into a continuous annular structure, and an annular sealing welding strip is formed between adjacent substrates through the annular structure.

[0014] Furthermore, at least one of the ceramic substrates is pre-processed with a cavity for accommodating active devices and / or passive devices.

[0015] Furthermore, before completing the welding of all the ceramic substrates, active devices and / or passive devices are assembled in the cavity by bonding or welding; and the topmost ceramic substrate acts as a packaging cover to seal the cavity.

[0016] A second aspect of the present invention provides a multilayer ceramic substrate package manufactured using the method described above.

[0017] Furthermore, the ceramic substrate is made of alumina ceramic; adjacent ceramic substrates are welded together by a gold-tin solder layer, and the gold-tin solder layer has different gold-tin ratios in different layers of the package.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: On the one hand, by using independent ceramic substrates as basic assembly units, conductive materials are filled into the through holes of each substrate until they are flush with the surface, and conductive patterns are made using thin film technology to cover the through hole ports. This achieves high-precision wiring on both the upper and lower surfaces, and simultaneously achieves hermetic sealing at both ends of the through holes by using the thin film metal layer covering the through hole ports. Thus, high-density interconnection and hermetic sealing are achieved in a single process step, effectively overcoming the shortcomings of traditional silicon-based TSV solutions, such as high dielectric loss, high batch scrap risk, and low wiring accuracy (limited linewidth) of LTCC / HTCC co-fired solutions.

[0019] On the other hand, by setting solder layers with different melting points on the surfaces to be soldered and welding them layer by layer in order of melting point from high to low, the current welding temperature is always lower than the melting point of the solder of the already welded layers. This avoids connection failure or interlayer misalignment caused by the lower layer solder joints remelting due to heat during the multi-layer stacking process. Combined with the excellent insulation, dimensional stability and dielectric properties of the ceramic substrate itself, a highly reliable and hermetic three-dimensional stacked package with high airtightness between multi-layer substrates is finally achieved. Moreover, the entire process is based on the independent processing of a single substrate before assembly, which greatly improves process flexibility and product yield, and reduces the development cycle and manufacturing cost. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a general process flow diagram disclosed in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of slurry filling in an embodiment of the present invention.

[0023] Figure 3 This is an internal assembly diagram of the cavity disclosed in an embodiment of the present invention.

[0024] Figure 4 This is a three-dimensional assembly diagram disclosed in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] This invention aims to provide an integrated assembly and packaging method for multilayer ceramic substrates. The method uses independently processed ceramic substrates as basic assembly units, achieves electrical interconnection between the upper and lower surfaces by filling conductive materials through through holes, fabricates high-precision conductive patterns through thin-film technology and simultaneously achieves hermetic sealing of the through hole ports, and avoids remelting of solder joints during multilayer stacking by setting solder layers with different melting points and welding them layer by layer in order of melting point from high to low, ultimately forming a highly reliable and hermetic three-dimensional stacked packaging structure.

[0027] Please see Figure 1 The method mainly includes: substrate preparation, through-hole filling, surface treatment, conductive pattern forming, solder layer prefabrication, and stack-up assembly. Each step is described in detail below.

[0028] I. Substrate Preparation Steps In the substrate preparation step, at least two ceramic substrates are provided. The preferred material for these ceramic substrates is alumina ceramic, which has a low dielectric constant (approximately 9.9), effectively reducing transmission loss under high-frequency operating conditions. Simultaneously, alumina ceramic possesses good insulation and structural rigidity, providing reliable mechanical protection for the internal chips and interconnect structures. In other embodiments, aluminum nitride ceramic or other suitable ceramic materials may also be used as the ceramic substrates.

[0029] The thickness of each ceramic substrate 10 can be selected according to the actual application requirements, generally 0.1~1.0mm. The substrate shape is preferably rectangular, but it can also be processed into a circle or other shapes according to the packaging structure requirements.

[0030] In the substrate preparation step, through-holes are also formed on each ceramic substrate. These through-holes are used to achieve electrical interconnection between the upper and lower surfaces of the ceramic substrate. The fabrication method for the through-holes is selected based on the hole diameter.

[0031] In some embodiments, when the target diameter of the through hole is 0.1~0.4mm, laser processing is preferred to form the through hole. Laser processing has the advantages of high processing accuracy, small heat-affected zone, and suitability for small-diameter hole processing. The laser processing parameters are appropriately selected according to the material and thickness of the ceramic substrate to ensure that the inner wall of the through hole is smooth and crack-free.

[0032] In other embodiments, when the target diameter of the through hole is greater than 0.5 mm, machining is preferably used to form the through hole. Machining is efficient and suitable for machining through holes with larger diameters.

[0033] The via is preferably circular, but can also be square or other shapes as needed. The distribution of the via on the ceramic substrate is determined by the circuit design, and multiple vias can be arranged in an array or flexibly according to wiring requirements.

[0034] On the same ceramic substrate, through holes of different diameters can coexist, which are completed using a combination of laser processing and machining. That is, small-diameter through holes are processed by laser processing, while large-diameter through holes are processed by machining, balancing processing accuracy and efficiency.

[0035] In the substrate preparation step, for implementations that need to accommodate active and / or passive devices, cavities are also formed on the ceramic substrate. The cavities can be formed using laser processing or mechanical processing. The depth of the cavity is determined based on the thickness of the device to be accommodated, typically 0.2~0.8 mm. The bottom surface of the cavity should be flat to facilitate subsequent mounting of devices within the cavity using methods such as bonding, welding, or wire bonding.

[0036] For ceramic substrates that do not require mounting devices, or ceramic substrates used as top-level encapsulation covers, no cavity processing is required.

[0037] After completing the above processing, the ceramic substrate is cleaned to remove dust and debris generated during processing. It is then dried for later use.

[0038] II. Filling Steps for Through Holes The through-hole filling step is used to fill each through-hole with conductive material to achieve electrical interconnection between the upper and lower surfaces of the ceramic substrate. In this embodiment, the conductive material is preferably conductive silver paste. Conductive silver paste has the advantages of good conductivity, strong adhesion to the ceramic substrate, moderate sintering temperature, and low cost. In other embodiments, conductive copper paste or conductive gold paste can also be used as the filling material.

[0039] In a preferred embodiment, the through-hole is filled by applying silver paste to the front side and vacuuming the back side, using negative pressure to draw in the conductive silver paste and fill the through-hole.

[0040] Specifically, a ceramic substrate is placed on a vacuum fixture, which has evacuation holes corresponding to the positions of the through-holes. Conductive silver paste is applied to the front (upper) surface of the ceramic substrate using a scraper, covering the upper port of the through-hole. Simultaneously, a vacuum pump connected to the vacuum fixture creates negative pressure at the lower port of the through-hole through the evacuation holes. Under this negative pressure, the conductive silver paste is drawn into the through-hole and flows out from the lower port, ensuring the through-hole is completely filled with conductive silver paste without any voids.

[0041] The time for applying vacuum is determined based on the diameter and depth of the through hole, typically ranging from 5 to 30 seconds. The vacuum level is preferably 10 to 100 Pa to ensure sufficient suction effect.

[0042] To ensure that the silver paste fills the through holes completely, the scraping and vacuuming operations can be repeated multiple times until it is confirmed that all through holes are filled.

[0043] After the through-holes are filled, the ceramic substrate filled with conductive silver paste is sintered and cured. The sintering temperature is determined according to the composition of the conductive silver paste, usually 700~900℃, and the sintering time is 15~20min. After sintering and curing, the organic carrier in the conductive silver paste volatilizes or decomposes, and the silver particles sinter together to form a continuous conductive path. The cured silver pillars are firmly attached to the inner wall of the through-holes.

[0044] III. Surface Treatment Steps After sintering and solidification, a surface treatment step is performed to remove excess conductive silver paste protruding from the substrate surface. In this embodiment, mechanical polishing is used to grind both the upper and lower surfaces of the ceramic substrate. After polishing, the end faces of the silver pillars are flush with the surface of the ceramic substrate; that is, the upper end face of the silver pillar is on the same plane as the upper surface of the ceramic substrate, and the lower end face of the silver pillar is on the same plane as the lower surface of the ceramic substrate. This flush structure facilitates the fabrication of conductive patterns in subsequent thin-film processes and avoids defects or broken lines caused by protrusions on the substrate surface during thin-film deposition.

[0045] After polishing, the ceramic substrate is thoroughly cleaned to remove dust and residue generated during grinding; it is then dried.

[0046] IV. Conductive Pattern Forming Steps The conductive pattern forming step employs thin-film technology to form conductive patterns on the surface of each ceramic substrate. Those skilled in the art will understand that thin-film technology offers higher pattern precision compared to traditional thick-film printing processes, enabling high-density wiring with linewidths and / or line spacings not exceeding 20 μm, far surpassing the approximately 150 μm linewidth limit in LTCC / HTCC sintered multilayer solutions.

[0047] Specifically, thin film processing includes photolithography patterning and film formation.

[0048] In the photolithography patterning step, a photoresist layer is first coated onto the surface of the ceramic substrate. After coating, a pre-baking process is performed to remove some of the solvent from the photoresist. After pre-baking, a photomask with the target pattern is aligned with the photoresist-coated ceramic substrate, and the photoresist is exposed using an exposure device. After exposure, a development process is performed to remove the photoresist from the exposed or unexposed areas, revealing the locations where conductive patterns need to be formed. After development, a hardening process is performed, where heating further solidifies the remaining photoresist, improving its etch resistance.

[0049] In the film deposition step, a metal layer is deposited on the surface of a ceramic substrate with patterned windows using physical vapor deposition or chemical vapor deposition. The preferred deposition method is magnetron sputtering deposition, but electron beam evaporation deposition or chemical vapor deposition can also be used. The deposited metal layer covers both the exposed ceramic substrate surface and the remaining photoresist layer surface. After film deposition, a lift-off process is performed to remove the metal layer covering the photoresist layer along with the photoresist layer, leaving the metal layer deposited on the ceramic substrate surface, forming a conductive pattern. The minimum linewidth and / or line spacing of the conductive pattern does not exceed 20 μm to meet the requirements of high-density packaging.

[0050] The conductive pattern covers both the upper and lower ports of the through-hole, forming a continuous metallic overlay at both ends of the through-hole. This metallic overlay completely covers the end face of the silver pillar and the interface between the silver pillar and the ceramic substrate, sealing the upper and lower ports of the through-hole to achieve a hermetically sealed connection.

[0051] Those skilled in the art should understand that the advantages of this hermetically sealed connection are: on the one hand, the metal cover layer blocks the communication path between the through hole and the external environment, preventing moisture, oxygen or other harmful atmospheres from entering the package through the through hole; on the other hand, the metal cover layer forms good electrical contact with the silver pillar, ensuring reliable transmission of electrical signals; and furthermore, the metal cover layer is tightly bonded to the surface of the ceramic substrate, exhibiting high bonding strength and long-term reliability.

[0052] It should be noted that for ceramic substrates with cavities fabricated in the substrate preparation step, conductive patterns should be fabricated away from the cavity area. Conductive patterns should not be fabricated on the sidewalls and bottom of the cavity to avoid affecting the subsequent mounting of devices inside the cavity.

[0053] After the conductive pattern is fabricated, the ceramic substrate is subjected to electrical performance tests, including testing the continuity resistance of each through hole and the insulation resistance between adjacent lines, to ensure that the conductive pattern meets quality standards.

[0054] V. Solder Layer Pre-fabrication Steps The solder layer prefabrication step involves prefabricating a solder layer on at least one of the surfaces to be soldered in two adjacent ceramic substrates. In actual processes, the solder layer only needs to be applied to one of the opposing upper and lower surfaces of the adjacent substrates, while the other surface only needs to retain a metal layer that can be wetted by the solder. During soldering, the molten solder will naturally spread and wet the metal surface, forming a strong metallurgical bond. Applying a solder layer to only one side not only saves on the amount of expensive gold-tin solder but also reduces the difficulty of alignment and thickness control before soldering.

[0055] In this embodiment, the solder layer is preferably gold-tin (AuSn) solder. Gold-tin solder has excellent solderability, high corrosion resistance, and good thermal fatigue characteristics, making it suitable for high-reliability packaging.

[0056] The solder layer is pre-formed on the surface of the ceramic substrate to be soldered using thin-film deposition or electroplating. For interfaces requiring interlayer bonding, the solder layer is disposed at the corresponding pad positions, blank support positions, and edge annular regions of the conductive patterns on at least one of the adjacent substrates.

[0057] The thickness of the solder layer is determined according to the welding requirements, and is preferably 4~8μm.

[0058] In this embodiment, the solder layers used between different ceramic substrates have different gold-tin ratios to create a melting point gradient during subsequent layer-by-layer soldering. Specifically, the solder layers are selected from at least two of AuSn18 alloy layers, AuSn20 alloy layers, and AuSn21 alloy layers.

[0059] Gold-tin alloys exhibit a relatively low melting point (approximately 280°C) near the eutectic composition (AuSn20, i.e., 80 wt% gold and 20 wt% tin). The melting point increases as the gold-tin ratio deviates from the eutectic composition. Specifically, the liquidus temperature of AuSn18 (82 wt% gold and 18 wt% tin) is approximately 290°C, that of AuSn20 is 280°C, and that of AuSn21 (79 wt% gold and 21 wt% tin) is approximately 285°C. By selecting different gold-tin ratios, a stepped melting point difference can be achieved within the 280–290°C range.

[0060] In a preferred embodiment, the solder layer comprises three solders with different gold-tin ratios: an AuSn18 solder layer, an AuSn20 solder layer, and an AuSn21 solder layer, with melting points of approximately 290°C, approximately 280°C, and approximately 285°C, respectively. By strategically arranging the positions of the solder layers with different ratios within the laminated structure, a layer-by-layer distribution of melting points from high to low can be achieved.

[0061] To achieve a more pronounced melting point gradient in multilayer stacks, gold-tin ratios can be selected over a wider range of compositions, such as AuSn15 (melting point approximately 310°C) and AuSn25 (melting point approximately 295°C), to further widen the melting point difference between layers.

[0062] The solder layer is preferably prefabricated as a continuous annular structure. Specifically, on the surface of the ceramic substrate to be soldered, the solder layer forms a closed ring along the edge region of the substrate, which surrounds the conductive patterns and through holes within the region. When adjacent ceramic substrates are soldered through this annular structure, the annular solder melts and forms an annular sealing solder band, achieving electrical interconnection and mechanical connection while completely isolating the internal region of the substrate from the external environment, thus achieving hermetically sealed interlayer packaging.

[0063] It should be noted that the width of the annular structure is determined based on the substrate size and welding strength requirements, and is preferably 0.5~2mm. The annular structure should be continuous and uninterrupted to ensure airtightness.

[0064] After the solder layer is prefabricated, the surface of the solder layer is cleaned to remove surface oxides and contaminants.

[0065] VI. Stacking Assembly Steps The stacking assembly step involves stacking the ceramic substrates along the thickness direction so that the surfaces to be soldered on adjacent ceramic substrates are facing each other and the adjacent solder layers are in contact with each other. Then, the layers are soldered one by one in order of melting point from high to low.

[0066] Specifically, the ceramic substrates that have completed the aforementioned steps are stacked sequentially in a predetermined order, and the correspondence between each layer is precisely aligned using positioning marks (positioning pins or optical marks). In the stacked structure, the transmission of interlayer electrical signals is accomplished through the paths formed by silver pillars in the through-holes and conductive patterns.

[0067] In terms of soldering sequence, the solder layer with the highest melting point is soldered first, followed by the solder layers with lower melting points. Specifically, assuming a three-layer ceramic substrate stack, the solder layer between the bottom and middle layers uses AuSn18 (melting point approximately 290℃), and the solder layer between the middle and top layers uses AuSn21 (melting point approximately 285℃). During soldering, the bottom and middle layers are soldered first at a temperature of approximately 290~295℃, and then the middle and top layers are soldered at a temperature of approximately 285~290℃. During the second soldering process, because the soldering temperature is lower than the melting point of the already soldered AuSn18 solder, the solder joints will not remelt, thus ensuring the reliability of the soldered layers.

[0068] Layer-by-layer welding employs a high-temperature, short-time welding process, meaning the welding temperature is relatively high (as close as possible to the melting point of the already welded solder while ensuring no remelting), but the welding time is relatively short. In some embodiments, layer-by-layer welding uses a peak temperature of 290~350℃ and a holding time of 25~40s to form an intermetallic compound layer at the welding interface, thereby inhibiting heat transfer to the already welded layers; and pressure is maintained throughout the welding process to ensure tight adhesion between the layers.

[0069] The advantage of this welding process is that: First, at higher welding temperatures, the solder melts fully, rapidly forming a high-quality intermetallic compound layer and resulting in a high-strength weld joint.

[0070] Secondly, when the welding time is short, the heat is confined to the area near the welding interface. The low thermal conductivity of the ceramic substrate itself delays the transfer of heat to the welded lower layer, so that the temperature of the welded layer is always kept below the melting point.

[0071] Third, the pressure applied throughout the welding process enables atomic diffusion and intermetallic compound formation at the welding interface to be completed in a shorter time, thus shortening the high-temperature dwell time.

[0072] In embodiments where cavities are fabricated during substrate preparation, active and / or passive devices are assembled within the cavities before all ceramic substrates are soldered. In some embodiments, electrical interconnection between the devices and conductive patterns is achieved through bonding, such as... Figure 3 As shown. Specifically, a wire bonding process is used, employing gold wires to connect the chip's pads to corresponding pads in the conductive pattern on the surface of the ceramic substrate. In other embodiments, the device can also be connected to the conductive pattern via flip-chip bonding, i.e., bumps are prepared on the device's pads, and the device is flipped over and aligned with the pads of the conductive pattern for soldering.

[0073] After the components within the cavity are assembled and bonded, the top ceramic substrate is then placed on top. The top ceramic substrate acts as a package cover, enclosing the cavity containing active and / or passive components within the multilayer ceramic substrate stack structure. The bottom surface of the top ceramic substrate also has a pre-installed solder layer, which is then welded to the underlying ceramic substrate for a sealed connection.

[0074] In some implementations, the order of the through-hole filling step and the conductive pattern forming step is interchanged. That is, the conductive pattern forming step is performed first, followed by the through-hole filling step.

[0075] In some embodiments, conductive silver paste is injected using a dispensing method during the through-hole filling step, such as... Figure 2As shown. Specifically, the dispensing needle is placed at the bottom of the through-hole, and conductive silver paste is dispensed at a set flow rate using a precision dispensing machine, while the dispensing needle is controlled to rise at a uniform speed. As the dispensing needle rises, the conductive silver paste is continuously injected into the through-hole until it is completely filled. After filling, a slightly convex silver paste ball is formed at the upper end of the through-hole, ensuring that the silver paste is completely filled without any voids.

[0076] This invention also protects multilayer ceramic substrate packages manufactured using the above method, such as... Figure 4 As shown. The ceramic substrate is made of alumina ceramic; adjacent ceramic substrates are connected by a gold-tin solder layer, and the gold-tin ratio varies between different layers of the package.

[0077] In one specific embodiment, the package includes five ceramic substrates stacked one on top of the other, with adjacent ceramic substrates welded together by a gold-tin solder layer, the solder layer forming an annular sealing weld band at the edge region; some ceramic substrates have cavities inside, in which chips and resistive and capacitive components are installed, and the chips are bonded to conductive patterns by gold wires; through holes are filled with silver pillars, and conductive patterns cover both ends of the through holes to achieve hermetically sealed connection; the top ceramic substrate acts as a package cover to seal the cavity.

[0078] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for integrated assembly and packaging of multilayer ceramic substrates, characterized in that, Includes the following steps: At least two ceramic substrates are provided, each of which has a through hole; Each of the through holes is filled with conductive material, and the end face of the conductive material is flush with the surface of the corresponding ceramic substrate. Conductive patterns are formed on the surface of each of the ceramic substrates using a thin-film process; and the conductive patterns are made to cover the port of the through hole to form an airtight opening; Solder layers are formed on the surfaces to be soldered of at least one of the two adjacent ceramic substrates, and at least a portion of the solder layers have different melting points; The ceramic substrates are stacked along the thickness direction and welded layer by layer in order of decreasing melting point; wherein the welding temperature of the current welding layer is lower than the melting point of the solder of the previously welded layers.

2. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, The step of filling each of the through holes with conductive material specifically includes: The conductive paste is drawn in and filled into each of the through holes by vacuum suction, and then cured. Excess conductive paste that overflows onto the surface of the corresponding ceramic substrate is removed by mechanical polishing, so that the end face of the conductive material is flush with the surface of the corresponding ceramic substrate.

3. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1 or 2, characterized in that, The conductive material is conductive silver paste.

4. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, The thin film process includes photolithography and film deposition; the minimum linewidth and / or line spacing of the conductive pattern is less than or equal to 20 μm.

5. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, At least a portion of the solder layer is selected from at least two of AuSn18, AuSn20, and AuSn21 to form a stepped melting point gradient.

6. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, The layer-by-layer welding process employs a peak temperature of 290~350℃ and a holding time of 25~40s to form an intermetallic compound layer at the welding interface, thereby inhibiting heat transfer to the welded layers; and pressure is maintained throughout the welding process to ensure tight adhesion between the layers.

7. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, The solder layer is prefabricated into a continuous ring structure, and an annular sealing welding strip is formed between adjacent substrates through the ring structure.

8. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 1, characterized in that, At least one of the ceramic substrates has a cavity pre-processed thereon for accommodating active devices and / or passive devices.

9. The integrated assembly and packaging method for multilayer ceramic substrates according to claim 8, characterized in that, Before all the ceramic substrates are soldered, active devices and / or passive devices are assembled in the cavity by bonding or welding; and the topmost ceramic substrate acts as a cover plate to seal the cavity.

10. A multilayer ceramic substrate package, characterized in that, Manufactured using the method described in any one of claims 1-9.

11. The multilayer ceramic substrate package according to claim 10, characterized in that, The ceramic substrate is made of alumina ceramic; adjacent ceramic substrates are welded together by a gold-tin solder layer, and the gold-tin solder layer has different gold-tin ratios in different layers of the package.

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