A method for manufacturing a multilayer ceramic substrate

Abstract

The application discloses a manufacturing method of a multilayer ceramic substrate, comprising the following steps: forming a conductive circuit on a sintered ceramic substrate; sequentially forming an insulating layer and a through hole, so that the through hole exposes part of the conductive circuit; then, filling the through hole with a conductive filling material and solidifying the conductive filling material to form a solid interlayer through hole body; performing a planarization treatment on the structure after solidification, so that the top of the conductive filling structure is flush with the surface of the insulating layer, and a conductive connection area is exposed; repeating the foregoing steps to form an intermediate layer conductive circuit and an intermediate insulating layer on the planarized surface until all the multilayer interconnection structures are completed, and finally manufacturing a top layer conductive circuit and a pad structure. The application does not use a plating thickening process to form the conductive circuit, and does not use a plating hole filling process to form the interlayer through hole structure, so that the process is simplified, the cost is reduced, the accumulation of metal steps is eliminated, and the reliability of interlayer interconnection is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and specifically relates to a method for manufacturing a multilayer ceramic substrate. Background Technology

[0002] Multilayer ceramic substrates (MLCs) are widely used in microelectromechanical systems (MEMS) device packaging, semiconductor test substrates, RF microwave modules, and high-density electronic packaging due to their excellent insulation properties, thermal stability, and high-density wiring capabilities. In these applications, MLCs require the formation of reliable interlayer conduction structures between different conductor layers to achieve vertical interconnection of electrical signals.

[0003] Currently, the interlayer conductive structure of multilayer ceramic substrates is mainly manufactured using the following process: First, vias are created on each green ceramic layer using laser processing or photolithography. Then, a seed layer is deposited on the substrate surface and via walls using processes such as physical vapor deposition (PVD) to make the via walls conductive. Based on this, the conductive layer on the via walls is thickened through multiple patterning electroplating processes to form the required interlayer conductive structure and surface pattern circuitry. As the number of substrate layers increases, the intermediate layers need to repeatedly undergo a series of processes, including seed layer sputtering or deposition, photolithography, electroplating thickening, electroplating filling, resist removal, and flash etching, to complete the fabrication of the conductive structure and interlayer stacking.

[0004] The aforementioned traditional manufacturing processes have the following technical problems:

[0005] First, the process is complex and the manufacturing cost is high. Each time a new layer is stacked, the seed layer deposition, photolithography, electroplating thickening, and electroplating filling processes need to be repeated. As the number of layers increases, the number of times the processes are repeated increases exponentially, making the overall manufacturing process very cumbersome, with large equipment investment and material consumption, which significantly increases production costs.

[0006] Secondly, it can easily form large metal steps, affecting the quality of subsequent processes. During multiple electroplating thickening and pattern electroplating for via filling, a significant height difference, i.e., a metal step, can easily form between the via area and the surrounding circuit area. This metal step will worsen the lamination flatness of the subsequent insulating dielectric layer and reduce the resolution and alignment accuracy during high-precision photolithography, thereby affecting the circuit fineness and interlayer bonding reliability of the multilayer ceramic substrate.

[0007] Third, the manufacturing cycle is long. Since the interlayer conductive structure mainly relies on the metallization of the hole walls and repeated electroplating to thicken the conductive path, the entire multilayer stacking process involves a large number of electroplating processes and a long time for each electroplating, which greatly extends the product manufacturing cycle and is not conducive to improving production efficiency and responding quickly to market demands.

[0008] Therefore, the existing manufacturing technology for interlayer conductive structures of multilayer ceramic substrates still has significant shortcomings in terms of process complexity, surface flatness, and manufacturing cycle, and urgently needs to be improved. Summary of the Invention

[0009] The purpose of this application is to overcome the shortcomings of the prior art and provide a manufacturing method for a multilayer ceramic substrate based on conductive filled vias and subtractive interconnection routes. This method simplifies the fabrication process, reduces the need for intermediate layer pattern electroplating thickening and electroplating via filling processes, improves the flatness of the multilayer ceramic substrate, and reduces manufacturing costs.

[0010] To achieve the above objectives, the technical solution adopted in this application is: a method for manufacturing a multilayer ceramic substrate, comprising the following steps:

[0011] S1) Provide a sintered ceramic substrate as a base material;

[0012] S2) Conductive lines are formed on the ceramic substrate using a subtractive process;

[0013] S3) An insulating layer is formed on the surface on which the conductive lines are formed;

[0014] S4) A via is formed in the insulating layer, the via exposing a portion of the conductive circuit;

[0015] S5) The conductive filling material is used to fill the through hole and cured to form a conductive filling structure, so that the conductive filling structure constitutes the interlayer conductive body that penetrates the insulating layer.

[0016] S6) Perform planarization to expose the top of the conductive filling structure, forming an exposed conductive connection area, and make the top of the conductive filling structure flush with the surface of the insulating layer;

[0017] S7), Repeat steps S2)-S6) until all conductive lines are fabricated;

[0018] S8) On the surface of the top insulating layer, a seed layer is deposited, and after photolithography, electroplating is performed to form the top conductive lines and several pads. The photoresist and excess seed layer are then removed.

[0019] In one feasible embodiment, during the formation of all intermediate layers, the conductive lines of each intermediate layer establish electrical connections with the adjacent exposed conductive connection areas through direct contact to achieve interlayer conductivity.

[0020] In one feasible embodiment, step S2) specifically includes:

[0021] S21) Deposit a seed layer on the corresponding substrate surface;

[0022] S22) Photoresist is coated on the seed layer and exposed and developed to form a circuit pattern;

[0023] S23) Remove the seed layer of non-circuit pattern areas using an etching process;

[0024] S24) Remove the photoresist to obtain the desired patterned conductive lines.

[0025] In one feasible embodiment, the seed layer is a Ti / Cu composite layer, wherein the thickness of the Ti layer is 20-100 nm and the thickness of the Cu layer is 0.8-1.5 μm.

[0026] In one feasible embodiment, the conductive filler material is a metal particle-filled conductive paste, including conductive silver paste or conductive copper paste.

[0027] In one feasible embodiment, the diameter of the through hole is 30-50 μm and the depth is 10-30 μm.

[0028] In one feasible embodiment, the insulating layer is an organic insulating layer with a thickness of 10-30 μm.

[0029] In one feasible embodiment, after the planarization process and before the formation of the intermediate layer conductive lines, a plasma cleaning step is further included on the planarized surface.

[0030] In a feasible embodiment, in step S8), a Cu layer, a Ni layer, and an Au layer are sequentially deposited on the exposed top seed layer by a pattern electroplating process to form the top conductive line and several pads; wherein the Cu layer formed by the pattern electroplating has a thickness of 5-10 μm, the Ni layer has a thickness of 1-2 μm, and the Au layer has a thickness of 80-150 nm.

[0031] In one feasible embodiment, the ceramic substrate has embedded conductive lines, conductive pillars, or other conductive structures.

[0032] In one feasible embodiment, after completing step S8), a solder resist coating is fabricated, and windows are precisely opened on the coating to expose the metal pads that need to be soldered, thus completing the fabrication of the multilayer ceramic substrate.

[0033] The multilayer ceramic substrate manufacturing method disclosed in this patent application has the following significant advantages over the traditional technical route that relies on multiple electroplating thickening and electroplating filling:

[0034] 1. The conductive paste is used to fill the through holes and directly solidify to form the conductive body, which greatly reduces the manufacturing steps, simplifies the manufacturing process, and shortens the production cycle.

[0035] 2. By eliminating a large number of electroplating processes in the intermediate layer, this method significantly reduces the consumption of precious metal materials (such as copper) and electroplating solutions, while also reducing the amount of related chemical reagents, photoresist, resist remover and etching solution used, effectively reducing manufacturing costs.

[0036] 3. This method involves direct chemical mechanical polishing (CMP) planarization after filling with conductive paste, which enables the conductive filling structure to be perfectly flush with the surface of the insulating layer. This fundamentally eliminates the problem of metal step accumulation, significantly improves the overall flatness of the multilayer structure, and thus ensures the subsequent insulating layer lamination quality and photolithography alignment accuracy, thereby improving the quality of subsequent processes.

[0037] 4. This method uses conductive filler material to completely fill the via and penetrate the entire thickness of the insulating layer, forming a continuous, solid conductive path as the main structure for interlayer conduction. Compared with the traditional structure that only relies on the metallization of the via walls, this bulk conductive structure has lower resistance and stronger resistance to thermomechanical stress. The interlayer connection interface is directly contacted through the seed layer, which effectively improves the long-term reliability and electrical performance stability of the interlayer interconnection. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a multilayer ceramic substrate given in one embodiment of this application.

[0039] The structure consists of: 1. Ceramic substrate; 2. First conductive layer; 3. First insulating layer; 4. Conductive filling structure; 5. Second conductive layer; 6. Second insulating layer; 7. Top conductive layer. Specific Implementation

[0040] To illustrate the technical content, structural features, achieved objectives, and effects of the invention in detail, the technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. In the following description, for illustrative purposes, numerous specific details are set forth to provide a detailed description of various exemplary embodiments or implementations of the invention. However, various exemplary embodiments may also be implemented independently without these specific details or in one or more equivalent arrangements. Furthermore, the various exemplary embodiments may differ, but are not necessarily exclusive. For example, the specific shape, construction, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0041] This application discloses a method for manufacturing a multilayer ceramic substrate. The method involves forming the multilayer ceramic substrate based on conductive-filled vias and subtractive interconnection paths. Electroplating for thickening is not used in the step of forming conductive lines, and electroplating for via filling is not used in the step of forming the interlayer conductive bodies. This application can improve the flatness of the multilayer ceramic substrate, reduce manufacturing costs, simplify process steps, and shorten the manufacturing cycle.

[0042] Specifically, the method for manufacturing a multilayer ceramic substrate includes the following steps:

[0043] Step S1) Provide a sintered ceramic substrate as a base material.

[0044] In some embodiments, the substrate may have some conductive lines and vertical conductive pillars pre-embedded inside according to the design, and the substrate surface is clean and flat, ready for subsequent processes.

[0045] Step S2) Forming conductive lines on the ceramic substrate using a subtractive method, specifically including:

[0046] S21) Deposit a seed layer on the corresponding substrate surface;

[0047] S22) Photoresist is coated on the seed layer and exposed and developed to form a conductive circuit pattern;

[0048] S23) Remove the seed layer of non-circuit pattern areas using an etching process;

[0049] S24) Remove the photoresist to obtain the desired patterned conductive lines.

[0050] In some embodiments, the seed layer is a Ti / Cu composite layer, wherein the thickness of the Ti layer is 20-100 nm and the thickness of the Cu layer is 0.8-1.5 μm.

[0051] Step S3) On the surface where the conductive lines are formed, an organic insulating layer (e.g., photosensitive polyimide) with a thickness of 10-30 μm is formed by spin coating or lamination. This insulating layer completely covers the conductive lines and is cured to form the subsequent interlayer insulation structure.

[0052] Step S4) A via is formed in the insulating layer using photolithography or laser processing. The via penetrates the insulating layer and exposes part of the conductive circuit.

[0053] In some embodiments, the diameter of the through hole is 30-50 μm and the depth is 10-30 μm.

[0054] Step S5) Fill the through holes with conductive filler material and cure it to form a conductive filler structure, so that the conductive filler structure constitutes the interlayer conductive body that penetrates the insulating layer.

[0055] The conductive filler material is a metal particle-filled conductive paste, including conductive silver paste or conductive copper paste. Vacuum screen printing or stencil printing processes are used to fully fill all the through-holes formed in step 4 with the conductive filler material, followed by curing to ensure good contact between the conductive filler material and the exposed conductive lines at the bottom.

[0056] In some embodiments, the ceramic substrate with the vias filled can be placed in an oven for thermosetting to accelerate the volatilization of the organic carrier in the conductive filler material and the sintering or densification of the metal particles, forming a solid silver conductive filler structure that extends through the thickness of the insulating layer within the vias. This structure will serve as the main interlayer conductive conductor for this layer and all subsequent intermediate layers.

[0057] (Step S6) After the conductive filler material has cured, some overflow or slight protrusion is inevitable at the opening of the via. At this point, the entire surface of the ceramic substrate is planarized to remove excess conductive filler material residue from the opening and the surface of the insulating layer until the top of the conductive filler structure is completely flush with the surrounding insulating layer surface, forming an exposed, flat conductive connection area. Chemical mechanical polishing (CMP) is the preferred method for planarization.

[0058] After CMP treatment, the surface of the ceramic substrate is plasma cleaned to thoroughly remove organic contaminants and particles remaining from polishing, activate the surface, and provide a clean and well-adhesive substrate for the deposition of the next seed layer.

[0059] Step S7) Using the same method, repeat steps S2) to S6) to continue fabricating intermediate conductive lines and intermediate insulating layers on the surface of the planarized insulating layer. The process and materials are the same as in steps S2) to S6) until all conductive lines are fabricated.

[0060] During the formation of all intermediate layers, the conductive lines of each intermediate layer establish electrical connections with the adjacent exposed conductive connection areas through direct contact to achieve interlayer conductivity.

[0061] Specifically, a Ti / Cu seed layer is redeposited on the planarized insulating layer surface. This seed layer continuously covers the exposed conductive regions formed by the Pi surface and conductive filling structures. The Ti thickness is 20-100 nm, and the Cu thickness is 0.8-1.5 μm. Subtractive methods are then used to form the conductive path pattern, including: applying photoresist to the seed layer surface; photolithography to form a new conductive path pattern; etching to remove the background seed layer; removing the photoresist; and forming intermediate layer interconnects. The formed paths establish electrical connections between the seed layer and the exposed conductive connection regions, achieving conductivity between adjacent circuit layers. Note that all intermediate layer conductive lines are formed using subtractive methods without electroplating for thickness enhancement, and all intermediate layer conductive structures do not use electroplating for via filling.

[0062] Then, an intermediate insulating layer is formed on the intermediate conductive line, and a via is drilled in the intermediate insulating layer. The via is then filled and cured. CMP planarization is then performed until the required number of layers of multilayer interconnect structure is completed. The interlayer conduction is mainly carried out by the conductive filling structure. The seed layer and conductive path formed later are mainly used to establish the interlayer connection interface.

[0063] Step S8) On the surface of the top insulating layer, a seed layer is deposited, photoresist is coated, and then the pattern is photolithographically patterned and electroplated to form the top conductive lines and several pads. Then the photoresist is removed, and the seed layer covered by the photoresist is quickly etched away by flash etching process to finally form a top line and pad structure with complete structure and thickness that meets the packaging requirements.

[0064] In some embodiments, a Cu layer, a Ni layer, and an Au layer are sequentially deposited on the exposed top seed layer using a patterned electroplating process to form the top conductive lines and several pads; wherein the Cu layer formed by the patterned electroplating has a thickness of 5-10 μm, the Ni layer has a thickness of 1-2 μm, and the Au layer has a thickness of 80-150 nm.

[0065] After completing step S8), a solder resist coating is made, and windows are precisely opened on the coating to expose the metal pads that need to be soldered, thus completing the manufacturing of the multilayer ceramic substrate.

[0066] The multilayer ceramic substrate obtained by the above method, such as Figure 1As shown, the structure includes a ceramic substrate 1, multiple conductive lines 2 and 5, and multiple organic insulating layers 3 and 6. Each organic insulating layer 3 and 6 has vias filled with conductive filler material, which, after curing, forms a conductive filler structure 4. The conductive filler structure 4 connects adjacent conductive lines 2 and 5, ultimately forming a multi-layer interconnect structure. Above the top insulating layer, a top conductive line 7 and several pads are also formed. Specifically: adjacent conductive line layers are electrically connected through the conductive filler structure, which extends through the thickness of the insulating layer to form a continuous conductive path. The top of the conductive filler structure is CMP-treated to form an exposed conductive connection area. The upper layer path establishes an electrical connection with the exposed connection area through a seed layer. The intermediate layers are formed using a subtractive method to create conductive paths. The intermediate path layers do not include patterned electroplating thickening structures, and the intermediate layer conductive structures do not include electroplated via filling structures. The top pads are formed using patterned electroplating.

[0067] The following is an illustration using a specific example. Figure 1 The manufacturing process of the multilayer ceramic substrate shown specifically includes:

[0068] 1. Provide a sintered MLC ceramic substrate 1, on which a Ti / Cu seed layer is deposited, the thickness of the Ti layer is 60nm and the thickness of the Cu layer is 800nm.

[0069] 2. The first layer of conductive circuit 2 is formed by subtraction method.

[0070] 3. A first insulating layer 3 of 15 micrometers is formed on the surface of the first conductive line 2, and a via with a diameter of 45 micrometers is formed by photolithography.

[0071] 4. Fill the vias with silver paste and cure it to form a conductive filling structure.

[0072] 5. The surface is polished using CMP process to make the top of the conductive filling structure 4 flush with the first insulating layer 3, thus forming an exposed conductive connection area.

[0073] 6. A Ti / Cu seed layer is redeposited on the surface of the first insulating layer 3, and a second conductive circuit 5 is formed by subtractive deposition.

[0074] 7. Repeat the process of forming a second insulating layer 6 on the surface of the second conductive line 5, and photolithographically forming several vias. Then, continue to fill the vias with silver paste and cure to form a conductive filling structure 4.

[0075] 8. On the surface of the second insulating layer 6, a Ti / Cu seed layer is deposited, and then a patterned electroplating process is used to form the top conductive line 7 and the pad structure. The top conductive line is made of Cu / Ni / Au composite material.

[0076] 9. Complete the subsequent solder resist and windowing processes to obtain the final product.

[0077] The present invention has the following advantages:

[0078] 1. This method completely eliminates the pattern electroplating thickening and electroplating hole filling processes. Instead, conductive paste is used to fill the vias and directly solidify to form the conductive body. The manufacturing steps are greatly reduced, eliminating the lengthy cycle of repeated seed layer deposition, photolithography, electroplating thickening, electroplating hole filling, resist removal, and flash corrosion in the traditional process. The overall process flow is significantly simplified and the production cycle is greatly shortened.

[0079] 2. By eliminating numerous electroplating steps in the intermediate layer, this method significantly reduces the consumption of precious metal materials (such as copper) and electroplating solutions, while also lowering the usage of related chemical reagents, photoresist, resist remover, and etching solution. Furthermore, the shorter process chain reduces equipment occupancy, energy consumption, and labor costs, thereby effectively controlling and reducing the overall manufacturing cost.

[0080] 3. In traditional methods, multiple electroplating thickening and electroplating filling easily form significant metal steps between the via area and the circuit area. As the number of layers increases, the cumulative step effect severely affects the lamination flatness of subsequent insulating layers and the alignment accuracy of high-precision photolithography. This method, by directly performing chemical mechanical polishing (CMP) planarization after conductive paste filling, enables the conductive filling structure to be perfectly flush with the surface of the insulating layer, fundamentally eliminating the problem of metal step accumulation. This significantly improves the overall flatness of the multilayer structure, thereby ensuring the lamination quality of subsequent insulating layers and the alignment accuracy of photolithography, providing a reliable guarantee for manufacturing higher density and finer multilayer substrates.

[0081] 4. This method uses conductive filler material to completely fill the vias and penetrate the entire thickness of the insulating layer, forming a continuous, solid conductive path as the main structure for interlayer conductivity. Compared to traditional structures that rely solely on metallization of the via walls, this bulk conductive structure has lower resistance and stronger resistance to thermomechanical stress. The interlayer connection interface is directly contacted through the seed layer, effectively improving the long-term reliability and electrical performance stability of the interlayer interconnect.

[0082] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope. The scope of protection of the present invention is defined by the appended claims, specification, and their equivalents.

Claims

1. A method for manufacturing a multilayer ceramic substrate, characterized in that, Includes the following steps: S1) Provide a sintered ceramic substrate as a base material; S2) Conductive lines are formed on the ceramic substrate using a subtractive process; S3) An insulating layer is formed on the surface on which the conductive lines are formed; S4) A via is formed in the insulating layer, the via exposing a portion of the conductive circuit; S5) The conductive filling material is used to fill the through hole and cured to form a conductive filling structure, so that the conductive filling structure constitutes the interlayer conductive body that penetrates the insulating layer. S6) Perform planarization to expose the top of the conductive filling structure, forming an exposed conductive connection area, and make the top of the conductive filling structure flush with the surface of the insulating layer; S7), Repeat steps S2)-S6) until all conductive lines are fabricated; S8) On the surface of the top insulating layer, a seed layer is deposited, and after photolithography, electroplating is performed to form the top conductive lines and several pads. The photoresist and excess seed layer are then removed.

2. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, During the formation of all intermediate layers, the conductive lines of each intermediate layer establish electrical connections with the adjacent exposed conductive connection areas through direct contact to achieve interlayer conductivity.

3. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, Step S2) specifically includes: S21) Deposit a seed layer on the corresponding substrate surface; S22) Photoresist is coated on the seed layer and exposed and developed to form a circuit pattern; S23) Remove the seed layer of non-circuit pattern areas using an etching process; S24) Remove the photoresist to obtain the desired patterned conductive lines.

4. The method for manufacturing a multilayer ceramic substrate according to claim 3, characterized in that, The seed layer is a Ti / Cu composite layer, wherein the thickness of the Ti layer is 20-100 nm and the thickness of the Cu layer is 0.8-1.5 μm.

5. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, The conductive filler material is a metal particle-filled conductive paste, including conductive silver paste or conductive copper paste.

6. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, The diameter of the through hole is 30-50μm and the depth is 10-30μm.

7. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, The insulating layer is an organic insulating layer with a thickness of 10-30 μm.

8. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, After the planarization process and before the formation of the intermediate layer conductive lines, the process further includes a plasma cleaning step on the planarized surface.

9. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, In step S8), a Cu layer, a Ni layer, and an Au layer are sequentially deposited on the exposed top seed layer using a pattern electroplating process to form the top conductive line and several pads; wherein the Cu layer formed by the pattern electroplating has a thickness of 5-10 μm, the Ni layer has a thickness of 1-2 μm, and the Au layer has a thickness of 80-150 nm.

10. The method for manufacturing a multilayer ceramic substrate according to claim 1, characterized in that, The ceramic substrate has embedded conductive lines, conductive pillars, or other conductive structures inside.

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