Semiconductor package with stacked high-side and low-side field effect transistors and method of manufacturing the same

Abstract

A semiconductor package includes a leadframe, a first high-side FET, a first low-side FET, a first set of metal clips, a second high-side FET, a second low-side FET, a second set of metal clips, and a molded package. A method of manufacturing a semiconductor package includes providing a leadframe, mounting a first high-side FET and a first low-side FET, mounting a first set of metal clips, mounting a second high-side FET and a second low-side FET, mounting a second set of metal clips, forming a molded package, and performing a singulation process.

Description

Technical Field

[0001] This invention generally relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package having a stacked high-side field-effect transistor (FET) and a stacked low-side FET, and a method for manufacturing the same. Background Technology

[0002] In power device applications, semiconductor packages are becoming smaller and smaller while performance requirements are becoming higher and higher, which poses a huge challenge to achieving internal insulation of semiconductor packages.

[0003] The semiconductor package disclosed herein includes a stacked high-side FET and a stacked FET. A thinning portion is provided on a first metal clip to prevent drain-source short circuit; another thinning portion is provided on a second metal clip to prevent drain-gate short circuit. Summary of the Invention

[0004] The present invention discloses a semiconductor package comprising a lead frame, a first high-side FET, a first low-side FET, a first set of metal clips, a second high-side FET, a second low-side FET, a second set of metal clips, and a molded package body.

[0005] The present invention also discloses a method for manufacturing a semiconductor package, the method comprising the following steps: providing a lead frame; mounting a first high-side FET and a first low-side FET; mounting a first set of metal clips; mounting a second high-side FET and a second low-side FET; mounting a second set of metal clips; forming a molded package; and performing a dicing process. Attached Figure Description

[0006] Figure 1A This is a top perspective view of the semiconductor package in an embodiment of this disclosure. Figure 1B This is a 3D view of the bottom. Figure 1C This is another bottom 3D view. Figure 1D This is a top view. Figure 1E This is a side view with a partial cross-section. Figure 1F This is a side view with another section view. Figure 1G This is a breakdown diagram.

[0007] Figure 2 This is a top perspective view of another semiconductor package in an embodiment of this disclosure.

[0008] Figure 3 This is a flowchart of the semiconductor packaging manufacturing process in an embodiment of this disclosure.

[0009] Figure 4A , 4B 4C, 4D, 4E, 4F, and 4G are embodiments of this disclosure. Figure 3 The diagram shows a top-view view of each step in the semiconductor packaging manufacturing process. Detailed Implementation

[0010] Figure 1A This is a top perspective view of the semiconductor package 100 in an embodiment of this disclosure. Figure 1B This is a 3D view of the bottom. Figure 1C This is another bottom 3D view. Figure 1D This is a top view. Figure 1E This is a cross-sectional view. Figure 1F Here is another cross-sectional view. Figure 1G This is a breakdown diagram. Figure 1C In the image, the molded package is shown in a transparent form. Figure 1E For along Figure 1D Viewed from the perpendicular direction of plane AA'. Figure 1F For along Figure 1D This is observed from the vertical direction of the plane BB'.

[0011] In embodiments of this disclosure, the first high-side FET 122, the first low-side FET 124, the second high-side FET 162, and the second low-side FET 164 are all independent transistor chips, preferably double-diffused metal-oxide-semiconductor (DMOS) FETs. The semiconductor package 100 is in the shape of a first cuboid.

[0012] Reference Figure 1G The semiconductor package 100 includes a lead frame 110, a first high-side FET 122, a first low-side FET 124, a first metal clip 140, a second high-side FET 162, a second low-side FET 164, a second metal clip 180, and a molded package body 190. The first high-side FET 122 and the second high-side FET 162 are in a second cuboid shape, and the first low-side FET 124 and the second low-side FET 164 are in a third cuboid shape.

[0013] In embodiments of this disclosure, reference is made to Figure 1F The semiconductor package 100 further includes a first solder layer 102, a second solder layer 104, a third solder layer 106, and a fourth solder layer 108. A first high-side FET 122 and a first low-side FET 124 are attached to the lead frame 110 via the first solder layer 102; a first set of metal clips 140 are attached to the first high-side FET 122 and the first low-side FET 124 via the second solder layer 104; a second high-side FET 162 and a second low-side FET 164 are attached to the first set of metal clips 140 via the third solder layer 106; and a second set of metal clips 180 are attached to the second high-side FET 162 and the second low-side FET 164 via the fourth solder layer 108.

[0014] Reference Figure 1GThe lead frame 110 includes a high-side drain pad 112, a high-side gate lead 114, a low-side source pad 116, and a low-side gate lead 118.

[0015] Reference Figure 1E , Figure 1F and Figure 1G The first high-side FET 122 is mounted on the high-side drain pad 112, and its front side includes a source electrode 122S and a gate electrode 122G, and its back side includes a drain electrode 122D. The first low-side FET 124 is flip-chip mounted on the low-side source pad 116, and its front side includes a source electrode 124S and a gate electrode 124G, and its back side includes a drain electrode 124D.

[0016] The first set of metal clips 140 includes a first metal clip 142 and a second metal clip 152. The first metal clip 142 connects the source electrode 122S of the first high-side FET 122 to the drain electrode 124D of the first low-side FET 124; the second metal clip 152 connects the gate electrode 122G of the first high-side FET 122 to the high-side gate lead 114 of the lead frame 110.

[0017] The first metal clip 142 includes a thinning portion 143 in its middle section to prevent drain-source short circuits in the first high-side FET and the second high-side FET. The thinning portion 143 is located between a first groove 145 on the front side of the first metal clip 142 and a second groove 147 on the back side (opposite to the front side). The thinning portion 143 of the first metal clip 142 includes a first portion 144 and a second portion 146, wherein the first portion 144 is located between the first high-side FET 122 and the second high-side FET 162, and the second portion 146 is not located between the first high-side FET 122 and the second high-side FET 162.

[0018] The second metal clip 152 includes a thinned portion 153 for preventing short circuits in the drain gate. The thinned portion 153 is located between the first recess 155 and the opposing second recess 157. The thinned portion 153 of the second metal clip 152 includes a first portion 154 and a second portion 156, wherein the first portion 154 is located between the first high-side FET 122 and the second high-side FET 162, and the second portion 156 is not located between the first high-side FET 122 and the second high-side FET 162.

[0019] In embodiments of this disclosure, the thinned portions 143 and 153 are formed by a precision pressing process.

[0020] The second high-side FET 162 is flip-chip mounted on the side of the first metal clip 142 opposite to the first high-side FET 122. The front side of the second high-side FET 162 includes a source electrode 162S and a gate electrode 162G, and the back side includes a drain electrode 162D. The source electrode 162S of the second high-side FET 162 is connected to the first metal clip 142, and the gate electrode 162G is connected to the second metal clip 152.

[0021] The second low-side FET 164 is mounted on the side of the first metal clip 142 opposite to the first low-side FET 124. The front side of the second low-side FET 164 includes a source electrode 164S and a gate electrode 164G, and the back side includes a drain electrode 164D. The drain electrode 164D of the second low-side FET 164 is connected to the first metal clip 142.

[0022] The second set of metal clips 180 includes a third metal clip 182, a fourth metal clip 184, and a fifth metal clip 186. Specifically, the third metal clip 182 connects the drain electrode 162D of the second high-side FET 162 to the high-side drain pad 112 of the lead frame 110; the fourth metal clip 184 connects the source electrode 164S of the second low-side FET 164 to the low-side source pad 116 of the lead frame 110; and the fifth metal clip 186 connects the gate electrode 164G of the second low-side FET 164 to the low-side gate lead 118 of the lead frame 110.

[0023] The molded package 190 encloses the first high-side FET 122, the first low-side FET 124, the first metal clip 140, the second high-side FET 162, the second low-side FET 164, the majority (“major” means more than 50%) of the lead frame 110, and at least the majority of the second metal clip 180.

[0024] In embodiments of this disclosure, the semiconductor package 100 does not include bonding leads.

[0025] Reference Figure 1D The first high-side FET 122 and the first low-side FET 124 are arranged side by side in the horizontal direction (X direction); the second high-side FET 162 and the second low-side FET 164 are arranged side by side in the horizontal direction (X direction); the first high-side FET 122 and the second high-side FET 162 are aligned in the vertical direction (Z direction); the first low-side FET 124 and the second low-side FET 164 are aligned in the vertical direction (Z direction).

[0026] Reference Figure 1B The bottom surface 111 of the lead frame 110 is exposed from the molded package 190.

[0027] In one embodiment, the top surfaces of the third metal clip 282, the fourth metal clip 284, and the fifth metal clip 286 are not exposed from the molded package 290.

[0028] In another embodiment, Figure 2 This is a top perspective view of the semiconductor package 200. The top surface 283 of the third metal clip 282, the top surface 285 of the fourth metal clip 284, and the top surface 287 of the fifth metal clip 286 are all exposed from the molded package body 290.

[0029] Figure 3 This is a flowchart of a semiconductor packaging manufacturing process 300 according to an embodiment of this disclosure. This process 300 may begin at step 302 and may manufacture multiple semiconductor packages simultaneously. For example, Figure 4G This shows the simultaneous manufacturing of two semiconductor packages; however, the number of semiconductor packages manufactured simultaneously can be adjusted according to actual needs. For simplicity, Figures 4A-4F The manufacturing steps of a single semiconductor package are shown only.

[0030] In step 302, refer to Figure 4A A lead frame 410 is provided, which includes a high-side drain pad 412, a high-side gate lead 414, a low-side source pad 416, and a low-side gate lead 418. Step 304 is performed after step 302.

[0031] In step 304, by Figure 1F The first solder layer 102 attaches the first high-side FET 422 and the first low-side FET 424 to the lead frame 410. (Refer to...) Figure 4B The first high-side FET 422 is mounted on the high-side drain pad 412, and its front side includes the source electrode 422S and the gate electrode 422G, while its back side includes... Figure 1E The drain electrode 122D is included; the first low-side FET 424 is flip-chip mounted on the low-side source pad 416, the front side of which includes... Figure 1F The source electrode 124S and gate electrode 124G are included, and the drain electrode 424D is included on the back side.

[0032] The first high-side FET 422 and the first low-side FET 424 are arranged side by side in the horizontal direction (X direction). Step 306 is executed after step 304.

[0033] In step 306, refer to Figure 4C ,pass Figure 1FThe second solder layer 104 is fitted with a first set of metal clips 440. The first set of metal clips 440 includes a first metal clip 442 and a second metal clip 452, wherein the first metal clip 442 connects the source electrode 422S of the first high-side FET 422 to the drain electrode 424D of the first low-side FET 424, and the second metal clip 452 connects the gate electrode 422G of the first high-side FET 422 to the high-side gate lead 414 of the lead frame 410.

[0034] The first metal clip 442 includes a thinned portion 443 for preventing short circuits between the drain and source poles. The thinned portion 443 is located in... Figure 1F The first groove 145 is located between the first groove 145 and the opposite second groove 147. The thinned portion 443 of the first metal clip 442 includes a first portion 444 and a second portion 446, wherein the first portion 444 is located between the first high side FET 422 and... Figure 4D Between the second high-side FET 462, the second portion 446 is not located between the first high-side FET 422 and... Figure 4D Between the second high-side FET 462 in the middle.

[0035] The second metal clip 452 includes a thinned portion 453 for preventing short circuits in the drain gate. The thinned portion 453 is located in... Figure 1E The first groove 155 is located between the first groove 155 and the opposite second groove 157. The thinned portion 453 of the second metal clip 452 includes a first portion 454 and a second portion 456, wherein the first portion 454 is located between the first high side FET 422 and... Figure 4D Between the second high-side FET 462, the second portion 456 is not located between the first high-side FET 422 and... Figure 4D Between the second high-side FET 462 in the middle.

[0036] In embodiments of this disclosure, the thinned portions 443 and 453 are formed by a precision pressing process. Step 308 is performed after step 306.

[0037] In step 308, refer to Figure 4D ,pass Figure 1F The third solder layer 106 mounts the second high-side FET 462 and the second low-side FET 464. The second high-side FET 462, after flip-chip bonding, is attached to the side of the first metal clip 442 opposite to the first high-side FET 422. The front side of the second high-side FET 462 includes... Figure 1E The source electrode 162S and the gate electrode 162G are included in the middle, and the drain electrode 462D is included on the back side. The source electrode 162S is connected to the first metal clip 442, and the gate electrode 162G is connected to the second metal clip 452.

[0038] The second low-side FET 464 is mounted on the side of the first metal clip 442 opposite to the first low-side FET 424. The front side of the second low-side FET 464 includes a source electrode 464S and a gate electrode 464G, and the back side includes… Figure 1F The drain electrode 164D is connected to the first metal clip 442.

[0039] The second high-side FET 462 and the second low-side FET 464 are arranged side by side in the horizontal direction (X direction); the first high-side FET 422 and the second high-side FET 462 are aligned in the vertical direction (Z direction); the first low-side FET 424 and the second low-side FET 464 are aligned in the vertical direction (Z direction). Step 308 is followed by step 310.

[0040] In step 310, refer to Figure 4E ,pass Figure 1F The fourth solder layer 108 is fitted with a second set of metal clips 480. The second set of metal clips 480 includes a third metal clip 482, a fourth metal clip 484, and a fifth metal clip 486. The third metal clip 482 connects the drain electrode 462D of the second high-side FET 462 to the high-side drain pad 412 of the lead frame 410. The fourth metal clip 484 connects the source electrode 464S of the second low-side FET 464 to the low-side source pad 416 of the lead frame 410. The fifth metal clip 486 connects the gate electrode 464G of the second low-side FET 464 to the low-side gate lead 418 of the lead frame 410. Step 312 is executed after step 310.

[0041] In step 312, refer to Figure 4F This forms a molded package 490. The molded package 490 encloses at least a majority ("major" means more than 50%) of the first high-side FET 422, the first low-side FET 424, the first set of metal clips 440, the second high-side FET 462, the second low-side FET 464, the lead frame 410, and the second set of metal clips 480.

[0042] In one embodiment, the top surfaces of the third metal clip 482, the fourth metal clip 484, and the fifth metal clip 486 are not exposed from the molded package 490.

[0043] In another embodiment, Figure 2 This is a top perspective view of the semiconductor package 200, in which the top surface 283 of the third metal clip 282, the top surface 285 of the fourth metal clip 284, and the top surface 287 of the fifth metal clip 286 are all exposed from the molded package body 290. Step 314 is performed after step 312.

[0044] Reference Figure 1B The bottom surface 111 of the lead frame 110 is exposed from the molded package 190.

[0045] In step 314, refer to Figure 4G The process 497 involves performing a cutting process to separate the semiconductor package 498 from the adjacent semiconductor package 499. In embodiments of this disclosure, both the semiconductor package 498 and the adjacent semiconductor package 499 are independent double-diffused metal-oxide-semiconductor FET (DMOSFET) chips.

[0046] In embodiments of this disclosure, the semiconductor package 498 is in the shape of a first cuboid; the first high-side FET 422 and the second high-side FET 462 are in the shape of a second cuboid; and the first low-side FET 424 and the second low-side FET 464 are in the shape of a third cuboid.

[0047] In embodiments of this disclosure, the semiconductor package 100 does not include bonding wires.

[0048] Those skilled in the art will understand that modifications can be made to the embodiments disclosed herein. For example, the thickness of the thinned portion 143 can be adjusted as needed. Other modifications may occur to those skilled in the art, and all such modifications should be considered to fall within the scope of protection of the invention as defined by the claims.

Claims

1. A semiconductor package, comprising: A lead frame, comprising: A high-side drain pad, A high-side gate lead, A low-side source pad, and A low-side gate lead; A first high-side field-effect transistor (FET) is mounted on the high-side drain pad. The first high-side FET includes a source electrode and a gate electrode located on the front side of the first high-side FET. A drain electrode located on the back of the first high-side FET; A first low-side FET, flip-chip bonded on the low-side source pad, the first low-side FET comprising: A source electrode and a gate electrode are located on the front side of the first low-side FET, and A drain electrode located on the back side of the first low-side FET; A first set of metal clips includes: A first metal clip connects the source electrode of the first high-side FET to the drain electrode of the first low-side FET; and A second metal clip connects the gate electrode of the first high-side FET to the high-side gate lead of the lead frame; A second high-side FET, flip-chip mounted on the first metal clip, the second high-side FET comprising: A source electrode and a gate electrode are located on the front side of the second high-side FET. The source electrode of the second high-side FET is connected to the first metal clip, and the gate electrode of the second high-side FET is connected to the second metal clip. A drain electrode located on the back of the second high-side FET; A second low-side FET is mounted on the first metal clip, the second low-side FET comprising: A source electrode and a gate electrode are located on the front side of the second low-side FET, and A drain electrode is located on the back of the second low-side FET, and the drain electrode of the second low-side FET is connected to the first metal clip; A second set of metal clips includes: A third metal clip connects the drain electrode of the second high-side FET to the high-side drain pad of the lead frame; a fourth metal clip connects the source electrode of the second low-side FET to the low-side source pad of the lead frame; and A fifth metal clip connects the gate electrode of the second low-side FET to the low-side gate lead of the lead frame, and A molded package encapsulates the first high-side FET, the first low-side FET, the first set of metal clips, the second high-side FET, the second low-side FET, a majority of the lead frame, and at least a majority of the second set of metal clips.

2. The semiconductor package of claim 1, wherein the first metal clip includes a thinned portion for preventing short circuit between the drain and source electrodes; The thinned portion of the first metal clip is located between the first groove and the opposite second groove; and The thinned portion of the first metal clip includes: A first portion is located between the first high-side FET and the second high-side FET; as well as A second portion is not located between the first high-side FET and the second high-side FET.

3. The semiconductor package of claim 1, wherein the second metal clip includes a thinned portion for preventing drain-gate short circuit; The thinned portion of the second metal clip is located between the first groove and the opposite second groove; and The thinned portion of the second metal clip includes: A first portion, located between the first high-side FET and the second high-side FET, and A second portion is not located between the first high-side FET and the second high-side FET.

4. The semiconductor package of claim 1, wherein the top surface of the third metal clip is exposed from the molded package body; The top surface of the fourth metal clip protrudes from the molded package; and The top surface of the fifth metal clip protrudes from the molded package.

5. The semiconductor package of claim 4, wherein the bottom surface of the lead frame is exposed from the molded package body.

6. The semiconductor package of claim 1, wherein the semiconductor package does not include bonding leads.

7. The semiconductor package of claim 1, wherein the first high-side FET and the first low-side FET are arranged side-by-side in a horizontal direction; and The second high-side FET and the second low-side FET are arranged side by side in a horizontal direction.

8. The semiconductor package of claim 7, wherein the first high-side FET and the second high-side FET are aligned in a vertical direction; and The first low-side FET and the second low-side FET are aligned in the vertical direction.

9. The semiconductor package of claim 1, wherein the first high-side FET, the first low-side FET, the second high-side FET and the second low-side FET are each independent double-diffused metal-oxide-semiconductor (DMOS) FET chips.

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