Power semiconductor device and end device

Abstract

The application relates to the technical field of power semiconductor device packaging, and discloses a power semiconductor device and a terminal device. The power semiconductor device comprises a base island frame, a semiconductor chip and a packaging body. The base island frame comprises a base island, a pin arranged on one side of the base island, and at least one heat-conducting side wall arranged on the non-pin side of the base island. The semiconductor chip has oppositely arranged first and second surfaces, and the electrodes of the first surface are fixed to the surface of the base island. The electrodes of the second surface of the semiconductor chip are electrically connected to the pin through a connecting sheet. The packaging body wraps the semiconductor chip and part of the base island frame. At least part of the surface of the connecting sheet away from the semiconductor chip, at least part of the surface of the base island away from the semiconductor chip, at least part of the surface of the pin and at least part of the surface of the heat-conducting side wall away from the semiconductor chip are not wrapped by the packaging body and are exposed outside the packaging body, so that the heat dissipation efficiency of the power semiconductor device is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device packaging technology, and in particular to a power semiconductor device and terminal equipment. Background Technology

[0002] Currently, most mainstream power semiconductor devices employ a unidirectional bottom-cooled packaging architecture, where heat conduction primarily relies on a single vertical conduction channel formed by the base island, thermal vias on the circuit board, and the cold plate. However, in immersion liquid cooling applications, the cooling medium can directly wet the device package surface. Its significantly higher convective heat transfer coefficient compared to air drastically reduces the convective thermal resistance between the package's outer surface and the coolant. Under these conditions, the bottleneck of the heat dissipation system changes significantly: the inherent thermal resistance of the multi-layered structure within the package, and the contact thermal resistance between the package's bottom surface and the cold plate due to uneven contact pressure distribution, interface roughness, and micro-voids, together constitute the key factors restricting overall heat dissipation performance, severely limiting the heat dissipation efficiency and long-term reliability of power semiconductor devices. Summary of the Invention

[0003] In view of this, the present application provides a power semiconductor device and terminal equipment, which can effectively solve the problem that the power semiconductor device in the prior art is severely restricted in terms of heat dissipation efficiency and long-term reliability due to the use of a unidirectional bottom heat dissipation packaging architecture.

[0004] In a first aspect, embodiments of this application provide a power semiconductor device, including a base island frame, a semiconductor chip, and a package; The base island frame includes a base island, pins disposed on one side of the base island, and at least one thermally conductive sidewall disposed on the non-pin side of the base island. The semiconductor chip has a first surface and a second surface disposed opposite to each other. The electrodes of the first surface are fixed to the surface of the base island, and the electrodes of the second surface of the semiconductor chip are electrically connected to the pins through connecting pieces. The package encapsulates the semiconductor chip and a portion of the base island frame, wherein at least a portion of the connector tab facing away from the surface of the semiconductor chip, at least a portion of the base island facing away from the surface of the semiconductor chip, at least a portion of the surface of the pin, and at least a portion of the thermally conductive sidewall facing away from the surface of the semiconductor chip are not encapsulated by the package and are exposed outside the package.

[0005] In some embodiments, the base island has a thermally conductive sidewall on its non-pin side or each non-pin side of the base island has a thermally conductive sidewall.

[0006] In some embodiments, the exposed surface of the thermally conductive sidewall is provided with a turbulence structure.

[0007] In some embodiments, the turbulence structure includes at least one protrusion protruding from the exposed surface of the heat-conducting sidewall, or includes at least one first groove recessed from the exposed surface of the heat-conducting sidewall.

[0008] In some embodiments, the turbulence structure includes a plurality of protrusions on the exposed surface of the heat-conducting sidewall, wherein each protrusion is teardrop-shaped or spherical. Alternatively, the turbulence structure may include a plurality of first grooves recessed on the exposed surface of the heat-conducting sidewall, wherein the first grooves are straight grooves and the first grooves are arranged side by side.

[0009] In some embodiments, the thermally conductive sidewall is provided with a first boss structure on the surface of the semiconductor chip, and / or the base island is provided with a second groove, the second groove surrounding at least a portion of the semiconductor chip.

[0010] In some embodiments, the area where the connecting piece connects to the pin is provided with a cavity structure.

[0011] In some embodiments, the connecting piece has a second boss structure on the surface facing the semiconductor chip.

[0012] In some embodiments, the base island frame is made of copper, and an isolation layer and a tin layer are sequentially disposed on the surfaces of the base island, the pins and the thermally conductive sidewalls exposed outside the package. The isolation layer is used to balance the potential difference between the base island frame and the tin layer and to isolate the base island frame from the tin layer.

[0013] In some embodiments, the material of the isolation layer includes a main component material and an auxiliary component material, wherein the mass percentage of the main component material in the isolation layer is greater than the mass percentage of the auxiliary component material in the isolation layer, the main component material includes at least one of chromium and nickel, and the auxiliary component material includes at least one of phosphorus, vanadium, molybdenum, niobium, and silicon.

[0014] In some embodiments, an insulating protective layer is disposed on the surface of the power semiconductor device, the insulating protective layer having a thickness at the nanometer level and being a continuous and complete film layer.

[0015] In some embodiments, the surface of the base island frame has a rough structure.

[0016] Thirdly, embodiments of this application provide a terminal device, which includes the power semiconductor device described in the first aspect above.

[0017] The embodiments of this application have the following beneficial effects: The power semiconductor device of this application includes a base island frame, a semiconductor chip, and a package. The base island frame includes a base island, pins disposed on one side of the base island, and at least one thermally conductive sidewall disposed on the non-pin side of the base island. The semiconductor chip has a first surface and a second surface disposed opposite to each other, with electrodes on the first surface fixed to the surface of the base island. Electrodes on the second surface of the semiconductor chip are electrically connected to the pins via connecting tabs. The package encloses the semiconductor chip and part of the base island frame, wherein at least a portion of the connecting tab facing away from the surface of the semiconductor chip, at least a portion of the base island facing away from the surface of the semiconductor chip, at least a portion of the surface of the pins, and at least a portion of the thermally conductive sidewall facing away from the surface of the semiconductor chip are not enclosed by the package and are exposed outside the package. This application achieves three-dimensional heat conduction through the thermally conductive sidewalls, allowing heat to be uniformly dissipated from the chip in multiple directions, significantly reducing the thermal load on the bottom main heat sink, greatly improving the heat dissipation efficiency of the power semiconductor device, and ensuring the long-term reliability of the power semiconductor device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A first structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 2 A rendered schematic diagram of the first structure of the power semiconductor device according to an embodiment of this application is shown; Figure 3 A schematic diagram of the base island frame structure according to an embodiment of this application is shown; Figure 4 This paper shows a schematic diagram of the base island framework and semiconductor chip structure according to an embodiment of this application; Figure 5 A partial structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 6 A schematic diagram of the connecting piece according to an embodiment of this application is shown; Figure 7 A second structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 8 A rendered schematic diagram of the second structure of the power semiconductor device according to an embodiment of this application is shown; Figure 9 A third structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 10 A fourth structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 11 A fifth structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 12 A sixth structural schematic diagram of a power semiconductor device according to an embodiment of this application is shown; Figure 13 A schematic diagram of a packaging method for a power semiconductor device according to an embodiment of this application is shown.

[0020] Explanation of key component symbols: 10: Semiconductor chip; 20: Base island frame; 21: Base island; 211: Second groove; 22: Pin; 23: Thermally conductive sidewall; 231: First boss structure; 24: Turbulence structure; 241: Spherical turbulence structure; 242: Teardrop-shaped turbulence structure; 243: Rectangular straight groove turbulence structure; 30: Connecting piece; 31: Cavity structure; 32: Second boss structure; 40: Package. Detailed Implementation

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0022] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0024] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0025] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] As the computing power demands of AI servers continue to rise, traditional air-cooling methods are increasingly unable to meet the sustained heat dissipation requirements of high-power-density chips, hindering the stable release of computing performance. Against this backdrop, immersion liquid cooling technology is gradually becoming a key thermal management solution in AI computing infrastructure. This technology immerses the heat-generating components entirely in an insulating coolant, relying on the liquid's significantly higher convective heat transfer capacity than air to efficiently remove the heat generated during operation. Currently, the mainstream commercial coolants mainly include two types: fluorocarbon-based fluorinated liquids and mineral oils. Fluorinated liquids possess excellent insulation, chemical inertness, non-flammability, and low viscosity, making them suitable for high-end, high-reliability computing scenarios; mineral oils are significantly cheaper than fluorinated liquids, making them suitable for low-to-medium power-density computing applications where cost is a concern.

[0027] Power discrete devices are fundamental components in the power conversion and distribution systems of artificial intelligence servers, undertaking functions such as mains power access, voltage transformation, power supply regulation, and circuit protection, directly affecting the overall power supply efficiency, operational stability, and lifespan of the system. However, the packaging structures of current mainstream power discrete devices are designed for air-cooled operation in atmospheric environments, and do not consider the actual operating conditions of long-term direct contact with liquid cooling media in terms of material selection, interface sealing, and heat dissipation path planning.

[0028] Practical applications show that directly using unmodified power discrete devices in immersion liquid-cooled environments presents three interrelated reliability issues. The first is heat dissipation path reconfiguration failure. Traditional packages use the bottom heat sink as the primary heat conduction path, with heat transferred to the outside via the circuit board. However, in immersion environments, the heat transfer efficiency between the coolant and the package surface increases significantly, making the internal thermal conduction resistance of the package and the contact thermal resistance between the metal and the coolant new bottlenecks. Especially when using mineral oil, its high viscosity easily leads to uneven coolant flow distribution on the package surface, forming stagnant zones with low flow rates in localized areas, affecting the timely dissipation of heat.

[0029] Secondly, there is the issue of multi-mechanism material corrosion failure. The base island frame, heat dissipation pads, and surface plating often use different metal materials, which are prone to galvanic corrosion due to differences in electrochemical potential in the coolant environment. Trace amounts of fluoride ions in the fluorinated solution can induce localized acidification on the metal surface, accelerating the corrosion of the plating and substrate. Organic acids generated from the oxidation of mineral oil under high-temperature operating conditions can also continuously erode the protective layer on the metal surface, causing material performance degradation.

[0030] Thirdly, there is the issue of liquid penetration and interfacial delamination failure. Epoxy molding compounds have a certain tendency for media penetration. Fluorinated liquids can slowly seep into the intermolecules of epoxy resin, while the organic acid components in mineral oil may damage the bonding interface between the filler and the resin matrix, leading to a decline in material performance. Furthermore, there are multiple microscopic interfacial gaps between the heat dissipation pads and the epoxy molding compound, exposed to the coolant. Due to the difference in thermal expansion coefficients between the metal and the molding compound, these gaps periodically open and close during temperature cycling, creating a pump-like effect that causes the coolant to gradually penetrate inwards along the copper-molded interface, potentially affecting the internal insulation performance.

[0031] This application aims to provide a power semiconductor device and terminal equipment suitable for immersion liquid cooling environments, improving the long-term reliability of the device in both fluorinated liquids and mineral oil coolants. The power semiconductor device of this application reconstructs the heat dissipation path by providing a thermally conductive sidewall 23 on the non-pin side of the base island 21 of the base island frame 20, exposing the top of the connecting piece, and forming three independent heat dissipation channels on the top, sides, and bottom in conjunction with the bottom main heat dissipation pad. Furthermore, a turbulence structure is provided on the thermally conductive sidewall 23 to optimize the flow state of the coolant on the package surface and improve convective heat transfer efficiency. Simultaneously, a first boss structure 231 is provided at the joint edge region between the thermally conductive sidewall 23 of the base island frame 20 and the package body 40, forming a mechanically interlocking multi-stage seal to disrupt the coolant flow. Along the capillary penetration path of the metal-molded interface; an isolation layer and a tin layer are sequentially disposed on the surfaces of the base island 21, pins 22 and thermally conductive sidewalls 23 exposed outside the package 40. The isolation layer balances the potential difference between the base island frame 20 and the tin layer to isolate the copper substrate and the tin layer, suppressing the galvanic corrosion effect between the copper substrate and the tin layer in the coolant environment, and improving the long-term tolerance to fluorinated liquid and mineral oil; furthermore, an insulating protective layer is disposed on the surface of the power semiconductor device to isolate the coolant from direct contact with the power semiconductor device and cut off the external channels for coolant penetration.

[0032] The power semiconductor device will be described below with reference to some specific embodiments.

[0033] Figure 1 A schematic diagram of a power semiconductor device according to an embodiment of this application is shown. Figure 2 The embodiments of this application are shown. Figure 1A rendering of the structure. Exemplarily, the power semiconductor device includes a semiconductor chip 10, a base island frame 20, and a package 40.

[0034] As an example, the base island frame 20 uses a high thermal conductivity copper alloy as its substrate, possessing excellent electrical and thermal conductivity. For example... Figure 3 As shown, the base island frame 20 includes a base island 21, pins 22 disposed on one side of the base island 21, and at least one thermally conductive sidewall 23 disposed on the non-pin side of the base island 21. It is understood that the pins 22 are used for connection to external circuits and are insulated from the base island 21. The number of thermally conductive sidewalls 23 can be set according to the actual application. There may be only one thermally conductive sidewall 23 on one side of the non-pin side of the base island 21, or thermally conductive sidewalls may be provided on two sides of the non-pin side of the base island 21, or thermally conductive sidewalls 23 may be provided on all three sides of the non-pin side of the base island 21. The thermally conductive sidewalls 23 may be insulated from the base island 21 or integrally formed with the base island 21. For example, Figure 3 As shown, heat-conducting sidewalls 23 are provided on three sides of the base island 21. Each heat-conducting sidewall 23 is integrally formed with the base island 21, which can greatly improve the structural stability of power semiconductor devices and reduce interface thermal stress fatigue damage. The base island frame 20 serves as the main support and simultaneously undertakes the triple functions of electrical conduction, mechanical load bearing, and multi-directional heat dissipation.

[0035] Furthermore, to disrupt the capillary penetration path of the coolant along the interface between the metal and the package 40, such as... Figure 3 As shown, the heat-conducting sidewall 23 has a first protrusion structure 231 on the surface facing the semiconductor chip 10, forming a multi-level mechanical interlocking seal. This extends the penetration path into an ultra-long, tortuous channel, significantly increasing the resistance to coolant climbing along the interface compared to a traditional straight interface, thus greatly reducing the possibility of coolant penetration. Furthermore, as... Figure 3 As shown, the base island 21 of the base island frame 20 has a second groove 211 on the surface facing the semiconductor chip 10. The second groove 211 surrounds at least a portion of the semiconductor chip 10 to enhance packaging reliability.

[0036] like Figure 4 As shown, the semiconductor chip 10 has a first surface and a second surface disposed opposite to each other. Exemplarily, the semiconductor chip 10 is a power MOSFET chip with a double-sided electrode distribution, including three electrodes: a source, a gate, and a drain. The drain, as the first electrode, is located on the first surface, i.e., the bottom surface of the chip; the source and gate, as the second and third electrodes respectively, are located on the second surface, i.e., the top surface of the chip. It is understood that the semiconductor chip 10 in this embodiment can also be an IGBT device, a SiC device, or a GaN device, and is not limited thereto.

[0037] The electrodes on the first surface are fixed to the surface of the base island 21. That is, the drain of the semiconductor chip 10 is electrically interconnected with the surface of the base island 21 through solder paste. The base island 21 thus forms the main path of drain current and the core path of bottom heat dissipation.

[0038] The electrodes on the second surface of the semiconductor chip 10 are electrically connected to the pin 22 via a connector 30; exemplary, the connector 30 is made of a high thermal conductivity copper alloy, such as... Figure 5 As shown, the connector 30 includes mutually isolated gate metal clips and source metal clips. The connector 30 is fixed to the second surface of the semiconductor chip 10 by solder paste and is electrically connected to the electrodes and pins 22 on the second surface. The gate metal clip is electrically connected to the gate electrode of the second surface of the semiconductor chip 10, and the source metal clip is electrically connected to the source electrode of the third surface, thus avoiding signal crosstalk. Furthermore, a cavity structure 31 is provided in the area where the connector 30 connects to the pins 22. The cavity structure 31 can be a groove or a through hole. The cavity structure 31 reduces the weight of the connector 30 while enabling a tighter connection between the connector 30 and the package 40, improving the bonding strength between the metal and the molding compound under thermal cycling conditions. Further, as... Figure 6 As shown, the connecting piece 30 has a second protrusion structure 32 on its surface facing the semiconductor chip 10; exemplary, the second protrusion structure 32 is integrally formed with the connecting piece 30, and the second protrusion structure 32 is embedded inside the package 40 to form a mechanical interlocking interface structure, which improves the bonding strength between the metal and the molding compound under thermal cycling conditions, while extending the penetration path of the coolant, increasing the coolant climbing resistance, and effectively suppressing interface delamination and peeling.

[0039] The package 40 is injection molded from epoxy resin molding compound at high temperature. The package 40 encapsulates the semiconductor chip 10 and part of the base island frame 20. At least a portion of the base island 21 facing away from the semiconductor chip 10, at least a portion of the surface of the pins 22, and at least a portion of the thermally conductive sidewall 23 facing away from the semiconductor chip 10 are exposed outside the package 40. Further, as... Figure 7 As shown and Figure 8 As shown, at least a portion of the connecting piece 30 facing away from the surface of the semiconductor chip 10 can be exposed outside the package 40 by means of grinding, etc., together forming a three-dimensional heat exchange interface of the device in the immersion liquid cooling environment. Specifically, the semiconductor chip 10 can transfer heat to the circuit board through the main heat dissipation pad formed by the bottom base island 21, or transfer heat to the coolant through the top connecting piece 30, or transfer heat to the coolant through the three heat-conducting sidewalls 23, so as to achieve multi-directional uniform heat dissipation, greatly reduce the heat load of the bottom main heat dissipation pad, avoid the unbalanced thermal stress caused by traditional single-sided heat dissipation, reduce the amplitude of interface thermal stress, significantly delay the fatigue aging rate of materials, and extend the power cycle life of the device.

[0040] Furthermore, the exposed surface of the heat-conducting sidewall 23 is provided with a turbulence structure, or the exposed surface of the connecting piece 30 is provided with a turbulence structure, or both the exposed surfaces of the heat-conducting sidewall 23 and the exposed surfaces of the connecting piece 30 are provided with turbulence structures. The turbulence structure optimizes the flow state of the coolant on the encapsulation surface, thereby improving convective heat transfer efficiency. For example, Figure 9 As shown, the turbulence structure 24 is disposed on the exposed surface of the heat-conducting sidewall 23.

[0041] The turbulence structure 24 can be configured according to the actual application. Exemplarily, the turbulence structure 24 includes at least one protrusion protruding from the exposed surface of the heat-conducting sidewall 23, or at least one first groove recessed into the exposed surface of the heat-conducting sidewall 23, such as... Figure 10 As shown, each protrusion can be a spherical cylindrical structure. Multiple spherical cylindrical structures form a spherical turbulence structure 241. The spherical turbulence structure 241, through the array of protrusions, forces the fluid to be diverted, deflected, and disturbed when it flows through, thereby breaking the static thermal boundary layer, forming local turbulence to enhance heat transfer, and improving the heat transfer intensity. However, the tail of the protrusion is prone to forming stagnant vortices and heat stagnation zones, resulting in high overall flow resistance and high power consumption of the liquid cooling pump. It is suitable for heat dissipation of general-purpose artificial intelligence servers, power modules, 48V power distribution units, and other conventional power consumption, mass-produced power semiconductor devices.

[0042] like Figure 11 As shown, each protruding structure can also be a teardrop-shaped structure, and multiple teardrop-shaped structures form a teardrop-shaped turbulence structure 242. The teardrop-shaped turbulence structure 242 has a streamlined feature with a head that gathers turbulence and a tail that tapers smoothly. It conforms to the fluid movement trajectory, has the best balance between heat dissipation and energy consumption, and can minimize flow resistance and break the thermal boundary layer. It is suitable for fully liquid-cooled artificial intelligence servers, ultra-high-power cabinets, and high-end computing core devices that operate continuously at full load. However, the streamlined curved surface structure of the teardrop shape requires strict processing precision, is difficult to form, and has a higher mass production cost compared to conventional structures.

[0043] like Figure 12 As shown, the first groove is a straight groove, and multiple straight grooves are arranged side by side to form a rectangular straight groove turbulence structure 243. The rectangular straight groove turbulence structure 243 has an array of rectangular straight grooves of equal width and depth, which greatly expands the effective heat exchange area, guides the fluid to flow in a directional and high-speed manner, and forms forced convection to enhance heat dissipation. It has the characteristics of significantly increased heat exchange area, stable heat dissipation gain, high structural strength, resistance to fluid erosion, controllable flow resistance, and wide applicability.

[0044] The aforementioned turbulence structure 24 synergistically generates four major physical effects when the coolant flows through it: First, it disrupts the laminar sublayer near the wall, reducing its thickness and lowering the convective heat transfer resistance; second, it stimulates local turbulence and vortices in the near-wall region, increasing the turbulence intensity of the fluid and accelerating heat transfer from the wall to the coolant; third, through the dense arrangement of microstructures, it significantly expands the effective heat transfer area within a limited space; and fourth, it guides the low-temperature mainstream fluid to impact the local high-temperature zone, promoting the mixing of hot and cold fluids and making the temperature field distribution more uniform. Combined with a high thermal conductivity copper alloy substrate, the sidewall heat dissipation ratio is increased to over 35%, the overall thermal resistance of the device is reduced by over 45%, and the junction temperature of the device can decrease by 18-25℃ during continuous high-power operation, fundamentally reducing the risk of thermal failure.

[0045] Furthermore, to enhance the interface reliability between the metal and the package 40, the surfaces of the base island frame 20 and the connecting piece 30 undergo ultra-fine roughening and passivation treatment, giving them a rough structure and forming a micron-level rough surface. This structure can significantly increase the mechanical interlocking area between the molding compound and the metal substrate, improve the bonding force between the molding compound and the metal substrate, and fundamentally alleviate interfacial stress fatigue and delamination caused by thermal cycling.

[0046] Furthermore, an isolation layer and a tin layer (not shown) are sequentially disposed on the surfaces of the base island 21, pins 22, thermally conductive sidewalls 23, and connecting tabs 30 exposed outside the package body 40. The isolation layer is used to balance the potential difference between the base island frame 20 and the tin layer, and to isolate the base island frame 20 from the tin layer. Tin plating on power semiconductor devices is a conventional surface treatment solution in packaging, which can meet the protection requirements of conventional air-cooling conditions. However, tin has a low standard electrode potential and high chemical reactivity. Under immersion liquid cooling conditions, trace amounts of water, ionic impurities, or acidic decomposition products are present in the coolant, and the tin layer will preferentially oxidize or electrochemically dissolve. Furthermore, the material of the base island frame 20 includes copper. The electrode potential of the copper alloy substrate used in the base island frame 20 or the connecting piece 30 is higher than that of tin. Under the ionic impurity environment of the coolant, the two materials will form a self-generating galvanic corrosion cell, causing the tin layer to be oxidized and corroded as the anode. When the local tin layer is corroded and perforated, the electrolyte will directly contact the base island frame 20 or the metal clip, inducing local pitting corrosion and intergranular corrosion of the substrate. In the short term, this will cause a decrease in the heat exchange efficiency of the heat-conducting sidewall 23, and in the long term, it may induce internal structural failure.

[0047] This embodiment employs chemical plating to add a 5-8 μm thick Ni-Cr based alloy interlayer between the substrate and the tin layer. Specifically, the interlayer material includes a main component and an auxiliary component, with the main component having a higher mass percentage than the auxiliary component. The main component includes one or more of chromium and nickel, while the auxiliary component includes one or more of phosphorus, vanadium, molybdenum, niobium, and silicon. The electrode potential of this interlayer is located between the copper substrate and the tin layer, effectively balancing the potential difference between the two metals and completely disrupting the galvanic corrosion path between copper and tin. Furthermore, this interlayer has a dense amorphous structure without penetrating pores, completely isolating the copper substrate from the tin layer and preventing corrosive media from contacting the copper substrate, thus fundamentally eliminating the corrosion risk of the copper substrate. The outermost tin layer retains excellent solder wettability, meeting the requirements of the reflow soldering process.

[0048] To further disrupt the capillary penetration path of coolant along the metal-encapsulation interface, an insulating protective layer (not shown) is applied to the surface of the power semiconductor device. This insulating protective layer has a nanometer-level thickness and is a continuous, complete film. Specifically, a layer of silicone-modified polyurethane nano-protective coating can be uniformly coated onto all heat exchange surfaces and the encapsulation area using a vapor deposition process. This coating is dense, pinhole-free, and highly flexible, allowing it to undergo micrometer-level deformation with the encapsulation material without cracking. Its surface is specially modified to provide moderate wettability to fluorinated liquids and mineral oils, effectively eliminating coolant buildup in structural dead zones. Its thermal conductivity is comparable to air, introducing no additional thermal resistance. Even after long-term immersion, it maintains complete coverage, thoroughly isolating the coolant from direct contact with the metal plating and encapsulation interface, thus cutting off the three failure paths at their source: electrochemical corrosion, swelling aging, and pump-suction penetration.

[0049] In summary, this power semiconductor device, through the integrated design of the base island frame 20 and the thermally conductive sidewall 23, constructs a three-dimensional thermally conductive network covering the entire area from the bottom of the chip to the circuit board, from the top of the chip to the connector 30 to the coolant, and from the chip sidewall to the coolant, breaking through the bottleneck of traditional unidirectional heat dissipation. Relying on the four-dimensional synergy of the turbulence structure, the rough structure, the Ni-Cr based alloy intermediate layer, and the nano-level dense protective coating, it systematically solves three common problems in immersion liquid cooling environments: heat dissipation path failure, multi-mechanism material corrosion failure, and liquid penetration and interface delamination failure. Ultimately, the device achieves full-condition compatibility with two mainstream cooling media, fluorinated liquid and mineral oil, in scenarios such as artificial intelligence servers, high-power computing devices, and vehicle charging modules, while possessing high heat dissipation efficiency, long service life, and strong environmental adaptability.

[0050] Figure 13 This paper illustrates a schematic flowchart of a packaging method for a power semiconductor device according to an embodiment of this application. The packaging method, exemplary, includes steps S101-S104: S101: A base island frame is provided, the base island frame including a base island, pins disposed on one side of the base island, and at least one thermally conductive sidewall disposed on the non-pin side of the base island.

[0051] Using a high thermal conductivity copper alloy as the base material, the lead frame is integrally formed using a combination of high-precision etching and stamping processes. This simultaneously completes the structural processing of the base island, leads, and the thermally conductive sidewall located on the non-lead side of the base island and continuously extending from it. During the forming stage, a turbulence structure is simultaneously formed on the outer surface of the thermally conductive sidewall. The turbulence structure morphology is selected from one or more of the following: teardrop-shaped turbulence structure, spherical turbulence structure, and rectangular straight groove turbulence structure. This integral forming process avoids secondary assembly interfaces such as welding or riveting, ensuring no contact thermal resistance and no stress concentration points between the thermally conductive sidewall and the base island, providing a structurally reliable foundation for multi-directional three-dimensional heat dissipation.

[0052] A first protrusion structure is provided on the surface of the heat-conducting sidewall facing the semiconductor chip. This first protrusion structure makes the molding compound and the metal interface form an ultra-long tortuous penetration path, which significantly increases the resistance of the coolant to capillary climbing along the interface, about three times higher than that of the traditional flat interface. At the same time, the first protrusion structure effectively blocks the pumping effect inlet caused by the difference in the thermal expansion coefficient of the materials during the hot and cold cycle, eliminating the driving force for liquid to penetrate into the package from the source.

[0053] The surface of the base island frame is subjected to ultra-fine roughening and passivation treatment to enhance the interface reliability between the metal and the package.

[0054] S102: Provide a semiconductor chip, the semiconductor chip including a first surface and a second surface disposed opposite to each other, and mounting electrodes of the first surface to the surface of the base island.

[0055] A layer of high thermal conductivity solder paste is applied to the surface of the base island of the base island frame using SMT printing process. This solder paste has excellent wettability, filling properties and thermal stability. Then, the power MOSFET chip with double-sided electrode distribution is precisely mounted on the base island, so that the drain of the first surface of the power MOSFET chip is in full contact with the solder paste layer. After reflow soldering, the drain and the base island form a strong electrical interconnection, and the base island thus simultaneously undertakes the dual functions of current conduction and bottom heat dissipation.

[0056] S103: Provides a connector to electrically connect the electrodes on the second surface of the semiconductor chip to the pins, thereby obtaining a chip interconnect structure.

[0057] Exemplarily, the connector includes mutually isolated gate and source metal clips to prevent signal coupling. Solder paste is also applied to the source and gate pads of the power MOSFET chip. After precise mounting of the connector, reflow soldering is performed, electrically connecting the gate metal clip to the gate electrode of the second surface of the semiconductor chip, and the source metal clip to the source electrode of the third surface, forming a chip interconnect structure. The connector is made of a high thermal conductivity copper alloy, and its chip-facing side has a second protrusion structure. This second protrusion structure is embedded inside the epoxy molding compound during subsequent molding, forming a mechanically interlocking interface structure.

[0058] The surface of the connector is subjected to ultra-fine roughening and passivation treatment to enhance the interface reliability between the metal and the package.

[0059] S104: Package the chip interconnect structure to obtain a power semiconductor device, wherein at least a portion of the base island facing away from the surface of the semiconductor chip, at least a portion of the surface of the pins, and at least a portion of the thermally conductive sidewall facing away from the surface of the semiconductor chip are not enclosed by the package and are exposed outside the package.

[0060] The above-mentioned chip interconnect structure is encapsulated by epoxy resin molding compound injection molding. The molten epoxy resin completely fills the internal gaps. After encapsulation, the heat dissipation pad surface of the base island frame away from the chip, the exposed end face of the pins, all the outer surfaces of the heat-conducting sidewalls, and the top flat surface of the connecting piece away from the chip are all exposed, together forming a direct heat exchange interface under immersion liquid cooling conditions.

[0061] All exposed metal surfaces are subjected to sequential chemical plating and electroplating treatments. First, a Ni-Cr based alloy intermediate layer is deposited using a chemical plating process. This intermediate layer is dense and amorphous, with an electrode potential between the copper substrate and the tin layer. This completely disrupts the copper-tin galvanic corrosion path and isolates ionic impurities in the fluorinated liquid or mineral oil from contacting the copper substrate. Subsequently, a tin layer is electroplated on top of this intermediate layer as a soldering functional layer that meets the requirements of the reflow soldering process. This dual-layer metal system balances long-term corrosion resistance and process compatibility, fundamentally solving failure problems such as preferential oxidation of the plating layer, localized perforation, and pitting corrosion of the substrate in immersion liquid cooling environments.

[0062] Finally, all exposed surfaces of the package are uniformly pretreated with plasma activation to activate surface molecules and enhance coating adhesion. Then, a layer of silicone-modified polyurethane nano-protective coating is uniformly coated using a vapor deposition process. This coating is dense, pinhole-free, and highly flexible, capable of undergoing micron-level deformation with the packaging material without cracking. Its surface is specially modified to provide moderate wetting properties for fluorinated liquids and mineral oils, effectively reducing coolant buildup in structural recesses or corners. Its thermal conductivity is comparable to air, without adding additional heat transfer resistance. Even after long-term immersion, it maintains complete coverage, thoroughly isolating the coolant from direct contact with the metal plating and the molded body interface. This nano-protective layer, together with the various boss structures and the Ni-Cr based alloy intermediate layer, constitutes a synergistic physical and electrochemical protection system, comprehensively disrupting the three major failure pathways: coolant penetration, interface delamination, and electrochemical corrosion.

[0063] In this embodiment, the integral molding of the heat-conducting sidewall ensures the integrity of the heat dissipation structure. The various protrusion structures and the rough surface work together to strengthen the interface bonding strength. The various protrusion structures also inhibit capillary penetration. The Ni-Cr based alloy intermediate layer and the nano-coating layer provide hierarchical barrier against corrosive media. The resulting power semiconductor device can be stably adapted to the full immersion liquid cooling conditions of two mainstream cooling media, fluorinated liquid and mineral oil, in scenarios such as artificial intelligence servers, high-power computing equipment, and vehicle charging modules. While ensuring high heat dissipation efficiency, it significantly extends the service life and operational reliability of the device in complex liquid cooling environments.

[0064] It is understood that the options in the above embodiments also apply to this embodiment, so they will not be described again here.

[0065] This application also provides a terminal device, exemplary of which includes the aforementioned power semiconductor device. Exemplarily, the terminal device can be an artificial intelligence server, a high-power computing device, or an on-board charging module, etc.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0068] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A power semiconductor device, characterized in that, Includes the base island framework, semiconductor chip, and package; The base island frame includes a base island, pins disposed on one side of the base island, and at least one thermally conductive sidewall disposed on the non-pin side of the base island. The semiconductor chip has a first surface and a second surface disposed opposite to each other. The electrodes of the first surface are fixed to the surface of the base island, and the electrodes of the second surface of the semiconductor chip are electrically connected to the pins through connecting pieces. The package encapsulates the semiconductor chip and a portion of the base island frame, wherein at least a portion of the connector tab facing away from the surface of the semiconductor chip, at least a portion of the base island facing away from the surface of the semiconductor chip, at least a portion of the surface of the pin, and at least a portion of the thermally conductive sidewall facing away from the surface of the semiconductor chip are not encapsulated by the package and are exposed outside the package.

2. The power semiconductor device according to claim 1, characterized in that, The base island has a heat-conducting sidewall on its non-pin side, or each non-pin side of the base island has a heat-conducting sidewall.

3. The power semiconductor device according to claim 1, characterized in that, The exposed surface of the heat-conducting sidewall is provided with a turbulence structure.

4. The power semiconductor device according to claim 3, characterized in that, The turbulence structure includes at least one protrusion on the exposed surface of the heat-conducting sidewall or at least one first groove recessed on the exposed surface of the heat-conducting sidewall.

5. The power semiconductor device according to claim 4, characterized in that, The turbulence structure includes a plurality of protrusions on the exposed surface of the heat-conducting sidewall, each of the protrusions being a teardrop-shaped structure or a spherical structure. Alternatively, the turbulence structure may include a plurality of first grooves recessed on the exposed surface of the heat-conducting sidewall, wherein the first grooves are straight grooves and the first grooves are arranged side by side.

6. The power semiconductor device according to claim 1, characterized in that, The thermally conductive sidewall is provided with a first boss structure on the surface of the semiconductor chip, and / or the base island is provided with a second groove, the second groove surrounding at least a portion of the semiconductor chip.

7. The power semiconductor device according to claim 1, characterized in that, The area where the connecting piece connects to the pin has a cavity structure.

8. The power semiconductor device according to claim 1, characterized in that, The connecting piece has a second protrusion structure on its surface facing the semiconductor chip.

9. The power semiconductor device according to claim 1, characterized in that, The base island frame is made of copper. An isolation layer and a tin layer are sequentially disposed on the surfaces of the base island, the pins and the thermally conductive sidewalls exposed outside the package. The isolation layer is used to balance the potential difference between the base island frame and the tin layer and to isolate the base island frame from the tin layer.

10. The power semiconductor device according to claim 9, characterized in that, The material of the isolation layer includes a main component material and an auxiliary component material. The mass percentage of the main component material in the isolation layer is greater than the mass percentage of the auxiliary component material in the isolation layer. The main component material includes at least one of chromium and nickel, and the auxiliary component material includes at least one of phosphorus, vanadium, molybdenum, niobium, and silicon.

11. The power semiconductor device according to claim 1, characterized in that, An insulating protective layer is disposed on the surface of the power semiconductor device. The insulating protective layer has a thickness at the nanometer level and is a continuous and complete film layer.

12. The power semiconductor device according to claim 1, characterized in that, The surface of the base island frame has a rough structure.

13. A terminal device, characterized in that, The terminal device includes the power semiconductor device as described in any one of claims 1 to 12.

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