Packaging structure

Abstract

A packaging structure comprises a silicon frame with a recess, a glass chip fixed in the recess, a first plastic encapsulation layer covering the silicon frame and the glass chip, a redistribution layer on the surface of the first plastic encapsulation layer, a plurality of via holes for interconnecting the redistribution layer and a plurality of first conductive plugs for electrically connecting the glass chip. The glass chip has extremely low dielectric constant and loss tangent, which can significantly improve signal integrity. The stress borne in the process is effectively dispersed to the entire silicon frame by the higher Young's modulus of the silicon material. The silicon frame can also provide a good heat conduction path, and the thermal expansion coefficient of the overall structure can be adjusted by the composite structure of the silicon frame and the glass chip, thereby reducing the thermal stress caused by the mismatch of the thermal expansion coefficient between the packaging substrate. The glass material and the silicon material both have no water absorption rate, which can ensure the long-term stability of the packaging structure in a high humidity environment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, chip manufacturing faces increasing challenges. At extremely small sizes, physical bottlenecks become more difficult to overcome, leading to rising R&D and production costs, declining product yields, and a gradual slowdown of Moore's Law, ushering in a post-Moore's Law era for the semiconductor industry. Traditional packaging can no longer meet the new demands represented by artificial intelligence and high-performance computing. Leading companies in the semiconductor manufacturing field are shifting their focus from improving wafer manufacturing technology nodes to exploring innovations in system-in-package (SiP) technologies, giving rise to advanced packaging technologies.

[0003] Advanced packaging technologies significantly improve chip performance by modifying packaging methods without shrinking process nodes. Fan-out packaging technologies, including Fan-Out Wafer Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP), have been a major driving force behind the advancement of advanced packaging. Emerging 2.5D and 3D packaging technologies further expand the application potential of flip-chip and wafer-level packaging processes by vertically stacking multiple chips, achieving more efficient input / output. Against the backdrop of the rapidly increasing computing power demands of artificial intelligence, these packaging technologies need to support higher frequencies and faster speeds of finer circuitry to shorten data transmission distances between chips, improve chip-to-die collaboration efficiency, thereby enhancing system performance and reducing overall power consumption.

[0004] However, there are still many problems with the packaging structure in the existing technology. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a packaging structure to improve the performance of the packaging structure.

[0006] To address the aforementioned problems, the present invention provides a packaging structure comprising: a silicon frame having a groove therein, with one side surface of the silicon frame exposing an opening of the groove; a glass chip fixed within the groove; a first molding compound covering the silicon frame and the glass chip; a redistribution layer located on the surface of the first molding compound; a plurality of via interconnect plugs located within the first molding compound, the first molding compound exposing opposite ends of the via interconnect plugs, one end of each via interconnect plug being electrically connected to the redistribution layer; a plurality of first conductive plugs located within the first molding compound, the first molding compound exposing one end of each first conductive plug, the exposed end being electrically connected to the redistribution layer, the other end of each first conductive plug being electrically connected to the glass chip; and a chip structure bonded to the redistribution layer, wherein high-frequency signals in the chip structure are transmitted to the glass chip via the redistribution layer and the first conductive plugs.

[0007] Optionally, the depth of the groove is less than the thickness of the silicon framework; the first molding layer exposes the surface of the silicon framework opposite to the other side.

[0008] Optionally, it further includes: a chip bonding film, the chip bonding film being adhered to the bottom surface of the groove, and the glass chip being adhered to the surface of the chip bonding film; and a first filling layer, the first filling layer filling the gap between the glass chip and the sidewall of the groove.

[0009] Optionally, the silicon framework serves only as a carrier for the glass chip.

[0010] Optionally, it may also include: a plurality of solder balls, which are electrically connected to the other end of the corresponding via interconnect plug.

[0011] Optionally, it further includes: a plurality of through-silicon via (TSV) plugs, the TSV plugs being located within the silicon frame and the silicon frame exposing opposite ends of the TSV plugs; and a plurality of second conductive plugs, the second conductive plugs being located within the first molding compound, the first molding compound exposing one end of the second conductive plug and the exposed end being electrically connected to the redistribution layer, and the other end of the second conductive plug being electrically connected to one end of the TSV plug.

[0012] Optionally, it may also include: a plurality of solder balls, wherein the plurality of solder balls are electrically connected to the other end of the corresponding via interconnect plug and the other end of the second conductive plug, respectively.

[0013] Optionally, the groove extends through the silicon frame, with the opening of the groove exposed on the opposite side surface of the silicon frame; the first molding layer exposes the opposite side surface of the silicon frame and the surface of the glass chip.

[0014] Optionally, it may also include: a first filling layer, which fills the gap between the glass chip and the sidewall of the groove.

[0015] Optionally, the silicon framework serves only as a carrier for the glass chip.

[0016] Optionally, it may also include: a plurality of solder balls, which are electrically connected to the other end of the corresponding via interconnect plug and the glass chip, respectively.

[0017] Optionally, it further includes: a plurality of through-silicon via (TSV) plugs, the TSV plugs being located within the silicon frame and the silicon frame exposing opposite ends of the TSV plugs; and a plurality of second conductive plugs, the second conductive plugs being located within the first molding compound, the first molding compound exposing one end of the second conductive plug and the exposed end being electrically connected to the redistribution layer, and the other end of the second conductive plug being electrically connected to one end of the TSV plug.

[0018] Optionally, it also includes: a plurality of solder balls, which are electrically connected to the other end of the corresponding via interconnect plug, the other end of the second conductive plug and the glass chip respectively.

[0019] Optionally, it also includes: a second filling layer, which fills the micro-gap after the chip structure is bonded to the redistribution layer.

[0020] Optionally, it may also include a second molding layer that covers the chip structure.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages: In the packaging structure of this invention, the glass chip is fixed within the groove of the silicon frame, and high-frequency signals in the chip structure are transmitted to the glass chip via the redistribution layer and the first conductive plug, achieving a synergistic improvement in high-frequency signal transmission performance and packaging structure reliability. Specifically, the glass chip has an extremely low dielectric constant and an extremely low loss tangent, which significantly reduces energy loss and crosstalk during high-frequency signal transmission compared to traditional silicon bridging chips, significantly improving signal integrity and thus meeting the requirements for high-frequency interconnection between high-performance chips. Simultaneously, addressing the inherent mechanical brittleness of the glass chip material, the glass chip is embedded in the groove by introducing the silicon frame. The high Young's modulus of silicon effectively disperses the stress borne by the glass chip during thinning, cutting, bonding, and subsequent packaging processes onto the entire silicon frame, thereby preventing glass breakage and significantly improving packaging yield. Furthermore, the silicon framework provides an excellent thermal conductivity path, facilitating rapid heat dissipation during high-frequency operation. The composite structure of the silicon framework and the glass chip allows for adjustment of the overall thermal expansion coefficient, mitigating thermal stress caused by the mismatch in thermal expansion coefficients between the silicon framework and the packaging substrate, and improving the temperature cycling reliability of the package. Both the glass and silicon materials have zero water absorption, ensuring the long-term stability of the packaging structure in high-humidity environments, thus comprehensively optimizing thermal management and packaging reliability.

[0022] Furthermore, it also includes: a chip bonding film, which is adhered to the bottom surface of the groove, and the glass chip is adhered to the surface of the chip bonding film; and a first filler layer, which fills the gap between the glass chip and the sidewall of the groove. The chip bonding film, adhered to the bottom surface of the groove and fixing the glass chip to its surface, provides flexible buffer support for the glass chip, effectively absorbing mechanical stress and vibration impact during the manufacturing process, and reducing the risk of breakage caused by direct rigid contact. The first filler layer, filling the gap between the glass chip and the sidewall of the groove, provides lateral limiting protection for the glass chip, ensuring the structural tightness between the silicon frame and the glass chip, and improving the overall mechanical stability and process yield of the package.

[0023] Furthermore, the silicon framework serves solely as a carrier for the glass chip. Since it contains no internal electrical structures, it does not bear any signal transmission responsibility, simplifying the manufacturing process and reducing costs and complexity. Simultaneously, it avoids introducing additional parasitic capacitance and electromagnetic interference, ensuring that high-frequency signals are transmitted solely through the glass chip. This fully leverages the low dielectric loss of the glass chip, guaranteeing the purity and integrity of signal transmission.

[0024] Furthermore, it also includes: a plurality of through-silicon via (TSV) plugs located within the silicon frame, with the silicon frame exposing opposite ends of the TSV plugs; and a plurality of second conductive plugs located within the first molding compound, with the first molding compound exposing one end of each second conductive plug, and the exposed end being electrically connected to the redistribution layer, and the other end of each second conductive plug being electrically connected to one end of the TSV plug. By placing the TSV plugs within the silicon frame and using the second conductive plugs within the first molding compound to achieve electrical connection between the TSV plugs and the redistribution layer, the three-dimensional space of the silicon frame is fully utilized to construct additional vertical interconnect channels. This structural design expands the electrical interconnect dimension of the package structure without affecting the high-frequency signal transmission performance of the glass chip, enabling the silicon frame to perform both load-bearing and auxiliary conductive functions, improving the overall package wiring density and integration, and meeting the diverse interconnect path requirements of complex multi-chip systems.

[0025] Furthermore, it also includes: a plurality of solder balls, wherein the solder balls are electrically connected to the other end of the corresponding via interconnect plug; or the plurality of solder balls are electrically connected to the other end of the corresponding via interconnect plug and the glass chip respectively; or the plurality of solder balls are electrically connected to the other end of the corresponding via interconnect plug, the other end of the second conductive plug, and the glass chip respectively. The solder balls provide a standardized packaging interface, facilitating surface mount soldering to the packaging substrate and improving the manufacturability and system-level integration capabilities of the package. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a packaging structure; Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA; Figure 3 This is a schematic diagram of the packaging structure in one embodiment of the present invention; Figure 4 yes Figure 3 Schematic diagram of the cross section along line BB; Figure 5 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 6 yes Figure 5 Schematic diagram of the cross-section along the CC line; Figure 7 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross-section along the DD line; Figure 9 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 10 yes Figure 9 Schematic diagram of the cross section along the EE line. Detailed Implementation

[0027] As described in the background section, existing packaging structures still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of a packaging structure; Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA.

[0029] Please refer to Figure 1 and Figure 2 A packaging structure includes: a silicon bridge chip 100; a molding compound 101 covering the silicon bridge chip 100; a redistribution layer 102 located on the surface of the molding compound 101; a plurality of via interconnect plugs 103 located within the molding compound 101, the molding compound 101 exposing opposite ends of the via interconnect plugs 103, one end of each via interconnect plug 103 being electrically connected to the redistribution layer 102; and a plurality of conductive plugs 1. 04. The conductive plug 104 is located within the molding layer 101. The molding layer 101 exposes one end of the conductive plug 104, and the exposed end is electrically connected to the redistribution layer 102. The other end of the conductive plug 104 is electrically connected to the silicon bridge chip 100. Chip structure 105 is bonded to the redistribution layer 102. High-frequency signals in the chip structure 105 are transmitted to the silicon bridge chip 100 based on the redistribution layer 102 and the conductive plug 104.

[0030] As semiconductor packaging technology accelerates its evolution towards high-performance computing and artificial intelligence, the demand for high-frequency interconnects between chips is becoming increasingly urgent. Although the silicon bridge chip 100 possesses excellent mechanical strength and a mature lithography process, its dielectric constant and loss tangent are relatively high, resulting in severe energy loss and transmission delay for high-frequency signals, which has become a key bottleneck restricting high-frequency transmission.

[0031] In contrast, glass, with its extremely low dielectric constant and loss tangent, exhibits great potential as an ideal low-loss insulating medium. However, glass has significant drawbacks in practical applications: its Young's modulus is only about one-third that of silicon, resulting in significant mechanical brittleness and making it extremely prone to breakage during thinning and packaging processes; secondly, the coefficient of thermal expansion of glass does not match that of silicon and organic packaging substrates, making it susceptible to thermal stress under temperature changes, which can lead to structural failure; furthermore, the surface roughness of glass is significantly higher than that of silicon, which is detrimental to the precise layout of fine circuits. These inherent shortcomings mean that glass materials still face severe challenges in replacing silicon interposers and meeting the requirements of high-frequency interconnects.

[0032] Based on this, the present invention provides a packaging structure that, by fixing the glass chip within the groove of the silicon frame, transmits high-frequency signals from the chip structure to the glass chip via the redistribution layer and the first conductive plug, achieving a synergistic improvement in high-frequency transmission performance and packaging reliability. The glass chip, with its extremely low dielectric constant and loss tangent, significantly reduces high-frequency signal energy loss and crosstalk compared to traditional silicon bridging chips, thus significantly improving signal integrity. Simultaneously, the silicon frame, utilizing its high Young's modulus, disperses the stress experienced by the glass chip during the manufacturing process throughout the overall structure, effectively preventing glass breakage and improving packaging yield. Furthermore, the silicon frame provides a good thermal conductivity path, aiding in high-frequency heat dissipation, and by controlling the overall coefficient of thermal expansion, mitigates thermal stress mismatch with the packaging substrate, improving temperature cycling reliability. Both the glass and silicon have no water absorption rate, ensuring long-term stability in high-humidity environments.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figure 3 This is a schematic diagram of the packaging structure in one embodiment of the present invention; Figure 4 yes Figure 3 Schematic diagram of the cross section along line BB.

[0035] Please refer to Figure 3 and Figure 4An encapsulation structure includes: a silicon frame 200 having a recess (not shown) therein, with one side surface of the silicon frame 200 exposing an opening of the recess; a glass chip 201 fixed within the recess; a first molding compound 202 covering the silicon frame 200 and the glass chip 201; a redistribution layer 203 located on the surface of the first molding compound 202; and a plurality of via interconnect plugs 204 located within the first molding compound 202, with the first molding compound 202 exposing opposite ends of the via interconnect plugs 204. One end of the via interconnect plug 204 is electrically connected to the redistribution layer 203; a plurality of first conductive plugs 205 are located within the first molding compound 202, the first molding compound 202 exposes one end of the first conductive plug 205, and the exposed end is electrically connected to the redistribution layer 203, the other end of the first conductive plug 205 is electrically connected to the glass chip 201; a chip structure 206 is bonded to the redistribution layer 203, and high-frequency signals in the chip structure 206 are transmitted to the glass chip 201 based on the redistribution layer 203 and the first conductive plugs 205.

[0036] By fixing the glass chip 201 within the groove of the silicon frame 200, and transmitting high-frequency signals from the chip structure 206 to the glass chip 201 via the redistribution layer 203 and the first conductive plug 205, a synergistic improvement in high-frequency signal transmission performance and packaging structure reliability is achieved. Specifically, the glass chip 201 has an extremely low dielectric constant and an extremely low loss tangent, which significantly reduces energy loss and crosstalk during high-frequency signal transmission compared to traditional silicon bridging chips, thereby significantly improving signal integrity and meeting the requirements for high-frequency interconnection between high-performance chips. Simultaneously, addressing the inherent mechanical brittleness of the glass chip 201 material, the silicon frame 200 is introduced to embed the glass chip 201 within the groove. The high Young's modulus of silicon effectively disperses the stress experienced by the glass chip 201 during thinning, cutting, bonding, and subsequent packaging processes onto the entire silicon frame 200, preventing glass breakage and significantly improving packaging yield. Furthermore, the silicon frame 200 provides a good thermal conductivity path, facilitating rapid heat dissipation during high-frequency operation. The composite structure of the silicon frame 200 and the glass chip 201 allows for adjustment of the overall thermal expansion coefficient, mitigating thermal stress caused by the mismatch in thermal expansion coefficients between the silicon frame 200 and the packaging substrate (not shown), thus improving the temperature cycling reliability of the package. Both the glass and silicon materials have zero water absorption, ensuring the long-term stability of the packaging structure in high-humidity environments and comprehensively optimizing thermal management and packaging reliability.

[0037] In this embodiment, the depth of the groove is less than the thickness of the silicon frame 200; the first molding layer 202 exposes the opposite surface of the silicon frame 200.

[0038] In this embodiment, the packaging structure further includes: a chip bonding film 207, which is adhered to the bottom surface of the groove, and the glass chip 201 is adhered to the surface of the chip bonding film 207; and a first filling layer 208, which fills the gap between the glass chip 201 and the sidewall of the groove.

[0039] The chip bonding film 207 is adhered to the bottom surface of the groove and fixes the glass chip 201 to its surface, providing flexible buffer support for the glass chip 201, effectively absorbing mechanical stress and vibration impact during the process, and reducing the risk of breakage of the glass chip 201 due to direct rigid contact. The first filling layer 208 fills the gap between the glass chip 201 and the sidewall of the groove, forming a lateral limiting protection for the glass chip 201, ensuring the structural tightness between the silicon frame 200 and the glass chip 201, and improving the overall mechanical stability and process yield of the package.

[0040] In this embodiment, the silicon frame 200 serves only as a carrier for the glass chip 201, meaning it contains no internal electrical structures. This eliminates the need for the silicon frame 200 to perform signal transmission, simplifying its fabrication process and reducing manufacturing costs and complexity. Simultaneously, it avoids introducing additional parasitic capacitance and electromagnetic interference, ensuring that high-frequency signals are transmitted solely through the glass chip 201. This fully leverages the low dielectric loss of the glass chip 201, guaranteeing the purity and integrity of signal transmission.

[0041] In this embodiment, the packaging structure further includes a plurality of solder balls 209, which are electrically connected to the other end of the corresponding via interconnect plug 204. The solder balls 209 provide a standardized packaging interface, facilitating surface mount soldering to the packaging substrate and improving the package's manufacturability and system-level integration capabilities.

[0042] In this embodiment, the packaging structure further includes a second filler layer 210, which fills the micro-gap between the chip structure 206 and the redistribution layer 203 after bonding. The second filler layer 210 fills the micro-gap between the chip structure 206 and the redistribution layer 203 through capillary action or molding processes, completely covering the micro-bump interconnect structure to form a buffer protective layer. When the package undergoes temperature cycling, the second filler layer 210, with its moderate elastic modulus and coefficient of thermal expansion, effectively absorbs and disperses the shear stress caused by thermal mismatch, preventing stress concentration at brittle solder joints and significantly reducing the risk of solder joint fatigue cracking. Simultaneously, the second filler layer 210 enhances the mechanical strength of the bonding interface and improves resistance to moisture erosion and chemical corrosion, making it a key material for ensuring the long-term reliability of flip-chip packaging.

[0043] In this embodiment, the packaging structure further includes a second molding layer 211, which covers the chip structure 206.

[0044] In this embodiment, both the first molding layer 202 and the second molding layer 211 provide comprehensive mechanical protection and environmental isolation, effectively blocking moisture, dust and chemical corrosion, while also achieving electrical insulation and auxiliary heat dissipation functions, protecting the glass chip 201 and the chip structure 206 from physical damage and environmental pollution, and ensuring their long-term stability and service life under various application conditions.

[0045] In this embodiment, both the first molding layer 202 and the second molding layer 211 are made of epoxy resin.

[0046] In this embodiment, the glass chip 201 has a redistribution layer for processing high-frequency signals between the chip structures 206. This redistribution layer is directly integrated inside the glass chip 201. Utilizing the extremely low dielectric constant and loss tangent of the glass, it ensures extremely low energy loss and crosstalk during high-frequency signal transmission through the glass medium, thereby optimizing signal integrity and meeting the stringent requirements of high-speed and high-frequency interconnection between the chip structures 206.

[0047] In this embodiment, the chip structure 206 is either a System-on-Chip (SoC) or a High-Bandwidth Memory (HBM) chip. The SoC integrates a central processing unit, a graphics processing core, and dedicated hardware acceleration units. The HBM is a memory structure formed by vertically stacking multiple layers of Dynamic Random Access Memory (DRAM) wafers through through-silicon vias (TSVs), possessing terabits per second data transfer capability and nanometer-level alignment precision requirements. The two are heterogeneously integrated using thermoforming or flip-chip bonding processes, melting and interconnecting microbumps to the redistribution layer 203 to form ultra-short electrical paths, reducing transmission latency and power consumption.

[0048] Figure 5 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 6 yes Figure 5 Schematic diagram of the cross section along the CC line.

[0049] This embodiment is based on the above embodiment ( Figure 3 and Figure 4 The encapsulation structure will continue to be described based on the previous embodiment, with the remainder being the same as the previous embodiment, except that the silicon frame 200 also has a through-silicon via plug. The following will provide a detailed description in conjunction with the accompanying drawings.

[0050] Please refer to Figure 5 and Figure 6 The packaging structure further includes: a plurality of through-silicon via (TSV) plugs 300, the TSV plugs 300 being located within the silicon frame 200, and the silicon frame 200 exposing opposite ends of the TSV plugs 300; and a plurality of second conductive plugs 301, the second conductive plugs 301 being located within the first molding compound 202, the first molding compound 202 exposing one end of the second conductive plug 301, and the exposed end being electrically connected to the redistribution layer 203, and the other end of the second conductive plug 301 being electrically connected to one end of the TSV plugs 300.

[0051] By placing the through-silicon via (TSV) plug 300 within the silicon frame 200 and using the second conductive plug 301 within the first molding compound 202 to achieve electrical connection between the TSV plug 300 and the redistribution layer 203, additional vertical interconnect channels are constructed by fully utilizing the three-dimensional space of the silicon frame 200. This structural design expands the electrical interconnect dimension of the package structure without affecting the high-frequency signal transmission performance of the glass chip 201, enabling the silicon frame 200 to perform both load-bearing and auxiliary conductive functions, improving the overall package wiring density and integration, and meeting the diverse interconnect path requirements of complex multi-chip systems.

[0052] Correspondingly, in this embodiment, the plurality of solder balls 209 are electrically connected to the other end of the corresponding via interconnect plug 204 and the other end of the second conductive plug 301.

[0053] Figure 7 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross section along the DD line.

[0054] This embodiment is based on the above embodiment ( Figure 3 and Figure 4 The encapsulation structure will continue to be described based on the previous embodiment, with the remainder being the same as the previous embodiment, except for the depth of the groove and the position of the glass chip 201. A detailed description will follow with reference to the accompanying drawings.

[0055] Please refer to Figure 7 and Figure 8 The groove extends through the silicon frame 200, and the opening of the groove is exposed on the opposite side surface of the silicon frame 200; the first molding layer 202 exposes the opposite side surface of the silicon frame 200 and the surface of the glass chip 201.

[0056] Correspondingly, in this embodiment, the chip bonding film 207 is no longer needed, and only the first filling layer 208 is retained, which fills the gap between the glass chip 201 and the groove sidewall.

[0057] Correspondingly, in this embodiment, the plurality of solder balls 209 are electrically connected to the other end of the corresponding via interconnect plug 204 and the glass chip 201.

[0058] Figure 9 This is a schematic diagram of the packaging structure in another embodiment of the present invention; Figure 10 yes Figure 9 Schematic diagram of the cross section along the EE line.

[0059] This embodiment is based on the above embodiment ( Figure 7 and Figure 8 The encapsulation structure will continue to be described based on the previous embodiment, with the remainder being the same as the previous embodiment, except that the silicon frame 200 also includes a through-silicon via plug 300. The following will provide a detailed description in conjunction with the accompanying drawings.

[0060] Please refer to Figure 9 and Figure 10The packaging structure further includes: a plurality of through-silicon via (TSV) plugs 400, the TSV plugs 400 being located within the silicon frame 200, and the silicon frame 200 exposing opposite ends of the TSV plugs 400; and a plurality of second conductive plugs 401, the second conductive plugs 401 being located within the first molding compound 202, the first molding compound 202 exposing one end of the second conductive plug 401, and the exposed end being electrically connected to the redistribution layer 203, and the other end of the second conductive plug 401 being electrically connected to one end of the TSV plugs 400.

[0061] By placing the through-silicon via (TSV) plug 400 within the silicon frame 200 and using the second conductive plug 401 within the first molding compound 202 to achieve electrical connection between the TSV plug 400 and the redistribution layer 203, additional vertical interconnect channels are constructed by fully utilizing the three-dimensional space of the silicon frame 200. This structural design expands the electrical interconnect dimension of the package structure without affecting the high-frequency signal transmission performance of the glass chip 201, enabling the silicon frame 200 to perform both load-bearing and auxiliary conductive functions, improving the overall package wiring density and integration, and meeting the diverse interconnect path requirements of complex multi-chip systems.

[0062] Correspondingly, in this embodiment, the plurality of solder balls 209 are electrically connected to the other end of the corresponding via interconnect plug 204, the other end of the second conductive plug 401 and the glass chip 201, respectively.

[0063] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A packaging structure, characterized in that, include: A silicon framework having a recess within it, with one side surface of the silicon framework exposing an opening in the recess; A glass chip, wherein the glass chip is fixed within the groove; A first molding layer, wherein the first molding layer covers the silicon framework and the glass chip; A redistribution layer, wherein the redistribution layer is located on the surface of the first molding layer; A plurality of via interconnect plugs are located within the first molding layer, the first molding layer exposing opposite ends of the via interconnect plugs, one end of the via interconnect plugs being electrically connected to the redistribution layer; A plurality of first conductive plugs are located within the first molding layer. The first molding layer exposes one end of the first conductive plug, and the exposed end is electrically connected to the redistribution layer. The other end of the first conductive plug is electrically connected to the glass chip. A chip structure is bonded to the redistribution layer, and high-frequency signals in the chip structure are transmitted to the glass chip via the redistribution layer and the first conductive plug.

2. The packaging structure as described in claim 1, characterized in that, The depth of the groove is less than the thickness of the silicon framework; the first molding layer exposes the surface of the silicon framework opposite to the other side.

3. The packaging structure as described in claim 2, characterized in that, It also includes: a chip bonding film, which is adhered to the bottom surface of the groove, and the glass chip is adhered to the surface of the chip bonding film; A first filling layer fills the gap between the glass chip and the sidewall of the groove.

4. The packaging structure as described in claim 2, characterized in that, The silicon framework serves only as a carrier for the glass chip.

5. The packaging structure as described in claim 4, characterized in that, Also includes: A plurality of solder balls, wherein the solder balls are electrically connected to the other end of the corresponding via interconnect plug.

6. The packaging structure as described in claim 2, characterized in that, Also includes: A plurality of through-silicon via plugs, the through-silicon via plugs being located within the silicon frame, and the silicon frame exposing the opposite ends of the through-silicon via plugs; A plurality of second conductive plugs are located within the first molding layer, the first molding layer exposes one end of the second conductive plug and the exposed end is electrically connected to the redistribution layer, and the other end of the second conductive plug is electrically connected to one end of the through-silicon via plug.

7. The packaging structure as described in claim 6, characterized in that, Also includes: A plurality of solder balls, wherein the plurality of solder balls are electrically connected to the other end of the corresponding via interconnect plug and the other end of the second conductive plug.

8. The packaging structure as described in claim 1, characterized in that, The groove extends through the silicon frame, and the opening of the groove is exposed on the opposite side surface of the silicon frame; the first molding layer exposes the opposite side surface of the silicon frame and the surface of the glass chip.

9. The packaging structure as described in claim 8, characterized in that, Also includes: A first filling layer fills the gap between the glass chip and the sidewall of the groove.

10. The packaging structure as described in claim 8, characterized in that, The silicon framework serves only as a carrier for the glass chip.

11. The packaging structure as described in claim 10, characterized in that, Also includes: A plurality of solder balls, wherein the plurality of solder balls are electrically connected to the other end of the corresponding via interconnect plug and the glass chip.

12. The packaging structure as described in claim 8, characterized in that, Also includes: A plurality of through-silicon via plugs, the through-silicon via plugs being located within the silicon frame, and the silicon frame exposing the opposite ends of the through-silicon via plugs; A plurality of second conductive plugs are located within the first molding layer, the first molding layer exposes one end of the second conductive plug and the exposed end is electrically connected to the redistribution layer, and the other end of the second conductive plug is electrically connected to one end of the through-silicon via plug.

13. The packaging structure as described in claim 12, characterized in that, Also includes: A plurality of solder balls are respectively electrically connected to the other end of the corresponding via interconnect plug, the other end of the second conductive plug, and the glass chip.

14. The packaging structure according to any one of claims 1 to 13, characterized in that, Also includes: The second filling layer fills the micro-gap between the chip structure and the redistribution layer after bonding.

15. The packaging structure according to any one of claims 1 to 13, characterized in that, Also includes: A second molding compound layer covers the chip structure.

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