Semiconductor package structure

Abstract

The application discloses a semiconductor package structure, which comprises a first die and a second die separated by a space along a first transverse direction; a third die located below the first die and the second die; a circuit layer located between the first die, the second die and the third die, the third die being electrically connected to the circuit layer, an active surface of each of the first die and the second die facing the circuit layer comprising a functional area and an edge area surrounding the functional area, the functional area being provided with a plurality of connecting components electrically connected to the circuit layer; and at least one dummy component located on the circuit layer and below the edge area, wherein each of the at least one dummy component extends along a second transverse direction perpendicular to the first transverse direction. The above technical scheme can at least resist stress, prevent delamination and inhibit warping by arranging the dummy component in the edge area of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] Delamination is observed between the copper pillars of the bridging chip and the RDL in the inter-chip region. This delamination is caused by structural stress. Delamination is most severe at the mold edges, but the situation improves from the top mold edge towards the center.

[0003] For example in Figure 1A and Figure 1B In the structure shown, the bridge die 10 is embedded in the molding layer 32 beneath the redistribution layer 20. The bridge die 10 is connected to the bottommost line of the redistribution layer (RDL) 20 via connection terminals 13 (e.g., copper pillars) on its surface. The bridge die 10 is located below the two chips 40 on the redistribution layer 20.

[0004] However, in Figure 1A and Figure 1B After assembly on the on-substrate (oS), failure analysis (FA) reveals that delamination occurs at the interface 13a between the connection terminals 13 of the bridging chip 10 and the bottommost lines of the redistribution layer 20. The delamination is most severe in the adjacent edge region 25 of the two chips 40, gradually improving in the direction 51 from the adjacent edge 42 towards the center. This delamination problem is not due to insufficient conventional adhesion. Conventional adhesion improvement methods, such as enhancing surface roughness through plasma treatment or acid pickling, are insufficient to defend against internal structural stresses and cannot effectively solve this type of delamination problem. This technical bottleneck limits the yield and reliability of semiconductor packaged products. Summary of the Invention

[0005] To address the above problems, this application proposes a semiconductor packaging structure that, by setting dummy components in the edge region of the chip, can at least resist stress, prevent delamination, and suppress warping.

[0006] According to one aspect of this application, a semiconductor package structure is provided, comprising: a first die and a second die, separated by a spacer along a first lateral direction; a third die located below the first die and the second die; a circuit layer located between the first die, the second die, and the third die, the third die being electrically connected to the circuit layer, each of the first die and the second die having an active surface facing the circuit layer including a functional region and an edge region between the functional region and the spacer, the functional region having a plurality of connection components electrically connected to the circuit layer; and at least one dummy component located on the circuit layer and below the edge region, wherein each of the at least one dummy component extends along a second lateral direction perpendicular to the first lateral direction.

[0007] In some embodiments, a first pitch is provided between a plurality of connecting components in a first lateral direction, and a second pitch is provided between at least one dummy component in the first lateral direction, wherein the first pitch and the second pitch are different.

[0008] In some embodiments, a first spacing is provided between a plurality of connecting components in a first lateral direction, and a second spacing is provided between at least one dummy component in the first lateral direction, wherein the first spacing is different from the second spacing.

[0009] In some embodiments, each of the plurality of connecting components has a first dimension in a first lateral direction, and each of the at least one dummy component has a second dimension in the first lateral direction, the second dimension being larger than the first dimension.

[0010] In some embodiments, the third die has a plurality of electrical connections electrically connected to the line layer, wherein, along a first lateral direction, each of at least one dummy component is located between the electrical connection and the spacing below the corresponding functional area.

[0011] In some embodiments, each of the at least one dummy component does not overlap with the interval in the vertical direction, wherein the vertical direction is perpendicular to the first lateral direction and the second lateral direction.

[0012] In some embodiments, each of the at least one dummy component includes multiple layers.

[0013] In some embodiments, each of the at least one dummy component and each of the plurality of connection components includes: a first metal layer located on the circuit layer; a second metal layer connected to the active surface of a corresponding one of the first die and the second die; and a connection layer located between the first metal layer and the second metal layer.

[0014] In some embodiments, at least one dummy component is arranged in multiple rows, each row extending along a second lateral direction, wherein the multiple rows include a first row and a second row adjacent to each other in the first lateral direction, a first gap exists between the dummy components in the first row, a second gap exists between the dummy components in the second row, and the first gap and the second gap are offset from each other in the first lateral direction.

[0015] According to another aspect of this application, a semiconductor package structure is provided, comprising: a circuit layer; a first die and a second die, located above the circuit layer and separated by a spacer along a first lateral direction; a third die, located below the circuit layer, a portion of the third die overlapping the spacer in a vertical direction, wherein the third die has a plurality of connection terminals electrically connected to the circuit layer, each of the first die and the second die having an active surface facing the circuit layer including a functional region and an edge region surrounding the functional region, the functional region having a plurality of connection components electrically connected to the circuit layer; and at least one dummy component located between the circuit layer and the edge region of a corresponding one of the first die and the second die, wherein, in the first lateral direction, each of the at least one dummy component is located between the plurality of connection terminals of the third die and the spacer.

[0016] In some embodiments, each of the plurality of connection terminals of the third die is connected to a corresponding via in the bottommost via layer of the circuit layer to form a connection interface, wherein the area of ​​the connection interface is smaller than the top surface area of ​​the corresponding one of the plurality of connection terminals.

[0017] In some embodiments, in the first lateral direction, at least one dummy component will space the interval between each connection terminal below the corresponding functional area of ​​the third die.

[0018] In some embodiments, each of the at least one dummy component extends vertically from the line layer to contact the active surface in the edge region of a corresponding one of the first die and the second die.

[0019] In some embodiments, the functional area of ​​each of the first die and the second die has a rectangular top view shape.

[0020] In some embodiments, each of the at least one dummy component extends along a second lateral direction perpendicular to the first lateral direction, and the third die has opposing sidewalls in the second lateral direction, with at least one dummy component extending beyond the sidewalls of the third die in the second lateral direction.

[0021] According to another aspect of this application, a semiconductor package structure is provided, comprising: a substrate; a circuit layer located above the substrate; a first die and a second die located above the circuit layer and separated by a spacer along a first lateral direction; a molding layer located above the circuit layer and surrounding the first die and the second die; a third die located below the circuit layer and electrically connected to the circuit layer, wherein an active surface of each of the first die and the second die facing the circuit layer includes a functional region and an edge region surrounding the functional region, the functional region having a plurality of connection members electrically connected to the circuit layer; and at least one dummy member located on the circuit layer and below the edge region, wherein each of the at least one dummy member extends along a second lateral direction perpendicular to the first lateral direction.

[0022] In some embodiments, the line layer is warped in the first lateral direction.

[0023] In some embodiments, the third die has a plurality of connection terminals that are in contact with and electrically connected to the line layer, and each of the at least one dummy component is located in a first lateral direction between the plurality of connection terminals of the third die and the spacing.

[0024] In some embodiments, the semiconductor package structure further includes a fill layer located between the first die and the circuit layer, and between the second die and the circuit layer, wherein the fill layer surrounds a plurality of connection components and at least one dummy component.

[0025] In some embodiments, the third die is a bridging die, and the first die and the second die are electrically connected to each other through a wiring layer and the third die. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1A and Figure 1B These are a cross-sectional view and a top view of an existing semiconductor packaging structure, respectively.

[0028] Figure 2A This is a cross-sectional schematic diagram of a semiconductor package structure according to one embodiment.

[0029] Figure 2B This is a top view schematic diagram of a semiconductor packaging structure according to an embodiment.

[0030] Figure 2C yes Figure 2AEnlarged schematic diagram of the connecting components and dummy components in the diagram.

[0031] Figure 3A This is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment.

[0032] Figure 3B yes Figure 3A A top view of multiple cores and dummy components.

[0033] Figure 4 This is a top view of a semiconductor package structure comprising multiple dies and dummy components according to another embodiment.

[0034] Figure 5A This is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment.

[0035] Figure 5B yes Figure 5A Layout diagram of the electrical connector of the third die below the middle interval.

[0036] Figure 5C yes Figure 5A A schematic diagram showing the layout of the pads for the first die and the pads for the second die at the interval.

[0037] Figure 5D yes Figure 5A A schematic diagram of the pads and their layout on the circuit layer below the spacing in the diagram.

[0038] Figures 6A to 6J This is a cross-sectional schematic diagram at multiple stages during the formation of a semiconductor package structure according to another embodiment. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0040] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0041] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] An embodiment of this application provides a semiconductor packaging structure. Figure 2A This is a cross-sectional schematic diagram of a semiconductor package structure according to one embodiment. Figure 2B This is a top view schematic diagram of a semiconductor packaging structure according to an embodiment. Figure 2A The cross section can correspond to Figure 2B The cross section at point AA in the diagram.

[0043] refer to Figure 2A and Figure 2B The semiconductor package structure 100 may include a first die 110 and a second die 120, which are separated by a spacing 135 along a first lateral direction X. The spacing 135 may be located between opposing sidewalls 110s and 120s of the first die 110 and the second die 120. The first die 110 and the second die 120 may be surrounded by a molding layer 172.

[0044] The circuit layer 140 is located below the first die 110 and the second die 120. The third die 150 is located below the circuit layer 140. It should be understood that, although in Figure 2B The outline of the third die 150 is shown in solid lines, but the third die 150 is located below the first die 110 and the second die 120. The third die 150 may be surrounded by a molding layer 174.

[0045] A portion of the third die 150 overlaps with the spacing 135 in the vertical direction Z. The third die 150 may serve as a bridge die. In some embodiments, the first die 110 and the second die 120 may be electrically connected to each other via the wiring layer 140 and the third die 150.

[0046] The active surface 110a of the first die 110 faces the circuit layer 140. The active surface 110a includes a functional region 111 and an edge region 112 between the functional region 111 and the spacing 135. The edge region 112 is adjacent to the sidewall 110s of the first die 110 and can extend along the sidewall 110s. A plurality of connecting members 113 (also referred to as functional connecting members) are provided in the functional region 111. The plurality of connecting members 113 can be used for electrical connection with the circuit layer 140. The connecting members 113 can be conductive bumps, such as copper bumps. No connecting members 113 are provided in the edge region 112.

[0047] The active surface 120a of the second die 120 faces the circuit layer 140. The active surface 120a includes a functional region 121 and an edge region 122 between the functional region 121 and the spacing 135. The edge region 122 is adjacent to and extends along the sidewall 120s of the second die 120. A plurality of connecting members 123 (also referred to as functional connecting members) are provided in the functional region 121. The plurality of connecting members 123 can be used for electrical connection with the circuit layer 140. The connecting members 123 can be conductive bumps, such as copper bumps. No connecting members 123 are provided in the edge region 122.

[0048] The top view shape of functional area 111 of the first die 110 and functional area 121 of the second die 120 can both be rectangular. Edge areas 112 and 122 are located outside the corresponding functional areas 111 and 121, respectively.

[0049] The surface of the third die 150 facing the circuit layer 140 has a plurality of electrical connectors 151 (also referred to as connection terminals). The electrical connectors 151 can be conductive connectors, such as copper pillars. The third die 150 is electrically connected to the circuit layer 140 through the plurality of electrical connectors 151.

[0050] The circuit layer 140 includes a dielectric layer 142 and a multilayer redistribution circuit 145 disposed in the dielectric layer 142. The multilayer redistribution circuit 145 includes multiple layers of laterally extending conductive lines 144 and multiple layers of vias 146 extending vertically between adjacent layers of conductive lines 144 and connecting adjacent layers of conductive lines 144. A plurality of electrical connectors 151 of the third die 150 are connected to the bottommost redistribution circuit 145 of the multilayer redistribution circuit 145.

[0051] Multiple dummy components 160 are disposed on the line layer 140, and located below edge region 112 and below edge region 122. The dummy components 160 are not electrically connected to the corresponding first die 110 and second die 120, and may not be electrically connected to the line layer 140. In some embodiments, the dummy components 160 may be formed of a metallic material.

[0052] Each dummy component 160 extends along a second lateral direction Y perpendicular to the first lateral direction X. It should be understood that the first lateral direction X is the warping direction of the circuit layer 140; that is, when the circuit layer 140 warps, the central region of the circuit layer 140 along the first lateral direction X protrudes or recedes compared to the edge region. In other words, the extension direction of the dummy component 160 is perpendicular to the warping direction of the semiconductor package structure 100.

[0053] By providing dummy components 160 below the edge regions 112 and 122 (areas without connecting components 113 and 123) of the first die 110 and the second die 120, the roughness and bonding strength of the area below the edge region 122 can be improved, thus strengthening the structure and resisting stress between the dies, preventing delamination at the interface between the third die 150 and the circuit layer 140. Furthermore, by setting the extension direction of the dummy components 160 perpendicular to the warping direction of the circuit layer 140, the bonding strength and anti-warping capability can be further enhanced.

[0054] Each dummy component 160 can extend vertically from the circuit layer 140 until it contacts the edge region 112, 122 of the corresponding one of the first die 110 and the second die 120. This can further enhance the structural strength and resist stress between the dies.

[0055] Each of the plurality of electrical connections 151 of the third die 150 may be located below a corresponding one of the functional areas 111 of the first die 110 and the functional area 121 of the second die 120. Each dummy component 160 does not overlap with the spacing 135 in the vertical direction Z, that is, no dummy component 160 is provided in the spacing 135. The vertical direction Z is the direction perpendicular to the first lateral direction X and the second lateral direction Y.

[0056] In the first lateral direction X, each dummy component 160 can be located between multiple connection terminals 151 and spacing 130 below the corresponding functional areas 111, 121. In the first lateral direction X, the dummy component 160 separates the spacing 130 from the connection terminals 151 below the corresponding functional areas 111, 121. Thus, stress can be resisted in the direction from the corresponding edge areas 112 and 122 of the first die 110 and the second die 120 toward the center of the first die 110 and the second die 120, preventing delamination at the interface between the third die 150 and the circuit layer 140.

[0057] In some embodiments, the electrical connector 151 is connected to the bottommost via 146 in the multilayer redistribution circuit 145. An interface 151f is formed between the electrical connector 151 and the bottommost via 146. In some embodiments, the area of ​​the interface 151f is smaller than the top surface area of ​​the corresponding electrical connector 151. By providing the dummy component 160, delamination can be prevented at such a small interface 151f.

[0058] See Figure 2B The dummy components 160 can be arranged in at least one row on opposite sides of the interval 130. In this embodiment, the dummy components 160 can be arranged in four rows on opposite sides of the interval 130, with each row extending along the second lateral direction Y. In this embodiment, in the top view, the plurality of dummy components 160 are all located within the region of the third die 150.

[0059] Taking a plurality of dummy components 160 below the first die 110 as an example, these dummy components 160 are arranged in four adjacent rows R1, R2, R3, and R4 in the first lateral direction X. Row R1 is adjacent to the sidewall 110s of the first die 110, and row R4 is closer to the center of the first die 110. There are gaps between the dummy components 160 in each row of R1, R2, R3, and R4, and the gaps in adjacent rows are offset from each other. Specifically, taking rows R1 and R2 as examples, there may be gaps 283 between the dummy components 160 in row R1, and gaps 284 between the dummy components 160 in row R2. Gap 283 and gap 284 are offset from each other in the first lateral direction X, that is, gap 283 and gap 284 are not aligned in the first lateral direction X. In some embodiments, the arrangement of rows R3 and R4 may be the same as the arrangement of rows R1 and R2. In some embodiments, the arrangement of the plurality of dummy components 160 below the second die 120 may be the same as the arrangement of the plurality of dummy components 160 below the first die 110, or they may be arranged symmetrically to each other. By setting the gaps between adjacent rows in an offset manner, the dummy components 160 can achieve stress blocking at various positions along the second lateral direction Y.

[0060] Further integration Figure 2CAs shown, the connection component 113 may include pads 1132 disposed on and electrically connected to the circuit layer 140, pads 1134 disposed on the functional area 111 of the active surface 110a of the first die 110, and a connection layer 1136 connecting the pads 1132 and 1134. The connection layer 1136 may be made of a material such as solder for electrically connecting the pads 1132 and 1134. The connection component 123 may include pads 1232 disposed on and electrically connected to the circuit layer 140, pads 1234 disposed on the functional area 121 of the active surface 120a of the second die 120, and a connection layer 1236 connecting the pads 1232 and 1234. The connection layer 1236 may be made of a material such as solder for electrically connecting the pads 1232 and 1234.

[0061] See Figure 2C In some embodiments, the plurality of connecting components 113 have a pitch P11 in the first lateral direction X. It should be understood that the pitch refers to the distance between the center of a first component (e.g., one connecting component 113) and the center of an adjacent second component (e.g., another adjacent connecting component 113). The dummy components 160 below the edge region 112 have a pitch P12 in the first lateral direction X. In some embodiments, the pitch P11 is different from the pitch P12. The plurality of connecting components 113 have a spacing S11 in the first lateral direction X. It should be understood that the pitch refers to the distance between adjacent sidewalls of two adjacent components (e.g., two adjacent connecting components 113). The dummy components 160 below the edge region 112 have a spacing S12 in the first lateral direction X. In some embodiments, the spacing S11 is different from the spacing S12. In some embodiments, the pitch P12 of the dummy components 160 may be greater than the pitch P11 of the connecting components 113. In some embodiments, the spacing S12 of the dummy components 160 may be greater than the spacing S11 of the connecting components 113.

[0062] A plurality of connecting components 123 are spaced together in a first lateral direction X by a pitch P21, and dummy components 160 below the edge region 122 are spaced together in the same direction X by a pitch P22. In some embodiments, the pitch P21 and the pitch P22 are different. A plurality of connecting components 123 are spaced together in a first lateral direction X by a spacing S21, and dummy components 160 below the edge region 122 are spaced together in the same direction X by a spacing S22. In some embodiments, the spacing S21 and the spacing S22 are different. In some embodiments, the pitch P22 of the dummy components 160 below the edge region 122 may be greater than the pitch P21 of the connecting components 123. In some embodiments, the spacing S22 of the dummy components 160 may be greater than the spacing S21 of the connecting components 123.

[0063] In some embodiments, each connecting component 113 may have a dimension W11 (also referred to as width) in the first lateral direction X, and each dummy component 160 may have a dimension W12 (also referred to as width) in the first lateral direction X. In some embodiments, dimension W12 may be larger than dimension W11.

[0064] In some embodiments, each connecting member 123 has a dimension W21 (also referred to as width) in the first lateral direction X, and each dummy member 160 has a dimension W22 (also referred to as width) in the first lateral direction X, wherein the dimension W22 is larger than the dimension W21. The larger width helps to enhance the stress dispersion effect.

[0065] In some embodiments, the pitch P12, spacing S12, and dimension W12 of the dummy component 160 below the edge region 112 may be the same as, or different from, the corresponding pitch P22, spacing S22, and dimension W22 of the dummy component 160 below the edge region 122. In some embodiments, the pitch P11, spacing S11, and dimension W11 of the connecting component 113 may be the same as, or different from, the corresponding pitch P21, spacing S21, and dimension W21 of the connecting component 123.

[0066] Figure 3A This is a cross-sectional schematic diagram of a semiconductor package structure 200 according to another embodiment. Figure 3B yes Figure 3A A top view of multiple cores and dummy components. Figure 3A and Figure 3B Several aspects of the illustrated embodiments are related to the above references. Figures 2A to 2C The descriptions are the same; only the descriptions below are identical. Figure 3A and Figure 3B The differences between the illustrated embodiments are as follows.

[0067] See Figure 3A In this embodiment, multiple dummy components 260 are disposed on the circuit layer 140, and located below edge region 112 and below edge region 122. Each dummy component 260 includes multiple layers. Specifically, the dummy component 260 may include a first metal layer 262 located on the circuit layer 140, a second metal layer 264 connected to a corresponding one of the first die 110 and the second die 120, and a connection layer 266 located between the first metal layer 262 and the second metal layer 264.

[0068] In some embodiments, the first metal layer 262 of the dummy component 260 may be formed simultaneously with the pads 1132 of the connecting component 113 and the pads 1232 of the connecting component 123. The second metal layer 264 of the dummy component 260 may be formed simultaneously with the pads 1134 of the connecting component 113 and the pads 1234 of the connecting component 123. The connection layer 266 of the dummy component 260 is formed simultaneously with the connection layer 1136 of the connecting component 113 and the connection layer 1236 of the connecting component 123, and may be made of the same material.

[0069] See Figure 3B As shown, the arrangement of the multiple dummy components 260 can be the same as the above reference. Figure 2B The same as shown and described.

[0070] Figure 4 A top view schematic diagram of a plurality of dies and dummy components of a semiconductor package structure 300 according to another embodiment is shown. See also Figure 4 As shown, each dummy component 360 can correspond to the above reference. Figures 2A to 2C The description of the dummy component 160 or above is referenced. Figure 3A and Figure 3B The described dummy component 260.

[0071] Each dummy component 360 extends along the second lateral direction Y. The third die 150 has sidewalls 152, 153 opposite each other in the second lateral direction Y. In this embodiment, at least one of the plurality of dummy components 360 below the first die 110 extends beyond the sidewall 152 of the third die 150 in the second lateral direction Y, and at least one dummy component 360 extends beyond the sidewall 153. Specifically, the uppermost and lowermost dummy components 360 in at least one of rows R1, R2, R3, and R4 extend beyond the sidewalls 152 and 153 of the third die 150, respectively. In this embodiment, the uppermost and lowermost dummy components 360 in rows R2 and R4 extend beyond the sidewalls 152 and 153 of the third die 150, respectively. The arrangement of the plurality of dummy components 360 below the second die 120 can be the same as the arrangement of the plurality of dummy components 160 below the first die 110, or symmetrically arranged with each other. By arranging the dummy component 360 beyond the sidewalls 152 and 153 of the third die 150, the extension of the dummy component 160 in the second lateral direction Y can cover the area of ​​the electrical connector 151 of the third die 150, thereby more effectively resisting stress and avoiding delamination at the interface.

[0072] Figure 5A This is a cross-sectional schematic diagram of a semiconductor package structure 400 according to another embodiment. Figure 5B yes Figure 5AA schematic diagram of the layout of the electrical connector 151 of the third die 150 below the interval 135. Figure 5C yes Figure 5A A schematic diagram showing the layout of pad 1134 of the first die 110 and pad 1234 of the second die 120 at interval 135. Figure 5D yes Figure 5A A schematic diagram of the layout of pads 1132 and 1232 on the circuit layer 140 below spacing 135. In this embodiment, the above reference can be used. Figure 3B and Figure 4 The described method is used to arrange multiple dummy components 260.

[0073] See Figure 5A and Figure 5B As shown, a plurality of electrical connectors 151 of the third die 150 can be disposed on the entire surface of the third die 150 facing the circuit layer 140. The plurality of electrical connectors 151 can be disposed in the region below the spacing 135, or in the region below the edge region 112 of the first die 110 and the edge region 122 of the second die 120. See also Figure 5C and Figure 5D The pads 1132 and 1232 on the circuit layer 140 are not located below the spacing 135. The layout of the pads 1134 of the first die 110 and the pads 1234 of the second die 120 is perfectly matched with the layout of the pads 1132 and 1232 on the circuit layer 140, so that the pads 1134 and 1234 can be correctly bonded to the pads 1132 and 1232.

[0074] Figures 6A to 6J A cross-sectional schematic diagram is shown at several stages during the formation of a semiconductor package structure 500 according to another embodiment.

[0075] See Figure 6A A carrier 1001 is provided, and a release layer 1002 is disposed on the carrier 1001. In some embodiments, the carrier 1001 may be a glass carrier, a ceramic carrier, etc. Further, a metal layer 1004 is formed on the release layer 1002.

[0076] Subsequently, a circuit layer 180 is formed on the patterned metal layer 1004. The circuit layer 180 may be referred to as a back-side circuit layer or a back-side redistribution layer. The circuit layer 180 may have a dielectric layer 182 and multiple layers of redistribution lines 185 embedded in the dielectric layer 182. In some embodiments, the dielectric layer 182 includes multiple dielectric layers, the interfaces between which are not shown in this embodiment. The multiple layers of redistribution lines 185 include multiple layers of laterally extending conductive lines 184, and multiple vias 186 extending vertically between adjacent layers of conductive lines 184 and connecting adjacent layers of conductive lines 184. In this embodiment, the circuit layer 180 is formed to include three dielectric layers and two layers of conductive lines 184.

[0077] See Figure 6B A through-hole 608 and pad 625 are formed above the circuit layer 180. See also Figure 6C The third die 150 is attached to the circuit layer 180 via an adhesive layer 617. Electrical connectors 151 of the third die 150 are disposed on the side facing away from the circuit layer 180. In some embodiments, other components may be electrically connected to pads 625 on the circuit layer 180. In this embodiment, a plurality of capacitors 613 are bonded to pads 625 on the circuit layer 180.

[0078] Next, see Figure 6D A molding layer 607 is formed around the through hole 608, the third die 150, and the capacitor 613. After the molding layer 607 is formed, the electrical connector 151 of the through hole 608 and the third die 150 can be exposed by a grinding process.

[0079] See Figure 6E The aforementioned circuit layer 140 is formed above the molding layer 607. The circuit layer 140 may be referred to as the front circuit layer or the front redistribution layer. Then, the aforementioned pads 1132, 1232 and the first metal layer 262 may be formed on the circuit layer 140 simultaneously, and connection layers 1136, 1236 and 266 may be formed on the pads 1132, 1232 and the first metal layer 262 simultaneously, respectively.

[0080] See Figure 6F The pads 1134 of the first die 110 are bonded to the pads 1132 via the connection layer 1136 to form a connection component 113. The pads 1234 of the second die 120 are bonded to the pads 1232 via the connection layer 1236 to form a connection component 123. Furthermore, the aforementioned second metal layers 264 are respectively provided in the edge regions of the active surfaces of the first die 110 and the second die 120 facing the line 140. Each second metal layer 264 is bonded to the corresponding first metal layer 262 via the connection layer 266 to form the aforementioned dummy component 260.

[0081] Then, a filler layer 690 is formed between the first die 110 and the wiring layer 140, and between the second die 120 and the wiring layer 140. The filler layer 690 may be, for example, a bottom filler. The filler layer 690 surrounds the plurality of connecting members 113, 123 and each dummy member 260. The filler layer 690 may be continuous below the first die 110 and the second die 120. A molding layer 609 covering the first die 110 and the second die 120 is formed above the wiring layer 140.

[0082] See Figure 6G ,Will Figure 6F The resulting structure is flipped, causing the release layer 1002 to detach, thereby removing the release layer 1002 and the carrier 1001. Then, the metal layer 1004 can be patterned using an etching process, and metal can be electroplated over the patterned metal layer 1004 to collectively form bumps 611, such as... Figure 6H As shown. Then, solder 612 is formed above the first bump 611.

[0083] See Figure 6I The back-side grinding process removes a portion of the molding seal layer 609, making the surface of the molding seal layer 609 away from the circuit layer 140 flush with the surfaces of the first die 110 and the second die 120 away from the circuit layer 140. The resulting structure can then be sawn.

[0084] Figure 6J As shown, solder 612 is used to... Figure 6I The resulting structure is attached to substrate 615. This process can be referred to as the upper substrate assembly process. An underfill 670 is formed between substrate 615 and circuit layer 180. Furthermore, external connectors 616, such as solder balls, are formed on the surface of substrate 615 opposite to circuit layer 180 for external connections. Thus, a semiconductor package structure 500 is formed.

[0085] In the semiconductor package structure 500, at least one dummy component 260 is included, located on the circuit layer 140. The dummy component 260 may be related to the above-referenced... Figures 2A to 4 The described dummy components are the same or similar. It should be understood that the above process uses the formation of dummy component 260 as an example, and in other embodiments, the above dummy component 160 may also be formed. In some embodiments, the third die 150 is a bridging die, and the first die 110 and the second die 120 are electrically connected to each other through the wiring layer 140 and the third die 150. In some embodiments, the semiconductor package structure 500 may be referred to as a FOCoS-B (Fan Out Chip on Substrate-Bridge) structure.

[0086] In some embodiments, the warpage direction of the circuit layer 140 is a first lateral direction X. By providing dummy components 160 at the edge regions 112 of the first die 110 and the second die 120 and below the edge regions, structural reinforcement can be achieved to resist inter-die stress and prevent delamination at the interface between the third die 150 and the circuit layer 140. In some embodiments, the extension direction of the dummy component 260 is perpendicular to the warpage direction of the circuit layer 140 (e.g., ...). Figure 3B This can enhance bonding strength and resistance to warping.

[0087] In some cases, Figure 6J After the described upper substrate assembly process, delamination is prone to occur at the interface between the third die 150 and the circuit layer 140. By providing a dummy component 160 in the semiconductor package structure 500, the stress between the first die 110 and the second die 120 can be resisted, and no delamination phenomenon was found after the upper substrate assembly process.

[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: The first die and the second die are separated by a gap along the first transverse direction; The third die is located below the first die and the second die; A circuit layer is located between the first die, the second die, and the third die. The third die is electrically connected to the circuit layer. The active surface of each of the first die and the second die facing the circuit layer includes a functional area and an edge area between the functional area and the interval. The functional area is provided with a plurality of connecting components electrically connected to the circuit layer. At least one dummy component is located on the line layer and below the edge region, wherein each of the at least one dummy component extends along a second lateral direction perpendicular to the first lateral direction.

2. The semiconductor packaging structure according to claim 1, characterized in that, The plurality of connecting components have a first pitch in the first lateral direction, and the at least one dummy component has a second pitch in the first lateral direction, wherein the first pitch and the second pitch are different.

3. The semiconductor packaging structure according to claim 1, characterized in that, The plurality of connecting components have a first spacing in the first lateral direction, and the at least one dummy component has a second spacing in the first lateral direction, wherein the first spacing is different from the second spacing.

4. The semiconductor packaging structure according to claim 1, characterized in that, Each of the plurality of connecting components has a first dimension in the first lateral direction, and each of the at least one dummy component has a second dimension in the first lateral direction, the second dimension being larger than the first dimension.

5. The semiconductor packaging structure according to claim 1, characterized in that, The third die has multiple electrical connectors that are electrically connected to the circuit layer. Wherein, along the first lateral direction, each of the at least one dummy component is located between the electrical connector and the interval below the corresponding functional area.

6. The semiconductor packaging structure according to claim 1, characterized in that, Each of the at least one dummy component does not overlap with the interval in the vertical direction, wherein the vertical direction is perpendicular to the first lateral direction and the second lateral direction.

7. The semiconductor packaging structure according to claim 1, characterized in that, Each of the at least one dummy component comprises multiple layers.

8. The semiconductor packaging structure according to claim 7, characterized in that, Each of the at least one dummy component and each of the plurality of connecting components includes: A first metal layer is located on the circuit layer; A second metal layer is connected to the active surface of a corresponding one of the first die and the second die; A connecting layer is located between the first metal layer and the second metal layer.

9. The semiconductor packaging structure according to claim 1, characterized in that, The at least one dummy component is arranged in multiple rows, with each row extending along the second lateral direction. The multiple rows include a first row and a second row that are adjacent in the first lateral direction. There is a first gap between the dummy components in the first row and a second gap between the dummy components in the second row. The first gap and the second gap are offset from each other in the first lateral direction.

10. A semiconductor packaging structure, characterized in that, include: Line layer; The first die and the second die are located above the circuit layer and are separated by a gap along the first lateral direction; A third die, located below the circuit layer, has a portion that overlaps the spacing in the vertical direction. The third die has a plurality of connection terminals electrically connected to the circuit layer. The active surface of each of the first and second dies facing the circuit layer includes a functional area and an edge area surrounding the functional area. The functional area is provided with a plurality of connection components electrically connected to the circuit layer. At least one dummy component is located between the circuit layer and the edge region of a corresponding one of the first die and the second die, wherein, in the first lateral direction, each of the at least one dummy component is located between the plurality of connection terminals of the third die and the spacing.

11. The semiconductor packaging structure according to claim 10, characterized in that, Each of the plurality of connection terminals of the third die is connected to a corresponding through hole in the bottommost through-hole layer of the circuit layer to form a connection interface, wherein the area of ​​the connection interface is smaller than the top surface area of ​​the corresponding one of the plurality of connection terminals.

12. The semiconductor packaging structure according to claim 10, characterized in that, In the first lateral direction, the at least one dummy component spaces the interval from each of the connection terminals below the corresponding functional area of ​​the third die.

13. The semiconductor packaging structure according to claim 10, characterized in that, Each of the at least one dummy component extends vertically from the line layer to contact the active surface in the edge region of a corresponding one of the first die and the second die.

14. The semiconductor packaging structure according to claim 10, characterized in that, The functional area of ​​each of the first die and the second die has a rectangular top view shape.

15. The semiconductor packaging structure according to claim 10, characterized in that, Each of the at least one dummy component extends along a second lateral direction perpendicular to the first lateral direction. The third die has sidewalls opposite each other in the second lateral direction, and the at least one dummy member extends beyond the sidewalls of the third die in the second lateral direction.

16. A semiconductor packaging structure, characterized in that, include: substrate; The circuit layer is located above the substrate; The first die and the second die are located above the circuit layer and are separated by a gap along the first lateral direction; A molding layer is located above the circuit layer and surrounds the first die and the second die; The third die is located below the circuit layer and electrically connected to the circuit layer. The active surface of each of the first die and the second die facing the circuit layer includes a functional area and an edge area surrounding the functional area. The functional area is provided with a plurality of connecting components electrically connected to the circuit layer. At least one dummy component is located on the line layer and below the edge region, wherein each of the at least one dummy component extends along a second lateral direction perpendicular to the first lateral direction.

17. The semiconductor packaging structure according to claim 16, characterized in that, The circuit layer is warped in the first lateral direction.

18. The semiconductor packaging structure according to claim 17, characterized in that, The third die has multiple connection terminals that are in contact with and electrically connected to the circuit layer. Each of the at least one dummy component is located in the first lateral direction between the plurality of connection terminals of the third die and the interval.

19. The semiconductor packaging structure according to claim 16, characterized in that, Also includes: A filler layer is located between the first die and the circuit layer, and between the second die and the circuit layer. The filling layer surrounds the plurality of connecting components and the at least one dummy component.

20. The semiconductor packaging structure according to claim 16, characterized in that, The third core is a bridge core, and the first core and the second core are electrically connected to each other through the circuit layer and the third core.

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