High thermal conductivity integrated power semiconductor package module and process

Abstract

The application discloses a high-thermal-conductivity integrated power semiconductor packaging module and a process. The packaging module comprises a packaging substrate, a power semiconductor chip, aluminum bonding wires, a plastic packaging shell and power lead terminals; the packaging substrate is formed by sequentially and directly connecting a chip solder copper layer, a high-thermal-conductivity insulating ceramic adhesive film layer and a metal heat dissipation bottom plate, and the high-thermal-conductivity insulating ceramic adhesive film layer is distributed with thermal conductive ceramic fillers. In the preparation, oxygen-free copper foil, high-thermal-conductivity ceramic insulating adhesive film and water-cooling copper bottom plate are one-time hot-pressed and compounded to form a shape, and then chip fixing, aluminum wire bonding, shell assembling, plastic packaging glue filling and terminal forming are sequentially completed. The application can reduce the thermal conductive interface, shorten the heat dissipation path, reduce the interface thermal resistance, simplify the packaging process, reduce the risk of welding defects, improve the heat dissipation performance, production efficiency and long-term use reliability of the packaging module.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging substrate technology, specifically relating to a high thermal conductivity integrated power semiconductor packaging module and process. Background Technology

[0002] Currently, the mainstream heat dissipation substrates for high-power modules are DBC (Direct Bonded Copper) and AMB (Active Metal Brazed) substrates. Figure 1 As shown, the standard packaging structure is: chip → DBC / AMB ceramic substrate → solder ribbon → copper water-cooled base plate. The ceramic substrate and the heat dissipation base plate are connected by solder ribbon brazing. The whole solution has four major pain points: Multi-layered interfaces result in high thermal resistance and poor heat dissipation. Traditional DBC insulating ceramic layers are 120μm thick, with a single-layer insulation thermal resistance as high as 0.23℃. cm² / W; at the same time, the four layers of materials, namely chip, ceramic, solder ribbon and base plate, form a multi-layer thermal interface. The superposition of interface thermal resistance leads to the obstruction of heat conduction of the chip. Under high-power SiC high-temperature conditions, the junction temperature is too high, which limits the improvement of module power density.

[0003] The process is lengthy and the processing cost is high. ① A secondary brazing process must be added, which consumes additional solder and welding material and takes up time in the welding production line; ② The coefficient of thermal expansion (CTE) of ceramic and copper base plate is very different. After hot and cold cycles, the base plate warps severely. The base plate needs to be pre-milled to pre-curve, which increases the cost of machining equipment, labor and material loss.

[0004] Welding voids and delamination result in poor reliability. The brazing process is prone to producing weld voids; during thermal shock and power cycling, the ceramic, solder, and copper base plate expand and contract inconsistently, making the interface prone to delamination and solder strip detachment. The conventional thermal shock cycle life is less than 2,000 cycles, which cannot meet the 15-year long-life requirement of new energy vehicles; multiple welding processes result in a large number of defective products, with high cost of defective materials, and all losses of defective materials are borne by the module manufacturer.

[0005] The overall cost of materials remains high: The metallization process of AMB ceramic substrates is complex and expensive. In addition, there are costs for solder ribbon procurement, base plate machining, welding processes, and defective product losses. Taking Infineon's HPD standard automotive module as an example, the comprehensive additional cost of a single module exceeds 25 yuan, which puts great pressure on the cost of vehicle electronic control under mass production.

[0006] Existing conventional IMS metal substrates are only used for low-voltage, low-power PCBs. The insulating film has low thermal conductivity and insufficient temperature and pressure resistance, making it unsuitable for high-temperature, high-power packaging scenarios of automotive high-voltage SiC / IGBTs. The industry lacks a new integrated packaging structure that combines low thermal resistance, simplified process, low cost, and high cycle reliability. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high thermal conductivity integrated power semiconductor packaging module and process, which overcomes the defects of traditional DBC / AMB ceramic substrate multilayer solder ribbon packaging, such as high thermal resistance, complex process, high processing cost, and easy interface delamination failure.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a high thermal conductivity integrated power semiconductor packaging module, including a packaging substrate, a power semiconductor chip, aluminum bonding wire, a plastic encapsulation shell, and power lead-out terminals; The packaging substrate includes a chip solder copper layer, a high thermal conductivity insulating ceramic film layer, and a metal heat dissipation base plate. The chip solder copper layer, the high thermal conductivity insulating ceramic film layer, and the metal heat dissipation base plate are directly connected from top to bottom. The thickness of the high thermal conductivity insulating ceramic film layer is 60-80 μm. The chip solder copper layer includes a chip mounting area and a power terminal area; the high thermal conductivity insulating ceramic film layer includes an insulating substrate and thermally conductive ceramic fillers distributed within the insulating substrate. The power semiconductor chip is disposed in the chip mounting area of ​​the chip solder copper layer and is connected to the chip solder copper layer. The aluminum bonding wire connects the electrodes of the power semiconductor chip to the power terminal area of ​​the chip's copper solder layer. The power lead-out terminal is disposed on the plastic-encapsulated housing and connected to the power terminal area; The plastic encapsulation shell is disposed on the packaging substrate, and a packaging space for accommodating the power semiconductor chip and aluminum bonding wire is formed between the plastic encapsulation shell and the packaging substrate. The metal heat sink base plate is used for heat dissipation of the encapsulated module.

[0009] Furthermore, the thermally conductive ceramic filler includes aluminum nitride filler and alumina filler.

[0010] Furthermore, the copper solder layer of the chip is an oxygen-free copper foil with a thickness of 0.2 to 0.4 mm.

[0011] Furthermore, the thickness of the metal heat dissipation base plate is 2-4mm, and the metal heat dissipation base plate is an oxygen-free copper base plate with built-in water cooling channels.

[0012] Furthermore, the power semiconductor chip includes at least one of IGBT power chips, FRD power chips, and SiC power chips.

[0013] Furthermore, the encapsulated shell contains potting compound, which covers the power semiconductor chip and aluminum bonding wire.

[0014] Furthermore, the surface of the copper layer of the chip is subjected to nickel metallization or nickel-palladium-gold metallization treatment.

[0015] A process for manufacturing a high thermal conductivity integrated power semiconductor package module includes the following steps: S1. Integrated substrate molding: Select 0.2-0.4mm oxygen-free copper foil, 60-80μm high thermal conductivity ceramic insulating film and 2-4mm water-cooled copper base plate, and hot press composite molding in an environment of 170-190℃; S2, chip sintering; S3, wire bonding; S4. Housing assembly, plastic encapsulation and potting, terminal injection molding, and finally, the power module packaging is completed.

[0016] Furthermore, the specific steps of step S2 are as follows: using high-temperature solder, the chip is directly sintered and fixed to the chip solder copper layer.

[0017] Furthermore, step S3 specifically involves the following steps: connecting the electrodes of the power semiconductor chip to the power terminal area of ​​the chip's copper solder layer using an aluminum wire bonding process to complete the electrical connection.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. Reduced thermal resistance of the packaging module and improved heat dissipation performance: This invention directly connects the chip solder copper layer, the high thermal conductivity insulating ceramic film layer and the metal heat sink base plate from top to bottom, and forms an integrated packaging substrate through one-time hot pressing. This eliminates the solder strip brazing layer between the traditional DBC or AMB ceramic substrate and the metal heat sink base plate, reduces the number of thermal interfaces, shortens the heat transfer path between the power semiconductor chip and the metal heat sink base plate, helps to reduce interface thermal resistance, improves the efficiency of heat transfer from the power semiconductor chip to the outside, thereby reducing the chip's operating junction temperature and improving the power carrying capacity of the packaging module.

[0019] 2. Balancing thermal conductivity and electrical insulation performance: The high thermal conductivity insulating ceramic film layer includes an insulating matrix and aluminum nitride and alumina fillers distributed within the insulating matrix. The thermally conductive ceramic fillers form a thermally conductive path within the insulating matrix, improving the thermal conductivity of the insulating layer while ensuring electrical insulation between the chip solder copper layer and the metal heat sink. The thickness of the high thermal conductivity insulating ceramic film layer is set to 60–80 μm, which can shorten the heat transfer distance through the insulating layer and further reduce the thermal resistance of the insulating layer.

[0020] 3. Improved heat dissipation under high-power conditions: The metal heat sink base plate adopts an oxygen-free copper base plate with built-in water-cooling channels, which can directly serve as the load-bearing structure and heat dissipation structure of the packaged module. The heat generated by the power semiconductor chip is transferred to the metal heat sink base plate through the chip solder copper layer and the high thermal conductivity insulating ceramic film layer. It can then be carried away in time by the cooling medium flowing through the built-in water-cooling channels, thereby improving the heat dissipation capacity of the packaged module under high-power and high heat flux density conditions.

[0021] 4. Simplified packaging process and improved production efficiency: The invention uses a one-time hot-pressing composite molding process at 170-190 ℃ to combine oxygen-free copper foil, high thermal conductivity ceramic insulating film, and water-cooled copper base plate, eliminating the soldering process between the ceramic substrate and the heat dissipation base plate and the corresponding secondary assembly process in traditional packaging structures. Subsequently, chip fixing, wire bonding, shell assembly, plastic encapsulation and potting, and terminal injection molding are completed in sequence, making the manufacturing process of the packaging module simpler, which helps to shorten the production cycle and improve the efficiency of mass production.

[0022] 5. Reduced risk of welding defects and interface failure: By eliminating the solder strip layer between the packaging substrate and the metal heat sink, the possibility of welding voids, solder strip detachment, and interface delamination during secondary brazing is reduced. At the same time, the high thermal conductivity insulating ceramic film layer has a certain degree of flexible buffering effect, which can alleviate the thermal stress caused by the difference in thermal expansion coefficients between the chip solder copper layer and the metal heat sink, thereby improving the structural stability and long-term reliability of the packaging module under thermal shock and power cycling conditions.

[0023] 6. Improved stability of electrical connections and packaging protection: The copper solder layer of the chip sets up the chip mounting area and the power terminal area. The power semiconductor chip is connected to the power terminal area via aluminum bonding wires, and the power terminal area is then connected to the power lead-out terminals, thus forming a complete and compact power output path. The nickel metallization layer or nickel-palladium-gold metallization layer on the surface of the chip solder layer helps to improve the stability of chip connection, aluminum wire bonding, and terminal connection; the plastic encapsulation shell and its internal potting can insulate, fix, and protect the power semiconductor chip and aluminum bonding wires, reducing the impact of moisture, dust, and external forces on internal components. Attached Figure Description

[0024] Figure 1 This is a front view of the AMB package structure mentioned in the background section of this invention. Figure 2 This is a front view of the packaging substrate in this invention. Figure 3 This is a performance test table for the packaging substrate in this invention.

[0025] The markings in the diagram are: 1. Copper layer for chip soldering; 2. High thermal conductivity insulating ceramic film layer; 3. Metal heat sink base; 4. Power semiconductor chip. Detailed Implementation

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation.

[0027] like Figures 2-3 As shown, this embodiment provides a high thermal conductivity integrated power semiconductor packaging module, including a packaging substrate, a power semiconductor chip 4, aluminum bonding wire, a plastic encapsulation shell, and power lead-out terminals.

[0028] The packaging substrate includes, from top to bottom, a chip solder copper layer 1, a high thermal conductivity insulating ceramic film layer 2, and a metal heat sink base plate 3. The chip solder copper layer 1, the high thermal conductivity insulating ceramic film layer 2, and the metal heat sink base plate 3 are directly connected in sequence and formed into an integrated structure through a one-time hot-pressing composite.

[0029] The chip soldering copper layer 1 uses oxygen-free copper foil with a thickness of 0.2–0.4 mm. The chip soldering copper layer 1 includes a chip mounting area and a power terminal area. The chip mounting area is used to mount the power semiconductor chip 4, and the power terminal area is used to form electrical connections with the electrodes and power leads of the power semiconductor chip 4. The oxygen-free copper foil has good electrical and thermal conductivity, enabling it to both support the power semiconductor chip 4 and form electrical connections, and to transfer the heat generated during the operation of the power semiconductor chip 4 to the high thermal conductivity insulating ceramic film layer 2.

[0030] The side of the chip solder copper layer 1 facing away from the high thermal conductivity insulating ceramic film layer 2 is subjected to nickel metallization or nickel-palladium-gold metallization to form a corresponding metallization layer on the surface of the chip solder copper layer 1. The metallization layer can be disposed in the chip mounting area and the power terminal area to improve the stability of the connection of the power semiconductor chip 4, the aluminum wire bonding, and the connection of the power lead terminal.

[0031] A high thermal conductivity insulating ceramic film layer 2 is disposed between the chip solder copper layer 1 and the metal heat sink 3, and its thickness is 60-80 μm. The high thermal conductivity insulating ceramic film layer 2 includes an insulating substrate and thermally conductive ceramic fillers distributed within the insulating substrate. The thermally conductive ceramic fillers include aluminum nitride fillers and alumina fillers, and the insulating substrate is specifically a modified epoxy system.

[0032] Aluminum nitride and alumina fillers are distributed within the insulating substrate, which can improve the thermal conductivity of the high thermal conductivity insulating ceramic film layer 2 while maintaining electrical insulation between the chip solder copper layer 1 and the metal heat sink base 3. Setting the thickness of the high thermal conductivity insulating ceramic film layer 2 to 60–80 μm can shorten the heat transfer distance through the insulating layer, reduce the thermal resistance of the insulating layer, and enable the heat generated by the power semiconductor chip 4 to be transferred to the metal heat sink base 3 more quickly.

[0033] The high thermal conductivity insulating ceramic film layer 2 can also buffer the thermal deformation between the chip solder copper layer 1 and the metal heat sink 3. When the packaged module experiences temperature changes, the high thermal conductivity insulating ceramic film layer 2 can alleviate the thermal stress caused by the difference in thermal expansion coefficients between the chip solder copper layer 1 and the metal heat sink 3, which helps to reduce the warpage of the packaged substrate and reduce the risk of interface delamination and connection failure.

[0034] The metal heat sink base plate 3 is made of oxygen-free copper with a thickness of 2 to 4 mm. The metal heat sink base plate 3 serves two purposes: firstly, to support the chip solder copper layer 1 and the high thermal conductivity insulating ceramic film layer 2; secondly, to receive and dissipate the heat transferred by the power semiconductor chip 4.

[0035] The performance values ​​of the packaging substrate are set as described above. Figure 3 As shown, its equivalent thermal resistance is small, and it can withstand more than 2,000 thermal shocks, which is particularly superior to traditional heat dissipation modules.

[0036] In this embodiment, the metal heat sink base plate 3 is preferably an oxygen-free copper base plate with built-in water-cooling channels. The built-in water-cooling channels are disposed inside the metal heat sink base plate 3 and correspond to the chip mounting area. The term "corresponding" here means that the area where the built-in water-cooling channels are located and the projected area of ​​the chip mounting area in the thickness direction of the packaging substrate at least partially overlap.

[0037] When the packaged module is in operation, the cooling medium flows through the built-in water-cooling channel and exchanges heat with the metal heat sink 3. The heat generated by the power semiconductor chip 4 is transferred sequentially through the chip solder copper layer 1 and the high thermal conductivity insulating ceramic film layer 2 to the metal heat sink 3, and then carried away by the cooling medium flowing through the built-in water-cooling channel, thereby improving the heat dissipation capacity of the packaged module under high power conditions.

[0038] A power semiconductor chip 4 is disposed in the chip mounting area of ​​the chip solder copper layer 1 and connected to the chip solder copper layer 1. The power semiconductor chip 4 may include at least one of IGBT power chips, FRD power chips, and SiC power chips. Depending on the circuit topology, power level, and usage requirements of the package module, one type of power semiconductor chip 4 may be provided, or two or more types of power semiconductor chips 4 may be combined.

[0039] Multiple power semiconductor chips 4 can be configured, and these chips 4 are arranged at intervals in the chip mounting area. The placement of each power semiconductor chip 4 can be adjusted according to the circuit configuration, current carrying capacity, and heat dissipation requirements of the package module.

[0040] The power semiconductor chip 4 is fixed to the chip mounting area of ​​the chip solder copper layer 1 by high-temperature solder. The high-temperature solder is placed between the power semiconductor chip 4 and the chip solder copper layer 1, thereby forming a mechanical connection, an electrical connection and a thermal connection between the power semiconductor chip 4 and the chip solder copper layer 1.

[0041] One end of the aluminum bonding wire is connected to the electrode of the power semiconductor chip 4, and the other end is connected to the power terminal area of ​​the copper bonding layer 1 of the chip, thereby realizing the electrical connection between the power semiconductor chip 4 and the power terminal area. Depending on the current carrying requirements of the power semiconductor chip 4, one or more aluminum bonding wires can be set between the power semiconductor chip 4 and the power terminal area.

[0042] The power lead-out terminals are disposed on the plastic package and connected to the power terminal area of ​​the chip solder copper layer 1. The power semiconductor chip 4 is electrically connected to the external circuit through aluminum bonding wire, the power terminal area and the power lead-out terminals in sequence, thereby realizing the power input and power output of the package module.

[0043] A plastic encapsulation shell is disposed on a packaging substrate, forming an encapsulation space between the plastic encapsulation shell and the packaging substrate to accommodate the power semiconductor chip 4 and the aluminum bonding wires. The plastic encapsulation shell contains potting compound, which fills the encapsulation space and covers the power semiconductor chip 4 and the aluminum bonding wires. The potting compound insulates, fixes, and protects the power semiconductor chip 4 and the aluminum bonding wires, reducing the impact of moisture, dust, and external forces on the power semiconductor chip 4 and its electrical connection structure.

[0044] The minimum thermal resistance of the insulating layer of the encapsulation module in this embodiment is only 0.008℃. With a thermal resistance of cm² / W, it reduces thermal resistance by over 84% compared to traditional DBCs, significantly decreasing the thermal resistance of the chip's heat dissipation path. Under the same operating conditions, the junction temperature is reduced by 10-25℃, allowing the module to handle higher output power and extending chip lifespan. The overall cost of a single standard automotive power module decreases by 15%, saving 15-25 yuan per module in materials, processing, and defect losses. Eliminating the base plate milling and secondary welding processes increases the daily capacity of a single packaging line by over 20%, shortening product delivery cycles. It eliminates solder joint voids and exhibits no delamination or cracking after ≥2000 thermal shock cycles, significantly reducing the risk of power cycle aging failure and making it suitable for demanding, long-life applications such as automotive and energy storage. With an insulation withstand voltage of ≥6kV and a long-term temperature resistance of 150℃, it is compatible with both silicon-based IGBTs and silicon carbide chips, and can be matched with both air-cooled and water-cooled heat dissipation solutions, covering all categories of power modules for passenger cars, commercial vehicles, energy storage, and industrial drives.

[0045] This embodiment also provides a process for a high thermal conductivity integrated power semiconductor packaging module, including the following steps: S1. Integrated substrate molding: 0.2-0.4mm oxygen-free copper foil, 60-80μm high thermal conductivity ceramic insulating film and 2-4mm water-cooled copper base plate are selected and hot-pressed in one step at 170-190℃. The metal heat sink base plate 3 after hot pressing does not need to be pre-curved. The high thermal conductivity insulating ceramic film layer buffers the thermal expansion deformation between different materials, which can reduce the warpage of the integrated packaging substrate, thereby eliminating or reducing the pre-curved milling process of the metal heat sink base plate.

[0046] S2, chip sintering; using high-temperature solder, the chip is directly sintered and fixed to the chip solder copper layer 1. The high-temperature solder is tin-silver-copper high-temperature solder.

[0047] S3. Wire bonding: The electrodes of the power semiconductor chip 4 are connected to the power terminal area of ​​the chip solder copper layer 1 through aluminum wire bonding process to complete the electrical connection.

[0048] S4. Housing assembly, plastic encapsulation and potting, terminal injection molding, and finally, the power module packaging is completed.

[0049] The detailed steps are as follows: First, select oxygen-free copper foil with a thickness of 0.2–0.4 mm, a high thermal conductivity ceramic insulating film with a thickness of 60–80 μm, and a water-cooled copper base plate with a thickness of 2–4 mm. Stack the oxygen-free copper foil, the high thermal conductivity ceramic insulating film, and the water-cooled copper base plate sequentially from top to bottom, with the high thermal conductivity ceramic insulating film positioned between the oxygen-free copper foil and the water-cooled copper base plate.

[0050] The stacked oxygen-free copper foil, high thermal conductivity ceramic insulating film, and water-cooled copper base plate are placed in a hot press and subjected to one-time hot pressing composite at 170–190 °C to form a stable integrated encapsulation substrate.

[0051] After the packaging substrate is formed, the chip solder copper layer 1 is processed to form a chip mounting area and a power terminal area that are adapted to the circuit structure of the packaging module. The surface of the chip solder copper layer 1 is subjected to nickel metallization or nickel-palladium-gold metallization treatment to improve the reliability of subsequent chip fixing, aluminum wire bonding and power terminal connection.

[0052] Subsequently, high-temperature solder is applied to the chip mounting area, and the power semiconductor chip 4 is placed in the corresponding chip mounting area. Through the chip fixing process, the power semiconductor chip 4 is fixed and electrically connected to the chip solder copper layer 1, while a thermally conductive connection is formed between the power semiconductor chip 4 and the chip solder copper layer 1.

[0053] After the power semiconductor chip 4 is fixed, an aluminum wire bonding process is used to connect one end of the aluminum bonding wire to the electrode of the power semiconductor chip 4 and the other end to the power terminal area of ​​the chip solder copper layer 1, thereby completing the electrical connection between the power semiconductor chip 4 and the power terminal area.

[0054] After aluminum wire bonding is completed, the plastic package is mounted on the packaging substrate, and the power lead terminals are placed on the plastic package, connecting the power lead terminals to the power terminal area of ​​the chip solder copper layer 1. Then, potting compound is poured into the packaging space formed by the plastic package and the packaging substrate, covering the power semiconductor chip 4 and the aluminum bonding wires. Finally, the plastic packaging and terminal injection molding are completed to obtain a high thermal conductivity integrated power semiconductor package module.

[0055] In use, the power semiconductor chip 4 is connected to an external circuit via power output terminals. The heat generated by the power semiconductor chip 4 during operation is transferred to the chip solder copper layer 1 via high-temperature solder, and then to the metal heat sink base 3 via the high thermal conductivity insulating ceramic film layer 2. The aluminum nitride and alumina fillers in the high thermal conductivity insulating ceramic film layer 2 promote heat transfer while maintaining electrical insulation. After receiving the heat, the metal heat sink base 3 exchanges heat with the cooling medium through its internal water-cooling channels, carrying the heat out of the packaging module.

[0056] Since the chip solder copper layer 1, the high thermal conductivity insulating ceramic film layer 2, and the metal heat sink base 3 are integrated into a single structure through a one-time hot-pressing process, and no solder ribbon is provided between the high thermal conductivity insulating ceramic film layer 2 and the metal heat sink base 3, the thermal interface in the traditional packaging structure can be reduced, the heat dissipation path between the power semiconductor chip 4 and the metal heat sink base 3 can be shortened, and the risks of solder voids, solder ribbon detachment, and interface delamination during the solder ribbon brazing process can be reduced. This preparation method can also eliminate the secondary solder ribbon brazing process between the packaging substrate and the metal heat sink base 3, simplifying the production process of the packaging module and reducing material and processing costs.

[0057] The foregoing has shown and described the basic principles and main features of this invention, as well as its advantages. Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of this invention as claimed.

Claims

1. A high thermal conductivity integrated power semiconductor package module, characterized in that: Includes packaging substrate, power semiconductor chip, aluminum bonding wire, plastic encapsulation shell and power lead-out terminals; The packaging substrate includes a chip solder copper layer, a high thermal conductivity insulating ceramic film layer, and a metal heat dissipation base plate. The chip solder copper layer, the high thermal conductivity insulating ceramic film layer, and the metal heat dissipation base plate are directly connected from top to bottom. The thickness of the high thermal conductivity insulating ceramic film layer is 60-80 μm. The chip solder copper layer includes a chip mounting area and a power terminal area; the high thermal conductivity insulating ceramic film layer includes an insulating substrate and thermally conductive ceramic fillers distributed within the insulating substrate. The power semiconductor chip is disposed in the chip mounting area of ​​the chip solder copper layer and is connected to the chip solder copper layer. The aluminum bonding wire connects the electrodes of the power semiconductor chip to the power terminal area of ​​the chip's copper solder layer. The power lead-out terminal is disposed on the plastic-encapsulated housing and connected to the power terminal area; The plastic encapsulation shell is disposed on the packaging substrate, and a packaging space for accommodating the power semiconductor chip and aluminum bonding wire is formed between the plastic encapsulation shell and the packaging substrate. The metal heat sink base plate is used for heat dissipation of the encapsulated module.

2. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The thermally conductive ceramic filler includes aluminum nitride filler and alumina filler.

3. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The copper solder layer of the chip is an oxygen-free copper foil with a thickness of 0.2 to 0.4 mm.

4. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The thickness of the metal heat dissipation base plate is 2-4mm, and the metal heat dissipation base plate is an oxygen-free copper base plate with built-in water cooling channels.

5. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The power semiconductor chip includes at least one of IGBT power chips, FRD power chips, and SiC power chips.

6. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The encapsulated shell contains potting compound, which covers the power semiconductor chip and aluminum bonding wire.

7. The high thermal conductivity integrated power semiconductor packaging module according to claim 1, characterized in that: The surface of the copper layer of the chip is treated with nickel metallization or nickel-palladium-gold metallization.

8. A process for a high thermal conductivity integrated power semiconductor packaging module, characterized in that: Manufacturing a high thermal conductivity integrated power semiconductor package module as described in any one of claims 1 to 7 includes the following steps: S1. Integrated substrate molding: Select 0.2-0.4mm oxygen-free copper foil, 60-80μm high thermal conductivity ceramic insulating film and 2-4mm water-cooled copper base plate, and hot press composite molding in an environment of 170-190℃; S2, chip sintering; S3, wire bonding; S4. Housing assembly, plastic encapsulation and potting, terminal injection molding, and finally, the power module packaging is completed.

9. The process for a high thermal conductivity integrated power semiconductor packaging module according to claim 8, characterized in that: The specific steps of step S2 are as follows: using high-temperature solder, the chip is directly sintered and fixed to the chip solder copper layer.

10. The process for a high thermal conductivity integrated power semiconductor packaging module according to claim 8, characterized in that: The specific steps of step S3 are as follows: the electrodes of the power semiconductor chip are connected to the power terminal area of ​​the chip's copper solder layer through an aluminum wire bonding process to complete the electrical connection.

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