Chip package substrate, method for manufacturing the same, and chip package structure
Patent Information
- Application Number
- CN202610966810.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-30
- Publication Date
- 2026-10-27
AI Technical Summary
但在产业化落地进程中，玻璃通孔的金属化填孔环节始终是行业公认的技术瓶颈，特别是高纵横比玻璃通孔设计，玻璃通孔填孔难度大，良率低
[0029]本申请实施例所提供的芯片封装载板、其制备方法及芯片封装结构，通过玻璃转接板具有第一表面和与第一表面相对的第二表面，玻璃转接板于第一表面开设有多个第一开孔，玻璃转接板于第二表面开设有多个第二开孔。第一开孔在第一表面的正投影为第一投影，第二开孔在第一表面的正投影为第二投影，第一投影至少部分位于第二投影外，第二投影至少部分位于第一投影外，所第一开孔的深度与第二开孔的深度均小于玻璃转接板的厚度，第一开孔的底部与第二开孔的底部连通，由此可将玻璃转接板上尺寸纵横比大的没有底壁的通孔结构改变为两个“尺寸纵横比较小且具有部分底壁的部分盲孔”结构，如此，在填孔过程中可以提升效率，而且可以有效避免出现填充空洞等问题，从而可较好实现通孔内部的致密填充，提升整体生产良率，能够适应向高密度封装对TGV技术的需求。
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Figure CN122995693A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging substrate, its preparation method and chip packaging structure. Background Technology
[0002] Glass-based chip packaging substrates are becoming increasingly popular as a strong contender for next-generation packaging substrates. However, in the process of industrialization, the metallization and filling of glass through-holes has always been a recognized technical bottleneck in the industry, especially for high aspect ratio glass through-hole designs, where filling is difficult and yield is low. Summary of the Invention
[0003] This application provides a chip packaging substrate, its preparation method, and chip packaging structure, aiming to improve the via filling quality of high aspect ratio through holes to improve product manufacturing yield.
[0004] In a first aspect, some embodiments of this application provide a chip packaging carrier board, which includes a glass adapter board, a first conductive post, a second conductive post, a first circuit structure, and a second circuit structure.
[0005] The glass adapter plate has a first surface and a second surface opposite to the first surface. The glass adapter plate has a plurality of first openings on the first surface and a plurality of second openings on the second surface.
[0006] The first conductive post is located inside the first opening, and the second conductive post is located inside the second opening.
[0007] The first circuit structure is located on one side of the corresponding first surface of the glass adapter plate, and the second circuit structure is located on one side of the corresponding second surface of the glass adapter plate.
[0008] Wherein, the orthographic projection of the first opening on the first surface is the first projection, the orthographic projection of the second opening on the first surface is the second projection, the first projection is at least partially located outside the second projection, the second projection is at least partially located outside the first projection, the depth of the first opening and the depth of the second opening are both less than the thickness of the glass transition plate, the bottom of the first opening and the bottom of the second opening are connected, the end of the first conductive post near the second surface is electrically connected to the end of the second conductive post near the first surface, the first conductive post is electrically connected to the first circuit structure, and the second conductive post is electrically connected to the corresponding second circuit structure.
[0009] In some embodiments, the sum of the depth of the second opening and the depth of the first opening is greater than the thickness of the glass transition plate, and the difference between the sum of the depth of the second opening and the depth of the first opening and the thickness of the glass transition plate is 15%-120% of the lateral dimension of the first opening or the second opening.
[0010] Preferably, the difference between the sum of the depths of the second opening and the first opening and the thickness of the glass transition plate is 50%-80% of the lateral dimension of the first or second opening.
[0011] Preferably, the difference between the sum of the depths of the second opening and the first opening and the thickness of the glass adapter plate is 2-10 micrometers.
[0012] In some embodiments, a portion of the second projection is located within the first projection, and the overlapping portion of the first and second projections has a size of 2-10 micrometers along the line connecting the centroid of the first projection and the centroid of the second projection.
[0013] In some embodiments, the bottom of the first opening does not overlap with the bottom of the second opening, and a connecting hole is provided on the glass adapter plate. The bottom of the first opening is connected to the bottom of the second opening through the connecting hole. A connecting part is provided in the connecting hole, and the end of the first conductive post near the second surface is electrically connected to the end of the second conductive post near the first surface through the connecting part.
[0014] Preferably, the bottom of the first opening is projected onto the first surface as a third projection, and the bottom of the second opening is projected onto the first surface as a fourth projection. The third projection is located within the first projection, and the fourth projection is located within the second projection. The first projection and the second projection partially overlap, while the third projection and the fourth projection do not overlap.
[0015] Preferably, the area of the cross section of the connecting part perpendicular to the line connecting the centroid of the third projection and the centroid of the fourth projection is greater than or equal to 35% of the area of the fourth projection and less than or equal to the area of the fourth projection.
[0016] Preferably, the minimum dimension of the connecting part in the direction of the line connecting the centroid of the third projection and the centroid of the fourth projection is 0-2 micrometers.
[0017] In some embodiments, the area of the second projection is smaller than the area of the first projection, and the depth of the second opening is smaller than the depth of the first opening.
[0018] Preferably, the ratio of the area of the overlapping portion of the first projection and the second projection to the area of the second projection is in the range of 35%-100%.
[0019] Secondly, some embodiments of this application provide a method for preparing a chip packaging substrate, the method comprising:
[0020] Multiple first openings are formed on the first surface of the glass transition plate, and multiple second openings are formed on the second surface of the glass transition plate. The depth of both the first and second openings is less than the thickness of the glass transition plate. The bottom of the first opening is connected to the bottom of the second opening. The orthographic projection of the first opening on the first surface is the first projection, and the orthographic projection of the second opening on the first surface is the second projection. The first projection is at least partially located outside the second projection, and the second projection is at least partially located outside the first projection. A first conductive post is formed within the first opening, and a second conductive post is formed within the second opening; A first circuit structure is formed on one side of the glass adapter plate; and A second circuit structure is formed on the side of the glass adapter plate that is away from the first circuit structure.
[0021] In some embodiments, a portion of the structure between the bottom of the first opening and the bottom of the second opening of the glass adapter plate is irradiated with a laser focal point to modify the material of the irradiated portion of the structure. After the first opening and / or the second opening is formed, the modified portion of the material is removed with an etching solution to obtain a connecting hole.
[0022] Preferably, the glass adapter plate has multiple first openings on its first surface and multiple second openings on its second surface, which includes: irradiating the portion of the glass adapter plate corresponding to the first opening and the portion of the glass adapter plate corresponding to the second opening with a pulsed laser focal point, thereby modifying the material of the irradiated portion; simultaneously irradiating the portion of the glass adapter plate corresponding to the connecting hole between the bottom of the first opening and the bottom of the second opening with a pulsed laser focal point; and simultaneously removing the modified material with an etching solution to obtain the first and second openings, thereby obtaining the connecting hole.
[0023] In some embodiments, electroplating forms a first conductive post located within a first opening and a second conductive post located within a second opening, including: Electroplating is performed using pulsed current to form a partition structure at the connecting part between the first opening and the second opening, which can separate the first opening and the second opening into two blind holes. Two blind holes are filled by electroplating with direct current to obtain the first conductive post and the second conductive post.
[0024] Preferably, the partition structure that separates the first opening and the second opening into two blind holes includes a connecting portion filled within the connecting hole.
[0025] In some embodiments, electroplating forms a first conductive post located within a first opening and a second conductive post located within a second opening, including: Sacrificial material is filled into the first opening to form a blind opening, and electroplating is used to form at least a portion of the structure of the second conductive pillar that closes the bottom of the second opening; Remove the sacrificial material inside the first opening and electroplate to form the first conductive pillar.
[0026] Preferably, the area of the second projection is smaller than the area of the first projection, and the depth of the second opening is smaller than the depth of the first opening.
[0027] Thirdly, some embodiments of this application provide a chip packaging structure, which includes a chip packaging carrier and a chip. The chip packaging carrier is the chip packaging carrier described above, or a chip packaging carrier prepared according to the method described above.
[0028] Preferably, the chip packaging substrate includes a first opening and a second opening, the area of the second opening projected onto the first surface is smaller than the area of the first opening projected onto the first surface, and the chip is disposed on the side of the chip packaging substrate corresponding to the second opening.
[0029] The chip packaging substrate, its fabrication method, and chip packaging structure provided in this application embodiment utilize a glass adapter plate having a first surface and a second surface opposite to the first surface. The glass adapter plate has multiple first openings on the first surface and multiple second openings on the second surface. The orthographic projection of the first opening on the first surface is a first projection, and the orthographic projection of the second opening on the first surface is a second projection. At least a portion of the first projection is located outside the second projection, and at least a portion of the second projection is located outside the first projection. Therefore, the depths of both the first and second openings are less than the thickness of the glass adapter plate. The bottoms of the first and second openings are connected. This transforms the large-aspect-ratio through-hole structure without a bottom wall on the glass adapter plate into two "partially blind holes with a small aspect ratio and partial bottom walls." This improves efficiency during the hole-filling process and effectively avoids problems such as filling voids, thereby achieving better dense filling inside the through holes, improving overall production yield, and meeting the demands of high-density packaging for TGV technology. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 A side cross-sectional schematic diagram of a chip packaging carrier provided for some embodiments of this application; Figure 2A top view schematic diagram of a partial structure in a chip packaging carrier provided for some embodiments of this application; Figure 3 A side cross-sectional schematic diagram of another chip packaging carrier provided for some embodiments of this application; Figure 4 A top view schematic diagram of a partial structure in another chip packaging carrier provided in some embodiments of this application; Figure 5 A side cross-sectional schematic diagram of another chip packaging carrier provided in some embodiments of this application; Figure 6 A side cross-sectional schematic diagram of another chip packaging carrier provided for some embodiments of this application; Figure 7 A top view schematic diagram of a partial structure in another chip packaging carrier provided in some embodiments of this application; Figure 8 and Figure 9 These are schematic side cross-sectional views of a chip packaging carrier provided in some embodiments of this application; Figure 10 A side cross-sectional schematic diagram of a chip packaging carrier provided for some embodiments of this application; Figures 11-13 This application provides side cross-sectional schematic diagrams of a chip packaging carrier in several states during the fabrication process, as shown in some embodiments of the present application. Figures 14-18 A side cross-sectional view of another chip packaging substrate provided in some embodiments of this application during several states of the fabrication process; Figures 19-21 These are side cross-sectional schematic diagrams of a chip packaging structure provided in some embodiments of this application.
[0032] Explanation of reference numerals in the attached figures: Glass adapter plate 20, first surface 21, second surface 22, first opening 23, first projection 231, third projection 232, second opening 25, second projection 251, fourth projection 252, connecting hole 26, first conductive post 30, second conductive post 32, connecting part 33, first wiring layer 50, first circuit structure layer 51, first circuit structure 52, first dielectric layer 53, second wiring layer 60, second circuit structure layer 61, second circuit structure 62, second dielectric layer 63, sacrificial material 81, chip 91, encapsulation layer 92, separator structure 96 Detailed Implementation To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0033] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0035] The following is in conjunction with the attached Figures 1-21 The technical solution of this application will be described in detail.
[0036] In the field of chip packaging substrate fabrication technology, through-holes in glass adapters are prone to problems such as voids during the filling process, especially for high aspect ratio through-holes that meet the needs of high-density packaging. The process yield is low and it is difficult to support the requirements of large-scale mass production.
[0037] To address the aforementioned problems, firstly, some embodiments of this application provide a chip packaging substrate, please refer to... Figures 1-21 The chip packaging substrate includes a glass adapter plate 20, a first conductive post 30, a second conductive post 32, a first circuit structure 52, and a second circuit structure 62.
[0038] The glass adapter plate 20 has a first surface 21 and a second surface 22 opposite to the first surface 21. The glass adapter plate 20 has a plurality of first openings 23 on the first surface 21 and a plurality of second openings 25 on the second surface 22.
[0039] The first conductive post 30 is located inside the first opening 23, and the second conductive post 32 is located inside the second opening 25.
[0040] The first circuit structure 52 is located on one side of the glass transition plate 20 corresponding to the first surface 21, and the second circuit structure 62 is located on one side of the glass transition plate 20 corresponding to the second surface 22.
[0041] Wherein, the orthographic projection of the first opening 23 onto the first surface 21 is the first projection 231, and the orthographic projection of the second opening 25 onto the first surface 21 is the second projection 251. The first projection 231 is at least partially located outside the second projection 251, and the second projection 251 is at least partially located outside the first projection 231. Therefore, the depth of the first opening 23 and the depth of the second opening 25 are both less than the thickness of the glass transition plate 20. The bottom of the first opening 23 is connected to the bottom of the second opening 25. The end of the first conductive post 30 near the second surface 22 is electrically connected to the end of the second conductive post 32 near the first surface 21. The first conductive post 30 is electrically connected to the first circuit structure 52, and the second conductive post 32 is electrically connected to the corresponding second circuit structure 62.
[0042] The chip packaging substrate provided in this application embodiment has a first surface 21 and a second surface 22 opposite to the first surface 21 via a glass adapter plate 20. The glass adapter plate 20 has a plurality of first openings 23 on the first surface 21 and a plurality of second openings 25 on the second surface 22. The first opening 23 is projected onto the first surface 21 as first projection 231, and the second opening 25 is projected onto the first surface 21 as second projection 251. The first projection 231 is at least partially located outside the second projection 251, and the second projection 251 is at least partially located outside the first projection 231. Therefore, the depth of both the first opening 23 and the second opening 25 is less than the thickness of the glass adapter plate 20. The bottom of the first opening 23 is connected to the bottom of the second opening 25. This allows the through-hole structure on the glass adapter plate 20, which has a large aspect ratio and no bottom wall, to be changed into two "partial blind holes with a small aspect ratio and partial bottom walls". This improves efficiency during the hole filling process and effectively avoids problems such as filling voids and surface depressions. It can achieve better dense filling inside the through holes, improve the overall manufacturing yield, and meet the needs of high-density packaging for TGV (Through Glass Via) technology.
[0043] It should be noted that a first wiring layer 50 may be formed on one side of the glass transition plate 20 corresponding to the first surface 21. The first wiring layer 50 includes at least one first circuit structure layer 51 and at least one first dielectric layer 53 disposed on the glass transition plate 20. The first circuit structure layer 51 includes a plurality of first circuit structures 52. A second wiring layer 60 may be formed on one side of the glass transition plate 20 corresponding to the second surface 22. The second wiring layer 60 includes at least one second circuit structure layer 61 and at least one second dielectric layer 63 disposed on the glass transition plate 20. The second circuit structure layer 61 includes a plurality of second circuit structures 62 (please refer to...). Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 8 and Figure 9 ).
[0044] In some embodiments of this application, the chip packaging carrier board is provided. Please refer to... Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 8 , Figure 9 and Figures 11-18 The sum of the depth H2 of the second opening 25 and the depth H1 of the first opening 23 is greater than the thickness H of the glass transition plate 20. The difference between the sum of the depth H2 of the second opening 25 and the depth H1 of the first opening 23 and the thickness H of the glass transition plate 20 is 15%-120% (specifically, it can be 15%, 25%, 35%, 50%, 60%, 70%, 80%, 100% and 120%) of the lateral dimension of the first opening 23 or the second opening 25.
[0045] In some embodiments of this application, the difference between the sum of the depths of the second opening 25 and the first opening 23 and the thickness of the glass transition plate 20 is 50%-80% of the lateral dimension of the first opening 23 or the second opening 25.
[0046] In some embodiments of this application, the chip packaging substrate provides a difference between the sum of the depths of the second opening 25 and the first opening 23 and the thickness of the glass transition plate 20, which is 2-10 micrometers (specifically, it can be 2 micrometers, 3 micrometers, 5 micrometers, 7 micrometers, and 10 micrometers). By controlling the difference between the sum of the depths of the second opening 25 and the first opening 23 and the thickness of the glass transition plate 20, or by controlling the relationship between this difference and the lateral dimension of the first opening 23 or the second opening 25, the chip packaging substrate provided in this application can ensure a sufficiently large contact area between the end of the first conductive post 30 near the second surface 22 and the end of the second conductive post 32 near the first surface 21. This effectively reduces contact resistance while improving product yield.
[0047] The depths of the first opening 23 and the second opening 25 and the thickness of the glass adapter plate 20 are the corresponding longitudinal dimensions. The measurement direction of the transverse dimension is perpendicular to the longitudinal dimension, and the aperture dimension is the transverse dimension.
[0048] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 In some embodiments of this application, the chip packaging substrate provides a portion of the second projection 251 located within the first projection 231. The dimension D1 of the overlapping portion of the first projection 231 and the second projection 251 along the line connecting the centroid of the first projection 231 and the centroid of the second projection 251 is 2-10 micrometers (specifically, it can be 2 micrometers, 3 micrometers, 5 micrometers, 7 micrometers, and 10 micrometers). The chip packaging substrate provided in the application embodiments, by placing a portion of the second projection 251 within the first projection 231 and controlling the dimension of the overlapping portion of the first projection 231 and the second projection 251 within an appropriate range along the line connecting the centroid of the first projection 231 and the centroid of the second projection 251, can ensure a sufficiently large contact area between the end of the first conductive post 30 near the second surface 22 and the end of the second conductive post 32 near the first surface 21, thereby effectively reducing contact resistance while improving product yield.
[0049] Please refer to Figure 6 , Figure 8 and Figure 9 In some embodiments of this application, the bottom of the first opening 23 and the bottom of the second opening 25 do not overlap. A connecting hole 26 is provided on the glass adapter plate 20. The bottom of the first opening 23 is connected to the bottom of the second opening 25 through the connecting hole 26. A connecting part 33 is provided in the connecting hole 26. The end of the first conductive post 30 near the second surface 22 and the end of the second conductive post 32 near the first surface 21 are electrically connected through the connecting part 33.
[0050] The chip packaging substrate provided in this embodiment of the application has a glass adapter plate 20 with a connecting hole 26 provided on it, where the bottom of the first opening 23 and the bottom of the second opening 25 do not overlap. The bottom of the first opening 23 is connected to the bottom of the second opening 25 through the connecting hole 26. A connecting part 33 is provided in the connecting hole 26. This allows the through-hole structure on the glass adapter plate 20 to be adjusted into two "blind holes with larger bottom walls" connected by the connecting hole 26. This can further improve efficiency during the hole filling process and effectively avoid problems such as filling voids and surface depressions. It can achieve dense filling inside the through holes, improve the overall production yield, and meet the requirements of TGV technology for high-density packaging.
[0051] Please refer to Figure 9 and Figure 10In some embodiments of this application, the bottom of the first opening 23 is projected onto the first surface 21 as a third projection 232, and the bottom of the second opening 25 is projected onto the first surface 21 as a fourth projection 252. The third projection 232 is located within the first projection 231, and the fourth projection 252 is located within the second projection 251. The first projection 231 and the second projection 251 partially overlap, while the third projection 232 and the fourth projection 252 do not overlap.
[0052] In some embodiments of this application, the chip packaging substrate is provided with the following configuration: the bottom of the first opening 23 is projected onto the first surface 21 as a third projection 232, and the bottom of the second opening 25 is projected onto the first surface 21 as a fourth projection 252. The third projection 232 is located within the first projection 231, and the fourth projection 252 is located within the second projection 251. This means that the bottoms of the first opening 23 and the second opening 25 are smaller. By controlling the first projection 231 and the second projection 251 to partially overlap, and the third projection 232 and the fourth projection 252 not to overlap, and the bottom of the first opening 23 is connected to the bottom of the second opening 25 through the connecting hole 26, the glass adapter plate 20 can have two "blind holes with larger bottom walls" structures, which can effectively avoid problems such as filling voids and surface depressions, and better achieve dense filling inside the through holes. On the other hand, the distance between the bottom of the first opening 23 and the bottom of the second opening 25 via the connecting hole 26 is small, which allows the first opening 23 and the second opening 25 to occupy a small area on the glass adapter plate 20, thereby improving the integration of related structures and meeting the development trend of chip packaging products. In the chip packaging carrier provided in some embodiments of this application, the area of the cross section of the connecting portion 33 perpendicular to the line connecting the centroid of the third projection 232 and the centroid of the fourth projection 252 is greater than or equal to 35% and less than or equal to the area of the fourth projection 252.
[0053] In some embodiments of this application, the minimum dimension of the connecting portion 33 in the direction of the line connecting the centroid of the third projection 232 and the centroid of the fourth projection 252 is 0-2 micrometers.
[0054] The chip packaging substrate provided in this application embodiment controls the ratio of the area of the cross section of the connecting part 33 perpendicular to the centroid of the third projection 232 and the centroid of the fourth projection 252 to the area of the fourth projection 252, and / or the minimum size of the connecting part 33 in the direction of the line connecting the centroid of the third projection 232 and the centroid of the fourth projection 252. This ensures that the connecting part 33 has a sufficiently large conductive area, thereby effectively reducing contact resistance and improving product yield.
[0055] When the minimum dimension of the connecting portion 33 in the direction connecting the centroid of the third projection 232 and the centroid of the fourth projection 252 is 0 micrometers, the first opening 23 and the second opening 25 can be in point contact or line contact, and the contact point or contact line is located in the middle of the connecting portion 33. The conductive post may include a seed layer, which may be formed by chemical plating.
[0056] Please refer to Figure 3 , Figure 5 , Figures 14-18 In some embodiments of this application, the area of the second projection 251 is smaller than the area of the first projection 231, and the depth of the second opening 25 is smaller than the depth of the first opening 23.
[0057] The chip packaging substrate provided in this application embodiment has a second projection 251 area smaller than the first projection 231 area, and a second opening 25 depth smaller than the first opening 23 depth. That is, a second opening 25 with a small lateral size and shallow depth is provided on one surface of the glass adapter plate 20, and a first opening 23 with a relatively large lateral size and deep depth is provided on the other surface. In this way, on the one hand, the corresponding side of one surface (second surface 22) of the glass adapter plate 20 is suitable for setting high-density circuits and bonding chips, and the corresponding side of the other surface (first surface 21) is suitable for setting low-density circuits and bonding circuit boards, etc.
[0058] In some embodiments of this application, the ratio of the area of the overlapping portion of the first projection 231 and the second projection 251 to the area of the second projection 251 ranges from 35% to 100%.
[0059] The chip packaging substrate provided in this application embodiment can effectively reduce contact resistance and improve product yield by controlling the ratio of the area of the overlapping part of the first projection 231 and the second projection 251 to the area of the second projection 251, thereby ensuring that the contact part structure has a sufficiently large conductive area.
[0060] Secondly, some embodiments of this application provide a method for preparing a chip packaging substrate, please refer to... Figures 11-13 , Figures 14-18 The methods for preparing chip packaging substrates include: A plurality of first openings 23 are formed on the first surface 21 of the glass transition plate 20, and a plurality of second openings 25 are formed on the second surface 22 of the glass transition plate 20. The depth of the first opening 23 and the depth of the second opening 25 are both less than the thickness of the glass transition plate 20. The bottom of the first opening 23 is connected to the bottom of the second opening 25. The orthographic projection of the first opening 23 on the first surface 21 is the first projection 231, and the orthographic projection of the second opening 25 on the first surface 21 is the second projection 251. The first projection 231 is at least partially located outside the second projection 251, and the second projection 251 is at least partially located outside the first projection 231. A first conductive post 30 is formed within the first opening 23 and a second conductive post 32 is formed within the second opening 25; A first circuit structure 52 is formed on one side of the glass adapter plate 20; and A second circuit structure 62 is formed on the side of the glass adapter plate 20 away from the first circuit structure 52.
[0061] The chip packaging substrate fabrication method provided in this application embodiment involves forming multiple first openings 23 on the first surface 21 of a glass adapter plate 20, and forming multiple second openings 25 on the second surface 22 of the glass adapter plate 20. The depths of both the first openings 23 and the second openings 25 are less than the thickness of the glass adapter plate 20. The bottoms of the first openings 23 and the second openings 25 are connected. The orthographic projection of the first opening 23 on the first surface 21 is a first projection 231, and the orthographic projection of the second openings 25 on the first surface 21 is a second projection 251. The first projection 231 is at least partially... Located outside the second projection 251, which is at least partially located outside the first projection 231, the through-hole structure on the glass adapter plate 20 can be adjusted into two "partially blind holes with partial bottom walls" structures. This improves efficiency during the electroplating process of forming the first conductive post 30 located in the first opening 23 and the second conductive post 32 located in the second opening 25, and effectively avoids problems such as filling voids and surface depressions. This allows for better dense filling of the through-holes, improves overall production yield, and meets the requirements of TGV technology for high-density packaging.
[0062] The first conductive post 30 located in the first opening 23 and the second conductive post 32 located in the second opening 25 can be formed by electroplating. Before electroplating the first conductive post 30 and the second conductive post 32, a seed layer can be formed on the hole wall of the first opening 23 and the hole wall of the second opening 25 by chemical plating.
[0063] In some embodiments of this application, the method for preparing a chip packaging substrate includes using a laser focal point to irradiate a portion of the structure between the bottom of the first opening 23 and the bottom of the second opening 25 of the glass adapter plate 20, thereby modifying the material of the irradiated portion of the structure. After forming the first opening 23 and / or the second opening 25, an etching solution is used to remove the modified portion of the material to obtain a connecting hole 26.
[0064] The chip packaging substrate preparation method provided in this application solves the problem of the difficulty in opening a transversely extending connecting hole 26 inside the glass adapter plate 20 by using a laser focal point to irradiate a portion of the structure between the bottom of the first opening 23 and the bottom of the second opening 25 of the glass adapter plate 20, thereby modifying the material of the irradiated portion of the structure, and using an etching solution to remove the modified material.
[0065] In the chip packaging substrate fabrication method provided in some embodiments of this application, a plurality of first openings 23 are formed on the first surface 21 of the glass adapter 20, and a plurality of second openings 25 are formed on the second surface 22 of the glass adapter 20. This includes: irradiating a portion of the glass adapter 20 corresponding to the first openings 23 and a portion of the glass adapter 20 corresponding to the second openings 25 with a pulsed laser focus point, thereby modifying the material of the irradiated portions; simultaneously irradiating a portion of the glass adapter 20 corresponding to the connecting hole 26 between the bottom of the first opening 23 and the bottom of the second opening 25 with a pulsed laser focus point; and removing the modified material with an etching solution to obtain the first openings 23 and the second openings 25, and simultaneously removing the modified material with an etching solution to obtain the connecting hole 26.
[0066] The chip packaging substrate fabrication method provided in this application embodiment modifies the structural material of the corresponding connecting hole 26 in the same stage by using a pulsed laser to irradiate the partial structure corresponding to the first opening 23 and the partial structure corresponding to the second opening 25 of the glass adapter plate 20. Removing the modified material of the corresponding connecting hole 26 in the same stage using an etching solution simplifies the process flow of the connecting hole 26 and reduces manufacturing costs.
[0067] The laser used is preferably a pulsed laser; using a pulsed laser can avoid heat concentration, thus preventing microcracks from forming on the glass adapter plate 20, thereby improving product yield.
[0068] Please refer to Figures 11-13 In some embodiments of this application, the method for preparing a chip packaging substrate includes electroplating to form a first conductive post 30 located within a first opening 23 and a second conductive post 32 located within a second opening 25, comprising: Electroplating is performed using pulsed current to form a partition structure 96 at the connecting portion between the first opening 23 and the second opening 25, which can separate the first opening 23 and the second opening 25 into two blind holes.
[0069] Two blind holes are filled by electroplating with direct current to obtain the first conductive post 30 and the second conductive post 32.
[0070] The chip packaging substrate fabrication method provided in this application divides the electroplating process for forming the first conductive pillar 30 and the second conductive pillar 32 into two stages. In the first stage, pulsed current electroplating is used to form a partition structure 96 at the connection between the first opening 23 and the second opening 25, which can separate the first opening 23 and the second opening 25 into two blind holes. After forming the blind hole structure, direct current electroplating is used to fill the two blind holes, resulting in the first conductive pillar 30 and the second conductive pillar 32. The pulsed current electroplating in the first stage can prevent the openings of the first opening 23 and the second opening 25 from forming seals, thereby avoiding defects such as holes in the first conductive pillar 30 and the second conductive pillar 32. In the second stage, direct current electroplating can improve electroplating efficiency while ensuring quality.
[0071] It should be noted that the current density of the pulse current can be 0.5-1.5 ASD, the current density of the reverse pulse can be 2.5-6 ASD, the pulse frequency is 50-1000 Hz, the forward time within one pulse is 0.1-0.16 seconds, and the reverse time is 0.02-0.04 seconds.
[0072] In the chip packaging substrate preparation method provided in some embodiments of this application, the partition structure 96 that separates the first opening 23 and the second opening 25 into two blind holes includes a connecting portion 33 filled in the connecting hole 26.
[0073] Please refer to Figures 14-18 In some embodiments of this application, the method for preparing a chip packaging substrate includes electroplating to form a first conductive post 30 located within a first opening 23 and a second conductive post 32 located within a second opening 25, comprising: Sacrificial material 81 is filled into the first opening 23 to form the second opening 25 as a blind hole, and electroplating is used to form at least a portion of the structure of the second conductive post 32 that closes the bottom of the second opening 25.
[0074] Remove the sacrificial material 81 inside the first opening 23, and electroplate to form the first conductive pillar 30.
[0075] In some embodiments of this application, the area of the second projection 251 is smaller than the area of the first projection 231, and the depth of the second opening 25 is smaller than the depth of the first opening 23.
[0076] The chip packaging substrate preparation method provided in this application uses sacrificial material 81 to temporarily fill the first opening 23, making the second opening 25 a blind hole. This facilitates high-quality and rapid first blind hole electroplating using a blind hole electroplating method (direct current). After removing the sacrificial material 81, the first opening 23 can be electroplated again using a blind hole electroplating method (direct current) with high quality and rapid speed. This can improve manufacturing efficiency and reduce product manufacturing costs.
[0077] The sacrificial material 81 can be liquid photoresist, ink, or other materials. The sacrificial material 81 can be filled by screen printing. The sacrificial material 81 in the first opening 23 can be removed by etching solution or alkaline film removal solution.
[0078] Thirdly, some embodiments of this application provide a chip packaging structure, please refer to... Figures 19-21 The chip packaging structure includes a chip packaging carrier and a chip 91. The chip packaging carrier is the chip packaging carrier 20 described above, or a chip packaging carrier 20 prepared according to the method described above.
[0079] In some embodiments of this application, the chip packaging structure includes a first opening 23 and a second opening 25. The area of the second opening 25 projected onto the first surface 21 is smaller than the area of the first opening 23 projected onto the first surface 21. The chip 91 is disposed on the side of the chip packaging carrier corresponding to the second opening 25.
[0080] The chip packaging structure provided in this application embodiment has a smaller area of the second opening 25 on the first surface 21 than the area of the first opening 23 on the first surface 21. The chip 91 is disposed on the side of the chip packaging carrier corresponding to the second opening 25. That is, one surface of the glass adapter plate 20 is provided with a second opening 25 with a small lateral size and shallow depth, and the other surface is provided with a first opening 23 with a large lateral size and deep depth. This makes the side of the surface with a large lateral size and deep depth suitable for large-size circuit boards (PCB and FPC), while the corresponding side of the other surface (second surface 22) of the glass adapter plate 20 is suitable for attaching the chip 91, thereby easily achieving a high degree of integration.
[0081] It should be noted that the different technical features in the aforementioned different embodiments can all be used as features in the same embodiment scheme if there is no conflict.
[0082] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0084] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A chip packaging carrier board, characterized in that, include: A glass adapter plate has a first surface and a second surface opposite to the first surface. The glass adapter plate has a plurality of first openings on the first surface and a plurality of second openings on the second surface. The first conductive post is located inside the first opening; The second conductive post is located inside the second opening; The first circuit structure is located on one side of the glass adapter plate corresponding to the first surface; as well as, The second circuit structure is located on one side of the glass adapter plate corresponding to the second surface; Wherein, the orthographic projection of the first opening onto the first surface is the first projection, and the orthographic projection of the second opening onto the first surface is the second projection. The first projection is at least partially located outside the second projection, and the second projection is at least partially located outside the first projection. Therefore, the depth of the first opening and the depth of the second opening are both less than the thickness of the glass adapter plate. The bottom of the first opening and the bottom of the second opening are connected. The end of the first conductive post near the second surface is electrically connected to the end of the second conductive post near the first surface. The first conductive post is electrically connected to the first circuit structure, and the second conductive post is electrically connected to the corresponding second circuit structure.
2. The chip packaging carrier board according to claim 1, characterized in that, The sum of the depth of the second opening and the depth of the first opening is greater than the thickness of the glass transition plate, and the difference between the sum of the depths of the second opening and the first opening and the thickness of the glass transition plate is 15%-120% of the lateral dimension of the first opening or the second opening; Preferably, the difference between the sum of the depth of the second opening and the depth of the first opening and the thickness of the glass transition plate is 50%-80% of the lateral dimension of the first opening or the second opening; Preferably, the difference between the sum of the depths of the second opening and the first opening and the thickness of the glass adapter plate is 2-10 micrometers.
3. The chip packaging carrier board according to claim 1, characterized in that, The second projection is located within the first projection, and the overlapping portion of the first and second projections has a size of 2-10 micrometers along the line connecting the centroid of the first projection and the centroid of the second projection.
4. The chip packaging carrier board according to claim 1, characterized in that, The bottom of the first opening does not overlap with the bottom of the second opening. A connecting hole is provided on the glass adapter plate. The bottom of the first opening is connected to the bottom of the second opening through the connecting hole. A connecting part is provided in the connecting hole. The end of the first conductive post near the second surface is electrically connected to the end of the second conductive post near the first surface through the connecting part. Preferably, the orthographic projection of the bottom of the first opening onto the first surface is a third projection, and the orthographic projection of the bottom of the second opening onto the first surface is a fourth projection. The third projection is located within the first projection, and the fourth projection is located within the second projection. The first projection and the second projection partially overlap, and the third projection and the fourth projection do not overlap. Preferably, the area of the cross section of the connecting part perpendicular to the line connecting the centroid of the third projection and the centroid of the fourth projection is greater than or equal to 35% of the area of the fourth projection and less than or equal to the area of the fourth projection. Preferably, the minimum dimension of the connecting portion in the direction of the line connecting the centroid of the third projection and the centroid of the fourth projection is 0-2 micrometers.
5. The chip packaging carrier board according to claim 1, 2, or 3, characterized in that, The area of the second projection is smaller than the area of the first projection, and the depth of the second opening is smaller than the depth of the first opening. Preferably, the ratio of the area of the overlapping portion of the first projection and the second projection to the area of the second projection is in the range of 35%-100%.
6. A method for preparing a chip packaging substrate, characterized in that, include: The glass adapter plate has multiple first openings on the first surface and multiple second openings on the second surface. The depth of both the first and second openings is less than the thickness of the glass adapter plate. The bottom of the first opening is connected to the bottom of the second opening. The orthographic projection of the first opening onto the first surface is called the first projection, and the orthographic projection of the second opening onto the first surface is called the second projection. The first projection is at least partially located outside the second projection, and the second projection is at least partially located outside the first projection. A first conductive post is formed within the first opening and a second conductive post is formed within the second opening; A first circuit structure is formed on one side of the glass adapter plate; as well as A second circuit structure is formed on the side of the glass adapter plate away from the first circuit structure.
7. The method for preparing a chip packaging substrate according to claim 6, characterized in that, The method includes using a laser focal point to irradiate a portion of the structure of the glass adapter plate between the bottom of the first opening and the bottom of the second opening, thereby modifying the material of the irradiated portion of the structure, and then using an etching solution to remove the modified material after forming the first opening and / or the second opening to obtain a connecting hole. Preferably, the step of opening a plurality of first openings on the first surface of the glass adapter plate and opening a plurality of second openings on the second surface of the glass adapter plate includes: irradiating the portion of the glass adapter plate corresponding to the first openings and the portion of the glass adapter plate corresponding to the second openings with a pulsed laser focal point, thereby modifying the material of the irradiated portion of the structure, and performing the irradiation of the portion of the glass adapter plate corresponding to the connecting hole between the bottom of the first opening and the bottom of the second opening with a pulsed laser focal point in the same stage; The modified material is removed using an etching solution to obtain the first opening and the second opening at the same stage, and the modified material is removed using an etching solution to obtain the connecting hole.
8. The method for preparing a chip packaging substrate according to claim 6 or 7, characterized in that, The electroplating process forms a first conductive pillar located within the first opening and a second conductive pillar located within the second opening, including: Electroplating is performed using pulsed current to form a partition structure at the connecting portion between the first opening and the second opening, which can separate the first opening and the second opening into two blind holes. The two blind holes are filled by electroplating with direct current to obtain the first conductive post and the second conductive post. Preferably, the partition structure that separates the first opening and the second opening into two blind holes includes a connecting portion filled within the connecting hole.
9. The method for preparing a chip packaging substrate according to claim 6, characterized in that, The electroplating process forms a first conductive pillar located within the first opening and a second conductive pillar located within the second opening, including: The first opening is filled with sacrificial material to form the second opening as a blind hole, and electroplating is used to form at least a portion of the structure of the second conductive pillar that closes the bottom of the second opening; Remove the sacrificial material from the first opening and electroplate to form a first conductive pillar; Preferably, the area of the second projection is smaller than the area of the first projection, and the depth of the second opening is smaller than the depth of the first opening.
10. A chip packaging structure, characterized in that, It includes a chip packaging carrier and a chip, wherein the chip packaging carrier is the chip packaging carrier according to any one of claims 1-5, or the chip packaging carrier prepared by the method according to any one of claims 6-9; Preferably, the chip packaging substrate includes a first opening and a second opening, the area of the second opening projected onto the first surface is smaller than the area of the first opening projected onto the first surface, and the chip is disposed on the side of the chip packaging substrate corresponding to the second opening.