Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a manufacturing method thereof, including forming a first circuit portion and a second circuit portion on opposite sides of an interposer, respectively, to form an interposer structure, and then packaging a semiconductor element on the second circuit portion to balance the stress of the interposer structure through the first circuit portion and the second circuit portion, thereby avoiding the warping of the semiconductor package.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging technology, and more particularly to a semiconductor package with an intermediate structure and its manufacturing method. Background Technology

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multifunctionality and high performance. Currently, technologies applied in the field of chip packaging include flip-chip packaging modules such as Chip Scale Package (CSP), Direct Chip Attached (DCA), or Multi-Chip Module (MCM), as well as 3D integrated circuit (3DIC) packaging technology that integrates chips in a three-dimensional stack.

[0003] In existing 3D IC packaging technology, the chip is placed on the top of a silicon interposer (TSI) with multiple through-silicon vias (TSVs), and the bottom of the silicon interposer is placed on a packaging substrate.

[0004] However, existing silicon interposers require the fabrication of TSVs, which leads to a complicated process, significantly increasing material costs and process time, making it difficult to reduce the manufacturing cost of packaged products.

[0005] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Summary of the Invention

[0006] In view of the various deficiencies of the prior art, the present invention provides a semiconductor package comprising: an interposer structure including: an interposer having a first side and a second side opposite to each other, wherein the interposer includes a dielectric layer and a wiring layer bonded to the dielectric layer; a first line portion disposed on the first side of the interposer, wherein the first line portion includes a first insulating layer and a first line layer bonded to the first insulating layer and electrically connected to the wiring layer; and a second line portion disposed on the second side of the interposer, wherein the second line portion includes a second insulating layer and a second line layer bonded to the second insulating layer and electrically connected to the wiring layer; a semiconductor element disposed on the second line portion of the interposer structure and electrically connected to the second line layer; and an encapsulation layer covering the semiconductor element.

[0007] The present invention also provides a method for manufacturing a semiconductor package, comprising: forming an intermediate on a carrier of a full-area size, the intermediate having opposing first and second sides, and the intermediate being disposed on the carrier with its second side, wherein the intermediate includes a dielectric layer and a wiring layer bonded to the dielectric layer; forming a first circuit portion on the first side of the intermediate and electrically connecting the intermediate to the first circuit portion, wherein the first circuit portion includes a first insulating layer and a first circuit layer bonded to the first insulating layer and electrically connected to the wiring layer; removing the carrier; forming a second circuit portion on the second side of the intermediate to form a plurality of intermediate structures, wherein the second circuit portion includes a second insulating layer and a second circuit layer bonded to the second insulating layer and electrically connected to the wiring layer; disposing a semiconductor element on the second circuit portion; and encapsulating the semiconductor element with an encapsulation layer.

[0008] The present invention further provides a method for manufacturing a semiconductor package, comprising: forming an intermediate on a carrier of a full-area size, the intermediate having opposing first and second sides, and the intermediate being disposed on the carrier with its second side thereon, wherein the intermediate includes a dielectric layer and a wiring layer bonded to the dielectric layer; forming a first circuit portion on the first side of the intermediate and electrically connecting the intermediate to the first circuit portion, wherein the first circuit portion includes a first insulating layer and a first wiring layer bonded to the first insulating layer and electrically connected to the wiring layer; removing the carrier; and forming a second circuit on the second side of the intermediate. The process involves: forming multiple intermediate structures in a circuit section, wherein the second circuit section includes a second insulating layer and a second circuit layer bonded to the second insulating layer and electrically connected to the wiring layer; performing a first cut-off process to separate each of the intermediate structures; placing semiconductor elements on the second circuit sections of each intermediate structure; performing a rearrangement operation to arrange the multiple intermediate structures with semiconductor elements on a temporary carrier; forming an encapsulation layer covering the multiple intermediate structures and the multiple semiconductor elements on the temporary carrier; performing a second cut-off process; and removing the temporary carrier to expose the first circuit section.

[0009] In the aforementioned semiconductor package and its manufacturing method, the linewidth / spacing of the wiring layer is 0.6 / 0.6 micrometers.

[0010] In the aforementioned semiconductor package and its manufacturing method, the linewidth / spacing of the first circuit layer is greater than the linewidth / spacing of the wiring layer.

[0011] In the aforementioned semiconductor package and its manufacturing method, the linewidth / spacing of the second circuit layer is greater than the linewidth / spacing of the wiring layer.

[0012] The aforementioned semiconductor package and its manufacturing method further include forming a plurality of conductive elements on the first line portion, and the plurality of conductive elements being electrically connected to the first line layer.

[0013] As can be seen from the above, the semiconductor package and its manufacturing method of the present invention mainly reduce the number of layers of the first circuit layer and / or the second circuit layer by making an intermediate with fine line width / fine line pitch specifications, and also reduce the thickness of the semiconductor package, so as to facilitate the thinning of the semiconductor package.

[0014] Furthermore, by configuring the first circuit portion and the second circuit portion on the opposite first and second sides of the intermediary, the stress of the intermediary structure is balanced, thus avoiding the problem of warping of the semiconductor package.

[0015] Furthermore, this intermediary structure eliminates the need for TSV fabrication, thereby reducing material costs and process time, and thus significantly lowering the manufacturing cost of the semiconductor package. Attached Figure Description

[0016] Figures 1A to 1J This is a schematic diagram of a first embodiment of the method for manufacturing a semiconductor package according to the present invention.

[0017] Figure 1K This is a schematic diagram illustrating the subsequent application of the semiconductor package of the present invention.

[0018] Figures 2A to 2I This is a schematic diagram of a second embodiment of the method for manufacturing a semiconductor package according to the present invention.

[0019] Explanation of reference numerals in the attached figures

[0020] 2 Semiconductor packages

[0021] 2a Intermediary Structure

[0022] 20 Intermediaries

[0023] 20a First side

[0024] 20b Second side

[0025] 200 dielectric layers

[0026] 201 Wiring Layer

[0027] 21 First Line Department

[0028] 210 First Insulation Layer

[0029] 211 First Line Layer

[0030] 22 Second Line Department

[0031] 220 Second Insulation Layer

[0032] 221 Second Line Layer

[0033] 23 Semiconductor components

[0034] 230 conductive bump

[0035] 24 Encapsulation Layer

[0036] 25 base rubber

[0037] 26 Conductive elements

[0038] 3. Intermediary Sector

[0039] 4 Packaging substrate

[0040] 40 Electrical contacts

[0041] 5. Separation tools

[0042] 6 carrier disks

[0043] 7 Temporary vehicles

[0044] 8. Supporting Structure

[0045] 80 plate body

[0046] 81 Release layer

[0047] 82 bonding layer

[0048] 9. Bearing components

[0049] 90 Passivation layer

[0050] 900 opening

[0051] S,L1,L2 Cutting paths. Detailed Implementation

[0052] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0053] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0054] Figures 1A to 1JThis is a schematic diagram of a first embodiment of the manufacturing method of the semiconductor package 2 of the present invention. In this embodiment, wafer-level packaging specifications are used.

[0055] like Figure 1A As shown, a carrier 9 of full panel size is provided, on which a passivation layer 90 is provided, and an intermediary 20 is provided on the passivation layer 90, wherein the intermediary 20 has a first side 20a and a second side 20b opposite to each other, and the intermediary 20 is attached to the passivation layer 90 with its second side 20b.

[0056] In this embodiment, the carrier 9 is a semiconductor substrate (e.g., a silicon substrate) with a full-area specification. The passivation layer 90 is made of materials such as silicon dioxide or silicon nitride. The intermediary 20 is a back end of line (BEOL) wafer. The first side 20a is the front side, and the second side 20b is the back side.

[0057] Furthermore, the interposer 20 includes at least one dielectric layer 200 and at least one wiring layer 201 bonded to the dielectric layer 200. For example, the dielectric layer 200 includes dielectric materials such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others, and the wiring layer 201 can be formed using patterned electroplated copper or other methods to form the required redistribution layer (RDL).

[0058] Furthermore, the dielectric layer 200 serves as an inter-metal dielectric (IMD), and the line width / spacing (L / S) of the wiring layer 201 is 0.6 / 0.6 micrometers (µm).

[0059] like Figure 1B As shown, a first circuit section 21 is formed on the first side 20a of the intermediary 20, and the intermediary 20 is electrically connected to the first circuit section 21.

[0060] In this embodiment, the first line portion 21 includes at least one first insulating layer 210 and at least one first line layer 211 bonded to the first insulating layer 210, and the wiring layer 201 is electrically connected to the first line layer 211. For example, the first insulating layer 210 is polyimide (PI) or other dielectric materials, and the first line layer 211 can be formed into an RDL by patterned electroplated metal materials (such as copper, nickel, gold, tin silver or other metals) or other methods.

[0061] Furthermore, the line width / spacing of the first line layer 211 is greater than the line width / spacing of the wiring layer 201.

[0062] like Figure 1C As shown, a full-page support structure 8 is provided on the first line section 21. Next, the carrier 9 is removed, while the passivation layer 90 is retained.

[0063] In this embodiment, the support structure 8 is formed on a plate 80 made of a semiconductor material (such as silicon or glass), on which a release layer 81 and a bonding layer 82, such as an adhesive material, are sequentially formed by means of coating, so that the bonding layer 82 is temporarily bonded to the first circuit portion 21.

[0064] Furthermore, the removal of the carrier 9 involves first removing most of the silicon material by grinding, and then removing the remaining thinner silicon layer by dry etching.

[0065] like Figure 1D As shown, a plurality of openings 900 are formed on the passivation layer 90 so that the wiring layer 201 is exposed to the plurality of openings 900.

[0066] In this embodiment, the aperture 900 can be fabricated by patterning photoresist to etch a portion of the passivation layer 90 and then removing the patterned photoresist.

[0067] like Figure 1E As shown, a second circuit portion 22 is formed on the passivation layer 90, and the intermediary 20 is electrically connected to the second circuit portion 22 to form an intermediary structure 2a. The intermediary structure 2a mainly combines the first circuit portion 21 and the second circuit portion 22 on the first side 20a and the second side 20b of the intermediary 20, respectively, and forms a sandwich structure.

[0068] In this embodiment, the second circuit portion 22 includes at least one second insulating layer 220 and at least one second circuit layer 221 bonded to the second insulating layer 220, and a portion of the second circuit layer 221 extends into the opening 900 and contacts the wiring layer 201, so that the wiring layer 201 is electrically connected to the second circuit layer 221. For example, the second insulating layer 220 is polyimide (PI) or other dielectric materials, and the second circuit layer 221 can be formed into an RDL by patterned electroplated copper or other methods.

[0069] Furthermore, the line width / spacing of the second line layer 221 is greater than that of the wiring layer 201.

[0070] like Figure 1F As shown, at least one semiconductor element 23 is disposed on the second circuit section 22 (the illustration in this embodiment shows multiple semiconductor elements 23), and then the semiconductor element 23 is covered by an encapsulation layer 24.

[0071] The semiconductor element 23 is an active element, a passive element, or a combination of both, and the active element is, for example, a semiconductor chip, while the passive element is, for example, a resistor, a capacitor, or an inductor.

[0072] In this embodiment, the semiconductor element 23 is a semiconductor chip with an active circuit layer, which is electrically connected to the second circuit layer 221 via multiple conductive bumps 230 made of copper and / or solder in a flip-chip manner. Additionally, an underfill 25 can be formed between the semiconductor element 23 and the second circuit portion 22 to cover the conductive bumps 230, and then an encapsulation layer 24 can be formed to cover the underfill 25 and the semiconductor element 23. The purpose of filling the underfill 25 is to fill the space between the lower surface of the semiconductor element 23 and the upper surface of the intermediate structure 2a. Alternatively, the formation of the underfill 25 can be omitted, and the conductive bumps 230 and the semiconductor element 23 can be directly covered by the encapsulation layer 24.

[0073] The encapsulation layer 24 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin.

[0074] In this embodiment, the encapsulation layer 24 is formed using a molding process to protect the semiconductor element 23 and cover the upper surface of the intermediate structure 2a.

[0075] like Figure 1G As shown, the support structure 8 is removed to expose the first insulation layer 210 and the first circuit layer 211 of the first circuit portion 21.

[0076] In this embodiment, the plate 80, release layer 81 and bonding layer 82 of the support structure 8 can be removed by physically peeling off the plate 80 and release layer 81, etching most of the material of the bonding layer 82, and laser debonding the remaining part of the bonding layer 82, thereby exposing the PI material and metal material (i.e. the first insulating layer 210 and the first circuit layer 211 of the first circuit portion 21) on the lower surface of the intermediate structure 2a.

[0077] like Figure 1H As shown, conductive elements 26, such as multiple conductive solder balls or conductive pillars, are formed on the first circuit section 21 so that these conductive elements 26 are electrically connected to the first circuit section 21.

[0078] In this embodiment, the conductive elements 26 are formed by a ball-mounting process or a surface mount process, so as to bond the conductive elements 26 to the exposed metal material (first circuit layer 211) on the lower surface of the intermediate structure 2a.

[0079] like Figure 1I and Figure 1J As shown, along as Figure 1H The cutting path S shown is used for a singulation process to obtain a semiconductor package 2.

[0080] In this embodiment, the intermediate structure 2a that has been packaged at the wafer level but has not yet been cut and separated can be placed on the adhesive layer of a carrier 6 with the conductive element 26 on its lower surface, and then a cutting process is performed with a separation tool 5 such as a knife, and the good products are sorted.

[0081] In subsequent processes, such as Figure 1K As shown, the semiconductor package 2 can be subjected to surface mount technology (SMT) process, and the conductive elements 26 are disposed on the electrical contacts 40 of a package substrate 4. The package substrate 4 is, for example, an ABF carrier, a bismaleimide triazine (BT) carrier, a PCB (printed circuit) carrier, a ceramic carrier, a copper stud carrier, or a carrier of other specifications.

[0082] Therefore, the method of this embodiment uses back-end process wafers to fabricate an intermediate 20 with fine linewidth / fine line pitch (L / S = 0.6 / 0.6um), which not only reduces the number of layers of the first circuit layer 211 and / or the second circuit layer 221, but also reduces the thickness of the semiconductor package 2, thereby facilitating the thinning of the semiconductor package 2.

[0083] Furthermore, the manufacturing method of this embodiment arranges RDL structures (first line portion 21 and second line portion 22) on the upper and lower sides of the intermediary 20 respectively to balance the stress of the intermediary structure 2a, thus avoiding the problem of warping of the semiconductor package 2.

[0084] Furthermore, the manufacturing method of this embodiment omits the fabrication of through silicon (TSV) through the intermediate structure 2a, thereby reducing material costs and process time, and thus significantly reducing the manufacturing cost of the semiconductor package 2.

[0085] Figures 2A to 2I This is a schematic diagram of a second embodiment of the manufacturing method of the semiconductor package 2 of the present invention. This embodiment is largely the same as the first embodiment, so the similarities will not be repeated below.

[0086] In this embodiment, a single unit level (SJL) packaging process is used.

[0087] like Figure 2A As shown above, Figures 1A to 1E As shown, a sandwich-shaped intermediate structure 2a is formed on the support structure 8, which includes an intermediate body 20 and a first line portion 21 and a second line portion 22 respectively provided on both sides of the intermediate body 20.

[0088] like Figure 2B and Figure 2C As shown, along as Figure 2A The cutting path L1 shown performs the first cutting process to separate each of the intermediate structures 2a, thereby obtaining multiple intermediate plates 3 containing intermediate structures 2a and support structures 8.

[0089] In this embodiment, the first cutting process is performed by a separation tool 5, such as a cutting tool.

[0090] like Figure 2D and Figure 2E As shown, semiconductor elements 23 are attached to the second circuit portion 22 of each intermediate plate 3 via multiple conductive bumps 230 using a flip-chip method (or die-attach method), and then the conductive bumps 230 are covered with a base adhesive 25. Next, a rearrangement operation is performed to arrange the multiple intermediate plates 3 with semiconductor elements 23 on them on a temporary carrier 7 using their support structures 8.

[0091] In this embodiment, the temporary vehicle 7 is strip-shaped, and the intermediate panels 3 are arranged in an array on the temporary vehicle 7.

[0092] like Figure 2F As shown, an encapsulation layer 24 is formed on the temporary carrier 7 to cover the intermediate plates 3 and the semiconductor elements 23 disposed thereon.

[0093] In this embodiment, multiple intermediary plates 3 that have undergone flip-chip or die-bonding processes are disposed on the temporary carrier 7, so that the temporary carrier 7 can undergo a molding process to protect the semiconductor device 23 and its adhesion to the upper surface of the intermediary plate 3.

[0094] like Figure 2G and Figure 2H As shown, along as Figure 2F The cutting path L2 shown is used for a second single-piece cutting process. Afterwards, the temporary carrier 7 and the support structure 8 are removed to expose the first circuit portion 21 to obtain multiple semiconductor packages 2.

[0095] In this embodiment, a second cutting process is performed using a separating tool 5, such as a cutting tool, to cut the molded intermediate plate 3 into individual pieces.

[0096] Furthermore, each molded intermediate plate 3, which has been cut into individual units, is first removed from the temporary carrier 7. Then, the plate 80, release layer 81, and bonding layer 82 of the support structure 8 are removed by physically peeling off the plate body 80 and release layer 81, etching most of the material of the bonding layer 82, and laser debonding the remaining part of the bonding layer 82. This exposes the PI material and metal material (i.e., the first insulating layer 210 and the first circuit layer 211 of the first circuit portion 21) on the lower surface of the intermediate structure 2a.

[0097] In addition, in subsequent processes, such as Figure 2I As shown, a plurality of conductive elements 26 electrically connected to the first circuit layer 211 are formed on the first circuit portion 21, so that the semiconductor package 2 can be disposed on a packaging substrate 4 through these conductive elements 26 (e.g., Figure 1K (As shown).

[0098] Therefore, the method of this embodiment uses back-end process wafers to fabricate an intermediate 20 with fine linewidth / fine line pitch (L / S = 0.6 / 0.6um), which not only reduces the number of layers of the first circuit layer 211 and / or the second circuit layer 221, but also reduces the thickness of the semiconductor package 2, thereby facilitating the thinning of the semiconductor package 2.

[0099] Furthermore, the manufacturing method of this embodiment arranges RDL structures (first line portion 21 and second line portion 22) on the upper and lower sides of the intermediary 20 respectively to balance the stress of the intermediary structure 2a, thus avoiding the problem of warping of the semiconductor package 2.

[0100] Furthermore, the manufacturing method of this embodiment omits the fabrication of the TSV by using the intermediate structure 2a, thereby reducing material costs and process time, and thus significantly reducing the manufacturing cost of the semiconductor package 2.

[0101] The present invention also provides a semiconductor package 2, comprising: an interposer structure 2a, at least one semiconductor element 23 and an encapsulation layer 24, wherein the interposer structure 2a comprises: an interposer 20, a first circuit portion 21 and a second circuit portion 22.

[0102] The intermediate body 20 has opposing first sides 20a and second sides 20b, wherein the intermediate body 20 includes at least one dielectric layer 200 and at least one wiring layer 201 bonded to the dielectric layer 200.

[0103] The first line portion 21 is disposed on the first side 20a of the intermediate body 20, wherein the first line portion 21 includes at least one first insulating layer 210 and at least one first line layer 211 which is combined with the first insulating layer 210 and electrically connected to the wiring layer 201.

[0104] The second line portion 22 is disposed on the second side 20b of the intermediate body 20, wherein the second line portion 22 includes at least one second insulating layer 220 and at least one second line layer 221 which is combined with the second insulating layer 220 and electrically connected to the wiring layer 201.

[0105] The semiconductor element 23 is disposed on the second line portion 22 of the intermediate structure 2a and electrically connected to the second line layer 221.

[0106] The encapsulation layer 24 covers the semiconductor element 23.

[0107] In one embodiment, the wiring layer 201 has a linewidth / spacing of 0.6 / 0.6 micrometers.

[0108] In one embodiment, the line width / spacing of the first line layer 211 is greater than the line width / spacing of the wiring layer 201.

[0109] In one embodiment, the line width / spacing of the second line layer 221 is greater than the line width / spacing of the wiring layer 201.

[0110] In one embodiment, the semiconductor package 2 further includes a plurality of conductive elements 26 disposed on the first line portion 21, which are electrically connected to the first line layer 211.

[0111] In summary, the semiconductor package and its manufacturing method of the present invention, by producing an intermediate with fine linewidth / fine line spacing specifications, can not only reduce the number of layers of the first circuit layer and / or the second circuit layer, but also reduce the thickness of the semiconductor package, thereby facilitating the thinning of the semiconductor package.

[0112] Furthermore, by arranging the first circuit portion and the second circuit portion on the upper and lower sides of the intermediary respectively, the stress of the intermediary structure is balanced, thus avoiding the problem of warping of the semiconductor package.

[0113] Furthermore, this intermediary structure eliminates the need for TSV fabrication, thereby reducing material costs and process time, and thus significantly lowering the manufacturing cost of the semiconductor package.

[0114] The above embodiments are used to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A semiconductor package, characterized in that, include: The intermediary structure includes: An intermediary having opposing first and second sides, wherein the intermediary includes a dielectric layer and a wiring layer bonded to the dielectric layer; A first wiring portion is disposed on a first side of the intermediate, wherein the first wiring portion includes a first insulating layer and a first wiring layer bonded to the first insulating layer and electrically connected to the wiring layer; and A second wiring portion is disposed on a second side of the intermediate body, wherein the second wiring portion includes a second insulating layer and a second wiring layer bonded to the second insulating layer and electrically connected to the wiring layer; A semiconductor element is disposed on the second circuit portion of the intermediate structure and electrically connected to the second circuit layer; and The encapsulation layer covers the semiconductor device.

2. The semiconductor package as claimed in claim 1, characterized in that, The line width / spacing of this wiring layer is 0.6 / 0.6 micrometers.

3. The semiconductor package as described in claim 1, characterized in that, The line width / spacing of the first line layer is greater than that of the wiring layer.

4. The semiconductor package as claimed in claim 1, characterized in that, The line width / spacing of the second line layer is greater than that of the wiring layer.

5. The semiconductor package as claimed in claim 1, characterized in that... The semiconductor package also includes a plurality of conductive elements disposed on the first line portion, which are electrically connected to the first line layer.

6. A method for manufacturing a semiconductor package, characterized in that, include: An intermediary is formed on a carrier of a full-page size. The intermediary has a first side and a second side opposite to each other, and the intermediary is disposed on the carrier with its second side. The intermediary includes a dielectric layer and a wiring layer bonded to the dielectric layer. A first circuit portion is formed on a first side of the intermediate, and the intermediate is electrically connected to the first circuit portion, wherein the first circuit portion includes a first insulating layer and a first circuit layer bonded to the first insulating layer and electrically connected to the wiring layer; Remove the carrier component; A second line portion is formed on the second side of the intermediary to form a plurality of intermediary structures, wherein the second line portion includes a second insulating layer and a second line layer bonded to the second insulating layer and electrically connected to the wiring layer; A semiconductor element is disposed on the second circuit section; and The semiconductor device is encapsulated with a packaging layer.

7. The method for manufacturing a semiconductor package as described in claim 6, characterized in that, The steps of disposing a semiconductor element on the second circuit portion and encapsulating the semiconductor element with an encapsulation layer further include: The first cut-off process is performed to separate the various intermediate structures; The semiconductor element is disposed on the second line portion of each of the separated intermediate structures; A rearrangement operation is performed to arrange multiple intermediate structures containing the semiconductor element on a temporary carrier; An encapsulation layer is formed on the temporary carrier to cover the plurality of intermediate structures and the plurality of semiconductor elements; Perform a second order cutting process; and Remove the temporary vehicle to expose the first line section.

8. The method for manufacturing a semiconductor package as described in claim 6 or 7, characterized in that, The line width / spacing of this wiring layer is 0.6 / 0.6 micrometers.

9. The method for manufacturing a semiconductor package as described in claim 6 or 7, characterized in that, The line width / spacing of the first line layer is greater than that of the wiring layer.

10. The method for manufacturing a semiconductor package as described in claim 6 or 7, characterized in that, The line width / spacing of the second line layer is greater than that of the wiring layer.

11. The method for manufacturing a semiconductor package as described in claim 6 or 7, characterized in that... The manufacturing method also includes forming a plurality of conductive elements on the first circuit portion, and the plurality of conductive elements being electrically connected to the first circuit layer.

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