Electronic package structure and method of manufacturing the same

Abstract

An electronic package structure includes a substrate structure and a wire. The substrate structure includes a circuit layer, a dielectric layer, and a bump layer. The circuit layer includes a pad portion. The dielectric layer covers the circuit layer and defines an opening to expose a top surface of the pad portion. An elevation of the top surface of the pad portion is lower than an elevation of a top surface of the dielectric layer. The bump layer is disposed on the pad portion of the circuit layer and extends beyond the top surface of the dielectric layer. The wire is disposed on the bump layer.

Description

Technical Field

[0001] This disclosure relates to an electronic packaging structure and a method for manufacturing the same, and further to an electronic packaging structure including a padding layer and a method for manufacturing the same. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips integrate more electronic components to achieve better electrical performance. Therefore, semiconductor chips are equipped with more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of both the semiconductor chip and the semiconductor package increases accordingly. To minimize the size of the semiconductor package containing semiconductor chips with an increased number of I / O connections, the density of the bonding pads on the semiconductor substrate carrying the semiconductor chip should be increased accordingly. Therefore, the bonding between the semiconductor chip and the bonding pads is a critical issue. Summary of the Invention

[0003] In some embodiments, the electronic package structure includes a substrate structure and conductive lines. The substrate structure includes a circuit layer, a dielectric layer, and a pad layer. The circuit layer includes pad portions. The dielectric layer covers the circuit layer and defines an opening to expose the top surface of the pad portions. The elevation of the top surface of the pad portions is lower than the elevation of the top surface of the dielectric layer. The pad layer is disposed on the pad portions of the circuit layer and extends beyond the top surface of the dielectric layer. The conductive lines are disposed on the pad layer.

[0004] In some embodiments, the electronic package structure includes a circuit layer, a dielectric layer, and a pad layer. The circuit layer includes pad portions. The dielectric layer covers the circuit layer and defines an opening to expose the top surface of the pad portions. The top surface of the pad portions is lower than the top surface of the dielectric layer. The pad layer is disposed on the pad portions of the circuit layer and arranged to reduce delamination between the conductors and the dielectric layer due to misalignment between the conductors and the pad portions of the circuit layer during the conductor bonding process.

[0005] In some embodiments, the electronic package structure includes a substrate structure and conductive wires. The substrate structure includes a circuit layer and a dielectric layer. The circuit layer includes pad portions. The dielectric layer covers the circuit layer and defines an opening to expose the top surface of the pad portions. The top surface of the pad portions is lower than the top surface of the dielectric layer. Conductors are electrically connected to the pad portions and located away from the pad portions. The bottom surface of the conductors is at a higher elevation than the top surface of the pad portions. Attached Figure Description

[0006] Various aspects of some embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that the structures may not be drawn to scale, and the dimensions of the structures may be arbitrarily enlarged or reduced for clarity of explanation.

[0007] Figure 1 This is a cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0008] Figure 2 for Figure 1 An enlarged view of region "A" in the image.

[0009] Figure 3 for Figure 1 An enlarged view of region "B" in the image.

[0010] Figure 4 This is a cross-sectional view of a first portion of a first circuit layer and a padding layer according to some embodiments of the present disclosure.

[0011] Figure 5 This is a cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0012] Figure 6 for Figure 5 An enlarged view of region "C" in the image.

[0013] Figure 7 for Figure 5 An enlarged view of region "D" in the image.

[0014] Figure 7A This is an enlarged cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0015] Figure 7B This is an enlarged cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0016] Figure 8 This is a cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0017] Figure 9 for Figure 8 An enlarged view of region "E" in the image.

[0018] Figure 10 This is a cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure.

[0019] Figure 11 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0020] Figure 12These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0021] Figure 13 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0022] Figure 14 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0023] Figure 15 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0024] Figure 16 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0025] Figure 17 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0026] Figure 18 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0027] Figure 19 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0028] Figure 20 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0029] Figure 21 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure.

[0030] Figure 22 These are examples of one or more stages of a method for manufacturing an electronic package structure according to some embodiments of the present disclosure. Detailed Implementation

[0031] In the accompanying drawings and detailed description, general reference numerals are used to denote the same or similar elements. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0032] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate specific aspects of the invention. Of course, these components, values, operations, materials, and arrangements are merely examples and are not intended to be limiting. For example, in the description provided herein, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features are formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances provided herein. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Figure 1 This is a cross-sectional view of a portion of an electronic packaging structure 1 according to some embodiments of the present disclosure. Figure 2 for Figure 1 An enlarged view of region "A" in the image. Figure 3 for Figure 1 An enlarged view of region "B" in the image. The electronic package structure 1 may include a substrate structure 2, an electronic component 12, at least one wire 4, a package body 14, and at least one external connector 19 (e.g., solder ball).

[0034] The substrate structure 2 can be a circuit pattern structure, a redistribution layer (RDL) structure, or a wiring structure. The substrate structure 2 can be an embedded trace substrate (ETS). The substrate structure 2 can include a dielectric structure 20, a first circuit layer 22, a booster layer 5, a second circuit layer 24, at least one inner via 23, a first protective layer 26, and a second protective layer 28.

[0035] The dielectric structure 20 (e.g., a dielectric layer) may be, or may include, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, other suitable materials, or combinations thereof. The dielectric structure 20 may be, or may include, for example, a sheet made of pre-impregnated composite fibers. For example, the dielectric structure 20 may include cured fiber-reinforced resin. The thickness of the dielectric structure 20 may be, for example, about 40 μm to 80 μm. The dielectric structure 20 may include a first surface 201 (e.g., a top surface) and a second surface 202 (e.g., a bottom surface) opposite the first surface 201. It should be noted that the dielectric structure 20 may include, or be formed from, a cured photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) or polypropylene (PP) including photoinitiators. In some embodiments, the dielectric structure 20 may be a single layer, a single sheet, a single-sheet structure, or a monolithic structure. In some embodiments, the dielectric structure 20 may include multiple dielectric layers.

[0036] The first circuit layer 22 may be embedded in the dielectric structure 20 and may be formed by a semi-additive process (SAP) or a modified semi-additive process (MSAP). The material of the first circuit layer 22 may be a conductive metal, such as copper, and the thickness of the first circuit layer 22 may be greater than about 10 μm (e.g., about 15 μm). A portion of the first circuit layer 22 (e.g., the top surface) may be exposed from the first surface 201 of the dielectric structure 20. For example, the dielectric structure 20 may not cover the top surface of the first circuit layer 22. The first circuit layer 22 may not protrude from the first surface 201 of the dielectric structure 20. The line width / line spacing (L / S) of the first circuit layer 22 may be greater than or equal to about 7 μm / about 7 μm, greater than or equal to about 5 μm / about 5 μm, or greater than or equal to about 2 μm / about 2 μm.

[0037] In some embodiments, the first circuit layer 22 may include a first portion 221 (e.g., a first pad portion, a first bonding pad, or a portion of a first trace) and a second portion 222 (e.g., a second pad portion, a second bonding pad, or a portion of a second trace). The first portion 221 of the first circuit layer 22 may have a first surface 2211 (e.g., a top surface), a second surface 2212 (e.g., a bottom surface) opposite the first surface 2211, and a side surface 2213 extending between the first surface 2211 and the second surface 2212. The first portion 221 of the first circuit layer 22 is recessed or recessed from the first surface 201 of the dielectric structure 20, and a first distance D1 may be formed between the first surface 2211 of the first portion 221 and the first surface 201 of the dielectric structure 20, thereby forming a recessed portion 205 (or a first opening) located above the first surface 2211 of the first portion 221 and below the first surface 201 of the dielectric structure 20. However, in some embodiments, the first surface 2211 of the first portion 221 may be coplanar or aligned with the first surface 201 of the dielectric structure 20.

[0038] Therefore, the dielectric structure 20 (e.g., a dielectric layer) may encapsulate the first circuit layer 22. The dielectric structure 20 (e.g., a dielectric layer) may define (or delineate) a recessed portion 205 (or an opening) to expose a first surface 2211 (e.g., a top surface) of the first portion 221 (e.g., a first pad portion). The elevation of the first surface 2211 (e.g., the top surface) of the first portion 221 (e.g., the first pad portion) may be lower than the elevation of the first surface 201 (e.g., the top surface) of the dielectric structure 20 (e.g., the dielectric layer).

[0039] Furthermore, the surface roughness value (e.g., expressed as root mean square surface roughness) of the first surface 2211 of the first portion 221 can be greater than about 0.4 μm, and the surface roughness value of the side surface 2213 of the first portion 221 can be in the range of about 0.25 μm to about 0.5 μm. For example, the surface roughness of the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 can be greater than the surface roughness of the side surface 2213 of the first portion 221 of the first circuit layer 22. In some embodiments, the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 can be a concave surface.

[0040] The width of the second portion 222 of the first circuit layer 22 may be greater than the width of the first portion 221 of the first circuit layer 22. The second portion 222 of the first circuit layer 22 may have a first surface 2221 (e.g., a top surface), a second surface 2222 (e.g., a bottom surface) opposite the first surface 2221, and a side surface 2223 extending between the first surface 2221 and the second surface 2222. The second portion 222 of the first circuit layer 22 is recessed or recessed from the first surface 201 of the dielectric structure 20, and a second distance D2 may be formed between the first surface 2221 of the second portion 222 and the first surface 201 of the dielectric structure 20, thereby forming a recessed portion 206 (or a second opening) located above the first surface 2221 of the second portion 222 and below the first surface 201 of the dielectric structure 20. The second distance D2 may be equal to or less than the first distance D1. However, in some embodiments, the first surface 2221 of the second portion 222 may be coplanar or aligned with the first surface 201 of the dielectric structure 20.

[0041] Furthermore, the surface roughness value (e.g., expressed as root mean square surface roughness) of the first surface 2221 of the second portion 222 can be greater than about 0.4 μm, and the surface roughness value of the side surface 2223 of the second portion 222 can be in the range of about 0.25 μm to about 0.5 μm. For example, the surface roughness of the first surface 2221 (e.g., the top surface) of the second portion 222 of the first circuit layer 22 can be greater than the surface roughness of the side surface 2223 of the second portion 222 of the first circuit layer 22. In some embodiments, the surface roughness of the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 can be different from (e.g., greater than or less than) the surface roughness of the first surface 2221 (e.g., the top surface) of the second portion 222 of the first circuit layer 22. In some embodiments, the first surface 2221 (e.g., the top surface) of the second portion 222 of the first circuit layer 22 can be concave. Furthermore, the lowest point 2214 of the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 may be lower than the lowest point 2224 of the first surface 2221 (e.g., the top surface) of the second portion 222 of the first circuit layer 22.

[0042] The padding layer 5 may also be referred to as an "added layer," "height adjustment layer," "elevated layer," or "thickening layer." The padding layer 5 may be disposed on a first portion 221 of the first circuit layer 22 and may extend beyond the first surface 201 of the dielectric structure 20. The padding layer 5 may include a first metal material 51 and a second metal material 52 disposed on the first metal material 51. The first metal material 51 and the second metal material 52 may together form a cap-like structure or an intermediate structure. The first metal material 51 may be disposed on a first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 and may extend beyond the first surface 201 of the dielectric structure 20. Therefore, the first metal material 51 may extend from the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 to above the first surface 201 of the dielectric structure 20. The first surface 201 of the dielectric structure 20 may overlap with the first metal material 51 in the horizontal direction.

[0043] The first metal material 51 may include an upper portion 512 and a lower portion 511. The lower portion 511 may be disposed in the recessed portion 205 and may be below the first surface 201 of the dielectric structure 20. The lower portion 511 may have a generally uniform thickness and width. The upper portion 512 may be disposed on the lower portion 511 and may be above the first surface 201 of the dielectric structure 20. The maximum width W1 of the upper portion 512 of the first metal material 51 may be greater than the maximum width W2 of the lower portion 511 of the first metal material 51. The maximum width W1 may include the thickness of the second metal material 52. The maximum width W2 of the lower portion 511 of the first metal material 51 is approximately equal to the width W2 of the first portion 221 of the first circuit layer 22. Therefore, the maximum width W1 of the pad layer 5 may be greater than the width W2 of the first portion 221 of the first circuit layer 22 (e.g., the first pad portion). The upper portion 512 of the first metal material 51 may taper away from the first surface 201 of the dielectric structure 20. The upper portion 512 of the first metallic material 51 may taper toward the first surface 201 away from the dielectric structure 20.

[0044] The upper portion 512 of the first metal material 51 may include a middle portion 5121 and a peripheral portion 5122 surrounding the middle portion 5121. The middle portion 5121 may have a generally uniform thickness and may have a generally flat top surface 5123. The peripheral portion 5122 may have side surfaces 5124. Therefore, the upper portion 512 of the first metal material 51 may have a flat top surface 5123 and side surfaces 5124 extending between the flat top surface 5123 and the first surface 201 of the dielectric structure 20. The generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51 may be generally parallel to the first surface 201 of the dielectric structure 20. The peripheral portion 5122 may taper away from the middle portion 5121. That is, the peripheral portion 5122 may taper away from the middle portion 5121. The peripheral portion 5122 may contact the first surface 201 of the dielectric structure 20. Furthermore, the width W3 of the generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51 can be less than, substantially equal to or greater than the width W2 of the first portion 221 of the first circuit layer 22. In some embodiments, the width W3 may not be less than the width W2.

[0045] The upper portion 512 and the lower portion 511 can be a single, integrally formed structure. The side surface 5124 of the upper portion 512 of the first metal material 51 can be curved or convex. Therefore, the first metal material 51 can generally have a mushroom shape or a "T" shape. There may be no interface between the upper portion 512 and the lower portion 511. The first metal material 51 may include nickel (Ni) and may be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / immersion gold (ENEPIG). Furthermore, the surface roughness of the generally flat top surface 5123 of the middle portion 5121 of the upper portion 5122 of the first metal material 51 can be less than the surface roughness of the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22.

[0046] A second metal material 52 may be disposed between the first metal material 51 and the first end portion 41 of the conductor 4. Therefore, the second metal material 52 may be configured to enhance the bonding strength between the first end portion 41 of the conductor 4 and the padding layer 5. The second metal material 52 may be conformally formed or disposed on the upper portion 512 of the first metal material 51. Therefore, the second metal material 52 may cover and contact the top surface 5123 and the side surface 5124 of the upper portion 512 of the first metal material 51. The second metal material 52 may be a metal layer having a substantially uniform thickness. The second metal material 52 may be formed or disposed on the entire top surface of the first metal material 51 and may contact the first surface 201 of the dielectric structure 20. The thickness of the second metal material 52 may be less than the thickness of the middle portion 5121 of the upper portion 512 of the first metal material 51, or less than the thickness of the lower portion 511 of the first metal material 51. In some embodiments, the thickness of the second metal material 52 can be from about 0.2 μm to about 10 μm, but is not limited to this range. The second metal material 52 may include gold (Au) and can be formed by a deposition process, such as an electroless nickel immersion gold process, or an electroless nickel / electroless palladium / immersion gold process.

[0047] The second metal material 52 may have a generally flat top surface 521 and side surfaces 522. The generally flat top surface 521 may be the generally flat top surface of the padding layer 5. The generally flat top surface 521 may also be referred to as a "joining area," "joining surface," or "receiving surface." The side surfaces 522 may be the side surfaces of the padding layer 5. The generally flat top surface 521 of the second metal material 52 may be generally parallel to the first surface 201 of the dielectric structure 20. Furthermore, the width W4 of the generally flat top surface 521 of the second metal material 52 may be less than, substantially equal to, or greater than the width W3 of the generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51. The area of ​​the generally flat top surface 521 of the padding layer 5 may be substantially equal to the area of ​​the top surface 2211 of the first portion 221 of the first circuit layer 22.

[0048] In some embodiments, the hardness of the second metal material 52 may be less than the hardness of the first metal material 51. The rigidity of the padding layer 5 may be greater than the rigidity of the first portion 221 of the first circuit layer 22. The padding layer 5 is not conformally fitted to the first portion 221 of the first circuit layer 22.

[0049] The second circuit layer 24 can be disposed on the second surface 202 of the dielectric structure 20, and can protrude or extend from the second surface 202 of the dielectric structure 20. The material of the second circuit layer 24 can be a conductive metal, such as copper, and the thickness of the second circuit layer 24 can be, for example, about 15 μm. The second circuit layer 24 can be electrically connected to the first circuit layer 22 via an internal via 23. A portion 245 of the second circuit layer 24 is used for external connection. The second circuit layer 24 may include a seed layer 243 and a conductive metal 244 disposed on the seed layer 243. The seed layer 243 can be sandwiched between the conductive metal 244 and the second surface 202 of the dielectric structure 20.

[0050] An internal via 23 can be embedded in the dielectric structure 20. The internal via 23 can be a single-piece structure. The first end of the internal via 23 can connect to the second surface 2222 (e.g., the bottom surface) of the second portion 222 of the first circuit layer 22, and the second end of the internal via 23 can connect to the second circuit layer 24. The vertical distance between the first circuit layer 22 and the second circuit layer 24 can be the thickness or height of one internal via 23. The width of the first end of the internal via 23 can be smaller than the width of its second end. Therefore, the internal via 23 can taper towards the first circuit layer 22. In some embodiments, the internal via 23 and the second circuit layer 24 can be formed integrally and simultaneously. For example, the internal via 23 may include a seed layer 233 and a conductive metal 234 formed on the seed layer 233. The seed layer 233 of the internal via 23 and the seed layer 243 of the second circuit layer 24 can be the same layer. The conductive metal 234 of the internal via 23 and the conductive metal 244 of the second circuit layer 24 can be the same layer.

[0051] A first protective layer 26 may be disposed on a first surface 201 of the dielectric structure 20 and may define at least one opening 265 to expose the pad layer 5 for external connection. The upper portion of the opening 265 may taper upwards, while the lower portion may taper downwards. That is, the sidewalls of the opening 265 may include curved surfaces. The upper portion of the opening 265 may taper away from the dielectric structure 20 (e.g., dielectric layer), while the lower portion may taper towards the dielectric structure 20 (e.g., dielectric layer). The material of the first protective layer 26 may be solder resist. The first protective layer 26 may extend into the recess 206 to cover and contact the first surface 2221 (e.g., top surface) of the second portion 222 of the first circuit layer 22. The pad layer 5 may be spaced apart from the first protective layer 26. That is, the pad layer 5 may not contact the first protective layer 26. In some embodiments, a first portion 221 of the first circuit layer 22 (e.g., a first pad portion) may be spaced apart from the first protective layer 26.

[0052] A second protective layer 28 may be disposed on the second surface 202 of the dielectric structure 20 and may cover the second circuit layer 24. The second protective layer 28 may define at least one opening 285 to expose a portion 245 of the second circuit layer 24 for external connection. For example, the portion 245 of the second circuit layer 24 may be a solder ball pad. The material of the second protective layer 28 may be solder resist. The upper portion of the opening 285 may gradually narrow upwards, and the lower portion of the opening 285 may gradually narrow downwards. That is, the sidewalls of the opening 285 may include curved surfaces. A first layer 61 may be formed on or disposed on a portion 245 of the second circuit layer 24, and a second layer 62 may be formed on or disposed on the first layer 61. The material of the first layer 61 may be the same as the first metal material 51 of the pad layer 5 and may include nickel (Ni). The material of the second layer 62 may be the same as the second metal material 52 of the pad layer 5 and may include gold (Au). Furthermore, a plurality of solder balls 19 may be formed on or disposed on the second layer 62. Solder ball 19 may contain re-flowable material, such as tin-silver alloy (SnAg alloy).

[0053] In some embodiments, the linewidth / spacing of the first circuit layer 22 may be smaller than the linewidth / spacing of the second circuit layer 24. For example, the linewidth / spacing of the second circuit layer 24 may be greater than about 20 μm / about 20 μm or about 50 μm / about 50 μm. Therefore, the first circuit layer 22 can be used to electrically connect to a semiconductor chip and is referred to as the "chip side". The second circuit layer 24 can be used to mount to solder balls 19 for connection to a motherboard and is referred to as the "solder ball side".

[0054] The second circuit layer 24 can also be referred to as a "low-density redistribution layer". The first circuit layer 22 can also be referred to as a "high-density redistribution layer". It should be noted that the density of circuit lines (e.g., including traces or pads) in the high-density redistribution layer is greater than the density of circuit lines in the low-density redistribution layer. That is, the count of circuit lines (e.g., including traces or pads) in a unit area of ​​the high-density redistribution layer is greater than the count of circuit lines in the same unit area of ​​the low-density redistribution layer, for example, about 1.2 times or more, about 1.5 times or more, about 2 times or more, or about 5 times or more. Alternatively, or in combination with the above, the line width / spacing of the high-density redistribution layer is smaller than the line width / spacing of the low-density redistribution layer, for example, about 90% or less, about 50% or less, or about 20% or less.

[0055] Electronic component 12 may be disposed above the first protective layer 26 of substrate structure 2 and the first surface 201 of dielectric structure 20. Electronic component 12 may be a semiconductor device, such as a semiconductor die or semiconductor chip. Electronic component 12 may have a first surface 121 (e.g., a top surface or active surface), a second surface 122 (e.g., a bottom surface or back surface) opposite to the first surface 121, and a side surface extending between the first surface 121 and the second surface 122. The second surface 122 of electronic component 12 may be adhered to the first protective layer 26 of substrate structure 2 via an adhesive layer 13.

[0056] Electronic component 12 may include a plurality of electrical contacts 125. Electrical contacts 125 may be disposed adjacent to a first surface 121 (e.g., an active surface) of electronic component 12. Electrical contacts 125 may be exposed or protruding from the first surface 121 (e.g., an active surface) for electrical connection. Electrical contacts 125 may be pads, bumps, studs, pillars, or posts. In some embodiments, the electrical contacts 125 of electronic component 12 may be electrically connected and physically connected to a second metal material 52 of the pad layer 5 of substrate structure 2 via wires 4. In other words, electronic component 12 may be electrically connected to substrate structure 2 via wire bonding.

[0057] The at least one conductor 4 may include a plurality of conductors 4. Each conductor 4 may be a bonding wire. In some embodiments, the conductor 4 may physically and electrically connect the electronic component 12 to the substrate structure 2 and be configured to transmit signals. In some embodiments, the conductor 4 may connect the electrical contacts 125 of the electronic component 12 to the second metal material 52 of the pad layer 5 of the substrate structure 2 via a wire bonding process. Thus, the conductor 4 may be disposed on the pad layer 5. The material of the conductor 4 may include copper (Cu), gold (Au), aluminum (Al), or other suitable metal materials.

[0058] The conductor 4 may include a main portion 40, a first end portion 41, and a second end portion 42. The first end portion 41 may be a generally circular plate and may directly contact the second metal material 52 of the pad layer 5 of the substrate structure 2. The width of the first end portion 41 may be greater than the width of the main portion 40. The main portion 40 of the conductor 4 may be cylindrical and may pass through the opening 265 of the first protective layer 26. The main portion 40 of the conductor 4 may have a generally uniform width and may be curved. The second end portion 42 may be a tapered tip and may directly contact the electrical contact 125 of the electronic component 12. The main portion 40, the first end portion 41, and the second end portion 42 may be a single, integrally formed structure. Figure 2As shown, the first end portion 41 may have a center point 415. The first portion 221 of the first circuit layer 22 may have a center point 2215. The center point 415 of the first end portion 41 may be aligned vertically with the center point 2215 of the first portion 221 of the first circuit layer 22. In some embodiments, the wire 4 may be electrically connected and may be spaced or distanced from the first portion 221 (e.g., the first pad portion). The elevation of the bottom surface 43 of the wire 4 is higher than the elevation of the first surface 2211 (e.g., the top surface) of the first portion 221 (e.g., the first pad portion) of the first circuit layer 22.

[0059] like Figure 1 As shown, the package 14 can be formed on or disposed on the first protective layer 26 of the substrate structure 2. The package 14 can encapsulate the electronic component 12, the adhesive layer 13, and the wire 4. Furthermore, the package 14 can extend into the opening 265 of the first protective layer 26 to contact the first surface 201 of the dielectric structure 20 and the second metal material 52 of the pad layer 5. The first portion 221 of the first circuit layer 22 can be below the bottom surface of the package 14. The material of the package 14 can be a molding compound with or without fillers.

[0060] exist Figures 1 to 3 In the illustrated embodiment, the conductor 4 can be electrically connected to the first portion 221 of the first circuit layer 22 via a pad layer 5 (comprising a first metal material 51 and a second metal material 52). Since the maximum width W1 of the upper portion 512 of the first metal material 51 can be greater than the width W2 of the first portion 221 of the first circuit layer 22, the flat receiving area for receiving (or supporting) the first end portion 41 of the conductor 4 can be increased. That is, the pad layer 5 is configured to reduce the risk of the conductor 4 bonding to the first surface 201 of the dielectric structure 20 during the conductor bonding process. Thus, the bonding reliability between the first end portion 41 of the conductor 4 and the second metal material 52 of the pad layer 5 can be improved. Furthermore, the second metal material 52, such as gold, can enhance the bonding between the conductor 4 and the first metal material 51, such as nickel.

[0061] Figure 4This diagram shows a cross-sectional view of a first portion 221 of a first circuit layer 22 and a padding layer 5 according to some embodiments of the present disclosure. The top surface 2211 of the first portion 221 of the first circuit layer 22 may not be symmetrical. The right end of the top surface 2211 of the first portion 221 may be higher than the left end of the top surface 2211 of the first portion 221. Furthermore, the middle portion 5121 of the upper portion 512 of the first metal material 51 may have an inconsistent thickness. The generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51 may not be parallel to the first surface 201 of the dielectric structure 20. The dimensions of the right peripheral portion 5122 may differ from the dimensions of the left peripheral portion 5122. Furthermore, the second metal material 52 may have an inconsistent thickness.

[0062] Figure 5 This is a cross-sectional view of a portion of an electronic packaging structure 1a according to some embodiments of the present disclosure. Figure 6 for Figure 5 An enlarged view of region "C" in the image. Figure 7 for Figure 5 An enlarged view of region "D" in the image. Figures 5 to 7 The electronic packaging structure 1a shown is... Figures 1 to 3 The electronic package structure 1a is similar to the one shown, with the differences explained below. In the electronic package structure 1a, the first surface 2221 (e.g., the top surface) of the second portion 222 of the first circuit layer 22 can be a generally flat surface. The first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22 can be a generally flat surface. Figure 6 As shown, the generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51 can be generally parallel to the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22. The width W3 of the generally flat top surface 5123 of the middle portion 5121 of the upper portion 512 of the first metal material 51 can be greater than the width W2 of the first portion 221 of the first circuit layer 22. Furthermore, the generally flat top surface 521 of the second metal material 52 (i.e., the generally flat top surface 521 of the padding layer 5) can be generally parallel to the first surface 2211 (e.g., the top surface) of the first portion 221 of the first circuit layer 22. The width W4 of the generally flat top surface 521 of the second metal material 52 (i.e., the generally flat top surface 521 of the padding layer 5) can be greater than the width W2 of the first portion 221 of the first circuit layer 22. Therefore, the pad layer 5 can have a generally flat top surface 521. The width W4 of the generally flat top surface 521 of the pad layer 5 can be greater than the width W2 of the first portion 221 of the first circuit layer 22 (e.g., the first pad portion).

[0063] like Figure 6 As shown, the flat top surface 521 of the pad layer 5 may include a peripheral portion 5211 extending beyond the side surface 2213 (e.g., edge) of the first portion 221 (e.g., the first pad portion) of the first circuit layer 22. The peripheral portion 5211 of the flat top surface 521 of the pad layer 5 may be configured to increase the area of ​​the flat top surface 521 of the pad layer 5 to receive (or support) the conductor 4. The peripheral portion 5211 of the flat top surface 521 of the pad layer 5 may be configured to reduce delamination between the conductor 4 and the dielectric layer 20 caused by misalignment or misalignment between the center point 415 of the first end portion 41 of the conductor 4 and the center point 2215 of the first portion 221 (e.g., the first pad portion) of the first circuit layer 22 during the conductor bonding process. It should be noted that if the first end portion 41 of the conductor 4 is bonded to the first surface 201 (e.g., the top surface) of the dielectric structure 20 (e.g., the dielectric layer), delamination may easily occur between the conductor 4 and the dielectric layer 20 due to the relatively low bonding strength between the conductor 4 and the dielectric layer 20. In some embodiments, the pad height 5 may be configured to prevent the first end portion 41 of the conductor 4 from contacting the first surface 201 (e.g., the top surface) of the dielectric structure 20 (e.g., the dielectric layer) during the conductor bonding process. In some embodiments, the pad height 5 may be configured to provide a flat receiving area (i.e., a generally flat top surface 521) of the top surface 2211 of the first portion 221 (e.g., the first pad portion) not smaller than the area of ​​the top surface 2211 of the first portion 221 (e.g., the first pad portion) during the conductor bonding process to receive (or support) the conductor 4.

[0064] Figure 7A This is an enlarged cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure. Figure 7A The structure shown is similar to Figure 6 The structures shown are similar, except that the position of the first end portion 41 of the conductor 4 is different. For example... Figure 7A As shown, even if the center point 415 of the first end portion 41 of the conductor 4 is slightly misaligned with the center point 2215 of the first portion 221 (e.g., the first pad portion) of the first circuit layer 22 during the conductor bonding process, the entire first end portion 41 of the conductor 4 can still be positioned on the generally flat top surface 521 of the pad layer 5 due to the surrounding portion 5211 of the flat top surface 521 of the pad layer 5. Therefore, reliable bonding between the first end portion 41 of the conductor 4 and the second metal material 52 of the pad layer 5 can be ensured.

[0065] Furthermore, the padding layer 5 may include a lower portion 5a and an upper portion 5b located on the lower portion 5a. The lower portion 5a of the padding layer 5 may be a lower portion 511 of a first metal material 51, positioned below the first surface 201 (e.g., top surface) of the dielectric structure 20 (e.g., dielectric layer). The upper portion 5b of the padding layer 5 may include an upper portion 512 of the first metal material 51 and a second metal material 52. The width W1 of the upper portion 5b of the padding layer 5 may be greater than the width W2 of the first portion 221 (e.g., first pad portion) of the first circuit layer 22. The thickness T1 of the lower portion 5a of the padding layer 5 may be less than the thickness T2 of the upper portion 5b of the padding layer 5. Figure 7A As shown, the upper portion 5b of the padding layer 5 may include a peripheral portion 5c. The peripheral portion 5c of the padding layer 5 may include a peripheral portion 5122 of the upper portion 512 of the first metal material 51, and a portion of the second metal material 52 located on the peripheral portion 5122. The peripheral portion 5c of the padding layer 5 may taper outwards. That is, the peripheral portion 5c of the padding layer 5 may taper away from the center of the upper portion 5b. Furthermore, the peripheral portion 5c of the padding layer 5 may gradually narrow upwards (taper upwards). That is, the peripheral portion 5c of the padding layer 5 may taper away from the first surface 201 of the dielectric structure 20.

[0066] Figure 7B This is an enlarged cross-sectional view of a portion of an electronic packaging structure according to some embodiments of the present disclosure. Figure 7B The structure shown is similar to Figure 7A The structure shown is similar, the difference being the position of the first end portion 41 of the conductor 4. For example... Figure 7B As shown, during the wire bonding process, the center point 415 of the first end portion 41 of the wire 4 is severely misaligned with the center point 2215 of the first portion 221 (e.g., the first pad portion) of the first circuit layer 22.

[0067] The first end portion 41 of the conductor 4 may include a first portion 411 and a second portion 412. The first portion 411 may extend beyond the flat top surface 521 of the padding layer 5 and may contact the side surface 522 of the padding layer 5. The first portion 411 of the conductor 4 may partially cover the side surface 522 of the padding layer 5. That is, the first portion 411 of the conductor 4 may cover and contact a portion of the side surface 522 of the padding layer 5, while another portion of the side surface 522 of the padding layer 5 may be exposed by the first portion 411 of the conductor 4. The first portion 411 of the conductor 4 may not cover and contact the first surface 201 (e.g., top surface) of the dielectric structure 20 (e.g., dielectric layer). The second portion 412 may be disposed on the flat top surface 521 of the padding layer 5. The horizontal width W5 of the first portion 411 of the first end portion 41 of the conductor 4 may be greater than the horizontal width W6 of the second portion 412 of the first end portion 41 of the conductor 4. Therefore, reliable bonding between the first end portion 41 of the conductor 4 and the second metal material 52 of the padding layer 5 can be ensured.

[0068] In a comparative embodiment, the bonding pad may protrude from the top surface of the dielectric structure. The bonding pad may be trapezoidal after the etching process. The area of ​​the top surface (i.e., the bonding surface) of the bonding pad is smaller than the area of ​​the bottom surface. A sloping side extends between the top and bottom surfaces. During the bonding process, because the top surface (i.e., the bonding surface) is relatively small, the end portion of the conductor will easily contact the sloping side as it moves downwards. Since the direction of conductor movement is not orthogonal to the sloping side, the end portion of the conductor will slide on the sloping side and be guided to contact the top surface of the dielectric structure. Therefore, due to the relatively low bonding strength between the conductor and the dielectric structure, delamination is likely to occur between the conductor and the dielectric structure.

[0069] Figure 8 This is a cross-sectional view of a portion of an electronic packaging structure 1b according to some embodiments of the present disclosure. Figure 9 for Figure 8 An enlarged view of region "E" in the image. Figure 8 and Figure 9 The electronic packaging structure 1b shown is... Figures 1 to 3 The electronic packaging structure 1b is similar to the one shown, but the differences are explained below. In the electronic packaging structure 1b, the wire 4b may include a main portion 40b, a first end portion 41b, and a second end portion 42b. Figure 8 and Figure 9 The main part 40b and the second end part 42b of the middle conductor 4b can be connected with Figures 1 to 3The main portion 40 and the second end portion 42 of the middle conductor 4 are identical. The center point 415 of the first end portion 41b may be misaligned, misplaced, or displaced in the vertical direction from the center point 2215 of the first portion 221 of the first circuit layer 22. Due to the material and structure of the padding layer 5 (containing the first metal material 51 and the second metal material 52), the joint between the second metal material 52 of the padding layer 5 and the first end portion 41b can still be ensured to be firm.

[0070] In some embodiments, a portion 411b of the first end portion 41b of the conductor 4b may contact the first surface 201 of the dielectric structure 20 of the substrate structure 2. Therefore, the portion 411b of the conductor 4b may overlap with the upper portion 512 of the first metal material 51 of the pad layer 5 in a direction parallel to the first surface 201 (e.g., the top surface) of the dielectric structure 20 (e.g., the dielectric layer). Furthermore, the spacing P1 between the conductors 4b may be different from (e.g., less than or greater than) the spacing P2 between the first portions 221 of the first circuit layer 22. Spacing P1 may be defined as the distance between the two center points 415 of two adjacent first end portions 41b of the conductor 4b. Spacing P2 may be defined as the distance between the two center points 2215 of the two first portions 221 of the first circuit layer 22. Therefore, the spacing P1 of the conductors 4b may be different from (e.g., less than or greater than) the spacing P2 of the first portions 221 of the first circuit layer 22.

[0071] like Figure 9 As shown, in the cross-section, the width W7 of the contact surface 44 between the first end portion 41b of the conductor 4b and the first surface 201 (e.g., top surface) of the dielectric structure 20 (e.g., dielectric layer) can be smaller than the width W8 of the contact surface 45 between the first end portion 41b of the conductor 4b and the flat top surface 521 of the padding layer 5.

[0072] Figure 10 This is a cross-sectional view of a portion of an electronic packaging structure 1c according to some embodiments of the present disclosure. Figure 10 The electronic packaging structure 1c shown is Figures 1 to 3The electronic package structure 1 shown is similar, with the differences described below. In the electronic package structure 1c, the wire 4c may include a main portion 40c, a first end portion 41c, and a second end portion 42c. The first end portion 41c may be a tapered tip and may directly contact the second metal material 52 of the pad layer 5. The main portion 40c of the wire 4c may be cylindrical and may pass through the opening 265 of the first protective layer 26. The main portion 40c of the wire 4c may have a generally uniform width and may be curved. The second end portion 42c may be a generally circular plate and may directly contact the electrical contact 125 of the electronic component 12. The width of the second end portion 42c may be greater than the width of the main portion 40c.

[0073] Figures 11 to 22 This is a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture, for example,... Figures 1 to 3 The electronic packaging structure 1 is shown.

[0074] refer to Figure 11 A carrier 70 and a metal foil 72 are provided. The metal foil 72 can be disposed on the surface of the carrier 70. Although the manufacturing process is shown to be performed on one side of the carrier 70, it is understood that the manufacturing process can also be performed on the other side of the carrier 70 in a similar manner. For example, the manufacturing process can be performed on both sides of the carrier 70.

[0075] The first circuit layer 22 can then be formed on or disposed on the metal foil 72, for example, by electroplating. The material of the first circuit layer 22 can be a conductive metal, such as copper. In some embodiments, the first circuit layer 22 may include a first portion 221 (e.g., a portion of a bonding pad or trace) and a second portion 222 (e.g., a portion of a bonding pad or trace). The first portion 221 of the first circuit layer 22 may have a first surface 2211 (e.g., a top surface), a second surface 2212 (e.g., a bottom surface) opposite the first surface 2211, and a side surface 2213 extending between the first surface 2211 and the second surface 2212.

[0076] The second portion 222 of the first circuit layer 22 may have a first surface 2221 (e.g., a top surface), a second surface 2222 (e.g., a bottom surface) opposite the first surface 2221, and a side surface 2223 extending between the first surface 2221 and the second surface 2222. The side surface 2213 of the first portion 221 and the side surface 2223 of the second portion 222 may be treated with brown oxide to enhance the dielectric structure 20 (e.g., Figure 12As shown in the figure, the surface roughness value of the side surface 2213 of the first part 221 can be in the range of about 0.25 μm to about 0.5 μm, and the surface roughness value of the side surface 2223 of the second part 222 can be in the range of about 0.25 μm to about 0.5 μm.

[0077] refer to Figure 12 The dielectric structure 20 may be formed on or disposed (e.g., stacked or laminated) on the metal foil 72 to cover the first circuit layer 22. The dielectric structure 20 may have a first surface 201 and a second surface 202 opposite to the first surface 201. A plurality of openings 204 may then be formed on the second surface 202 of the dielectric structure 20 to expose a portion of the second surface 2222 of the second portion 222 of the first circuit layer 22. A seed layer 74 may then be formed on or disposed on the second surface 202 and the openings 204 of the dielectric structure 20.

[0078] refer to Figure 13 The conductive material 76 can be formed on or disposed on the seed layer 74. Therefore, the conductive material 76 can be formed on or disposed on the second surface 202 and the opening 204 of the dielectric structure 20. Next, the conductive material 76 and the seed layer 74 can be patterned to form a second circuit layer 24 and at least one internal via 23.

[0079] refer to Figure 14 The carrier 70 can be removed from the metal foil 72.

[0080] refer to Figure 15The metal foil 72 can be removed, for example, by etching. Therefore, a portion (e.g., the top surface) of the first circuit layer 22 can be exposed from the first surface 201 of the dielectric structure 20. In some embodiments, the top surface of the first circuit layer 22 can be over-etched, so that the first circuit layer 22 can be recessed from the first surface 201 of the dielectric structure 20. For example, a second portion 222 of the first circuit layer 22 can be recessed from the first surface 201 of the dielectric structure 20, and a second distance D2 can be formed between the first surface 2221 of the second portion 222 and the first surface 201 of the dielectric structure 20, thereby forming a recessed portion 206 located above the first surface 2221 of the second portion 222 and below the first surface 201 of the dielectric structure 20. Furthermore, a first portion 221 of the first circuit layer 22 may be recessed from the first surface 201 of the dielectric structure 20, and a third distance D3 may be formed between the first surface 2211 of the first portion 221 and the first surface 201 of the dielectric structure 20, thereby forming a recessed portion 205', which is located above the first surface 2211 of the first portion 221 and below the first surface 201 of the dielectric structure 20. The third distance D3 may be approximately equal to the second distance D2.

[0081] refer to Figure 16 A first protective layer 26 may be formed on or disposed on a first surface 201 of the dielectric structure 20 and may define at least one opening 265 to expose a recessed portion 205'. The first protective layer 26 may extend to the recessed portion 206 to cover and contact a first surface 2221 (e.g., a top surface) of a second portion 222 of the first circuit layer 22. A second protective layer 28 may be formed on or disposed on a second surface 202 of the dielectric structure 20 and may cover the second circuit layer 24. The second protective layer 28 may define at least one opening 285 to expose a portion 245 of the second circuit layer 24.

[0082] refer to Figure 17 A pre-processing procedure can be performed to further etch the first portion 221 of the first circuit layer 22. A first distance D1 can be formed between the first surface 2211 of the first portion 221 and the first surface 201 of the dielectric structure 20, thereby forming a recessed portion 205, which is located above the first surface 2211 of the first portion 221 and below the first surface 201 of the dielectric structure 20. The first distance D1 can be greater than a third distance D3. Therefore, the recessed portion 205 can be deeper than the recessed portion 205'.

[0083] refer to Figure 18The padding layer 5 may be formed on or disposed on the recessed portion 205 and the first portion 221 of the first circuit layer 22. The padding layer 5 may include a first metal material 51 and a second metal material 52. The first metal material 51 may be formed on or disposed on the recessed portion 205 and may extend beyond the first surface 201 of the dielectric structure 20. The first metal material 51 may include nickel (Ni) and may be formed by a deposition process, such as an electroless nickel immersion gold process, or an electroless nickel / electroless palladium / immersion gold process. The second metal material 52 may then be conformally formed on or disposed on the first metal material 51. The second metal material 52 may be a metal layer having a substantially uniform thickness. The second metal material 52 may be formed on or disposed over the entire top surface of the first metal material 51 and may contact the first surface 201 of the dielectric structure 20. The second metal material 52 may include gold (Au) and may be formed by a deposition process, such as an electroless nickel immersion gold process, or an electroless nickel / electroless palladium / immersion gold process.

[0084] Furthermore, the first layer 61 may be formed on or disposed on a portion 245 of the second circuit layer 24, and the second layer 62 may be formed on or disposed on the first layer 61. The material of the first layer 61 may be the same as the first metal material 51 of the pad layer 5, and may include nickel (Ni). The material of the second layer 62 may be the same as the second metal material 52 of the pad layer 5, and may include gold (Au). At this time, the substrate structure 2 can be formed.

[0085] refer to Figure 19 Electronic component 12 may be disposed above the first protective layer 26 of substrate structure 2. Electronic component 12 may have a first surface 121 (e.g., a top surface or active surface), a second surface 122 (e.g., a bottom surface or back surface) opposite the first surface 121, and a side surface extending between the first surface 121 and the second surface 122. The second surface 122 of electronic component 12 may be adhered to the first protective layer 26 of substrate structure 2 via an adhesive layer 13. Electronic component 12 may include a plurality of electrical contacts 125. Electrical contacts 125 may be disposed adjacent to the first surface 121 (e.g., the active surface) of electronic component 12.

[0086] refer to Figure 20Multiple wires 4 can be formed or disposed to electrically connect the electrical contacts 125 of the electronic component 12 to the second metal material 52 of the pad layer 5 of the substrate structure 2. In other words, the electronic component 12 can be electrically connected to the substrate structure 2 via wire bonding. Each of the wires 4 can be a bonding wire. The material of the wires 4 can include copper (Cu), gold (Au), aluminum (Al), or other suitable metal materials. The wire 4 can include a main portion 40, a first end portion 41, and a second end portion 42. The first end portion 41 can be generally circular and can directly contact the second metal material 52 of the pad layer 5 of the substrate structure 2. The width of the first end portion 41 can be greater than the width of the main portion 40. The main portion 40 of the wire 4 can be cylindrical and can pass through the opening 265 of the first protective layer 26. The main portion 40 of the wire 4 can have a generally uniform width and can be curved. The second end portion 42 can be a tapered tip and can directly contact the electrical contacts 125 of the electronic component 12.

[0087] refer to Figure 21 The package 14 can be formed on or disposed on the first protective layer 26 of the substrate structure 2. The package 14 can encapsulate the electronic component 12, the adhesive layer 13, and the wire 4. Furthermore, the package 14 can extend into the opening 265 of the first protective layer 26 to contact the first surface 201 of the dielectric structure 20 and the second metal material 52 of the pad layer 5. The material of the package 14 can be a molding material with or without fillers.

[0088] refer to Figure 22 Multiple solder balls 19 may be formed on or disposed on the second layer 62. The solder balls 19 may contain a resolderable material, such as a tin-silver alloy.

[0089] Next, a monomerization process can be performed to obtain Figures 1 to 3 The multiple electronic packaging structures shown are 1.

[0090] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0091] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered “generally” the same as or equal to the second numerical value. For example, "roughly" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0092] If the displacement between two surfaces is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces are considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface is considered substantially flat.

[0093] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include a plural or multiple indicators.

[0094] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0095] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0096] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

[0097] Figure Labels

[0098] 1 Electronic Packaging Structure

[0099] 1a Electronic Packaging Structure

[0100] 1b electronic packaging structure

[0101] 1C electronic packaging structure

[0102] 2. Substrate Structure

[0103] 4 wires

[0104] 4b wire

[0105] 4C wire

[0106] 5. High-rise building

[0107] 5a lower part

[0108] 5b upper part

[0109] 5c surrounding area

[0110] 12 electronic components

[0111] 13 Adhesive Layer

[0112] 14-package

[0113] 19 solder balls

[0114] 20 Dielectric Structure

[0115] 22 First Circuit Layer

[0116] 23 Internal through holes

[0117] 24 Second Circuit Layer

[0118] 26 First protective layer

[0119] 28 Second protective layer

[0120] 40 main parts

[0121] 40b main part

[0122] 40c main parts

[0123] 41 First end part

[0124] 41b First end portion

[0125] 41c First end portion

[0126] 42 Second end portion

[0127] 42b second end portion

[0128] 42c second end portion

[0129] 43 bottom

[0130] 44 contact surfaces

[0131] 45 contact surface

[0132] 51 First Metal Materials

[0133] 52 Second Metal Materials

[0134] 61 First Floor

[0135] 62 Second layer

[0136] 70 carriers

[0137] 72 metal foil

[0138] 74 seed layers

[0139] 76 Conductive Materials

[0140] 121 First Surface

[0141] 122 Second Surface

[0142] 125 electrical contacts

[0143] 201 First Surface

[0144] 202 Second Surface

[0145] 204 opening

[0146] 205 recessed portion

[0147] 205' recessed portion

[0148] 206 recessed portion

[0149] 221 Part 1

[0150] 222 Part Two

[0151] 233 seed layer

[0152] 234 conductive metal

[0153] 243 seed layer

[0154] 244 conductive metal

[0155] Part 245

[0156] 265 opening

[0157] 285 opening

[0158] 411 Part 1

[0159] Part 411b

[0160] 412 Part Two

[0161] 415 center point

[0162] 511 lower part

[0163] 512 Upper Part

[0164] 521 Top Surface

[0165] 522 side view

[0166] 2211 First Surface

[0167] 2212 Second Surface

[0168] 2213 side view

[0169] 2214 Lowest point

[0170] 2215 center point

[0171] 2221 First Surface

[0172] 2222 Second Surface

[0173] 2223 Side View

[0174] 2224 Lowest point

[0175] 5121 Middle Part

[0176] 5122 surrounding area

[0177] 5123 Top Surface

[0178] 5124 side view

[0179] 5211 surrounding area

[0180] D1 First Distance

[0181] D2 Second Distance

[0182] D3 Third Distance

[0183] P1 Spacing

[0184] P2 spacing

[0185] T1 thickness

[0186] T2 thickness

[0187] W1 width

[0188] W2 width

[0189] W3 width

[0190] W4 width

[0191] W5 horizontal width

[0192] W6 Horizontal Width

[0193] W7 width

[0194] W8 width.

Claims

1. An electronic packaging structure, comprising: Substrate structure, comprising: The circuit layer includes pad portions; A dielectric layer covers the circuit layer and defines an opening to expose the top surface of the pad portion, wherein the elevation of the top surface of the pad portion is lower than the elevation of the top surface of the dielectric layer. as well as A padding layer is disposed on the pad portion of the circuit layer and extends beyond the top surface of the dielectric layer; as well as The conductor is placed on the raised floor.

2. The electronic packaging structure according to claim 1, wherein in cross-section, the width of the upper portion of the pad layer is greater than the width of the pad portion of the circuit layer.

3. The electronic packaging structure according to claim 2, wherein the pad layer has a flat top surface, wherein in cross-section, the width of the flat top surface of the pad layer is greater than the width of the pad portion of the circuit layer.

4. The electronic packaging structure of claim 3, wherein the flat top surface of the pad layer includes a peripheral portion extending beyond the side of the pad portion of the circuit layer and configured to increase the area of ​​the flat top surface of the pad layer to support the conductor.

5. The electronic packaging structure of claim 3, wherein the conductor comprises a first portion and a second portion, the first portion extending beyond the flat top surface of the pad layer, the second portion being disposed on the flat top surface of the pad layer, wherein the horizontal width of the first portion of the conductor is greater than the horizontal width of the second portion of the conductor.

6. The electronic packaging structure of claim 5, wherein the first portion of the wire partially covers the side of the pad layer.

7. The electronic packaging structure of claim 5, wherein the first portion of the conductor does not contact the top surface of the dielectric layer.

8. The electronic packaging structure of claim 1, wherein the pad layer comprises a first metal material and a second metal material located between the first metal material and the conductor, wherein the second metal material is configured to enhance the bonding strength between the conductor and the pad layer.

9. The electronic packaging structure according to claim 8, wherein the second metal material covers the top surface of the first metal material and the side surface of the first metal material.

10. The electronic packaging structure of claim 1, wherein the pad layer comprises a lower portion and an upper portion, the lower portion being lower than the top surface of the dielectric layer, the upper portion being disposed above the lower portion, wherein the thickness of the lower portion of the pad layer is less than the thickness of the upper portion of the pad layer.

11. The electronic packaging structure of claim 10, wherein the upper portion of the pad layer includes a surrounding portion that tapers outward or upward.

12. The electronic packaging structure according to claim 1, wherein the rigidity of the pad layer is greater than the rigidity of the pad portion of the circuit layer.

13. An electronic packaging structure, comprising: The circuit layer includes the pad portion; A dielectric layer, covering the circuit layer, and defining an opening to expose the top surface of the pad portion, wherein the top surface of the pad portion is lower than the top surface of the dielectric layer; and A padding layer is placed on the pad portion of the circuit layer and arranged to reduce delamination between the conductor and the dielectric layer due to misalignment between the conductor and the pad portion of the circuit layer during the conductor bonding process.

14. The electronic packaging structure of claim 13, wherein a portion of the conductive wire overlaps the pad layer in a direction parallel to the top surface of the dielectric layer.

15. The electronic packaging structure of claim 14, wherein, in cross-section, the width of the contact surface between the conductor and the dielectric layer is less than the width of the contact surface between the conductor and the flat top surface of the padding layer.

16. The electronic packaging structure according to claim 13, wherein the top surface of the pad portion of the circuit layer is concave.

17. The electronic packaging structure according to claim 13, wherein the surface roughness of the top surface of the pad portion of the circuit layer is less than the surface roughness of the top surface of the second pad portion of the circuit layer.

18. The electronic packaging structure according to claim 13, further comprising: A protective layer is disposed on the top surface of the dielectric layer and defines an opening to expose the padding layer, wherein the padding layer is spaced apart from the protective layer, wherein the upper portion of the opening tapers away from the dielectric layer and the lower portion of the opening tapers toward the dielectric layer.

19. An electronic packaging structure, comprising: Substrate structure, comprising: The circuit layer includes the pad portion; and A dielectric layer, covering the circuit layer, and defining an opening to expose the top surface of the pad portion, wherein the top surface of the pad portion is lower than the top surface of the dielectric layer; and A conductor is electrically connected to the pad portion and located away from the pad portion, wherein the elevation of the bottom surface of the conductor is higher than the elevation of the top surface of the pad portion.

20. The electronic packaging structure of claim 19, wherein the circuit layer further includes a second pad portion, the dielectric layer further defines a second opening to expose the second pad portion, and wherein the substrate structure further includes: A protective layer is disposed on the top surface of the dielectric layer and covers the second pad portion, wherein the pad portion is spaced apart from the protective layer.

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