A quantum wiring architecture with phase space time division multiplexing and methods of making the same

Abstract

The application provides a phase space time division multiplexing quantum wiring architecture and a preparation method thereof, and relates to the technical field of semiconductors, and comprises: an alumina ceramic substrate, a plurality of signal source modules, a phase space reconstruction time sequence controller and a main chip are connected on the alumina ceramic substrate; output ends of the plurality of signal source modules are all connected to a shared transmission conductor formed by the same pad; the application compresses multiple quantum control signals to a single shared transmission conductor for parallel transmission by using the principle of phase space time division multiplexing, improves wiring density, reduces the number of packaging layers and physical lines, thereby simplifying the process flow and reducing the process difficulty.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a phase-space time-division multiplexing quantum wiring architecture and its fabrication method. Background Technology

[0002] The continuous expansion of the integration scale of quantum computing chips has led to a sharp increase in the number of qubits. In the existing packaging structure, each qubit needs to be independently configured with microwave control circuits and signal readout circuits. This independent wiring method causes the number of circuits to increase exponentially with the increase in the number of bits.

[0003] In the existing technology, the current packaging is limited to the wiring in a three-dimensional physical space. The large number of densely arranged lines cause physical space congestion and force the number of redistribution layers to increase continuously. At the same time, near-field electromagnetic crosstalk is easily generated between dense parallel lines, and the process limitations of multi-layer wiring cause the number of packaging layers to reach a physical bottleneck, making it impossible to meet the mass production requirements of hundreds of bits or thousands of bits of quantum chips. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a phase-space time-division multiplexing quantum wiring architecture and its fabrication method. This architecture transforms the time dimension into a geometric degree of freedom, replacing multiple independent lines with a single physical wire in physical space. By utilizing the dynamic coding interval on the time axis, multiple control pulses form non-overlapping orthogonal geometric trajectories in the six-dimensional phase space. Combined with a grounded closed cavity composed of a copper-nickel alloy electromagnetic shielding layer, internal radiation and external field interference are suppressed, thereby achieving high-density, low-crosstalk quantum signal transmission without increasing the number of lines and layers.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a phase-space time-division multiplexing quantum wiring architecture, comprising: an alumina ceramic substrate, wherein pads are provided on the alumina ceramic substrate, a transition conductive layer is provided between the alumina ceramic substrate and the pads, and a copper ground layer is connected to one side of the pads; characterized in that a plurality of signal source modules, a phase-space reconstruction timing controller, and a main chip are connected to the pads; the output terminals of the plurality of signal source modules are all connected to a shared transmission line formed by the same pads; The main chip is connected to a microwave interface, and the microwave interface is connected to a microwave coupling interface; the pads, signal source module, timing controller and main chip are provided with a polyimide insulating dielectric layer, and the surfaces of the polyimide insulating dielectric layer, copper ground layer, sintering point and grounding conductor pin are all provided with a sputtered titanium copper layer, and the surface of the sputtered titanium copper layer is provided with a copper nickel alloy electromagnetic shielding layer.

[0006] Furthermore, the phase space reconstruction timing controller is located on the transmission path between the signal source module and the main chip, and is used to set a preset dynamic encoding time interval for the multi-channel quantum control pulses output by the plurality of signal source modules; based on the dynamic encoding time interval, the multi-channel control pulses form mutually orthogonal geometric trajectories in the six-dimensional phase space geometric model composed of spatial position and time derivative, and are transmitted to the corresponding target qubit inside the main chip through the shared transmission wire.

[0007] Furthermore, one side of the pad is provided with an electrical interconnect pin, which is connected to an electrical interconnect solder joint; the copper ground layer is connected to a grounding conductor pin through a sintering point, and the copper ground layer is fixed to one side of the alumina ceramic substrate; sealant is provided at the connection points of the electrical interconnect pin and the electrical interconnect solder joint, and at the connection points of the microwave interface and the microwave coupling interface.

[0008] Furthermore, it also includes an epoxy encapsulation layer that wraps the entire architecture, with the ends of the electrical interconnect solder joints, grounding pins, and microwave coupling interfaces extending out of the epoxy encapsulation layer.

[0009] A method for fabricating a phase-space time-division multiplexing quantum wiring architecture includes the following steps: Step S1: Prepare an alumina ceramic substrate, and prepare a copper grounding layer, sintering point and grounding pin on the alumina ceramic substrate to obtain an integrated substrate of ceramic substrate and grounding pin; Step S2: Prepare pads, a transition conductive layer, and electrical interconnect pins, and connect the pads to the copper ground layer for conduction; the pads are configured as a single shared transmission line structure for multiple signals to be shared, to obtain a ceramic wiring substrate containing a shared line; Step S3: Using a vacuum nozzle, the main chip is precisely aligned and mounted on the pad. Eutectic solder is used to fix the chip to the pad, forming electrical coupling. A microwave interface is fabricated on the main chip. The microwave interface is used for subsequent signal docking with the microwave coupling interface, resulting in a chip mounting and microwave interface coupling semi-finished product. Step S4: Mount a plurality of signal source modules and a phase space reconstruction timing controller patch on the pads. Connect the output terminals of the plurality of signal source modules to a single shared transmission line formed by the pads. Simultaneously, electrically connect the phase space reconstruction timing controller to the plurality of signal source modules, enabling the phase space reconstruction timing controller to set a dynamic encoding time interval for multiple control pulses, thereby obtaining a wiring integrated component with phase space timing control function. The dynamic encoding time interval set by the phase space reconstruction timing controller is 15~20ns. After fabrication, the transmission efficiency of multiple quantum signals in the single shared transmission line is ≥99%, and the inter-channel electromagnetic crosstalk is ≤-60dB. Step S5: A polyimide insulating dielectric layer, a sputtered titanium-copper layer, and a copper-nickel alloy electromagnetic shielding layer are sequentially prepared on top of the wiring integration component with phase space timing control function to obtain a multi-layer electromagnetic shielding packaged semi-finished product. Step S6: Prepare a sealant to seal and protect the connection between the electrical interconnection weld and the microwave coupling interface, and obtain a semi-finished interface sealing and protection product; Step S7: Prepare an epoxy molding layer to cover the entire structure except for the interface terminals, and expose the terminals of the electrical interconnect solder joint, grounding pin, and microwave coupling interface to obtain an epoxy-molded integrated quantum wiring package.

[0010] Furthermore, in step S1, the thickness of the alumina ceramic substrate is 0.8~1.2mm, and after preparation, the total grounding resistance of the alumina ceramic substrate and the grounding conductor pin is ≤0.1Ω.

[0011] Furthermore, in step S5, the sputtered titanium-copper layer is formed sequentially by a sputtering process to create a titanium adhesion layer and a copper conductive seed layer; the copper-nickel alloy electromagnetic shielding layer is formed by an electroplating process, with a copper-nickel ratio of 80:20, a shielding layer thickness of 5~10μm, and a shielding effectiveness ≥80dB in the 10~3000MHz frequency band; the copper-nickel alloy electromagnetic shielding layer is seamlessly electrically connected to the grounding conductor pin.

[0012] Furthermore, in step S6, the sealant is a high-temperature resistant sealant with a temperature resistance of ≥150℃, and after step S6 is completed, the overall protection level of the interface reaches IP67.

[0013] Furthermore, in step S7, the thickness of the epoxy encapsulation layer is 0.8~1.2mm, and the epoxy encapsulation layer is tightly bonded to the alumina ceramic substrate without delamination or peeling.

[0014] Compared with the prior art, the advantages and positive effects of the present invention are as follows: This invention utilizes the phase-space time-division multiplexing principle to compress multiple quantum control signals into a single shared transmission wire for parallel transmission, increasing wiring density and reducing the number of packaging layers and physical lines, thereby simplifying the process and reducing manufacturing difficulty. At the same time, the mutually orthogonal trajectories constructed based on the six-dimensional phase-space geometric model physically eliminate electromagnetic crosstalk between multiple signals. The copper-nickel alloy electromagnetic shielding layer forms a closed cavity that seamlessly connects with the grounding pin, effectively suppressing internal radiation and external high-frequency interference, achieving high signal transmission efficiency and low channel crosstalk. Attached Figure Description

[0015] Figure 1This is a flowchart illustrating a method for fabricating a phase-space time-division multiplexing quantum wiring architecture according to the present invention; Figure 2 This is a schematic diagram of a phase-space time-division multiplexing quantum wiring architecture according to the present invention; Figure 3 This is a schematic diagram of the integrated ceramic substrate and grounding pin substrate obtained in step S1 of the preparation method of a phase space time-division multiplexing quantum wiring architecture of the present invention. Figure 4 This is a schematic diagram of the structure of the ceramic wiring substrate containing shared wires obtained in step S2 of the preparation method of the phase space time-division multiplexing quantum wiring architecture of the present invention. Figure 5 This is a schematic diagram of the structure of the chip mounting and microwave interface coupling semi-finished product obtained in step S3 of the preparation method of the phase space time division multiplexing quantum wiring architecture of the present invention. Figure 6 The images show the front and top views of the wiring integration component with phase space timing control function obtained in step S4 of the preparation method of a phase space time-division multiplexing quantum wiring architecture of the present invention. Figure 7 This is a schematic diagram of the structure of the multilayer electromagnetic shielding packaged semi-finished product obtained in step S5 of the preparation method of a phase space time-division multiplexing quantum wiring architecture of the present invention. Figure 8 This is a schematic diagram of the interface sealing and protection semi-finished product obtained in step S6 of the preparation method of a phase space time-division multiplexing quantum wiring architecture of the present invention. Figure 9 This is a schematic diagram of the epoxy-encapsulated integrated quantum wiring package obtained in step S7 of the preparation method of a phase space time-division multiplexing quantum wiring architecture of the present invention.

[0016] Figure label: 1. Alumina ceramic substrate; 2. Pads; 3. Transition conductive layer; 4. Electrical interconnect pins; 5. Electrical interconnect solder joints; 6. Copper grounding layer; 7. Sintering point; 8. Grounding pin; 9. Signal source module; 10. Phase space reconstruction timing controller; 11. Main chip; 12. Microwave interface; 13. Microwave coupling interface; 14. Sealant; 15. Polyimide insulating dielectric layer; 16. Sputtered titanium-copper layer; 17. Copper-nickel alloy electromagnetic shielding layer; 18. Epoxy encapsulation layer. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0018] like Figure 2 As shown, this invention provides a technical solution: a phase-space time-division multiplexing quantum wiring architecture, comprising: an alumina ceramic substrate 1, pads 2 on the alumina ceramic substrate 1, a transition conductive layer 3 between the alumina ceramic substrate 1 and the pads 2, and a copper ground layer 6 connected to one side of the pads 2; in this design, the alumina ceramic substrate 1, as the overall load-bearing structure, is made of highly thermally conductive alumina ceramic material, providing a heat dissipation path and mechanical support foundation; the pads 2, as conductive metal layers, undertake the transmission function of multiple quantum control signals, and the pads 2 are configured as a single shared transmission wire structure to achieve collinear transmission of multiple signals in a single physical channel, reducing the friction between the metal pads and the ceramic substrate. The interface stress caused by the difference in thermal expansion coefficients between the metal pads and the ceramic substrate is reduced, and the adhesion strength of the metal layer on the alumina ceramic surface is enhanced. The transition conductive layer 3 serves as an intermediate functional layer, buffering the thermomechanical stress and promoting a stable bond between the metal pads and the ceramic substrate. The copper ground layer 6 is arranged on the side area of ​​the ceramic substrate, and through physical connection, the electrical signal on the pad 2 can extend to the outer edge of the ceramic substrate via the copper ground layer 6, connecting to the external grounding structure or signal transmission interface, thus forming a complete conductive path between the pad 2 and the copper ground layer 6. The arrangement of the copper ground layer 6 corresponds to the edge area of ​​the ceramic substrate to serve subsequent grounding and electrical interconnection operations. A plurality of signal source modules 9, a phase space reconstruction timing controller 10, and a main chip 11 are connected to pad 2. The outputs of the plurality of signal source modules 9 are all connected to a shared transmission line formed by the same pad 2. The phase space reconstruction timing controller 10 is located on the transmission path between the signal source modules 9 and the main chip 11, and is used to set a preset dynamic encoding time interval for the multi-channel quantum control pulses output by the plurality of signal source modules 9. Based on the dynamic encoding time interval, the multi-channel control pulses form mutually orthogonal geometric trajectories in a six-dimensional phase space geometric model composed of spatial position and time derivative, and are transmitted to the corresponding target qubit inside the main chip 11 through the shared transmission line. In this design, an independent geometric degree of freedom is constructed using the time dimension, so that the signal can complete path separation at the physical level without relying on spatial isolation. The plurality of signal source modules 9 are all connected to a shared transmission line formed by the same pad 2, and this connection method provides a shared physical transmission channel for the multi-channel quantum control pulses. The phase space reconstruction timing controller 10 is located on the transmission path between the signal source modules 9 and the main chip 11. On the transmission path between chips 11, a preset dynamic encoding time interval is applied directly to the multiple quantum control pulses output by multiple signal source modules 9. This dynamic encoding time interval divides the multiple control pulses into continuous and non-overlapping time segments on the time axis. Based on these time segments, the multiple control pulses form mutually orthogonal and non-overlapping geometric trajectories in a six-dimensional phase space geometric model composed of spatial position and time derivative. The orthogonality in the phase space geometric model originates from the staggered arrangement on the time coordinates, so that the time sequence signals that originally shared the same physical wire occupy independent geometric coordinate positions in the six-dimensional phase space. This achieves the splitting of multiple signals without increasing the number of physical lines. The shared transmission wire transmits the time-interlaced multiple control pulses to the main chip 11 according to the orthogonality of the trajectories in the phase space geometric model. After receiving the signal, the main chip 11 distributes it to each target quantum bit according to the trajectory characteristics of the pulse in the phase space model. This achieves the effect of a single physical wire carrying multiple quantum control signals in parallel and without interference. One side of pad 2 is provided with an electrical interconnect pin 4, which is connected to an electrical interconnect solder joint 5. A copper ground layer 6 is connected to a grounding conductor pin 8 through a sintering point 7. The copper ground layer 6 is fixed to one side of the alumina ceramic substrate 1. Sealant 14 is provided at the connection points of the electrical interconnect pin 4 and the electrical interconnect solder joint 5, and at the connection points of the microwave interface 12 and the microwave coupling interface 13. In this design, the electrical interconnect pin 4 is used to physically extend the internal circuit of pad 2 to the external electrical interconnect port, the electrical interconnect solder joint 5 provides a transmission channel and physical connection interface for external electrical signals, and the copper ground layer 6 is connected to the grounding conductor pin 8 through the sintering point 7. The grounding conductor pin 8 and the sintering point 7 are integrated into a metallurgical connection between the copper grounding layer 6 and the grounding conductor pin 8 by high-temperature sintering process, and the secondary welding interface is eliminated. The copper grounding layer 6 is fixed to one side of the alumina ceramic substrate 1 so that the grounding structure is rigidly combined with the bearing substrate. The integrated metallurgical connection completed by the above sintering can reduce the total contact resistance of the grounding circuit and ensure the stability of the grounding impedance. The sealant 14 can fill the interface gap of each connection point, cut off the path of external water vapor and dust to enter the connection interface, and thus achieve the physical isolation and environmental protection effect of the connection area between the electrical interconnection welding port 5 and the microwave coupling interface 13. The main chip 11 is connected to a microwave interface 12, and a microwave coupling interface 13 is connected to the microwave interface 12. A polyimide insulating dielectric layer 15 is provided on the pads 2, signal source module 9, timing controller 10, and main chip 11. A sputtered titanium-copper layer 16 is provided on the surface of the polyimide insulating dielectric layer 15, copper ground layer 6, sintering point 7, and grounding pin 8. A copper-nickel alloy electromagnetic shielding layer 17 is provided on the surface of the sputtered titanium-copper layer 16. In this design, the microwave interface 12 connects to the microwave coupling interface 13, forming a transmission path for microwave signals from inside the main chip 11 to outside the package, used to achieve physical docking and signal communication between the microwave coupling interface 13 and external microwave transmission devices. The polyimide insulating dielectric layer 15 is used to maintain the electrical insulation state of the structures connected to the pads 2 and eliminate electrical short circuits between adjacent conductive structures. The polyimide insulating dielectric layer 15 also provides a surface for the adhesion of the upper metal film. A planarized substrate surface is provided; a sputtered titanium-copper layer 16 is formed on each structural surface via a sputtering process. The titanium layer in the sputtered titanium-copper layer 16 enhances the interfacial adhesion between the metal layer and the underlying structural surface, and the copper layer in the sputtered titanium-copper layer 16 provides a conductive seed layer for the subsequent metal electroplating process; a copper-nickel alloy electromagnetic shielding layer 17 utilizes the conductivity and magnetic permeability of the copper-nickel alloy material to form an electromagnetic shield. The electromagnetic shield achieves physical grounding of the structure through the electrical connection between the sputtered titanium-copper layer 16 and the copper grounding layer 6, the sintering point 7, and the grounding pin 8. The grounded electromagnetic shield forms a fully enclosed cavity that encloses the internal circuit. The enclosed cavity suppresses electromagnetic radiation crosstalk generated by the internal circuit and blocks the intrusion and interference of external electromagnetic fields on the internal quantum control signal, thereby ensuring that the signal transmission environment in the area where the pad 2, signal source module 9, timing controller 10, and main chip 11 are located is not affected by high-frequency electromagnetic fields. It also includes an epoxy encapsulation layer 18 that wraps the entire structure. The dense insulating solid layer formed after the epoxy resin is cured physically isolates the internal components from the external environment. By blocking external moisture, dust, and mechanical forces from directly acting on the internal circuit structure, it maintains the working stability of the internal components. At the same time, the curing process of the epoxy encapsulation layer 18 rigidly fixes the internal components, preventing relative displacement or vibration damage. The ends of the electrical interconnection solder joint 5, the grounding pin 8, and the microwave coupling interface 13 extend out of the epoxy encapsulation layer 18. This design ensures that external connection devices can directly contact the electrical interconnection solder joint 5 for electrical signal feeding, directly contact the grounding pin 8 to connect the grounding loop, and directly contact the microwave coupling interface 13 to connect microwave signals. The boundary of the epoxy encapsulation layer 18 and the junction of each extended end form a sealed interface to maintain the overall sealing. Thus, while ensuring the integrity of external electrical and microwave connection functions, it also achieves environmental sealing and mechanical protection for the internal structure.

[0019] In this embodiment, the alumina ceramic substrate 1 serves as the load-bearing and heat dissipation base. A transition conductive layer 3 is provided between the substrate and the pad 2 to buffer thermal stress and enhance the interface bonding. The pad 2 is configured as a single shared transmission wire. A copper grounding layer 6 is provided on the side of the substrate to extend the electrical signal path. Furthermore, the output terminals of multiple signal source modules 9 are connected to the shared pad 2. The phase space reconstruction timing controller 10 assigns a preset dynamic encoding time interval to the multiple quantum control pulses. This interval enables the multiple pulses to form mutually orthogonal geometric trajectories in the six-dimensional phase space composed of spatial position and time derivative, thereby completing the signal splitting based on the time dimension. The main chip 11 distributes the pulses to the corresponding target qubits according to the trajectory orthogonality. Furthermore, the electrical interconnect pin 4 and the electrical interconnect solder joint 5 constitute an external signal feed channel. The copper grounding layer 6 is integrally sintered with the grounding conductor pin 8 through the sintering point 7 to reduce the grounding loop impedance. The electrical interconnect solder joint 5 and the microwave coupling interface 13 are connected with sealant 14 to block external moisture and dust erosion. Meanwhile, the polyimide insulating dielectric layer 15 covers the relevant structure and provides electrical insulation and a flat substrate, the sputtered titanium copper layer 16 provides an electroplating substrate based on the adhesion of the titanium layer and the conductive seed function of the copper layer, and the copper-nickel alloy electromagnetic shielding layer 17 forms a grounded closed cavity to suppress internal radiation crosstalk and external high-frequency electromagnetic intrusion. In addition, the epoxy molding layer 18 encapsulates the internal structure to form a dense insulating solid layer to physically isolate the external environment and achieve rigid fixation. The electrical interconnection solder joint 5, the grounding pin 8, and the microwave coupling interface 13 extend out of the molding layer to ensure the feeding of electrical signals from external devices, the connection of the grounding circuit, and the docking of microwave signals. Example 2

[0020] A method for fabricating a phase-space time-division multiplexed quantum wiring architecture, used to fabricate the phase-space time-division multiplexed quantum wiring architecture in Example 1, specifically includes the following steps: Step S1: Prepare an alumina ceramic substrate 1, and prepare a copper grounding layer 6, sintering points 7, and grounding disconnect pins 8 on the alumina ceramic substrate 1. The copper grounding layer 6 and grounding disconnect pins 8 are fabricated by screen printing metal paste onto corresponding areas of the alumina ceramic substrate 1, and then sintered at high temperature. This high-temperature sintering allows the copper grounding layer 6 to form a metallurgical bond structure with the grounding disconnect pins 8 through the sintering points 7, without a secondary welding interface, resulting in the desired structure. Figure 3 The ceramic substrate and grounding pin are integrated into a substrate shown; wherein, the thickness of the alumina ceramic substrate 1 is 0.8~1.2mm, and after the preparation is completed, the total grounding resistance of the alumina ceramic substrate 1 and the grounding pin 8 is ≤0.1Ω; Step S2: Fabricate pad 2, transition conductive layer 3, and electrical interconnect pin 4, and connect pad 2 to the copper ground layer 6 for conductivity. Pad 2, transition conductive layer 3, and electrical interconnect pin 4 are sequentially patterned on the surface of alumina ceramic substrate 1 using photolithography. Subsequently, a titanium-copper seed layer is deposited as a conductive substrate using sputtering, and then electroplated to thicken it into a metal conductive layer with a set thickness. The transition conductive layer 3 is located between alumina ceramic substrate 1 and pad 2 and directly contacts the two interfaces. This intermediate layer buffers the interface caused by the difference in thermal expansion coefficients through the intermetallic bonding force at the interface. Stress and enhance the adhesion of pad 2 to the ceramic surface. Pad 2 extends along the substrate surface as a continuous transverse strip conductive structure. Electrical interconnect pins 4 are arranged on one edge of pad 2 as conductive branches extending from pad 2 to external electrical interconnect ports. Pad 2 and copper ground layer 6 are electrically connected through direct overlap on the substrate surface or integrated photolithography. Pad 2 is configured as a single shared transmission line structure for multiple signals. Its continuous conductivity supports the parallel transmission of multiple quantum control signals within the same physical channel without physical spatial separation, resulting in... Figure 4 The ceramic wiring substrate with shared conductors shown in the design allows the electrical signal on pad 2 to be conducted to the edge of the substrate via the copper ground layer 6 to achieve subsequent grounding or signal docking. The transition conductive layer 3, together with pad 2 and copper ground layer 6, constitutes a complete bottom layer wiring network. The single shared conductor structure of pad 2 provides a physical channel basis for the subsequent installation of multiple signal source modules and the realization of multi-channel signal co-line transmission. Step S3: Using a vacuum nozzle, negative pressure is applied to adsorb the upper surface of the main chip 11. The visual alignment system calibrates the coordinate offset of the main chip 11 relative to the bonding area of ​​the pad 2. After the coordinate offset is eliminated, the main chip 11 is precisely aligned and mounted above the pad 2. The eutectic solder pre-placed in the bonding area of ​​the pad 2 is heated to a molten state. The molten eutectic solder spreads and wets the bottom electrode of the main chip 11 and the surface of the pad 2, forming an intermetallic compound. The intermetallic compound is cooled and solidified, achieving mechanical fixation and low-resistance electrical connection between the main chip 11 and the pad 2, forming an electrical coupling. A microwave interface 12 is fabricated on the main chip 11. The microwave interface 12 is fabricated on the surface of the fixed main chip 11 through photolithography etching and electroplating deposition processes. The microwave interface 12 is located in the microwave signal output section of the main chip 11. The microwave interface 12 serves as the physical contact for transmitting microwave signals from the inside of the main chip 11 to the outside. The microwave interface 12 is used for subsequent signal docking with the microwave coupling interface 13. After the microwave interface 12 and the microwave coupling interface 13 are physically docked, a microwave signal transmission path is formed, resulting in... Figure 5 The chip mounting and microwave interface coupling semi-finished product shown is shown. Step S4: The plurality of signal source modules 9 and the phase space reconstruction timing controller 10 are respectively fixed to the corresponding mounting points above the pads 2 using surface mount technology. The output terminals of the plurality of signal source modules 9 are connected to a single shared transmission line formed by the pads 2 using wire bonding or direct pad bonding technology. Simultaneously, the signal control terminals of the phase space reconstruction timing controller 10 are electrically connected to the electrical control input terminals of each signal source module 9 through metal wiring. This electrical connection enables the phase space reconstruction timing controller 10 to send timing control commands to each signal source module 9 to control the start time and duration of the output pulses of each signal source module 9, allowing the phase space reconstruction timing controller 10 to control the output pulses of each signal source module 9 according to a preset encoding algorithm. A dynamic encoding time interval is applied to the quantum control pulses. This dynamic encoding time interval arranges the pulses output from different signal source modules 9 along the time axis with a fixed or variable spacing. The resulting time sequence ensures that the pulses do not overlap in the physical time dimension. Since different pulses occupy different time intervals, the time-domain coordinates corresponding to each pulse in the six-dimensional phase space geometric model with the time derivative as an independent coordinate axis undergo discrete displacement. This discrete displacement causes each pulse to occupy different coordinate positions in the phase space, forming mutually orthogonal geometric trajectories. Orthogonality ensures that although the pulses share the same physical wire when transmitting on the shared transmission wire, they still maintain their independent signal properties. Thus, without increasing the number of wires, the splitting and interference-free transmission of multiple control pulses are achieved, resulting in... Figure 6 The wiring integration component shown includes phase space timing control functionality; Step S5: A polyimide insulating dielectric layer 15, a sputtered titanium-copper layer 16, and a copper-nickel alloy electromagnetic shielding layer 17 are sequentially fabricated above the wiring integration component containing phase-space timing control functionality. Specifically: First, a polyimide precursor solution is coated on the wiring integration component containing phase space timing control function. Then, an imidization curing process is used to form a polyimide insulating dielectric layer 15. The polyimide insulating dielectric layer 15 covers the upper surface area of ​​the pad 2, signal source module 9, phase space reconstruction timing controller 10, and main chip 11. The polyimide insulating dielectric layer 15 can electrically isolate the active devices and metal traces below from the upper metal shielding layer to avoid short circuits or parasitic capacitance coupling between the shielding layer and the internal conductive structure. At the same time, the polyimide material itself has the characteristics of low dielectric constant and low loss factor, which can reduce the energy loss of high-frequency microwave signals when passing through the dielectric layer. Then, on the surface of the polyimide insulating dielectric layer 15 and the copper grounding layer 6, sintering point 7 and grounding conductor pin 8, a titanium metal layer is first deposited as a titanium adhesion layer using a DC magnetron sputtering process. The titanium adhesion layer can form an intermetallic bond with the underlying ceramic or metal surface to improve the adhesion strength of the upper copper film. Subsequently, a copper metal layer is sputtered and deposited on the surface of the titanium adhesion layer as a copper conductive seed layer. This copper conductive seed layer provides a uniform conductive substrate for subsequent electroplating deposition. The sputtered titanium copper layer 16 completely covers the exposed surface of the insulating dielectric layer and the grounding area to ensure that the subsequent electroplating layer can grow continuously in the entire covered area. Using sputtered titanium-copper layer 16 as the cathode, a copper-nickel alloy layer is deposited on the surface of sputtered titanium-copper layer 16 by electroplating to form a copper-nickel alloy electromagnetic shielding layer 17. During the electroplating process, the concentration ratio of copper ions to nickel ions in the plating solution is controlled so that the mass ratio of copper to nickel in the deposited alloy is maintained at 80:20. The thickness of the shielding layer is controlled to be 5 to 10 micrometers. Under this thickness condition, the copper-nickel alloy has high magnetic permeability and electrical conductivity, which can effectively attenuate electromagnetic wave energy through reflection and absorption. In the frequency band of 10 to 3000 MHz, the electromagnetic shielding effectiveness reaches not less than 80 dB, thereby suppressing the intrusion of external electromagnetic fields and internal electromagnetic radiation crosstalk. Furthermore, during the electroplating process, the copper-nickel alloy electromagnetic shielding layer 17 is continuously deposited in the area where the grounding pin 8 is located, and directly contacts the grounding pin 8 to complete a seamless electrical connection, ensuring that the grounding potential of the shielding layer remains consistent, forming a grounded closed cavity. This closed cavity isolates the internal circuit from the external electromagnetic environment, ensuring that the transmission of the internal quantum control signal is not affected by high-frequency electromagnetic interference; finally, the result is as follows: Figure 7 The multi-layer electromagnetic shielding packaged semi-finished product shown; Step S6: Prepare sealant 14. Apply high-temperature resistant sealant 14 to the connection interfaces of the electrical interconnection solder joint 5 and the microwave coupling interface 13 to seal and protect the connection between the electrical interconnection solder joint 5 and the microwave coupling interface 13, resulting in the following... Figure 8 The interface sealing and protection semi-finished product shown; Among them, the sealant 14 is a high-temperature resistant sealant, which is filled in the contact gap between the electrical interconnection welding joint 5 and the corresponding terminal and the assembly gap between the microwave coupling interface 13 and the mating end by room temperature vulcanization or heat curing. After the sealant 14 is cured, it forms a continuous elastic sealing layer. This sealing layer completely blocks the path of external water vapor and dust particles to penetrate into the internal electronic component area through the connection gap by physical filling. The temperature resistance threshold of the material properties of the high-temperature resistant sealant 14 is set to ≥150℃. Within this temperature range, the sealant 14 does not melt or decompose, thereby ensuring the dimensional stability and bonding strength of the sealing structure when operating at high temperature or when the ambient temperature fluctuates. After step S6 is completed, the overall protection level of the interface reaches IP67. The test conditions corresponding to this level are that after being immersed in water at a depth of one meter for thirty minutes, there is no water ingress inside the interface and the insulation performance remains normal. At the same time, dust particles with a diameter of less than or equal to 75 micrometers cannot penetrate the sealing interface and enter the internal contact area of ​​the interface, thereby ensuring the electrical connection reliability and microwave signal transmission stability of the interface. Step S7: Prepare an epoxy molding layer 18, covering the entire structure except for the interface terminals, and exposing the terminals of the electrical interconnect solder joint 5, the grounding pin 8, and the microwave coupling interface 13, to obtain the following result. Figure 9 The epoxy-encapsulated integrated quantum wiring package shown is as follows: First, the semi-finished interface sealing and protection product is placed in the cavity of the molding die. Epoxy resin molding compound is then used for transfer molding under high temperature and pressure conditions. The epoxy resin molding compound melts and flows within the mold temperature range of 170 to 180°C. The molten epoxy resin fills the internal space of the mold cavity and covers all internal structures except for the electrical interconnect welding joint 5, the grounding conductor pin 8, and the microwave coupling interface 13. After curing at this temperature for 15 to 20 minutes, the epoxy resin cross-links and forms an epoxy molding layer 18. The thickness of the cured epoxy molding layer 18 remains within the range of 0.8 to 1.2 mm. This thickness provides sufficient mechanical strength to resist external impacts and prevent moisture intrusion. The bonding interface between the epoxy molding layer 18 and the alumina ceramic substrate 1 relies on the shrinkage stress generated during epoxy resin curing and the chemical bonding of the interface to achieve a tight fit. This bonding force prevents gaps from forming between the interfaces due to temperature cycling or mechanical vibration, thereby ensuring that the epoxy molding layer 18 does not delaminate or peel off. The dense three-dimensional encapsulation formed by the epoxy molding layer 18 completely isolates the internal active devices, metal traces, and electromagnetic shielding layer from the external atmospheric environment, preventing water vapor, dust, and chemical media from corroding the internal circuits. At the same time, the cured rigid epoxy layer applies a uniform clamping force to each component, limiting the relative displacement of each component under vibration conditions to prevent lead fatigue fracture or solder joint cracking. Furthermore, the ends of the electrical interconnection solder joint 5, the grounding pin 8, and the microwave coupling interface 13 extend from the openings reserved at the corresponding positions of the mold cavity, allowing the external connector to directly contact the electrical interconnection solder joint 5 for electrical signal input and output, directly contact the grounding pin 8 to complete the grounding circuit conduction, and directly contact the microwave coupling interface 13 to achieve microwave signal coupling transmission. The boundary of the epoxy molding layer 18 and the junction of each protruding end are formed by the molding material being tightly bonded to the end surface during molding, thus forming a closed interface and maintaining the physical isolation between the interior and exterior environment of the overall package. The epoxy encapsulation layer 18 has a thickness of 0.8~1.2mm, and the epoxy encapsulation layer 18 is tightly bonded to the alumina ceramic substrate 1 without delamination or peeling.

[0021] In this embodiment, the quantum wiring architecture is constructed sequentially through seven steps: First, a copper grounding layer, sintering point, and grounding conductor pin are formed on an alumina ceramic substrate using screen printing and high-temperature integrated sintering to reduce grounding impedance. Then, a transition conductive layer and pads are constructed by photolithography sputtering electroplating, and the pads are configured as a single shared transmission line and connected to the copper grounding layer to extend the signal path. Then, the main chip is mounted by vacuum adsorption and visual alignment, and the intermetallic compound is formed by eutectic solder to achieve fixed connection and low-resistance coupling between the main chip and the pad. At the same time, the microwave interface is prepared by photolithography on the surface of the main chip. Then, multiple signal source modules and phase space reconstruction timing controllers are mounted on the pads and electrically connected. The timing controller applies dynamic encoding time intervals to multiple pulses, causing each pulse to be misaligned on the time axis and form mutually orthogonal geometric trajectories in the six-dimensional phase space, thereby ensuring that each signal sharing the same transmission line remains independent. Subsequently, polyimide is coated and imidized on top of the component to form an insulating dielectric layer. Then, a titanium adhesion layer and a copper conductive seed layer are sputtered and deposited. A copper-nickel alloy electromagnetic shielding layer is electroplated and deposited and seamlessly connected to the grounding conductor pin to form a grounding closed cavity to suppress crosstalk and electromagnetic interference. Finally, high-temperature resistant sealant is filled at the interface connection and cured to achieve an IP67 protection level. Finally, the internal structure was prepared by transfer molding with an epoxy encapsulation layer, exposing only the interface end to enable external electrical signal feeding, grounding, and microwave docking. The encapsulation layer was tightly bonded to the ceramic substrate without delamination or peeling.

[0022] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A phase-space time-division multiplexing quantum wiring architecture and its fabrication method, characterized in that, include: An alumina ceramic substrate (1) is provided with pads (2), a transition conductive layer (3) is provided between the alumina ceramic substrate (1) and the pads (2), and a copper ground layer (6) is connected to one side of the pads (2); characterized in that a plurality of signal source modules (9), a phase space reconstruction timing controller (10) and a main chip (11) are connected to the pads (2); the output terminals of the plurality of signal source modules (9) are all connected to the same shared transmission line formed by the pads (2); The main chip (11) is connected to a microwave interface (12), and a microwave coupling interface (13) is connected to the microwave interface (12); the pad (2), the signal source module (9), the timing controller (10) and the main chip (11) are provided with a polyimide insulating dielectric layer (15), and the surfaces of the polyimide insulating dielectric layer (15), the copper ground layer (6), the sintering point (7) and the grounding conductor pin (8) are all provided with a sputtered titanium copper layer (16), and the surface of the sputtered titanium copper layer (16) is provided with a copper nickel alloy electromagnetic shielding layer (17).

2. The quantum wiring architecture for phase space time-division multiplexing and its fabrication method according to claim 1, characterized in that: The phase space reconstruction timing controller (10) is located on the transmission path between the signal source module (9) and the main chip (11) and is used to set a preset dynamic encoding time interval for the multi-channel quantum control pulses output by the plurality of signal source modules (9); Based on the dynamic encoding time interval, the multiple control pulses form mutually orthogonal geometric trajectories in the six-dimensional phase space geometric model composed of spatial position and time derivative, and are transmitted to the corresponding target qubit inside the main chip (11) through the shared transmission wire.

3. The phase-space time-division multiplexing quantum wiring architecture and its fabrication method according to claim 1, characterized in that: The pad (2) has an electrical interconnect pin (4) on one side, and the electrical interconnect pin (4) is connected to an electrical interconnect solder joint (5); the copper ground layer (6) is connected to a grounding pin (8) through a sintering point (7), and the copper ground layer (6) is fixed on one side of the alumina ceramic substrate (1); the connection point between the electrical interconnect pin (4) and the electrical interconnect solder joint (5) and the connection point between the microwave interface (12) and the microwave coupling interface (13) are both provided with sealant (14).

4. The phase-space time-division multiplexing quantum wiring architecture and its fabrication method according to claim 1, characterized in that: It also includes an epoxy encapsulation layer (18) that wraps the entire architecture, with the ends of the electrical interconnect solder joint (5), grounding pin (8) and microwave coupling interface (13) extending out of the epoxy encapsulation layer (18).

5. A method for fabricating a phase-space time-division multiplexed quantum wiring architecture, as described in any one of claims 1 to 4, characterized in that: Includes the following steps: Step S1: Prepare an alumina ceramic substrate (1), and prepare a copper grounding layer (6), a sintering point (7) and a grounding lead (8) on the alumina ceramic substrate (1) to obtain an integrated substrate of ceramic substrate and grounding lead; Step S2: Prepare pads (2), transition conductive layer (3) and electrical interconnect pins (4), and connect the pads (2) to the copper ground layer (6); the pads (2) are configured as a single shared transmission line structure for multiple signals to be shared, and a ceramic wiring substrate containing shared lines is obtained; Step S3: Using a vacuum nozzle, the main chip (11) is precisely aligned and mounted on the pad (2). The eutectic solder is used to fix the chip to the pad (2) to form an electrical coupling. A microwave interface (12) is fabricated on the main chip (11). The microwave interface (12) is used for subsequent signal docking with the microwave coupling interface (13) to obtain a chip mounting and microwave interface coupling semi-finished product. Step S4: Mount a plurality of signal source modules (9) and a phase space reconstruction timing controller (10) on the pad (2), connect the output terminals of the plurality of signal source modules (9) to a single shared transmission line formed by the pad (2), and electrically connect the phase space reconstruction timing controller (10) to the plurality of signal source modules (9) so that the phase space reconstruction timing controller (10) can set a dynamic encoding time interval for multiple control pulses, thereby obtaining a wiring integrated component with phase space timing control function; wherein, the dynamic encoding time interval set by the phase space reconstruction timing controller (10) is 15~20ns, and after preparation, the transmission efficiency of multiple quantum signals in the single shared transmission line is ≥99%, and the electromagnetic crosstalk between channels is ≤-60dB; Step S5: On the wiring integration component with phase space timing control function, a polyimide insulating dielectric layer (15), a sputtered titanium copper layer (16), and a copper-nickel alloy electromagnetic shielding layer (17) are sequentially prepared to obtain a multi-layer electromagnetic shielding packaged semi-finished product. Step S6: Prepare sealant (14) to seal and protect the connection between the electrical interconnection weld (5) and the microwave coupling interface (13) to obtain a semi-finished interface sealing and protection product; Step S7: Prepare an epoxy molding layer (18) to cover the entire structure except for the interface end, and expose the ends of the electrical interconnection solder joint (5), grounding pin (8) and microwave coupling interface (13) to obtain an epoxy-molded integrated quantum wiring package.

6. The method for fabricating a phase-space time-division multiplexing quantum wiring architecture according to claim 5, characterized in that: In step S1, the thickness of the alumina ceramic substrate (1) is 0.8~1.2mm. After preparation, the total grounding resistance of the alumina ceramic substrate (1) and the grounding conductor (8) is ≤0.1Ω.

7. The method for fabricating a phase-space time-division multiplexing quantum wiring architecture according to claim 5, characterized in that: In step S5, the sputtered titanium-copper layer (16) is formed by sputtering a titanium adhesion layer and a copper conductive seed layer in sequence; the copper-nickel alloy electromagnetic shielding layer (17) is formed by electroplating, with a copper-nickel ratio of 80:20, a shielding layer thickness of 5~10μm, and a shielding effectiveness of ≥80dB in the 10~3000MHz frequency band. The copper-nickel alloy electromagnetic shielding layer (17) is seamlessly electrically connected to the grounding conductor pin (8).

8. The method for fabricating a phase-space time-division multiplexing quantum wiring architecture according to claim 5, characterized in that: In step S6, the sealant (14) is a high-temperature resistant sealant with a temperature resistance of ≥150℃, and after step S6 is completed, the overall protection level of the interface reaches IP67.

9. The method for fabricating a phase-space time-division multiplexing quantum wiring architecture according to claim 5, characterized in that: In step S7, the epoxy encapsulation layer (18) has a thickness of 0.8~1.2mm, and the epoxy encapsulation layer (18) is tightly bonded to the alumina ceramic substrate (1), without delamination or peeling.

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