A bonding wire compensation structure for efficient interconnection of chips in a multilayer LCP substrate

Abstract

The application provides a bonding wire compensation structure and a design method for efficient interconnection of chips in a multilayer LCP substrate and a PCB structure, and relates to the technical field of multilayer polymer package substrate design. The bonding wire compensation structure is based on a multilayer LCP substrate with excellent millimeter wave transmission characteristics, adopts a bonding wire matching structure with wideband transmission characteristics, and is arranged at a position corresponding to the bonding wire on the multilayer LCP substrate, so as to construct a signal transmission path with preset impedance characteristics between the chip and the multilayer LCP substrate, and effectively reduce or avoid the adverse effects of the bonding wire parasitic parameters on the signal transmission performance between the chip and the substrate. In addition, the processing difficulty of the related process can be effectively improved by designing the bonding wire matching structure, such as introducing a specific defect structure.

Description

Technical Field

[0001] This invention relates to the field of multilayer polymer packaging substrate design technology, and more specifically, to a bonding line compensation structure and design method for efficient chip interconnection in a multilayer LCP substrate, as well as a PCB structure. Background Technology

[0002] System-in-Package (SIP), as a high-density integration technology, has become one of the preferred solutions for packaging multifunctional chips due to its advantages such as high integration, lightweight, and small size.

[0003] In SiP (System-in-Package) packaging, bonding wires have become the mainstream solution for chip interconnection due to their lower cost and more reliable manufacturing process, and are widely used for electrical connections between chips and between chips and substrates. However, with the continuous increase in the operating frequency of corresponding circuit systems, especially in radio frequency and millimeter-wave applications, bonding wires are used to transmit high-frequency signals. During signal transmission, they introduce non-negligible parasitic parameters, making them difficult to consider as ideal conductors and adversely affecting the signal transmission performance of the circuit. In other words, the parasitic parameters introduced by bonding wires have become an important factor limiting the signal transmission performance between chips and substrates. Summary of the Invention

[0004] The problem addressed by this invention is how to reduce or avoid the adverse effects of bonding wire parasitic parameters on signal transmission performance between the chip and the substrate.

[0005] To address the aforementioned issues, this invention provides a bonding wire compensation structure and design method for efficient chip interconnection in a multilayer LCP substrate, as well as a PCB structure.

[0006] In a first aspect, the present invention provides a bonding wire compensation structure for efficient chip interconnection in a multilayer LCP substrate, comprising bonding wires and bonding wire matching structures disposed on the multilayer LCP substrate; the multilayer LCP substrate is provided with high-frequency signal transmission lines and chips, and corresponding pins of the chips are electrically connected to the corresponding high-frequency signal transmission lines through the bonding wires; the bonding wire matching structure is disposed on the multilayer LCP substrate at a position corresponding to the bonding wires, and the bonding wire matching structure and the bonding wires form a signal transmission path with preset impedance characteristics.

[0007] Optionally, the multilayer LCP substrate includes at least one LCP dielectric layer and at least one conductor layer, wherein the LCP dielectric layer and the conductor layer are stacked. The bonding wire matching structure includes an equivalent capacitance structure disposed at the corresponding position of the bonding wire, the equivalent capacitance structure being formed by at least one of the conductor layer of the multilayer LCP substrate, the high-frequency signal transmission line, or the pad structure; and / or, the bonding wire matching structure includes a defect ground structure in the conductor layer for grounding disposed at the corresponding position of the bonding wire.

[0008] Optionally, the conductor layer includes a signal layer for signal transmission disposed on the surface of the multilayer LCP substrate, and a ground layer for grounding disposed inside or on the back of the multilayer LCP substrate; the high-frequency signal transmission line adopts a microstrip line structure, which is formed by a conductor strip disposed on the signal layer and the ground layer.

[0009] Optionally, one end of the conductor strip of the microstrip line structure used for electrical connection to the chip via the bonding wire is in a T-shape, and the T-shape is electrically connected to the corresponding pin of the chip via the bonding wire.

[0010] Optionally, the same high-frequency signal transmission line is electrically connected to the same pin of the chip via at least two parallel bonding wires.

[0011] Optionally, the multilayer LCP substrate is formed by laminating an LCP copper-clad laminate and an LCP prepreg; the LCP copper-clad laminate includes the LCP dielectric layer and the conductor layer.

[0012] In a second aspect, the present invention also provides a PCB structure, including a bonding wire compensation structure for efficient interconnection of chips in a multilayer LCP substrate as described in the first aspect.

[0013] Thirdly, the present invention also provides a method for designing a bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate, comprising: Based on the high-frequency signal transmission requirements of the chips on the multilayer LCP substrate, determine the corresponding signal transmission operating frequency band and the required preset impedance characteristics. Based on the signal transmission operating frequency band and the preset impedance characteristics, the first design parameters of the high-frequency signal transmission line on the multilayer LCP substrate are determined. The parasitic parameters generated when the high-frequency signal transmission line with the first design parameters is electrically connected to the chip through a bonding wire matching structure under the signal transmission operating frequency band are determined. Based on the parasitic parameters, a target structure for a multilayer LCP substrate is determined for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line. Based on the first design parameters and the target structure, the high-frequency signal transmission line, the bonding line, and the multilayer LCP substrate structure are designed collaboratively to determine the structure of the bonding line compensation structure for efficient chip interconnection in the multilayer LCP substrate.

[0014] Optionally, the parasitic parameters generated when the high-frequency signal transmission line with the first design parameters is electrically connected to the chip via the bonding wire matching structure under the signal transmission operating frequency band include: Based on the chip, the high-frequency signal transmission line using the first design parameters, and the bonding wire, modeling and simulation analysis are performed to determine the parasitic parameters of the bonding wire in the signal transmission operating frequency band.

[0015] Optionally, determining the target structure of the multilayer LCP substrate for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line based on the parasitic parameters includes: Based on the distribution characteristics of the parasitic parameters within the signal transmission operating frequency band, the type of bond wire matching structure used to adjust the equivalent electrical characteristics is determined; wherein, the bond wire matching structure includes at least one of equivalent capacitance structure and defective ground structure; The target structure is determined based on the determined bond line matching structure type.

[0016] Compared with existing technologies, this invention has the following advantages: The bonding wire compensation structure of this invention can achieve efficient interconnection between the multilayer LCP substrate and the chip based on a multilayer LCP substrate, effectively solving the problem of high-frequency signal transmission performance degradation caused by bonding wire parasitic parameters. Specifically, based on the excellent millimeter-wave transmission characteristics of the multilayer LCP substrate, and utilizing the low and stable dielectric constant, low dielectric loss, and low water absorption of LCP material, the transmission environment of high-frequency signals in the multilayer LCP substrate is made more stable. This helps to reduce the impact of dielectric loss and environmental factors on signal transmission performance, thereby providing reliable electromagnetic foundation conditions for high-frequency or millimeter-wave signal transmission. On this basis, the chip is electrically connected to the high-frequency signal transmission lines on the multilayer LCP substrate through bonding wires, forming a compact high-frequency interconnect structure that meets the integration and packaging requirements of high-frequency application scenarios. Furthermore, addressing the issue of parasitic parameters inevitably introduced by bonding wires under high-frequency conditions, and the resulting impedance discontinuities between the chip and high-frequency signal transmission lines, the bonding wire compensation structure further incorporates a bonding wire matching structure at the corresponding location of the bonding wire. By having the bonding wire matching structure electrically participate in the signal transmission process alongside the bonding wire, the electrical characteristics of the bonding wire connection area are no longer solely determined by the bonding wire itself. Instead, the bonding wire and the bonding wire matching structure collaboratively form a signal transmission path with preset impedance characteristics. This creates a relatively continuous and stable impedance environment between the chip and the high-frequency signal transmission line, significantly mitigating the adverse effects of impedance abrupt changes caused by bonding wire parasitic parameters. Moreover, by designing the electrical characteristics of the bonding wire matching structure, the signal transmission path can maintain impedance stability over a wide frequency range, thus enabling the bonding wire matching structure to possess broadband signal transmission characteristics. Therefore, based on the above-mentioned interconnection method between the chip and the multilayer LCP substrate and the synergistic cooperation of the signal transmission path, the PCB structure using the multilayer LCP substrate and the bonding wire compensation structure is beneficial to reducing the reflection and additional loss of high-frequency signals in the bonding wire connection area, supporting broadband signal transmission, improving signal integrity, and effectively reducing or avoiding the adverse effects of bonding wire parasitic parameters on the signal transmission performance between the chip and the substrate in high-frequency or millimeter-wave application scenarios, thereby making the high-frequency signal transmission between the chip and the high-frequency signal transmission line more stable and reliable. Attached Figure Description

[0017] Figure 1 This is a partial structural diagram of the PCB structure in an embodiment of the present invention; Figure 2 This is a partial structural diagram of the PCB structure in another embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the multilayer conductor layer of the multilayer LCP substrate in an embodiment of the present invention; Figure 4 This is a schematic diagram of the fabrication process of the multilayer LCP substrate in an embodiment of the present invention. Detailed Implementation

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0020] Combination Figure 1 As shown, this embodiment of the invention provides a bonding wire compensation structure for efficient chip interconnection in a multilayer LCP substrate, including bonding wires and bonding wire matching structures disposed on the multilayer LCP substrate; a high-frequency signal transmission line and a chip are disposed on the multilayer LCP substrate, and the corresponding pins of the chip are electrically connected to the corresponding high-frequency signal transmission line through the bonding wire; the bonding wire matching structure is disposed on the multilayer LCP substrate at a position corresponding to the bonding wire, and the bonding wire matching structure and the bonding wire form a signal transmission path with a preset impedance characteristic.

[0021] In this embodiment, the bonding line compensation structure for efficient chip interconnection in the multilayer LCP substrate can be used in the multilayer LCP substrate (or the PCB structure using the multilayer LCP substrate) to be applied to high-frequency signal transmission scenarios, such as realizing the functions of radio frequency or millimeter wave signal transmission, processing or transmission based on the chip packaged on the multilayer LCP substrate in the PCB structure.

[0022] Multilayer LCP substrates employ a multilayer structure (including multilayer LCP substrates with excellent millimeter-wave transmission characteristics). Specifically, the LCP substrate uses liquid crystal polymer (LCP) material as the dielectric, which possesses material properties such as low and stable dielectric constant with frequency variation, low dielectric loss, and low water absorption. In high-frequency, especially millimeter-wave signal transmission conditions, due to the high signal frequency, the propagation loss of electromagnetic waves in the dielectric is mainly affected by dielectric loss and dielectric constant stability. LCP material has a low dielectric loss factor, which can effectively reduce energy attenuation during signal propagation. Simultaneously, the dielectric constant of LCP material changes little with frequency, which helps maintain the stability of the transmission line characteristic impedance, thereby reducing signal reflection caused by impedance fluctuations. Furthermore, the low water absorption of LCP material can reduce the impact of environmental humidity changes on dielectric properties, further ensuring consistency and stability during millimeter-wave signal transmission. Therefore, signal transmission based on LCP substrates exhibits low insertion loss and good impedance control capabilities in the millimeter-wave band, thus demonstrating excellent millimeter-wave transmission characteristics. Furthermore, LCP materials possess excellent dimensional and thermal stability, making them suitable for long-term operation in high-frequency applications. This helps improve the reliability and consistency of multilayer LCP substrates and PCB structures during actual use.

[0023] A multilayer LCP substrate has high-frequency signal transmission lines (such as microstrip lines) on it. These lines are used to transmit high-frequency signals on the LCP substrate. The LCP substrate also serves as a carrier, on which chips are mounted to perform corresponding functions. These chips are disposed on the LCP substrate and electrically connected to the high-frequency signal transmission lines via bonding wires. This electrical connection configuration of the chips on the LCP substrate forms a signal transmission path between the chips and the high-frequency signal transmission lines. This allows the high-frequency signals generated or processed by the chips to be transmitted to the high-frequency signal transmission lines via the bonding wires, or to the corresponding pins of the chips via the high-frequency signal transmission lines, thus supporting the transmission and processing of high-frequency signals.

[0024] Considering that bonding wires introduce non-negligible parasitic parameters (such as parasitic inductance and the resulting impedance discontinuities) during high-frequency signal transmission, which adversely affect the high-frequency signal transmission performance between the chip and the high-frequency signal transmission line, the bonding wire compensation structure for efficient chip interconnection in a multilayer LCP substrate also includes a bonding wire matching structure. The bonding wire matching structure is located on the multilayer LCP substrate at the position corresponding to the bonding wire and electrically participates in the signal transmission process together with the bonding wire. This creates a signal transmission path with preset impedance characteristics between the chip and the high-frequency signal transmission line, forming a relatively continuous and stable impedance environment. This reduces the impact of impedance abrupt changes caused by bonding wire parasitic parameters on high-frequency signal transmission, thereby helping to reduce reflections and additional losses in the bonding wire connection area and improve signal integrity during transmission. Moreover, in high-frequency or millimeter-wave applications, the electrical synergy between the bonding wire matching structure and the bonding wire effectively mitigates the adverse effects of bonding wire parasitic parameters on high-frequency signal transmission performance, making signal transmission between the chip and the high-frequency signal transmission line more stable and reliable. Furthermore, by designing the electrical characteristics of the bond wire matching structure, the parasitic effects of the bond wire can be continuously adjusted within the target frequency range. This allows the signal transmission path to maintain relatively stable impedance characteristics over a wider frequency range, thereby giving the bond wire matching structure broadband transmission characteristics. This is beneficial for improving the broadband signal transmission capability of the PCB structure in high-frequency or millimeter-wave bands. The bond wire matching structure can be directly electrically connected to the bond wire to participate in the signal transmission process, or it can be located in the vicinity of the bond wire and participate in the signal transmission process through electromagnetic coupling or equivalent electrical effects. Thus, the bond wire matching structure and the bond wire together electrically constitute the signal transmission path, and the equivalent impedance characteristics of the signal transmission path are determined collaboratively by the bond wire and the bond wire matching structure. In some embodiments, by selecting a bond wire matching structure with corresponding electrical characteristics to cooperate with the corresponding bond wire, a signal transmission path with the required preset impedance characteristics can be obtained. This effectively adjusts the parasitic parameters of the bond wire, reducing or avoiding their adverse effects on high-frequency signal transmission performance.

[0025] In summary, the bonding wire compensation structure enables efficient interconnection between the multilayer LCP substrate and the chip, effectively solving the problem of high-frequency signal transmission performance degradation caused by bonding wire parasitic parameters. Specifically, based on the excellent millimeter-wave transmission characteristics of the multilayer LCP substrate, the low and stable dielectric constant, low dielectric loss, and low water absorption of LCP material make the transmission environment of high-frequency signals in the multilayer LCP substrate more stable. This helps reduce the impact of dielectric loss and environmental factors on signal transmission performance, thus providing reliable electromagnetic foundation conditions for high-frequency or millimeter-wave signal transmission. On this basis, the chip is electrically connected to the high-frequency signal transmission lines on the multilayer LCP substrate via bonding wires, forming a compact high-frequency interconnect structure that meets the integration and packaging requirements of high-frequency applications. Furthermore, addressing the issue of parasitic parameters inevitably introduced by bonding wires under high-frequency conditions, and the resulting impedance discontinuities between the chip and high-frequency signal transmission lines, the bonding wire compensation structure further incorporates a bonding wire matching structure at the corresponding location of the bonding wire. By having the bonding wire matching structure electrically participate in the signal transmission process alongside the bonding wire, the electrical characteristics of the bonding wire connection area are no longer solely determined by the bonding wire itself. Instead, the bonding wire and the bonding wire matching structure collaboratively form a signal transmission path with preset impedance characteristics. This creates a relatively continuous and stable impedance environment between the chip and the high-frequency signal transmission line, significantly mitigating the adverse effects of impedance abrupt changes caused by bonding wire parasitic parameters. Moreover, by designing the electrical characteristics of the bonding wire matching structure, the signal transmission path can maintain impedance stability over a wide frequency range, thus enabling the bonding wire matching structure to possess broadband signal transmission characteristics. Therefore, based on the above-mentioned interconnection method between the chip and the multilayer LCP substrate and the synergistic cooperation of the signal transmission path, the PCB structure using the multilayer LCP substrate and the bonding wire compensation structure is beneficial to reducing the reflection and additional loss of high-frequency signals in the bonding wire connection area, supporting broadband signal transmission, improving signal integrity, and effectively reducing or avoiding the adverse effects of bonding wire parasitic parameters on the signal transmission performance between the chip and the substrate in high-frequency or millimeter-wave application scenarios, thereby making the high-frequency signal transmission between the chip and the high-frequency signal transmission line more stable and reliable.

[0026] Optionally, combined Figure 1 As shown, the multilayer LCP substrate includes at least one LCP dielectric layer and at least one conductor layer, wherein the LCP dielectric layer and the conductor layer are stacked.

[0027] In this embodiment, the multilayer LCP substrate serves as a substrate structure for supporting devices such as chips. It includes at least one LCP dielectric layer and at least one conductor layer. The LCP dielectric layer provides electrical insulation and dielectric support. Its material is liquid crystal polymer (LCP), which effectively utilizes the low and stable dielectric constant, low dielectric loss, and low water absorption of LCP material. This makes the transmission environment of high-frequency signals in the substrate more stable, reducing the impact of dielectric loss and environmental changes on signal transmission performance, thereby providing reliable electromagnetic foundation conditions for high-frequency or millimeter-wave signal transmission. The conductor layer (e.g., copper-clad laminate) is disposed on one side or opposite sides of the LCP dielectric layer, forming high-frequency signal transmission lines or reference conductor structures (e.g., reference ground). By stacking the LCP dielectric layer and the conductor layer, the multilayer LCP substrate can meet the dielectric performance requirements of high-frequency signal transmission while providing the necessary conductive structure for signal traces and chip interconnections. In some embodiments, the specific number of LCP dielectric layers, their arrangement order, and thickness parameters can be designed and adjusted according to actual application requirements.

[0028] Optionally, the bonding wire matching structure includes an equivalent capacitance structure disposed at the corresponding position of the bonding wire, the equivalent capacitance structure being formed by at least one of the conductor layer of the multilayer LCP substrate, a high-frequency signal transmission line, or a pad structure; and / or, the bonding wire matching structure includes a defect ground structure in the conductor layer for grounding disposed at the corresponding position of the bonding wire.

[0029] In this embodiment, the bonding wire matching structure is disposed at the position corresponding to the bonding wire, and is used to participate in the signal transmission process in an electrical manner in cooperation with the bonding wire, so as to improve the equivalent impedance characteristics of the bonding wire connection area.

[0030] The bonding wire matching structure includes an equivalent capacitance structure, which can be formed by at least one of the conductor layer, high-frequency signal transmission line, or pad structure in the multilayer LCP substrate. For example, different conductor layers, high-frequency signal transmission lines, or pad structures form an equivalent capacitance effect in an electrical sense through their spatial distribution in the multilayer LCP substrate and their electromagnetic interactions with each other. This allows the equivalent capacitance structure to work together with the bonding wire during high-frequency signal transmission and participate in the formation of the equivalent electrical characteristics of the signal transmission path. Thus, compared to using physical capacitors, the equivalent capacitance structure does not require the introduction of additional independent discrete components. Instead, it forms an equivalent capacitance effect in an electrical sense through the electromagnetic coupling relationship between existing conductor layers, high-frequency signal transmission lines, or pad structures in the multilayer LCP substrate. This helps reduce the complexity of the package structure and the space occupied by additional components. At the same time, since the equivalent capacitance structure can be integrally formed with the multilayer LCP substrate, its electrical characteristics have good synergy with the spatial distribution of high-frequency signal transmission lines and bonding wires. This helps to obtain more stable equivalent impedance characteristics under high-frequency or millimeter-wave conditions, thereby improving the overall performance of the signal transmission path in the bonding wire connection area and effectively reducing or avoiding the adverse effects of bonding wire parasitic parameters on the signal transmission performance between the chip and the substrate.

[0031] Alternatively, the bond wire matching structure includes a defective ground structure (DGS), which is disposed in a grounding conductor layer (denoted as the ground conductor layer) at the location corresponding to the bond wire. For example, by forming a local discontinuity structure in the ground conductor layer (such as etching a periodic or aperiodic grid structure on the ground conductor layer) as a defective ground structure, the electromagnetic distribution state of the ground conductor layer in that region is changed, thereby having an equivalent effect to the bond wire in an electrical sense. This allows the defective ground structure to adjust the equivalent impedance characteristics of the bond wire connection region without directly participating in signal conduction. Thus, compared to the case where no structural modulation is applied to the ground conductor layer, the defective ground structure, by adjusting the local electromagnetic environment within the ground conductor layer, ensures that the equivalent impedance characteristics of the bond wire connection region are no longer solely determined by the bond wire itself, but rather by the synergistic influence of the bond wire and the defective ground structure. This facilitates a smoother and more continuous impedance transition in the bond wire connection region. Simultaneously, since the defective ground structure is located within the ground conductor layer, it can adjust the equivalent impedance characteristics of the signal transmission path without directly participating in signal conduction, thereby avoiding the introduction of additional conduction structures into the signal path and helping to maintain the integrity and stability of the high-frequency signal transmission path. Furthermore, the defective ground structure can be integrally formed with the multilayer LCP substrate structure, and its electrical characteristics exhibit good synergy with the spatial distribution of the high-frequency signal transmission lines and bond wires. In high-frequency or millimeter-wave applications, this helps to obtain more stable equivalent impedance characteristics, thereby improving the overall signal transmission performance of the bond wire connection region and effectively reducing or mitigating the adverse effects of bond wire parasitic parameters on the high-frequency signal transmission performance between the chip and the substrate. Furthermore, since the defective ground structure can modulate the equivalent impedance characteristics of the signal transmission path in the bond wire connection area without directly participating in signal conduction, it can achieve the required impedance adjustment effect within the limited PCB layout space. This is because the defective ground structure can adjust the equivalent impedance characteristics of the signal transmission path in the bond wire connection area by modulating the equivalent inductance and equivalent capacitance characteristics of the ground conductor layer. Therefore, compared with the method of achieving impedance adjustment by widening the signal line or introducing an additional impedance transmission line, the defective ground structure can achieve the required impedance adjustment effect within the limited PCB layout space. This is beneficial to reduce the on-chip area of ​​the PCB structure, reduce (or improve) the complexity and manufacturing difficulty of the bond wire compensation structure and the corresponding PCB structure, and improve the miniaturization and integration level of the bond wire compensation structure, the corresponding PCB structure, and the corresponding high-frequency circuit.

[0032] Alternatively, the bonding wire matching structure can employ both the equivalent capacitance structure and the defective ground structure. Through this combination, the equivalent capacitance structure and the defective ground structure work together with the bonding wire in an electrical sense, so that the equivalent impedance characteristics of the signal transmission path are no longer determined by a single structure, but by the synergistic influence of the bonding wire, the equivalent capacitance structure, and the defective ground structure. This creates a continuous and stable impedance environment in the bonding wire connection area, which helps to reduce or avoid the adverse effects of bonding wire parasitic parameters on the signal transmission performance between the chip and the substrate.

[0033] For example, the bond wire matching structure can adopt different forms of equivalent electrical regulation methods according to different high-frequency application requirements to adapt to different operating frequency ranges and signal transmission requirements. For instance, in corresponding high-frequency application scenarios (such as the operating frequency range from DC to approximately 70 GHz), the bond wire matching structure can improve the impedance continuity of the bond wire connection area by introducing an equivalent capacitance structure to regulate the equivalent impedance characteristics of the bond wire during high-frequency signal transmission. For high-frequency application scenarios with further increased operating frequencies (such as the frequency range from approximately 75 GHz to 110 GHz, i.e., the W-band), the bond wire matching structure can enhance its ability to regulate the parasitic effects of the bond wire to adapt to higher frequency signals. For example, by introducing defective ground structures, the bond wire matching structure can exhibit a higher-order regulation effect in an equivalent electrical sense, thereby improving the compensation capability for high-frequency signals and broadening the frequency range for effectively regulating the parasitic effects of the bond wire (such as achieving W-band ultra-wideband transmission). In this way, the bonding wire matching structure can affect the electromagnetic distribution of the bonding wire connection area without directly changing the signal conduction path, making the equivalent electrical characteristics of the signal transmission path more suitable for the target high-frequency application requirements, thereby further improving the transmission performance of high-frequency signals in this area.

[0034] For example, when the bonding wire matching structure adopts an equivalent capacitance structure, the equivalent capacitance structure being located at the corresponding position of the bonding wire can be understood as follows: the equivalent capacitance structure is electrically associated with the signal node connected to the bonding wire, enabling it to participate in the formation of equivalent electrical characteristics of the signal transmission path together with the bonding wire during high-frequency signal transmission. For example, the equivalent capacitance structure can be formed by a pad structure located at one or both ends of the bonding wire, a conductor structure connected to the high-frequency signal transmission line, or by the spatial stacking relationship between different conductor layers in a multilayer LCP substrate, so that the equivalent capacitance structure is electrically connected in parallel or equivalent parallel with the bonding wire, thereby compensating for the parasitic inductance introduced by the bonding wire. In this case, even if the equivalent capacitance structure is not completely coincident with the bonding wire in geometric position, as long as it acts electrically on the same or related signal node as the bonding wire, it can be regarded as being located at the corresponding position of the bonding wire. Similarly, when the bonding wire matching structure employs a defective ground structure, its placement at the corresponding location of the bonding wire can be understood as follows: the defective ground structure is located within the conductor layer used for grounding, and electromagnetically, it lies within the electromagnetic field region influenced by the bonding wire. This allows it to adjust the equivalent electrical characteristics of the signal transmission path where the bonding wire is located. For example, the defective ground structure can be placed below, adjacent to, or in the grounding conductor layer region associated with the high-frequency signal transmission line, below the signal path corresponding to the bonding wire during high-frequency signal transmission. This allows the defective ground structure to adjust the equivalent impedance characteristics of the bonding wire connection region by altering the local electromagnetic distribution of the grounding conductor layer, without directly participating in signal conduction. In this case, strict geometric alignment between the defective ground structure and the bonding wire is not a necessary condition; as long as it can act on the signal transmission path where the bonding wire is located electrically or electromagnetically, it can be considered to be placed at the corresponding location of the bonding wire.

[0035] Optionally, the conductor layer includes a signal layer for signal transmission disposed on the surface of the multilayer LCP substrate, and a ground layer for grounding disposed inside or on the back of the multilayer LCP substrate; the high-frequency signal transmission line adopts a microstrip line structure, which is formed by a conductor strip disposed on the signal layer and a ground layer.

[0036] In this embodiment, a conductor layer (serving as a signal layer) disposed on the surface of the multilayer LCP substrate serves as a signal conductor. It includes a conductor strip extending along a predetermined trace direction (which can be formed from the signal layer through an etching process or through other conductor patterning processes suitable for high-frequency applications) for high-frequency signal transmission. A conductor layer (serving as a ground layer) disposed inside or on the back of the multilayer LCP substrate serves as a ground conductor, providing a reference potential and return path for signal transmission. The high-frequency signal transmission line adopts a microstrip line structure, which includes the conductor strip disposed on the signal layer and a ground layer disposed opposite it. The conductor strip and the ground layer are isolated from each other by an LCP dielectric layer in the multilayer LCP substrate, thereby forming a stable transmission line structure in the multilayer LCP substrate to meet the impedance control requirements of high-frequency signal transmission. In this microstrip line structure, because LCP material has characteristics such as low dielectric constant and stable frequency variation, low dielectric loss, and low water absorption, it can provide a stable electromagnetic transmission environment in high-frequency or millimeter-wave application scenarios, which helps to reduce dielectric loss during signal transmission and minimize the impact of external environmental changes on transmission characteristics. In some embodiments, the ground conductor layer (i.e., ground layer) disposed inside or on the back of the multilayer LCP substrate can also serve as a carrier for introducing defective ground structures. By performing local structural design on the ground conductor layer, it can be made to work electrically with the conductor strip and bonding wire disposed on the surface of the multilayer LCP substrate, thereby further improving the transmission performance of high-frequency signals in the microstrip line and bonding wire connection area.

[0037] Optionally, combined Figure 2 As shown, one end of the conductor strip of the microstrip line structure used for electrical connection to the chip via bonding wires has a T-shaped structure, and the T-shaped structure is electrically connected to the corresponding pin of the chip via bonding wires.

[0038] In this embodiment, the conductor strip of the microstrip line structure used for electrical connection to the chip via bonding wires has a T-shaped structure at its end near the chip pin. The T-shaped structure is electrically connected to the corresponding pin of the chip via the bonding wire. Specifically, the T-shaped structure includes a main section extending along the direction of the conductor strip and branch sections extending to both sides from the main section, so that the conductor strip forms a locally extended structure in the bonding wire connection area. By setting the T-shaped structure, it is convenient to provide connection positions for the bonding wires, and on the other hand, it can introduce an equivalent capacitance effect electrically, which interacts with the parasitic inductance introduced by the bonding wires, thereby adjusting the equivalent impedance characteristics of the bonding wire connection area. Thus, in the signal transmission path formed between the chip pin and the microstrip line structure, it is beneficial to reduce the impedance discontinuity problem caused by the parasitic parameters of the bonding wires, thereby reducing signal reflection and improving signal integrity.

[0039] Optionally, the dimensional parameters of the T-structure (such as branch length and width) can be designed according to the target frequency range and required impedance characteristics, so that the T-structure can compensate for the parasitic effects of the bonding wire in the corresponding frequency band, thereby further improving the signal transmission performance.

[0040] For example, combined Figure 2 As shown, a high-frequency signal transmission line for transmitting high-frequency signals is provided on a multilayer LCP substrate. The high-frequency signal transmission line includes a conductor strip disposed on the substrate surface. A chip is disposed on the multilayer LCP substrate and electrically connected to the high-frequency signal transmission line via bonding wires, thereby forming a signal transmission path between the chip and the high-frequency signal transmission line. At the corresponding position of the bonding wire connection area, a bonding wire matching structure is provided to adjust the parasitic parameters introduced by the bonding wire. Through the above structure, the electrical characteristics of the bonding wire connection area are no longer determined solely by the bonding wire, but are determined collaboratively by the bonding wire and the bonding wire matching structure. This forms a signal transmission path with preset impedance characteristics between the chip and the high-frequency signal transmission line, which helps to reduce impedance discontinuities, reduce signal reflection, and improve the transmission performance of high-frequency signals. In addition, an array of grounding vias (shielding vias) distributed around the high-frequency signal transmission line and the bonding wire connection area can be provided on the multilayer LCP substrate to form an electromagnetic shielding structure to suppress electromagnetic leakage and parasitic coupling, thereby improving the stability of high-frequency signal transmission.

[0041] For example, combined Figure 2 As shown, one end of the conductor strip of the microstrip line structure used for electrical connection to the chip via bonding wires has a T-shaped structure, which includes a long... l T ,Width w T The first part, and l 1. Width w The second part, the first part is used to connect the bonding wire, and w T > w This forms a T-shaped structure.

[0042] Optionally, the same high-frequency signal transmission line is electrically connected to the same pin of the chip via at least two parallel bonding wires.

[0043] In this embodiment, the same high-frequency signal transmission line and the same pin of the chip are electrically connected through at least two parallel bonding wires. That is, for a given node (or pad) of a high-frequency signal transmission line used to connect to a corresponding pin of the chip, it is electrically connected to the corresponding pin of the chip through at least two parallel bonding wires (the parallel bonding wires connect to the same electrical node), thus forming a parallel signal transmission path between the corresponding pin of the chip and the corresponding high-frequency signal transmission line. By using at least two parallel bonding wires, the high-frequency signal can be transmitted between the corresponding pin of the chip and the corresponding high-frequency signal transmission line via multiple bonding wires, thereby effectively distributing the parasitic effects introduced by a single bonding wire. This helps improve the equivalent electrical characteristics of the bonding wire connection area, making signal transmission in that area more stable.

[0044] For example, combined Figure 2 As shown, one end of the conductor strip of the microstrip line structure used for electrical connection to the chip via bonding wires is electrically connected to the corresponding pin of the chip via two parallel bonding wires. The diameter of the bonding wires is... d The spacing is s The arch height is h , length is l .

[0045] Optionally, the multilayer LCP substrate is formed by laminating an LCP copper-clad laminate and an LCP prepreg; the LCP copper-clad laminate includes an LCP dielectric layer and a conductor layer.

[0046] In this embodiment, the multilayer LCP substrate adopts a multilayer stacked structure. For example, the multilayer LCP substrate is formed by laminating LCP copper-clad laminates and LCP prepregs. This allows for the fabrication of the multilayer LCP substrate required for PCB structures based on the pre-prepared LCP copper-clad laminates and LCP prepregs, achieving the integration of multilayer dielectric and multilayer conductor structures. The LCP copper-clad laminate includes an LCP dielectric layer and a conductor layer disposed on the LCP dielectric layer. The conductor layer can be used to form high-frequency signal transmission lines, ground conductor layers, or other conductive structures. The LCP prepreg is disposed between adjacent LCP copper-clad laminates to achieve bonding and dielectric isolation between different layers during the lamination process. By stacking multiple LCP copper-clad laminates and LCP prepregs and performing a lamination process, a multilayer LCP substrate can be formed. The resulting multilayer LCP substrate generally includes multiple LCP dielectric layers and multiple conductor layers, facilitating the provision of dielectric support required for high-frequency signal transmission and providing corresponding conductive structures for signal traces, grounding, and chip interconnection.

[0047] For example, combined Figure 4As shown, the following explanation uses a four-layer LCP substrate as an example of a multilayer LCP substrate. The fabrication of a four-layer LCP substrate can use LCP copper-clad laminate (such as RF-705S type double-sided LCP copper-clad laminate) and LCP prepreg (such as R-BM17 type prepreg) as base materials. In the fabrication process, the LCP copper-clad laminate can first be cut to obtain a substrate of a predetermined size. Next, outer layer processing is performed, etching two double-sided copper-clad LCP boards into single-sided copper-clad structures, serving as the two outer layers of the four-layer LCP substrate. Then, inner layer processing is performed, using a development-etch-stripping (DES) process on one of the double-sided copper-clad LCP boards used as the inner layer substrate of the four-layer LCP substrate to pattern the conductor layers on its upper and lower surfaces, forming a predetermined inner conductor structure, thus completing the fabrication of the inner layer substrate between the two outer layers of the four-layer LCP substrate. Following this, a lamination process is performed, placing an adhesive sheet (i.e., an LCP prepreg) between the outer and inner layers, and aligning and stacking the outer, inner, and adhesive sheets according to a predetermined stacking order. The lamination process is then used to bond the aforementioned layers together, forming the four-layer LCP substrate. Finally, further outer layer processing is performed, using a YAG ultraviolet laser to perform through-hole processing and chip cavity etching on the four-layer LCP substrate, completing the fabrication of the four-layer LCP substrate. In the process of fabricating through-holes (with conductive materials electroplated in the through-holes) and etching the chip cavity on the four-layer LCP substrate, the processing can be tailored to the preset impedance characteristics of the required signal transmission path. The position and size of the through-holes and the geometry of the chip cavity are designed and processed accordingly, ensuring that after the chip is mounted in the chip cavity, its pins form a signal transmission path with the high-frequency signal transmission lines in the multilayer LCP substrate that meets the preset impedance requirements. Therefore, by combining the synergistic design of the through-hole structure and the chip cavity structure during the fabrication of the multilayer LCP substrate, not only can the structural requirements for chip packaging and interconnection be met, but it also facilitates the construction of a stable and continuous high-frequency impedance environment between the chip and the multilayer LCP substrate, thus providing a good electromagnetic foundation for subsequent high-frequency signal interconnection via bonding wires.

[0048] For example, combined Figure 3As shown, a four-layer LCP substrate is used as an example for illustration. The multilayer LCP substrate includes four conductor layers arranged sequentially from top to bottom. The conductor layers are insulated and isolated from each other by LCP dielectric layers and stacked to form a multilayer structure. The first (top) conductor layer forms the signal layer, with conductor strips on it, which are used to form high-frequency signal transmission lines. The fourth conductor layer forms the ground layer, providing a reference potential and return path for signal transmission, thus forming a microstrip line structure together with the signal layer. The second and third conductor layers serve as intermediate functional layers, and window structures can be provided on them. Aligned window structures can form cavities to accommodate chips, allowing chips to be embedded or partially embedded in the multilayer LCP substrate. This shortens the length of bonding wires in the signal transmission path and helps reduce the impact of bonding wire parasitic inductance on high-frequency signal transmission performance. In this multilayer structure, the conductor strip on the first conductor layer and the ground layer on the fourth layer are isolated by an LCP dielectric layer to form a microstrip line structure. Due to the low and stable dielectric constant, low dielectric loss, and low water absorption of LCP material, this microstrip line structure can provide a stable electromagnetic transmission environment in high-frequency or millimeter-wave applications, which helps reduce signal transmission loss and improve impedance control accuracy. In some embodiments, the fourth conductor layer can also serve as a carrier for introducing defective ground structures. By setting local discontinuities in the ground layer, the equivalent electrical characteristics of the signal transmission path can be adjusted, thereby further improving the transmission performance of high-frequency signals in the bonded wire connection region.

[0049] Another embodiment of the present invention provides a PCB structure including the bonding wire compensation structure for efficient interconnection of chips in the multilayer LCP substrate described above.

[0050] In this embodiment, the PCB structure adopts the bonding line compensation structure for efficient chip interconnection in the multilayer LCP substrate described above. Its advantages over the prior art are the same as those of the bonding line compensation structure compared to the prior art, and will not be repeated here.

[0051] Another embodiment of the present invention provides an electronic device, including the bonding wire compensation structure for efficient chip interconnection in the multilayer LCP substrate described above, or the PCB structure described above.

[0052] In this embodiment, the electronic device adopts the bonding wire compensation structure for efficient chip interconnection in the multilayer LCP substrate described above, or adopts the PCB structure with bonding wire compensation structure described above. Its advantages over the prior art are the same as the advantages of the bonding wire compensation structure over the prior art, and will not be repeated here.

[0053] Another embodiment of the present invention provides a method for designing a bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate, comprising: Based on the high-frequency signal transmission requirements of the chips on the multilayer LCP substrate, the corresponding signal transmission operating frequency band and the required preset impedance characteristics are determined.

[0054] The method in this embodiment is used to design a bonding line compensation structure for efficient interconnection of chips in a multilayer LCP substrate used in high-frequency signal transmission scenarios, so as to improve the signal transmission performance between chips and high-frequency signal transmission lines on the multilayer LCP substrate.

[0055] Specifically, based on the application scenarios, signal types, and operating conditions involved in the chip, the frequency range of the high-frequency signals that the chip needs to transmit in the multilayer LCP substrate or the corresponding PCB structure is determined, and the target impedance characteristics that the signal transmission path between the chip and the multilayer LCP substrate needs to meet are further determined as electrical constraints for subsequent structural design.

[0056] Based on the signal transmission operating frequency band and preset impedance characteristics, the first design parameters of the high-frequency signal transmission line on the multilayer LCP substrate are determined.

[0057] Specifically, based on the structure of the high-frequency signal transmission line, the geometric dimensions, routing method, and related structural parameters of the high-frequency signal transmission line on the multilayer LCP substrate are designed so that the high-frequency signal transmission line has transmission characteristics that match the preset impedance characteristics within the signal transmission operating frequency band.

[0058] The parasitic parameters generated when a high-frequency signal transmission line with the first design parameters is electrically connected to a chip via a bonding wire matching structure under the signal transmission operating frequency band are determined.

[0059] Specifically, based on the structural characteristics of the chip structure, high-frequency signal transmission line structure, and bonding wire, the signal transmission structure formed between the chip pins, high-frequency signal transmission line, and bonding wire can be analyzed to determine the parasitic parameters introduced by the bonding wire in the signal transmission operating frequency band, thereby evaluating the impact of parasitic parameters on the equivalent electrical characteristics of the signal transmission path.

[0060] Based on parasitic parameters, a target structure for a multilayer LCP substrate is determined for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line.

[0061] Specifically, the structure of the required multilayer LCP substrate can be designed based on the influence of parasitic parameters on impedance continuity, signal reflection and loss within the signal transmission operating frequency band. This allows the required multilayer LCP substrate to participate in the adjustment of the equivalent electrical characteristics of the signal transmission path in an electrical sense, thereby compensating for or mitigating the adverse effects of bond wire parasitic parameters.

[0062] Based on the first design parameters and the target structure, the high-frequency signal transmission line, bonding line and multilayer LCP substrate structure are designed collaboratively to determine the structure of the bonding line compensation structure for efficient chip interconnection in the multilayer LCP substrate.

[0063] Specifically, based on the first design parameters and the target structure, the high-frequency signal transmission line, bonding wire, and multilayer LCP substrate structure are co-designed to ensure that the chip, high-frequency signal transmission line, bonding wire, and LCP multilayer substrate are structurally and electrically matched. This creates a signal transmission path with preset impedance characteristics between the chip and the high-frequency signal transmission line, improving the overall performance and stability of the bonding wire compensation structure and the corresponding PCB structure under high-frequency signal transmission conditions. Furthermore, the determined bonding wire compensation structure can serve as the design basis for subsequent PCB structure implementation and manufacturing, guiding the arrangement of each layer in the PCB structure, the formation of conductor patterns, and the implementation of chip packaging and interconnection methods. This ensures that the actual fabricated PCB structure maintains consistency with the design results in terms of structure and electrical characteristics, guaranteeing that the high-frequency signal transmission performance meets design expectations.

[0064] Optionally, the parasitic parameters generated when a high-frequency signal transmission line with the first design parameters is electrically connected to the chip via a bonding wire matching structure in the signal transmission operating frequency band include: Based on the chip, high-frequency signal transmission lines and bonding wires using the first design parameters are modeled and simulated to determine the parasitic parameters of the bonding wires in the signal transmission operating frequency band.

[0065] When determining parasitic parameters, modeling and simulation analysis can be used. Specifically, electromagnetic modeling can be performed on the signal transmission structure formed by the chip, the high-frequency signal transmission line using the first design parameters, and the spatial morphology of the bonding wire, based on the chip's pin structure, the geometry of the high-frequency signal transmission line using the first design parameters, and the bonding wire. For example, during the modeling process, the chip pins, the high-frequency signal transmission line, and the bonding wire can be modeled as a whole structure to reflect its actual electrical behavior in the signal transmission operating frequency band. After completing the modeling, simulation analysis is performed on the model to obtain the parasitic parameters introduced by the bonding wire in the signal transmission operating frequency band. For example, the equivalent parasitic effects, such as parasitic inductance, parasitic capacitance, or combinations thereof, exhibited by the bonding wire during high-frequency signal transmission can be obtained through simulation analysis, thereby determining the parasitic parameter characteristics of the bonding wire in the corresponding operating frequency band.

[0066] Thus, the parasitic parameters obtained through the above modeling and simulation analysis can serve as the basis for determining the target structure of the LCP substrate and for co-designing the PCB structure. This allows for targeted adjustments to be made to the impact of the bonding line parasitic parameters on the equivalent electrical characteristics of the signal transmission path during the subsequent design process, thereby improving the overall performance between the chip and the high-frequency signal transmission line under high-frequency signal transmission conditions.

[0067] Optionally, based on parasitic parameters, the target structure of the multilayer LCP substrate for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line includes: Based on the distribution characteristics of parasitic parameters within the signal transmission operating frequency band, the type of bond wire matching structure used to adjust the equivalent electrical characteristics is determined; wherein, the bond wire matching structure includes at least one of equivalent capacitance structure and defective ground structure; The target structure is determined based on the identified bond line matching structure type.

[0068] Specifically, when designing the structure of a multilayer LCP substrate, the variation trend of parasitic parameters in the signal transmission operating frequency band, frequency response characteristics, and their influence on the continuity of the equivalent impedance of the signal transmission path can be analyzed to determine the appropriate type of bonding wire matching structure. When parasitic parameters primarily cause equivalent impedance shifts or local impedance mismatches within the target frequency band, an equivalent capacitance structure can be selected as the bonding wire matching structure type. This allows the equivalent capacitance structure to work synergistically with the bonding wire in an electrical sense to adjust the equivalent electrical characteristics of the signal transmission path. Conversely, when parasitic parameters significantly affect the equivalent electrical characteristics of the signal transmission path at higher frequencies, and it is necessary to adjust the electromagnetic distribution without directly altering the signal conduction path, a defective ground structure can be selected as the bonding wire matching structure type. By introducing a defective ground structure into the ground conductor layer of the multilayer LCP substrate, the defective ground structure participates in adjusting the equivalent electrical characteristics of the signal transmission path in an electrical sense, thereby improving the impedance continuity of the bonding wire connection area. Furthermore, based on the comprehensive impact of parasitic parameters within the signal transmission operating frequency band, both an equivalent capacitance structure and a defective ground structure can be selected as bonding wire matching structure types, allowing them to work synergistically to obtain a signal transmission path that better conforms to the preset impedance characteristics.

[0069] Once the bonding wire matching structure type is determined, the structure of the multilayer LCP substrate can be designed accordingly to form the target structure. For example, when the bonding wire matching structure type is an equivalent capacitance structure, the spatial arrangement of conductor layers, high-frequency signal transmission lines, or pad structures in the multilayer LCP substrate can electrically form an equivalent capacitance effect that works in conjunction with the bonding wire, thereby allowing the equivalent capacitance structure to participate in the adjustment of the equivalent electrical characteristics of the signal transmission path. When the bonding wire matching structure type is a defective ground structure, a corresponding defective ground structure can be set in the ground conductor layer of the multilayer LCP substrate to change the electromagnetic distribution state of the area, thereby adjusting the equivalent impedance characteristics of the bonding wire connection area without directly participating in signal conduction. When both the equivalent capacitance structure and the defective ground structure are selected as bonding wire matching structure types, the equivalent capacitance structure and the defective ground structure can be introduced together in the multilayer LCP substrate, allowing them to work together electrically to form a target structure for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line. Thus, by designing the multilayer LCP substrate structure specifically based on the type of bonding wire matching structure, the target structure is determined, enabling the multilayer LCP substrate to cooperate with the bonding wires and high-frequency signal transmission lines at the structural level. This allows a signal transmission path with preset impedance characteristics to be constructed between the chip and the high-frequency signal transmission lines, which helps to improve the impedance continuity of the bonding wire connection area and enhance the stability and reliability of high-frequency signal transmission.

[0070] For example, to investigate the impact of different bond wire matching structure types on signal transmission performance in different high-frequency operating bands, an electromagnetic simulation model can be established based on the chip, high-frequency signal transmission line, and bond wire. A comparative analysis can be conducted on different schemes, including those without a bond wire matching structure, those with an equivalent capacitance structure, and those with a defective ground structure. The simulation results show that in relatively low high-frequency operating bands (e.g., from DC to approximately 70 GHz), introducing an equivalent capacitance structure at the corresponding position of the bond wire allows the parasitic inductance of the bond wire and the equivalent capacitance to form a higher-order compensation structure in an electrical sense. This effectively improves the impedance continuity of the signal transmission path in the bond wire connection area, significantly improving return loss and insertion loss compared to the uncompensated structure. However, in high-frequency application scenarios with further increased operating frequencies (e.g., from approximately 75 GHz to 110 GHz), the compensation capability of a single equivalent capacitance structure for the parasitic effects of the bond wire is limited. By introducing a defective ground structure in the ground conductor layer, the signal transmission path exhibits a higher-order equivalent modulation effect in an electrical sense, further broadening the effective compensation bandwidth and significantly improving signal transmission performance at higher frequency bands. Therefore, by modeling and simulating different types of bond wire matching structures, we can not only verify the applicability advantages of various matching structures in different frequency bands, but also provide a basis for selecting the appropriate bond wire matching structure type based on the parasitic parameter distribution characteristics, thereby improving the overall signal transmission performance of the designed PCB structure in high-frequency or millimeter-wave application scenarios.

[0071] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate, characterized in that, The invention includes bonding wires and bonding wire matching structures disposed on the multilayer LCP substrate; the multilayer LCP substrate is provided with high-frequency signal transmission lines and chips, and the corresponding pins of the chips are electrically connected to the corresponding high-frequency signal transmission lines through the bonding wires; the bonding wire matching structure is disposed on the multilayer LCP substrate at a position corresponding to the bonding wires, and the bonding wire matching structure and the bonding wires form a signal transmission path with preset impedance characteristics.

2. The bonding line compensation structure for high-efficiency chip interconnection in a multilayer LCP substrate as described in claim 1, characterized in that, The multilayer LCP substrate includes at least one LCP dielectric layer and at least one conductor layer, wherein the LCP dielectric layer and the conductor layer are stacked. The bonding wire matching structure includes an equivalent capacitance structure disposed at the corresponding position of the bonding wire, the equivalent capacitance structure being formed by at least one of the conductor layer of the multilayer LCP substrate, the high-frequency signal transmission line, or the pad structure; and / or, the bonding wire matching structure includes a defect ground structure in the conductor layer for grounding disposed at the corresponding position of the bonding wire.

3. The bonding line compensation structure for high-efficiency chip interconnection in a multilayer LCP substrate as described in claim 2, characterized in that, The conductor layer includes a signal layer for signal transmission disposed on the surface of the multilayer LCP substrate, and a ground layer for grounding disposed inside or on the back of the multilayer LCP substrate; the high-frequency signal transmission line adopts a microstrip line structure, which is formed by a conductor strip disposed on the signal layer and the ground layer.

4. The bonding line compensation structure for high-efficiency chip interconnection in a multilayer LCP substrate as described in claim 3, characterized in that, One end of the conductor strip of the microstrip line structure, which is used for electrical connection to the chip via the bonding wire, is in a T-shape, and the T-shape is electrically connected to the corresponding pin of the chip via the bonding wire.

5. The bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate as described in any one of claims 1-4, characterized in that, The same high-frequency signal transmission line is electrically connected to the same pin of the chip via at least two parallel bonding wires.

6. The bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate as described in any one of claims 2-4, characterized in that, The multilayer LCP substrate is formed by laminating an LCP copper-clad laminate and an LCP prepreg; the LCP copper-clad laminate includes the LCP dielectric layer and the conductor layer.

7. A PCB structure, characterized in that, Includes a bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate as described in any one of claims 1-6.

8. A method for designing a bonding line compensation structure for efficient chip interconnection in a multilayer LCP substrate, characterized in that, include: Based on the high-frequency signal transmission requirements of the chips on the multilayer LCP substrate, determine the corresponding signal transmission operating frequency band and the required preset impedance characteristics. Based on the signal transmission operating frequency band and the preset impedance characteristics, the first design parameters of the high-frequency signal transmission line on the multilayer LCP substrate are determined. The parasitic parameters generated when the high-frequency signal transmission line with the first design parameters is electrically connected to the chip through a bonding wire matching structure under the signal transmission operating frequency band are determined. Based on the parasitic parameters, a target structure for a multilayer LCP substrate is determined for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line. Based on the first design parameters and the target structure, the high-frequency signal transmission line, the bonding line, and the multilayer LCP substrate structure are designed collaboratively to determine the structure of the bonding line compensation structure for efficient chip interconnection in the multilayer LCP substrate.

9. The bonding line compensation structure design method for high-efficiency chip interconnection in a multilayer LCP substrate as described in claim 8, characterized in that, The parasitic parameters generated when the high-frequency signal transmission line with the first design parameters is electrically connected to the chip via the bonding wire matching structure under the signal transmission operating frequency band include: Based on the chip, the high-frequency signal transmission line using the first design parameters, and the bonding wire, modeling and simulation analysis are performed to determine the parasitic parameters of the bonding wire in the signal transmission operating frequency band.

10. The bonding line compensation structure design method for high-efficiency chip interconnection in a multilayer LCP substrate as described in claim 8, characterized in that, The step of determining the target structure of the multilayer LCP substrate for adjusting the equivalent electrical characteristics of the signal transmission path between the chip and the high-frequency signal transmission line based on the parasitic parameters includes: Based on the distribution characteristics of the parasitic parameters within the signal transmission operating frequency band, the type of bond wire matching structure used to adjust the equivalent electrical characteristics is determined; wherein, the bond wire matching structure includes at least one of equivalent capacitance structure and defective ground structure; The target structure is determined based on the determined bond line matching structure type.

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