High-thermal-conductivity low-warp bridge type ceramic packaging substrate structure and manufacturing method

Abstract

The application belongs to the technical field of semiconductor chip packaging, and discloses a high-thermal-conductivity low-warp bridge type ceramic packaging substrate structure and a manufacturing method. The upper surface and the lower surface of the ceramic core plate in the high-thermal-conductivity low-warp bridge type ceramic packaging substrate structure are symmetrically provided with ABF / PP / PI composite layers, the bridge chip is closely attached to the metal layer boss, and the chip pads in the interconnection surface of the bridge chip are electrically connected to the metal wiring layer. The manufacturing method comprises the following steps: S11, ceramic core plate preparation; S12, bottom composite layer manufacturing, slotting and blind hole processing; S13, bridge chip mounting; S14, upper ABF / PP / PI composite layer laminating; and S15, substrate surface treatment and packaging integration. The application can greatly improve the chip power upper limit, reduce the warping risk, meet the high-speed interconnection demand, realize 2.5D packaging at low cost, reduce the industry threshold, and is mature, controllable and highly adaptable to mass production.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging technology, specifically relating to a high thermal conductivity, low warpage bridging ceramic packaging substrate structure and its fabrication method. Background Technology

[0002] Against the backdrop of rapid iteration in high-end electronic information industries such as artificial intelligence, cloud computing, and 5G communication, high-performance chips, HBM and other devices are continuously upgrading towards high integration and high power consumption. Electronic devices have dramatically increased their requirements for high performance, miniaturization, high reliability and long life of chips. Traditional packaging substrates can no longer meet the multiple stringent requirements of systems for heat dissipation efficiency, dimensional stability, high-speed interconnect performance, high-density wiring, integration adaptability and low-cost mass production.

[0003] As the core carrier of chip packaging, the packaging substrate undertakes key functions such as electrical interconnection, heat dissipation, structural support and protection, and system integration. For every 10°C increase in chip operating temperature, its lifespan decreases by about 50%. The performance shortcomings caused by insufficient heat dissipation of traditional substrates will directly lead to the degradation of chip signal transmission, decrease in reliability, and shorten lifespan, which has become a key technical bottleneck restricting the overall performance and large-scale application of high-end semiconductor packaging.

[0004] The three mainstream solutions in the current semiconductor packaging field—ABF / BT (PP) multilayer packaging substrates, 2.5D packaging substrates, and fan-out coreless substrates—cannot fully meet the advanced packaging requirements of high-end computing chips and HBM chips. They generally suffer from five major defects: First, due to the significant difference in thermal expansion coefficients between the organic substrate and copper foil, ABF / BT (PP) multilayer substrates are prone to irreversible warping deformation, leading to poor soldering reliability, cold solder joints, desoldering, and degradation of high-frequency signal transmission. Second, the organic substrate has extremely low thermal conductivity, resulting in insufficient heat dissipation capacity and an inability to dissipate heat from high-power chips in a timely manner, easily causing overheating and heat accumulation. Third, limited by high dielectric loss and traditional wiring structures, high-speed interconnect performance is insufficient, making it difficult to meet the requirements of high bandwidth and ultra-high-speed signal transmission. Fourth, 2.5D packaging substrates rely on silicon interposers and ultra-high precision processes, which are complex, have long cycles, low yields, and high costs, making them unsuitable for cost-sensitive mass production. Fifth, existing bridging packaging structures have poor compatibility with embedded chips, and heat accumulation can easily lead to heat dissipation failure. Furthermore, increased temperature can significantly reduce chip performance and accelerate material aging.

[0005] Existing packaging substrate technologies cannot simultaneously meet the core technical requirements of high thermal conductivity, low warpage, high trace density, high integration, high-speed interconnection, and low-cost mass production. This has become a key technical barrier restricting the large-scale and low-cost application of high-performance chips and HBM chips in high-end packaging. Summary of the Invention

[0006] The purpose of this invention is to provide a high thermal conductivity, low warpage bridging ceramic packaging substrate structure and manufacturing method to solve at least one of the above-mentioned problems in the prior art.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: On one hand, the present invention provides a high thermal conductivity, low warpage bridging ceramic packaging substrate structure, including a ceramic core board, an ABF / PP / PI composite layer, a bridging chip, a solder resist layer and surface pads; The ceramic core board comprises a ceramic substrate and a ceramic core metal layer. The ceramic substrate has only a few interconnecting holes penetrating the upper and lower surfaces; the remaining area is a completely flat structure except for the interconnecting holes. The ceramic core metal layer consists of a ceramic core board metal filler and an electroplated copper coating layer. The ceramic core board metal filler fills the interior of the interconnecting holes, and the electroplated copper coating layer completely covers the upper and lower surfaces of the ceramic substrate and the walls of the interconnecting holes. The surface of the electroplated copper coating layer is provided with metal layer bosses and connecting pads, and the connecting pads on the upper and lower surfaces of the ceramic substrate are electrically connected through the ceramic core metal layer. The ceramic substrate is made of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond, a high thermal conductivity ceramic material. The ceramic core board has symmetrically arranged ABF / PP / PI composite layers on its upper and lower surfaces, so that the ceramic core board and the ABF / PP / PI composite layers on its upper and lower surfaces cooperate to form a bridged ceramic encapsulation composite substrate. The ABF / PP / PI composite layer is composed of multiple layers of ABF / PP / PI dielectric layers. Each ABF / PP / PI dielectric layer has a metal trace layer on its outer side. Blind holes are opened between adjacent metal trace layers. Solid copper pillars that connect adjacent metal trace layers are electroplated in the blind holes. The multiple ABF / PP / PI dielectric layers and the corresponding metal trace layers close to the ceramic core board have slots that match the position and size of the metal layer bosses. The slots expose the surface of the metal layer bosses. The bridging chip is mounted in the slot and is tightly attached to the metal layer boss; the interconnect surface of the bridging chip is provided with chip pads, and the chip pads are electrically connected to the metal trace layer through corresponding blind vias inside the ABF / PP / PI composite layer. The outermost ABF / PP / PI dielectric layer is covered with a solder mask layer. The surface pads are located outside the solder mask layer and are electrically connected to the inner metal trace layer through solid copper pillars in blind vias. The HBM and computing chip are flip-chip mounted on surface pads for electrical connection. The back of the HBM and computing chip are connected to the heat sink via TIM adhesive. A back power supply structure is provided on the back of the bridged ceramic packaged composite substrate, and IPD passive devices / SiC chips / GaN chips are provided on the back power supply structure.

[0008] As a preferred technical solution of the present invention, the ceramic core metal layer is an integrated electroplated structure with the ceramic core plate metal filler and the electroplated copper coating layer, and the ceramic core plate metal filler is a conductive filler structure that fills the interconnect holes.

[0009] As a preferred technical solution of the present invention, the electroplated copper coating layer is polished to form a flat double-sided copper layer structure, which, together with the grooveless ceramic substrate, constitutes a high-rigidity support substrate.

[0010] As a preferred technical solution of the present invention, the outline dimensions of the metal layer boss correspond to and match the outline dimensions of the slot, and the top surface of the metal layer boss serves as the mounting support surface and thermal contact surface for bridging the chip.

[0011] As a preferred technical solution of the present invention, the bridging chip is an embedded silicon or glass bridging chip, which is mounted in the slot by means of a DAF film.

[0012] As a preferred technical solution of the present invention, the embedded silicon or glass bridging chip is a high-density interconnect bridging device. The embedded silicon or glass bridging chip realizes high-speed signal interconnection between the computing chip and HBM through the cooperation of its own chip pads and blind holes and metal traces inside the composite layer.

[0013] As a preferred technical solution of the present invention, the bridging chip is an embedded silicon or glass three-dimensional bridging chip, which is mounted in the slot by conductive adhesive; and the embedded silicon or glass three-dimensional bridging chip is provided with TSV / TGV for realizing three-dimensional connection inside the chip.

[0014] As a preferred technical solution of the present invention, the embedded silicon or glass three-dimensional bridging chip is a high-density three-dimensional interconnect bridging device. The embedded silicon or glass three-dimensional bridging chip realizes high-speed signal interconnection between the computing chip and HBM through the cooperation of its internal TSV / TGV with its own chip pads, blind holes inside the composite layer, and metal traces.

[0015] On the other hand, for embedded silicon or glass bridging chips, the present invention also provides a method for fabricating a high thermal conductivity, low warpage bridging ceramic packaging substrate structure, comprising the following steps: S11, Ceramic core plate preparation: A ceramic substrate made of high thermal conductivity ceramic materials such as alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond is selected. The ceramic substrate is then subjected to grinding, ultrasonic cleaning, and drying. Several interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate are processed using laser drilling. The interconnecting holes are filled with ceramic core metal filler. The entire ceramic substrate is electroplated, forming an electroplated copper coating layer on its upper and lower surfaces and the walls of the interconnecting holes. The ceramic core metal filler and the electroplated copper coating layer together constitute the ceramic core metal layer. Then, metal layer bosses and connecting pads are processed on the surface of the electroplated copper coating layer using etching or electroplating layering processes to obtain the ceramic core board. S12. Fabrication of the bottom composite layer and grooving, blind hole processing: Multiple ABF / PP / PI dielectric layers are laminated onto the upper and lower surfaces of the ceramic core board to form a bottom composite layer. A metal trace layer is fabricated on the outside of each ABF / PP / PI dielectric layer. Grooves adapted to the metal layer bosses are machined on the multiple metal trace layers and the corresponding ABF / PP / PI dielectric layers to expose the surface of the metal layer bosses. At the same time, blind vias are machined on each ABF / PP / PI dielectric layer and electroplated to form solid copper pillars. The solid copper pillars enable electrical connections between adjacent metal trace layers and between the ceramic core board and adjacent metal trace layers. S13, Embedded Bridge Chip Mounting: The embedded silicon or glass bridge chip is mounted in the slot using a DAF film, so that the embedded silicon or glass bridge chip is tightly attached to the metal layer boss; the interconnection alignment of the chip pads on the embedded silicon or glass bridge chip and the blind vias inside the bottom composite layer is completed simultaneously. S14, Upper ABF / PP / PI composite laminate: The process of repeatedly laminating ABF / PP / PI dielectric layers, preparing metal trace layers, processing blind vias, and electroplating solid copper pillars on the surface of the bottom composite layer is used to form the upper ABF / PP / PI composite layer. Each metal trace layer in the upper ABF / PP / PI composite layer is patterned. By stacking the upper ABF / PP / PI composite layer on the surface of the bottom composite layer, a set number of ABF / PP / PI composite layers are obtained, and the ceramic core board is combined with the ABF / PP / PI composite layers on its upper and lower surfaces to form a bridged ceramic packaging composite substrate. S15. Substrate surface treatment and packaging integration: A solder resist layer is coated on the outermost ABF / PP / PI dielectric layer. Surface pads are fabricated on the outside of the solder resist layer, and corresponding blind vias are machined to achieve electrical connection between the surface pads and the inner metal trace layer. The HBM and computing chip are mounted on the surface pads using the MCM flip-chip packaging process. IPD passive devices / SiC chips / GaN chips are mounted on the back power supply structure at the bottom of the bridged ceramic package composite substrate. TIM adhesive is coated on the back of the HBM and computing chip, and a heat sink is attached to complete the bridged 2.5D advanced packaging.

[0016] On the other hand, for embedded silicon or glass three-dimensional bridging chips, the present invention also provides a method for fabricating a high thermal conductivity, low warpage bridging ceramic packaging substrate structure, comprising the following steps: S11, Ceramic core plate preparation: A ceramic substrate made of high thermal conductivity ceramic materials such as alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond is selected. The ceramic substrate is then subjected to grinding, ultrasonic cleaning, and drying. Several interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate are processed using laser drilling. The interconnecting holes are filled with ceramic core metal filler. The entire ceramic substrate is electroplated, forming an electroplated copper coating layer on its upper and lower surfaces and the walls of the interconnecting holes. The ceramic core metal filler and the electroplated copper coating layer together constitute the ceramic core metal layer. Then, metal layer bosses and connecting pads are processed on the surface of the electroplated copper coating layer using etching or electroplating layering processes to obtain the ceramic core board. S12. Fabrication of the bottom composite layer and grooving, blind hole processing: Multiple ABF / PP / PI dielectric layers are laminated onto the upper and lower surfaces of the ceramic core board to form a bottom composite layer. A metal trace layer is fabricated on the outside of each ABF / PP / PI dielectric layer. Grooves adapted to the metal layer bosses are machined on the multiple metal trace layers and the corresponding ABF / PP / PI dielectric layers to expose the surface of the metal layer bosses. At the same time, blind vias are machined on each ABF / PP / PI dielectric layer and electroplated to form solid copper pillars. The solid copper pillars enable electrical connections between adjacent metal trace layers and between the ceramic core board and adjacent metal trace layers. S13, Embedded Bridge Chip Mounting: The embedded silicon or glass 3D bridging chip is mounted in the slot using conductive adhesive, so that the embedded silicon or glass 3D bridging chip is tightly attached to the metal layer boss; at the same time, the interconnection alignment of the chip pads on the embedded silicon or glass 3D bridging chip and the blind vias inside the bottom composite layer is completed. S14, Upper ABF / PP / PI composite laminate: The process of repeatedly laminating ABF / PP / PI dielectric layers, preparing metal trace layers, processing blind vias, and electroplating solid copper pillars on the surface of the bottom composite layer is used to form the upper ABF / PP / PI composite layer. Each metal trace layer in the upper ABF / PP / PI composite layer is patterned. By stacking the upper ABF / PP / PI composite layer on the surface of the bottom composite layer, a set number of ABF / PP / PI composite layers are obtained, and the ceramic core board is combined with the ABF / PP / PI composite layers on its upper and lower surfaces to form a bridged ceramic packaging composite substrate. S15. Substrate surface treatment and packaging integration: A solder resist layer is coated on the outermost ABF / PP / PI dielectric layer. Surface pads are fabricated on the outside of the solder resist layer, and corresponding blind vias are machined to achieve electrical connection between the surface pads and the inner metal trace layer. The HBM and computing chip are mounted on the surface pads using the MCM flip-chip packaging process. IPD passive devices / SiC chips / GaN chips are mounted on the back power supply structure at the bottom of the bridged ceramic package composite substrate. TIM adhesive is coated on the back of the HBM and computing chip, and a heat sink is attached to complete the bridged 2.5D advanced packaging.

[0017] Beneficial effects: 1. Two-way high thermal conductivity heat dissipation significantly increases the chip's power limit. Using high thermal conductivity ceramic as the core board substrate, the bridging chip is directly bonded to the metal layer protrusion of the ceramic core board, forming a dedicated low-resistance heat conduction path downwards; at the same time, the HBM and the back of the computing chip are directly connected to the heat sink through TIM adhesive, forming an upward main heat dissipation path. The bidirectional collaborative heat dissipation effectively solves the problems of heat accumulation in embedded chips and overheating of high-power chips, significantly improving the chip's working stability and lifespan, and releasing the performance potential of high-power chips.

[0018] 2. High-rigidity symmetrical structure, significantly reducing the risk of warping. The grooveless flat ceramic core board itself has excellent structural rigidity. Combined with the symmetrical stacked ABF / PP / PI composite layer design on the upper and lower surfaces, it can effectively offset interlayer thermal stress, significantly reduce the warpage of large-size substrates, ensure dimensional stability during the packaging process, avoid problems such as solder joint cracking and interconnect failure caused by substrate deformation, and improve packaging yield.

[0019] 3. High trace density design to meet high-speed interconnect requirements. By embedding the bridging chip in the organic wiring dielectric layer, the chip pads of the bridging chip are directly interconnected with the multi-layer wiring through blind vias inside the composite layer. Combined with the multi-layer patterned wiring and the low-impedance structure of the blind via solid copper pillars, ultra-high trace density and low-loss high-speed signal transmission are achieved. This can fully meet the high-bandwidth, high-speed signal interconnection requirements between computing chips and HBM, and is suitable for high-integration computing packaging scenarios.

[0020] 4. Low-cost 2.5D packaging, lowering the industry barrier. This solution eliminates the need for the silicon interposer and ultra-high precision processing equipment required for traditional 2.5D packaging. It achieves an equivalent 2.5D interconnect effect solely through mature substrate manufacturing processes and MCM flip-chip packaging, significantly simplifying the process flow, reducing manufacturing costs, and combining high cost-effectiveness with high practicality. This can promote the large-scale application of high-end computing power packaging.

[0021] 5. The process is mature and controllable, with strong adaptability to mass production. The overall manufacturing process is based on mature semiconductor processes such as laser drilling, electroplating, dielectric lamination, and machining, with clear and controllable steps. The metal layer protrusions can serve as both a slotting positioning reference and a chip mounting support, making it easy to bridge chip embedding and interconnect alignment processes without the need for additional special equipment, thus meeting the needs of large-scale industrial production. Attached Figure Description

[0022] Figure 1 This is a schematic cross-sectional view of the ceramic core board of the present invention. Figure 2 This is a schematic diagram showing that an ABF / PP / PI dielectric layer is provided on both the upper and lower surfaces of the ceramic core plate of the present invention. Figure 3 This is a schematic diagram of the fabrication, grooving, and blind hole processing of the bottom composite layer according to the present invention; Figure 4 This is a schematic diagram of the embedded silicon or glass bridging chip of the present invention embedded in a slot. Figure 5 This is a schematic diagram of the finished product of the bridged ceramic packaging composite substrate structure when the embedded silicon or glass bridged chip is used in this invention. Figure 6 This is a circuit packaging diagram of the present invention when using an embedded silicon or glass three-dimensional bridging chip. Figure 7 This is a schematic diagram of the embedded silicon or glass three-dimensional bridging chip of the present invention embedded in a slot. Figure 8 This is a schematic diagram of the finished product of the bridged ceramic packaging composite substrate structure when the embedded silicon or glass three-dimensional bridged chip is used in this invention. Figure 9 This is a schematic diagram of the circuit package when the present invention uses an embedded silicon or glass bridging chip.

[0023] In the diagram: 001 - Bridged ceramic packaging composite substrate; 100 - Ceramic core board; 101 - Ceramic substrate; 210 - Electroplated copper coating layer; 220 - Ceramic core metal layer; 230 - Blind via; 240 - Metal trace layer; 241 - Metal layer boss; 250 - Surface pad; 300 - ABF / PP / PI composite layer; 310 - Ceramic core board metal filler; 320 - ABF / PP / PI dielectric layer; 330 - Solder resist layer; 401 - TIM adhesive; 420 - DAF film; 510 - Embedded silicon or glass bridging chip; 520 - Embedded silicon or glass 3D bridging chip; 530 - IPD passive device / SiC chip / GaN chip; 550 - HBM; 560 - Computing chip; 601 - TSV / TGV; 602 - Chip pad. Detailed Implementation

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0025] Example: like Figures 1-9As shown, this embodiment provides a high thermal conductivity, low warpage bridging ceramic packaging substrate structure, including a ceramic core board 100, an ABF / PP / PI composite layer 300, a bridging chip, a solder resist layer 330, and surface pads 250 (the bridging chip can be an embedded silicon or glass bridging chip 510, or an embedded silicon or glass three-dimensional bridging chip 520). The ABF / PP / PI composite layer 300 can be an ABF composite layer, a PP composite layer, or a PI composite layer. The embedded silicon or glass bridging chip 510 can be an embedded silicon bridging chip or an embedded glass bridging chip. The embedded silicon or glass three-dimensional bridging chip 520 can be an embedded silicon three-dimensional bridging chip or an embedded glass three-dimensional bridging chip, configured according to actual conditions and requirements. The ceramic core board 100 includes a ceramic substrate. The ceramic substrate 101 consists of a ceramic core metal layer 220. The ceramic substrate 101 has several interconnect holes penetrating its upper and lower surfaces; the remaining area is a completely flat structure except for the interconnect holes. The ceramic core metal layer 220 is composed of a ceramic core metal filler 310 and an electroplated copper coating layer 210. The ceramic core metal filler 310 fills the interconnect holes, and the electroplated copper coating layer 210 completely covers the upper and lower surfaces of the ceramic substrate 101 and the walls of the interconnect holes, forming a double-sided copper layer structure. The surface of the electroplated copper coating layer 210 is provided with metal layer bosses 241 and connecting pads, and the connecting pads on the upper and lower surfaces of the ceramic substrate 101 are electrically connected through the ceramic core metal layer 220. The ceramic substrate 101 is made of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond high thermal conductivity ceramic material.

[0026] The ceramic core board 100 has symmetrically arranged ABF / PP / PI composite layers 300 on its upper and lower surfaces, so that the ceramic core board 100 and the ABF / PP / PI composite layers 300 on its upper and lower surfaces cooperate to form a bridged ceramic encapsulation composite substrate 001; the ABF / PP / PI composite layer 300 is composed of multiple layers of ABF / PP / PI dielectric layers 320, and corresponding to the ABF / PP / PI composite layer 300, the ABF / PP / PI dielectric layer 320 can be an ABF dielectric layer, a P ... The P-dielectric layer or PI-dielectric layer is selected according to the actual situation. Each ABF / PP / PI dielectric layer 320 is provided with a metal trace layer 240 on the outside. A blind hole 230 is opened between adjacent metal trace layers 240. A solid copper pillar connecting the adjacent metal trace layers 240 is electroplated in the blind hole 230. The multilayer ABF / PP / PI dielectric layer 320 and the corresponding metal trace layer 240 near the ceramic core board 100 are processed with slots that match the position and size of the metal layer boss 241. The slots expose the surface of the metal layer boss 241.

[0027] When the bridging chip is an embedded silicon or glass bridging chip 510, the embedded silicon or glass bridging chip 510 is mounted in the slot via a DAF film 420, and the embedded silicon or glass bridging chip 510 is tightly bonded to the metal layer protrusion 241, forming a direct heat conduction path; the interconnect surface of the embedded silicon or glass bridging chip 510 is provided with chip pads 602, and the chip pads 602 are electrically connected to the metal trace layer 240 through corresponding blind vias 230 inside the ABF / PP / PI composite layer 300; when the bridging chip is an embedded silicon or glass three-dimensional bridging chip 520, the embedded silicon or glass three-dimensional bridging chip 520 is mounted in the slot via conductive adhesive 430, and the embedded silicon or glass three-dimensional bridging chip 52 ... interconnect surface of the embedded silicon or glass bridging chip 510 is tightly bonded to the metal layer protrusion 241, forming a direct heat conduction path; the interconnect surface of the embedded silicon or glass bridging chip 510 is The chip 520 is tightly attached to the metal layer protrusion 241 to form a direct heat conduction path; the embedded silicon or glass three-dimensional bridging chip (520) is provided with TSV / TGV601 for realizing three-dimensional interconnection inside the chip; the interconnect surface of the embedded silicon or glass three-dimensional bridging chip 520 is provided with chip pad 602, and the chip pad 602 is electrically connected to the metal trace layer 240 through the corresponding blind via 230 inside the ABF / PP / PI composite layer 300; the outermost ABF / PP / PI dielectric layer 320 is covered with a solder resist layer 330, and the surface pad 250 is provided outside the solder resist layer 330, and the surface pad 250 is electrically connected to the inner metal trace layer 240 through the solid copper pillar in the blind via 230.

[0028] The HBM550 and computing chip 560 are flip-chip mounted on surface pad 250 for electrical connection. The back sides of the HBM550 and computing chip 560 are connected to the heat sink via TIM adhesive 401 to form a heat dissipation path. The back side of the bridged ceramic packaged composite substrate 001 is provided with a back power supply structure, on which IPD passive devices / SiC chips / GaN chips 530 are provided. These can be IPD passive devices, SiC chips, or GaN chips, depending on the actual situation and requirements.

[0029] As a preferred embodiment of this invention, it should be further explained that the ceramic core metal filler 310 and the electroplated copper coating layer 210 in the ceramic core metal layer 220 are an integrated electroplated structure, which significantly reduces the contact resistance of the interconnect path and eliminates the additional thermal resistance caused by the layered bonding surface, further enhancing the overall thermal and electrical conductivity of the substrate, and meeting the stable working requirements of high-performance chips under long-term high-load operation. The ceramic core metal filler 310 is a conductive filler structure that fills the interconnect holes. The hole diameter and filling density of the ceramic core metal filler 310 can be flexibly adjusted according to the interconnect layout and power density requirements of HBM550 and computing chip 560, maximizing the optimization of interconnect and thermal conductivity efficiency while ensuring the mechanical strength of the substrate.

[0030] As a preferred embodiment of this invention, it should be further explained that the electroplated copper coating layer 210 is polished to form a flat double-sided copper layer structure, ensuring the alignment accuracy when subsequently mounting chips and passive devices, reducing the risk of mounting misalignment, and also improving the oxidation and roughness of the copper layer surface, enhancing the adhesion and long-term reliability of the plating, and avoiding plating blistering and peeling problems under long-term temperature cycling. Combined with the groove-free ceramic substrate 101, it forms a high-rigidity support substrate, avoiding the stress concentration problem caused by slotting, further improving the anti-warping performance of the entire packaging substrate structure, and better adapting to the application requirements of large-size, high-power packaging.

[0031] As a preferred embodiment of this invention, it should be further explained that the outline dimensions of the metal layer protrusion 241 correspond to and match the outline dimensions of the slot. The top surface of the metal layer protrusion 241 serves as the mounting support surface and thermally conductive contact surface for the bridging chip, directly conducting the heat generated by the bridging chip to the heat dissipation structure on the other side of the substrate through the metal layer protrusion, significantly improving the overall heat dissipation efficiency. Matching the corresponding outline dimensions ensures a tight fit between the metal layer protrusion and the slot sidewall, avoiding gaps that could affect structural stability and thermal conductivity. Simultaneously, the embedded mounting method can reduce the overall package thickness, meeting the current design requirements for miniaturization and thinness in high-end packaging.

[0032] As a preferred embodiment of this invention, it should be further explained that the embedded silicon or glass bridging chip 510 is a high-density interconnect bridging device. The embedded silicon or glass bridging chip 510 achieves high-speed signal interconnection between the computing chip 560 and the HBM550 through the cooperation of its own chip pads with blind vias and metal traces inside the composite layer. This integrates the signal interconnection path inside the substrate, freeing up wiring space on the substrate surface and reserving space for mounting larger and more numerous functional chips, adapting to the development trend of multi-chip integrated packaging. Similarly, the embedded silicon or glass three-dimensional bridging chip 520 is a high-density three-dimensional interconnect bridging device. The embedded silicon or glass three-dimensional bridging chip 520 achieves high-speed signal interconnection between the computing chip 560 and the HBM550 through the cooperation of its internal TSV / TGV601 with its own chip pads, blind vias and metal traces inside the composite layer.

[0033] A method for fabricating the above-mentioned high thermal conductivity, low warpage bridging ceramic packaging substrate structure includes the following steps: S11, Ceramic core plate preparation: A ceramic substrate 101 made of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond high thermal conductivity ceramic material is selected. The ceramic substrate 101 is then subjected to grinding, ultrasonic cleaning, and drying treatment in sequence. Several interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate 101 are processed using laser drilling technology, and ceramic core metal filler 310 is filled into the interconnecting holes. The ceramic substrate 101 is then electroplated as a whole, forming an electroplated copper coating layer 210 on its upper and lower surfaces and the walls of the interconnecting holes, so that the ceramic core metal filler 310 and the electroplated copper coating layer 210 together constitute the ceramic core metal layer 220. Then, metal layer bosses 241 and connecting pads are processed on the surface of the electroplated copper coating layer 210 using etching or electroplating layer-adding technology to obtain the ceramic core board 100. S12. Fabrication of the bottom composite layer and grooving, blind hole processing: Multiple ABF / PP / PI dielectric layers 320 are laminated onto the upper and lower surfaces of the ceramic core board 100 to form a bottom composite layer. A metal trace layer 240 is prepared on the outside of each ABF / PP / PI dielectric layer 320. Slots adapted to the metal layer bosses 241 are processed on the multiple metal trace layers 240 and the corresponding ABF / PP / PI dielectric layers 320, exposing the surface of the metal layer bosses 241 through the slots. At the same time, blind holes 230 are processed on each ABF / PP / PI dielectric layer 320 and electroplated to form solid copper pillars. The solid copper pillars realize the electrical connection between adjacent metal trace layers 240 and between the ceramic core board 100 and adjacent metal trace layers 240. S13, Embedded (3D) Bridge Chip Mounting: When the bridging chip is an embedded silicon or glass bridging chip 510, the embedded silicon or glass bridging chip 510 is mounted in the slot using DAF film 420. When the bridging chip is an embedded silicon or glass three-dimensional bridging chip 520, the embedded silicon or glass three-dimensional bridging chip 520 is mounted in the slot using conductive adhesive 430, so that the bridging chip is tightly attached to the metal layer protrusion 241; the interconnection alignment of the chip pad 602 on the bridging chip and the blind via 230 inside the bottom composite layer is completed simultaneously. S14, Upper ABF / PP / PI composite laminate: The process of repeatedly laminating ABF / PP / PI dielectric layer 320, preparing metal trace layer 240, processing blind via 230 and electroplating solid copper pillars on the surface of the bottom composite layer is used to form upper ABF / PP / PI composite layer. Each metal trace layer 240 in the upper ABF / PP / PI composite layer is patterned. By stacking the upper ABF / PP / PI composite layer on the surface of the bottom composite layer, a set number of ABF / PP / PI composite layers 300 are obtained, and the ceramic core board 100 and the ABF / PP / PI composite layers 300 on its upper and lower surfaces are matched to form a bridged ceramic packaging composite substrate 001. S15. Substrate surface treatment and packaging integration: A solder resist layer 330 is coated on the outermost ABF / PP / PI dielectric layer 320. A surface pad 250 is prepared on the outside of the solder resist layer 330, and corresponding blind vias 230 are processed to achieve electrical connection between the surface pad 250 and the inner metal trace layer 240. The HBM550 and computing chip 560 are mounted on the surface pad 250 using the MCM flip-chip packaging process. IPD passive devices / SiC chips / GaN chips 530 are mounted on the back power supply structure at the bottom of the bridged ceramic package composite substrate 001. TIM adhesive 401 is coated on the back of the HBM550 and computing chip 560 and a heat sink is attached to complete the bridged 2.5D advanced packaging.

[0034] Case 1 This case study illustrates the bridging ceramic packaging composite substrate 001, using the aluminum nitride 95 ceramic core board 100 as its core. The ceramic substrate 101 has a thickness of 0.5 mm and a thermal conductivity of 180 W / (m²). K); The substrate is only machined with through interconnects with a diameter of 100μm, and the holes are filled with ceramic core metal filler 310; The upper surface, lower surface and hole walls of the ceramic substrate 101 are covered with a 15μm thick electroplated copper coating layer 210, and the ceramic core metal filler 310 and the electroplated copper coating layer 210 together constitute the ceramic core metal layer 220; The surface of the coating layer is machined with metal layer bosses 241 with a height of 0.2mm and connecting pads.

[0035] Four ABF / PP / PI dielectric layers 320 are symmetrically stacked on the upper and lower surfaces of the ceramic core board 100, with a trace spacing of 30μm for each ABF / PP / PI dielectric layer 320. A 0.2mm deep slot is formed on each of the multilayer dielectric layers and the corresponding metal trace layers 240, exposing the top surface of the metal layer bosses 241. An embedded silicon or glass bridging chip 510 is mounted within the slot via a DAF film 420, tightly fitting against the metal layer bosses 241. Chip pads 602 are provided on the interconnect surface of the bridging chip, electrically connected to the metal trace layers 240 through blind vias 230 inside the composite layer. The metal trace layers 240 are interconnected through blind vias 230 with a diameter of 50μm, and the blind vias are plated with 20μm thick solid copper pillars.

[0036] The bridging ceramic packaging composite substrate 001 has an overall size of 100mm and a warpage of 0.08% / mm. The outermost dielectric layer is covered with a solder resist layer 330, and surface pads 250 are fabricated outside the solder resist layer. These surface pads are connected to the inner layer traces via blind vias. The back of the bridging ceramic packaging composite substrate 001 integrates IPD passive devices / SiC chips / GaN chips 530. The surface pads 250 are adapted for the flip-chip mounting of the computing chip 560 and the HBM550 MCM. The backs of the HBM550 and the computing chip 560 are coated with TIM adhesive 401, which is bonded to the heat sink to form a top heat dissipation path.

[0037] The interconnection method in Case 1 follows these steps: S1: Select aluminum nitride 95 ceramic substrate 101, and perform grinding, ultrasonic cleaning and drying treatment in sequence to ensure that the surface is flat and free of impurities; S2: A 100μm through-hole interconnect is processed using laser drilling technology, and a ceramic core metal filler 310 is filled into the hole; the ceramic substrate 101 is electroplated as a whole to form a 15μm thick full-coverage electroplated copper film layer 210, and the two together constitute the ceramic core metal layer 220. S3: Using an electroplating layering process, a metal layer boss 241 with a height of 0.2mm is processed on the surface of the electroplated copper film layer 210, and a connecting pad is formed by etching, thus obtaining a ceramic core board 100. S4: A multilayer ABF / PP / PI dielectric layer 320 is symmetrically laminated on the upper and lower surfaces of the ceramic core board 100, and a metal trace layer 240 is prepared; a slot adapted to the metal layer boss 241 is formed by machining, exposing the boss surface; at the same time, a blind hole 230 with a diameter of 50μm is machined, and a 20μm thick solid copper pillar is formed by electroplating, so as to realize the electrical connection between the multilayer trace and the ceramic core board; S5: The embedded silicon or glass bridging chip 510 is mounted into the slot through the DAF film 420, so that it is tightly attached to the metal layer protrusion 241, and the alignment and interconnection of the chip pad 602 and the blind via structure are completed simultaneously. S6: Repeat the process of laminating ABF / PP / PI dielectric layer 320, preparing metal trace layer, processing blind via and electroplating copper pillar to complete the stacking of the remaining 3 layers of ABF / PP / PI composite layer 300, and simultaneously complete the patterned routing of each layer. S7: Coat the outermost dielectric layer surface with solder mask 330, prepare surface pads 250 on the outside of the solder mask layer, and process corresponding blind holes to achieve electrical connection with the inner metal trace layer. S8: IPD passive devices / SiC chips / GaN chips 530 are mounted on the power supply structure on the back of the substrate; HBM550 and computing chip 560 are mounted on surface pad 250 using MCM flip-chip packaging process. S9: Apply TIM adhesive 401 to the back of HBM550 and computing chip 560, attach the heat sink and cure to complete the bridging 2.5D advanced package.

[0038] Case 2 This case study presents a high wiring density solution using an alumina ceramic core board and a 6-layer composite layer. It is suitable for high-integration packaging scenarios with large size and multiple signal channels, offering controllable costs and enhanced wiring capabilities.

[0039] The key difference between this case and Case 1 is: The ceramic substrate 101 uses alumina 99 ceramic, is 0.8mm thick, and has a thermal conductivity of 30W / (m²). K); the interconnect hole is filled with ceramic core metal filler 310, and the substrate surface and hole wall are covered with electroplated copper film layer 210, which together constitute ceramic core metal layer 220; the metal layer boss 241 has a height of 0.3mm and a corresponding slot depth of 0.3mm, and the embedded silicon or glass bridging chip 510 is mounted through DAF film 420.

[0040] The ABF / PP / PI composite layer 300 includes 6 ABF / PP / PI dielectric layers 320 with a dielectric layer trace spacing of 20μm, resulting in higher wiring density; the overall substrate size is 150mm, and the warpage is 0.09% / mm.

[0041] The interconnect aperture is 150μm, the blind via 230 aperture is 80μm, and the thickness of the copper pillar inside the via is 30μm.

[0042] The remaining structural components, interconnection logic, and manufacturing process are the same as in Case 1. Only the process parameters for laser drilling, electroplating, and machining need to be adjusted according to the structural parameters.

[0043] Case 3 This case study presents a high thermal conductivity silicon-based TSV 3D bridging solution, designed for high-power AI computing packaging scenarios. It employs an aluminum nitride ceramic core board paired with a silicon-based 3D bridging chip, balancing extreme heat dissipation performance with high-speed 3D interconnect capabilities.

[0044] In this case, the bridging ceramic packaging composite substrate 001 uses an aluminum nitride 96 ceramic core board 100 as its core. The ceramic substrate 101 has a thickness of 0.6 mm and a thermal conductivity of 200 W / (m²). K); The substrate is only machined with through interconnects with a diameter of 80μm, and the holes are filled with ceramic core metal filler 310; The upper and lower surfaces of the ceramic substrate 101 and the hole walls are covered with a 12μm thick electroplated copper coating layer 210, and the ceramic core metal filler 310 and the electroplated copper coating layer 210 together constitute the ceramic core metal layer 220; The surface of the coating layer is machined with a metal layer boss 241 with a height of 0.25mm and a connecting pad, and the surface of the boss is precision polished to ensure the flatness of the bonding.

[0045] Four ABF / PP / PI composite layers 300 are symmetrically stacked on the upper and lower surfaces of the ceramic core board 100, with a trace spacing of 25μm for each ABF / PP / PI dielectric layer 320. A 0.25mm deep slot is formed on the multilayer dielectric layers and the corresponding metal trace layers 240, exposing the top surface of the metal layer bosses 241. An embedded silicon-based three-dimensional bridging chip 520 is mounted in the slot using conductive adhesive 430, ensuring complete and tight contact with the metal layer bosses 241. TSVs (Transient Vias) are fabricated inside the three-dimensional bridging chip to achieve vertical three-dimensional interconnection; the TSVs have a diameter of 20μm and a spacing of 50μm. Chip pads 602 are distributed on the chip interconnect surface, electrically connected to the metal trace layers 240 through blind vias 230 inside the composite layers. The metal trace layers 240 are interconnected through blind vias 230 with a diameter of 40μm, and 18μm thick solid copper pillars are plated inside the blind vias.

[0046] The substrate has an overall size of 110mm and a warpage of 0.07% / mm. The outermost dielectric layer is covered with a solder resist layer 330, and surface pads 250 are fabricated outside the solder resist layer. These surface pads are connected to the inner layer traces via blind vias. The back of the substrate integrates IPD passive devices and a SiC power chip 530. Surface pads 250 are adapted for flip-chip mounting of a single computing chip and four HBM3 MCMs. The backs of the HBM550 and computing chip 560 are coated with TIM adhesive 401 and bonded to a copper heat sink to form the main heat dissipation path at the top.

[0047] The steps for creating this case are as follows: S1: Select aluminum nitride 96 ceramic substrate 101, and perform grinding, ultrasonic cleaning and drying treatment in sequence to ensure that the surface is flat and free of impurities; S2: A through interconnect hole with a diameter of 80μm is processed by laser drilling, and the hole is filled with ceramic core metal filler 310; the ceramic substrate 101 is electroplated as a whole to form a 12μm thick full-coverage electroplated copper film layer 210, and the two together constitute the ceramic core metal layer 220. S3: Using an electroplating layering process, a metal layer boss 241 with a height of 0.25mm is machined on the surface of the electroplated copper film layer 210, and a connecting pad is formed by etching. The surface of the boss is polished to obtain the ceramic core board 100. S4: A multilayer ABF / PP / PI dielectric layer 320 is symmetrically laminated on the upper and lower surfaces of the ceramic core board 100, and a metal trace layer 240 is prepared; a slot adapted to the metal layer boss 241 is formed by machining, exposing the boss surface; at the same time, a blind hole 230 with a diameter of 40μm is machined, and a 18μm thick solid copper pillar is formed by electroplating, so as to realize the electrical connection between the multilayer trace and the ceramic core board; S5: The embedded silicon-based three-dimensional bridging chip 520 is mounted into the slot using conductive adhesive 430, so that it is tightly attached to the metal layer protrusion 241, and the alignment and interconnection of the chip pad 602 and the blind via structure are completed simultaneously. S6: Repeat the process of laminating dielectric layers, preparing metal trace layers, processing blind vias and electroplating copper pillars to complete the stacking of the remaining 3 layers of ABF / PP / PI composite layer 300, with patterned routing completed simultaneously for each layer; S7: Coat the outermost dielectric layer surface with solder mask 330, prepare surface pads 250 on the outside of the solder mask layer, and process corresponding blind holes to achieve electrical connection with the inner metal trace layer. S8: IPD passive devices and SiC power chip 530 are mounted on the power supply structure on the back of the substrate; HBM550 and computing chip 560 are mounted on surface pad 250 using MCM flip-chip packaging process. S9: Apply TIM adhesive 401 to the back of HBM550 and computing chip 560, attach the copper heat sink and cure it to complete the advanced packaging with high thermal conductivity three-dimensional bridging.

[0048] Case 4 This case study presents a high-density glass-based TGV 3D bridging solution, designed for ultra-high integration multi-chip packaging scenarios. It employs a silicon nitride ceramic core board paired with a glass-based 3D bridging chip to achieve higher interconnect density and superior high-frequency signal performance.

[0049] The key difference between this case and Case 3 is: The ceramic substrate 101 is made of silicon nitride ceramic, with a thickness of 0.7 mm and a thermal conductivity of 90 W / (m²). K), with a lower dielectric constant and less high-frequency signal loss; the interconnect aperture is 120μm, the metal layer boss 241 has a height of 0.35mm, corresponding to a slot depth of 0.35mm, and the glass-based three-dimensional bridging chip 520 is mounted with conductive adhesive 430; the chip uses TGV to achieve vertical interconnection inside, with a TGV diameter of 15μm and a spacing of 40μm, resulting in higher channel density and better high-frequency signal transmission performance.

[0050] The substrate features a 6-layer ABF / PP / PI composite layer with a 15μm spacing between dielectric traces, significantly improving wiring density. The overall substrate size is 160mm, with a warpage of 0.085% / mm, supporting heterogeneous integration of two computing chips and eight HBMs. The 230 blind vias have a 60μm diameter and a 30μm thick copper pillar inside, meeting the dual requirements of high-current power supply and high-density signal transmission.

[0051] The remaining structural components, interconnection logic, and manufacturing process are the same as in Case 3. Only the process parameters for laser drilling, electroplating, grooving, and chip mounting need to be adjusted according to the material and structural parameters.

[0052] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high thermal conductivity, low warpage bridging ceramic packaging substrate structure, characterized in that, It includes a ceramic core board (100), an ABF / PP / PI composite layer (300), a bridging chip, a solder mask layer (330), and surface pads (250). The ceramic core plate (100) includes a ceramic substrate (101) and a ceramic core metal layer (220). The ceramic substrate (101) has only a few interconnect holes that penetrate the upper and lower surfaces, and the remaining area is a complete flat structure except for the interconnect holes. The ceramic core metal layer (220) is composed of a ceramic core plate metal filler (310) and an electroplated copper coating layer (210). The ceramic core plate metal filler (310) fills the inside of the interconnect holes, and the electroplated copper coating layer (210) completely covers the upper surface, lower surface and interconnect hole walls of the ceramic substrate (101). The surface of the electroplated copper coating layer (210) is provided with metal layer bosses (241) and connecting pads, and the connecting pads on the upper and lower surfaces of the ceramic substrate (101) are electrically connected through the ceramic core metal layer (220). The ceramic substrate (101) is an alumina, aluminum nitride, silicon nitride, silicon carbide or diamond high thermal conductivity ceramic material. The ceramic core board (100) has symmetrically arranged ABF / PP / PI composite layers (300) on its upper and lower surfaces, so that the ceramic core board (100) and the ABF / PP / PI composite layers (300) on its upper and lower surfaces cooperate to form a bridged ceramic encapsulation composite substrate (001); the ABF / PP / PI composite layer (300) is composed of multiple layers of ABF / PP / PI dielectric layers (320), each ABF / PP / PI dielectric layer (320) is stacked. Metal trace layers (240) are provided on the outer side of each of the ceramic core boards (100). Blind holes (230) are provided between adjacent metal trace layers (240). Solid copper pillars connecting adjacent metal trace layers (240) are electroplated in the blind holes (230). The multilayer ABF / PP / PI dielectric layer (320) near the ceramic core board (100) and the corresponding metal trace layer (240) are processed with slots that match the position and size of the metal layer boss (241). The slots expose the surface of the metal layer boss (241). The bridging chip is mounted in the slot and is tightly attached to the metal layer boss (241); the interconnect surface of the bridging chip is provided with chip pads (602), and the chip pads (602) are electrically connected to the metal trace layer (240) through the corresponding blind vias (230) inside the ABF / PP / PI composite layer (300); The outermost ABF / PP / PI dielectric layer (320) is covered with a solder mask layer (330), and the surface pads (250) are located outside the solder mask layer (330). The surface pads (250) are electrically connected to the inner metal trace layer (240) through solid copper pillars in the blind vias (230). The HBM (550) and computing chip (560) are flip-chip mounted on surface pads (250) to achieve electrical connection. The back sides of the HBM (550) and computing chip (560) are connected to the heat sink via TIM adhesive (401). A back power supply structure is provided on the back side of the bridged ceramic packaged composite substrate (001), and IPD passive devices / SiC chips / GaN chips (530) are provided on the back power supply structure.

2. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to claim 1, characterized in that, The ceramic core metal layer (220) has a ceramic core plate metal filler (310) and an electroplated copper coating layer (210) as an integrated electroplated structure. The ceramic core plate metal filler (310) is a conductive filler structure that fills the interconnect holes. The electroplated copper coating layer (210) is polished to form a flat double-sided copper layer structure, which, together with the grooveless ceramic substrate (101), constitutes a high-rigidity support substrate.

3. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to claim 1, characterized in that, The outline dimensions of the metal layer protrusion (241) correspond to and match the outline dimensions of the slot. The top surface of the metal layer protrusion (241) serves as the mounting support surface and thermal contact surface for bridging the chip.

4. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to any one of claims 1-3, characterized in that, The bridging chip is an embedded silicon or glass bridging chip (510), which is mounted in the slot through a DAF film (420).

5. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to claim 4, characterized in that, The embedded silicon or glass bridge chip (510) is a high-density interconnect bridge device. The embedded silicon or glass bridge chip (510) achieves high-speed signal interconnection between the computing chip (560) and HBM (550) through the cooperation of its own chip pads with blind holes and metal traces inside the composite layer.

6. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to any one of claims 1-3, characterized in that, The bridging chip is an embedded silicon or glass three-dimensional bridging chip (520), which is mounted in the slot by conductive adhesive (430); and the embedded silicon or glass three-dimensional bridging chip (520) is provided with TSV / TGV (601) for realizing three-dimensional connection inside the chip.

7. The high thermal conductivity, low warpage bridging ceramic packaging substrate structure according to claim 6, characterized in that, The embedded silicon or glass three-dimensional bridge chip (520) is a high-density three-dimensional interconnection bridge device. The embedded silicon or glass three-dimensional bridge chip (520) achieves high-speed signal interconnection between the computing chip (560) and HBM (550) through the cooperation of the internal TSV / TGV (601) with its own chip pads, blind holes inside the composite layer, and metal traces.

8. A method for preparing the high thermal conductivity, low warpage bridging ceramic packaging substrate structure as described in claim 4, characterized in that, Includes the following steps: S11, Ceramic core plate preparation: A ceramic substrate (101) made of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond high thermal conductivity ceramic material is selected. The ceramic substrate (101) is then ground, ultrasonically cleaned, and dried in sequence. Several interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate (101) are processed using laser drilling technology. Ceramic core metal filler (310) is filled into the interconnecting holes. The ceramic substrate (101) is electroplated as a whole, and an electroplated copper coating layer (210) is formed on its upper and lower surfaces and the walls of the interconnecting holes. The ceramic core metal filler (310) and the electroplated copper coating layer (210) together constitute the ceramic core metal layer (220). Then, metal layer bosses (241) and connecting pads are processed on the surface of the electroplated copper coating layer (210) using etching or electroplating layering technology to obtain the ceramic core board (100). S12. Fabrication of the bottom composite layer and grooving, blind hole processing: Multiple ABF / PP / PI dielectric layers (320) are laminated on the upper and lower surfaces of the ceramic core board (100) to form a bottom composite layer, and a metal trace layer (240) is prepared on the outside of each ABF / PP / PI dielectric layer (320); slots adapted to the metal layer bosses (241) are processed on the multiple metal trace layers (240) and the corresponding ABF / PP / PI dielectric layers (320), and the surface of the metal layer bosses (241) is exposed through the slots; at the same time, blind holes (230) are processed on each ABF / PP / PI dielectric layer (320) and electroplated to form solid copper pillars, and the solid copper pillars realize the electrical connection between adjacent metal trace layers (240) and between the ceramic core board (100) and adjacent metal trace layers (240); S13, Embedded Bridge Chip Mounting: The embedded silicon or glass bridge chip (510) is mounted in the slot through the DAF film (420), so that the embedded silicon or glass bridge chip (510) is tightly attached to the metal layer boss (241); the interconnection alignment of the chip pad (602) on the embedded silicon or glass bridge chip (510) and the blind via (230) inside the bottom composite layer is completed simultaneously. S14, Upper ABF / PP / PI composite laminate: The process of repeatedly laminating ABF / PP / PI dielectric layers (320), preparing metal trace layers (240), processing blind vias (230), and electroplating solid copper pillars on the surface of the bottom composite layer is repeated to form an upper ABF / PP / PI composite layer. Each metal trace layer (240) in the upper ABF / PP / PI composite layer is patterned. The upper ABF / PP / PI composite layer is stacked on the surface of the bottom composite layer to obtain a set number of ABF / PP / PI composite layers (300). The ceramic core board (100) and its upper and lower surfaces of the ABF / PP / PI composite layers (300) are matched to form a bridged ceramic packaging composite substrate (001). S15. Substrate surface treatment and packaging integration: A solder resist layer (330) is coated on the outermost ABF / PP / PI dielectric layer (320). A surface pad (250) is prepared on the outside of the solder resist layer (330). Corresponding blind holes (230) are processed to realize the electrical connection between the surface pad (250) and the inner metal trace layer (240). The HBM (550) and the computing chip (560) are mounted on the surface pad (250) using the MCM flip-chip packaging process. The IPD passive device / SiC chip / GaN chip (530) is mounted on the back power supply structure at the bottom of the bridged ceramic package composite substrate (001). TIM adhesive (401) is coated on the back of the HBM (550) and the computing chip (560) and a heat sink is attached to complete the bridged 2.5D advanced packaging.

9. A method for preparing the high thermal conductivity, low warpage bridging ceramic packaging substrate structure as described in claim 6, characterized in that, Includes the following steps: S11, Ceramic core plate preparation: A ceramic substrate (101) made of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond high thermal conductivity ceramic material is selected. The ceramic substrate (101) is then ground, ultrasonically cleaned, and dried in sequence. Several interconnecting holes penetrating the upper and lower surfaces of the ceramic substrate (101) are processed using laser drilling technology. Ceramic core metal filler (310) is filled into the interconnecting holes. The ceramic substrate (101) is electroplated as a whole, and an electroplated copper coating layer (210) is formed on its upper and lower surfaces and the walls of the interconnecting holes. The ceramic core metal filler (310) and the electroplated copper coating layer (210) together constitute the ceramic core metal layer (220). Then, metal layer bosses (241) and connecting pads are processed on the surface of the electroplated copper coating layer (210) using etching or electroplating layering technology to obtain the ceramic core board (100). S12. Fabrication of the bottom composite layer and grooving, blind hole processing: Multiple ABF / PP / PI dielectric layers (320) are laminated on the upper and lower surfaces of the ceramic core board (100) to form a bottom composite layer, and a metal trace layer (240) is prepared on the outside of each ABF / PP / PI dielectric layer (320); slots adapted to the metal layer bosses (241) are processed on the multiple metal trace layers (240) and the corresponding ABF / PP / PI dielectric layers (320), and the surface of the metal layer bosses (241) is exposed through the slots; at the same time, blind holes (230) are processed on each ABF / PP / PI dielectric layer (320) and electroplated to form solid copper pillars, and the solid copper pillars realize the electrical connection between adjacent metal trace layers (240) and between the ceramic core board (100) and adjacent metal trace layers (240); S13, Embedded 3D Bridging Chip Mounting: The embedded silicon or glass three-dimensional bridge chip (520) is mounted in the slot using conductive adhesive (430), so that the embedded silicon or glass three-dimensional bridge chip (520) is tightly attached to the metal layer boss (241); the interconnection alignment of the chip pad (602) on the embedded silicon or glass three-dimensional bridge chip (520) and the blind via (230) inside the bottom composite layer is completed simultaneously. S14, Upper ABF / PP / PI composite laminate: The process of repeatedly laminating ABF / PP / PI dielectric layers (320), preparing metal trace layers (240), processing blind vias (230), and electroplating solid copper pillars on the surface of the bottom composite layer is repeated to form an upper ABF / PP / PI composite layer. Each metal trace layer (240) in the upper ABF / PP / PI composite layer is patterned. The upper ABF / PP / PI composite layer is stacked on the surface of the bottom composite layer to obtain a set number of ABF / PP / PI composite layers (300). The ceramic core board (100) and its upper and lower surfaces of the ABF / PP / PI composite layers (300) are matched to form a bridged ceramic packaging composite substrate (001). S15. Substrate surface treatment and packaging integration: A solder resist layer (330) is coated on the outermost ABF / PP / PI dielectric layer (320). A surface pad (250) is prepared on the outside of the solder resist layer (330). Corresponding blind holes (230) are processed to realize the electrical connection between the surface pad (250) and the inner metal trace layer (240). The HBM (550) and the computing chip (560) are mounted on the surface pad (250) using the MCM flip-chip packaging process. The IPD passive device / SiC chip / GaN chip (530) is mounted on the back power supply structure at the bottom of the bridged ceramic package composite substrate (001). TIM adhesive (401) is coated on the back of the HBM (550) and the computing chip (560) and a heat sink is attached to complete the bridged 2.5D advanced packaging.

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