Embedded component package structure and method of manufacturing the same

Abstract

The present application relates to a buried element package structure and a manufacturing method thereof. A buried element package structure includes a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, the first thickness is greater than a second thickness of the dielectric structure corresponding to a position above the first polymer layer, wherein the first polymer layer has a first opening, the dielectric structure has a second opening, and the first opening is smaller than the second opening. The patterned conductive layer covers an upper surface of the dielectric structure and extends above the first polymer layer and in the first opening and the second opening, and the patterned conductive layer is electrically connected to the semiconductor chip.

Description

[0001] This application is a divisional application of the invention patent application filed on July 19, 2019, with application number 201910655008.4 and invention title "Embedded Component Packaging Structure and Manufacturing Method Thereof". Technical Field

[0002] This invention relates to a component packaging structure and a method for manufacturing the same, and more particularly to an embedded component packaging structure and a method for manufacturing the same. Background Technology

[0003] In system-in-package (SiP) architectures, the technology of embedding semiconductor chips within the package substrate (SESUB) has become a key research focus for manufacturers in this field in recent years due to its advantages of reducing noise interference to the package substrate and reducing product size. To improve production yield, the embedded components must be fixed within the dielectric structure of the circuit board to facilitate electrical connection between the subsequently fabricated patterned conductive layer and the embedded components.

[0004] Currently, blind vias in the dielectric structure above embedded components are completed using a sandblasting process. However, the depth of the blind via directly affects the opening size (i.e., the aperture), causing the opening size to be unable to be further reduced, which needs to be further addressed. Summary of the Invention

[0005] This invention relates to an embedded component packaging structure and its manufacturing method, which utilizes a polymer material to replace a dielectric structure above the embedded component, thereby reducing the thickness of the dielectric structure and reducing the opening size in the subsequent sandblasting process.

[0006] According to one aspect of the present invention, an embedded component packaging structure is provided, comprising a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, the first thickness being greater than a second thickness of the dielectric structure located above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends above the first polymer layer, and is electrically connected to the semiconductor chip.

[0007] According to one aspect of the present invention, an embedded component packaging structure is provided, comprising a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness greater than a second thickness corresponding to a dielectric structure located above the first polymer layer. The first polymer layer has a first opening, and the dielectric structure has a second opening, the first opening being smaller than the second opening. The patterned conductive layer covers an upper surface of the dielectric structure and extends above the first polymer layer and into the first and second openings. The patterned conductive layer is electrically connected to the semiconductor chip.

[0008] According to one aspect of the present invention, a method for manufacturing an embedded component packaging structure is provided, comprising the following steps: providing a semiconductor chip on a carrier, the semiconductor chip including a polymer layer; providing a dielectric structure on the carrier to cover the semiconductor chip, wherein the thickness of the polymer layer is greater than the thickness of the dielectric structure corresponding to the polymer layer; forming a patterned conductive layer on an upper surface of the dielectric structure and extending above the polymer layer. Attached Figure Description

[0009] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0010] Figures 1A to 1C A partial schematic diagram of the sandblasting process performed on the embedded component packaging structure is shown.

[0011] Figures 2 to 5 A partial cross-sectional schematic diagram of the embedded component packaging structure according to different embodiments of the present invention is shown.

[0012] Figures 6A to 6D A flowchart illustrating a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention is shown.

[0013] Figures 7A to 7G A flowchart illustrating a method for manufacturing an embedded component packaging structure according to another embodiment of the present invention is shown.

[0014] Figures 8A to 8J A flowchart illustrating a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention is shown.

[0015] Explanation of component labels in the diagram:

[0016] 10: Embedded component packaging structure

[0017] 11: Components

[0018] 12: Electrical pads

[0019] 16: Dielectric structure

[0020] 16a: Blind hole

[0021] 17: Conductive layer

[0022] 17a: Patterned conductive layer

[0023] D: Thickness

[0024] W: Aperture

[0025] 100: Embedded component packaging structure

[0026] 101: Carrier

[0027] 103: Lower conductive layer

[0028] 104: Lower conductive layer

[0029] 105: Blind Hole

[0030] 106: Conductive blind via

[0031] 110: Embedded component packaging structure

[0032] 111: Semiconductor chip

[0033] 112: Electrical pad

[0034] 113: Insulation layer

[0035] 114: Rewire Layer

[0036] 114a: First rewiring layer

[0037] 114b: Second wiring layer

[0038] 115a: First polymer layer

[0039] 115b: Second polymer layer

[0040] 115c: Third polymer layer

[0041] 116, 116a: Dielectric structure

[0042] 117: Patterned conductive layer

[0043] 117a: Seed layer

[0044] 117b: Electroplated copper layer

[0045] 117c: Copper cladding

[0046] 118: Dielectric layer

[0047] 118a: Blind hole

[0048] 118b: Conductive blind via

[0049] 119: Upper conductive layer

[0050] D1: First thickness

[0051] D2: Second thickness

[0052] S1, S2: Upper surface

[0053] S3, S4: Side surfaces

[0054] OP1: First opening

[0055] OP2: Second opening

[0056] W1: First aperture

[0057] W2: Second aperture Detailed Implementation

[0058] The following embodiments are provided for detailed description. These embodiments are merely illustrative and are not intended to limit the scope of protection of this invention. The same / similar symbols are used to denote the same / similar elements in the description. Directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0059] Please refer to Figures 1A to 1C The diagram illustrates a partial schematic of a sandblasting process for an embedded component package structure 10. First, a component 11 is provided and embedded within a dielectric structure 16. The upper surface of the embedded component 11 has, for example, a plurality of electrical pads 12. The dielectric structure 16 is made of, for example, resin, which can be heat-cured to fix the component 11 within the dielectric structure 16. Next, the dielectric structure 16 is sandblasted to form blind vias 16a. Then, a conductive layer 17 is formed on the upper surface of the dielectric structure 16 and extends into the blind vias 16a, and a patterned conductive layer 17a is formed by etching. However, the thickness D of the dielectric structure 16 needs to be greater than 12 micrometers to achieve good bonding uniformity, and the higher the thickness D of the dielectric structure 16, the more sandblasting passes are required to form the blind vias 16a. Furthermore, the greater the depth of the blind hole 16a, the larger the aperture W of the blind hole 16a is, which means that the aperture W of the blind hole 16a to be formed by the subsequent sandblasting process cannot be less than 40 micrometers, and the minimum size of the electrical pad 12 located below the blind hole 16a cannot be less than 60 micrometers, thus making it impossible to reduce the spacing between the electrical pads 12.

[0060] According to one embodiment of the present invention, an embedded component packaging structure is proposed, which allows the thickness of the dielectric structure above the embedded component to be less than a preset value while still having good pressing uniformity. Since the thickness of the dielectric structure is reduced, relatively fewer sandblasting is required to form blind holes, and the diameter of the blind holes is also relatively reduced.

[0061] Please refer to Figure 2 According to one embodiment of the present invention, the embedded component package structure 100 includes a semiconductor chip 111, a first polymer layer 115a, a dielectric structure 116, and a patterned conductive layer 117. The semiconductor chip 111 is embedded in the dielectric structure 116. The first polymer layer 115a covers the semiconductor chip 111 and has a first thickness D1, which is greater than a second thickness D2 of the dielectric structure 116a located above the first polymer layer 115a. Since the thickness of the dielectric structure 116a is less than the thickness of the first polymer layer 115a, the number of sandblasting operations required to form blind vias in the dielectric structure 116a can be reduced. The patterned conductive layer 117 covers an upper surface of the dielectric structure 116 and extends above the first polymer layer 115a, and the patterned conductive layer 117 is electrically connected to the semiconductor chip 111. The dielectric structure 116 can be formed by laminating a semi-cured dielectric material (e.g., resin) onto the semiconductor chip 111 and then curing it by heating. In order to ensure good uniformity of the dielectric material lamination, the thickness of the lamination is, for example, greater than 12 micrometers. Subsequently, the thickness of the dielectric structure 116a located above the semiconductor chip 111 (i.e., the second thickness D2) can be reduced by sandblasting.

[0062] In one embodiment, the semiconductor chip 111 includes at least one electrical pad 112 and an insulating layer 113, wherein a first polymer layer 115a is disposed on top of the insulating layer 113, and a patterned conductive layer 117 can pass through the openings of the insulating layer 113 and the first polymer layer 115a and be electrically connected to the electrical pad 112. Furthermore, the semiconductor chip 111 may have, for example, a redistribution layer 114, which covers the top of the insulating layer 113 and is located between the first polymer layer 115a and the insulating layer 113. The patterned conductive layer 117 can be electrically connected to the electrical pad 112 via the redistribution layer 114. The electrical pad 112 may be an aluminum pad or a copper pad, and the insulating layer 113 may be, for example, silicon nitride or silicon oxynitride. The first polymer layer 115a may be, for example, a cured photosensitive resin, which can be patterned by exposure and development (photolithography process) and formed by heat curing. The above-mentioned exposure and development process is different from the method of forming openings by sandblasting for dielectric structure 116.

[0063] In one embodiment, the material of the first polymer layer 115a may be a photosensitive polyimide resin or a photosensitive acrylic resin, wherein a high light absorption coefficient photoinitiator and a crosslinking agent are mixed to obtain a polymer layer with low exposure energy, high photosensitivity and low film thickness loss, which is conducive to the formation of patterned openings.

[0064] exist Figure 2 In this process, the thickness of the first polymer layer 115a (i.e., the first thickness D1) is, for example, greater than 3 micrometers and less than 15 micrometers, wherein the aperture size of the first polymer layer 115a depends on the exposure capability to facilitate the formation of a smaller aperture W1. Furthermore, the thickness of the dielectric structure 116a located above the first polymer layer 115a (i.e., the second thickness D2) is, for example, less than 4.5 micrometers, relative to... Figure 1A The thickness of the dielectric structure 16 needs to be greater than 12 micrometers to significantly reduce the thickness. The sum of the first thickness D1 and the second thickness D2 is, for example, between 3 micrometers and 7.5 micrometers, but the invention is not limited thereto. When the sum of the first thickness D1 and the second thickness D2 is less than 3 micrometers, the electrical insulation is insufficient; when the sum of the first thickness D1 and the second thickness D2 is greater than 7.5 micrometers, the hole depth increases, which is not conducive to subsequent electroplating. Therefore, the thickness of the dielectric structure 116a is preferably less than 4.5 micrometers, but is not limited thereto.

[0065] In this embodiment, since the first polymer layer 115a is a photosensitive resin, the aperture W1 of the opening formed by exposure and development (photolithography process) is relatively small (i.e., W1 is smaller than W2). In addition, the thickness of the dielectric structure 116a is smaller than the thickness of the first polymer layer 115a, which can reduce the aperture W2 of the blind hole formed on the dielectric structure 116a in the future, and relatively reduce the hole depth (D1+D2). Therefore, the number of sandblasting operations and the size of the apertures W1 and W2 can be reduced to meet the requirements of small aperture (about 20 micrometers).

[0066] Please refer to Figure 3 This illustration depicts an embedded component packaging structure 100 according to another embodiment of the present invention. Unlike the embodiments described above, there is no dielectric structure 116a above the first polymer layer 115a; therefore, the thickness of the dielectric structure 116a (i.e., the second thickness D2) is 0. In other words, the patterned conductive layer 117 directly covers the first polymer layer 115a. The patterned conductive layer 117 includes, for example, an electroless seed layer 117a and an electroplated copper layer 117b. The electroplated copper layer 117b can cover the electroless seed layer 117a, and the patterned conductive layer 117 is formed by locally etching the electroplated copper layer 117b and the seed layer 117a. The remaining components are the same as those described in the above embodiments and will not be repeated here.

[0067] Please refer to Figure 4This illustration depicts an embedded component packaging structure 100 according to another embodiment of the present invention. Unlike the two embodiments described above, this embodiment further includes a second polymer layer 115b, wherein a redistribution layer 114 is stacked between the first polymer layer 115a and the second polymer layer 115b, and the second polymer layer 115b is stacked between the redistribution layer 114 and the insulating layer 113. Relative to... Figure 2 In the embodiment with dielectric structure 116a, the blind holes do not need to be formed by sandblasting. Instead, blind holes are formed in the first polymer layer 115a in advance. Therefore, the size of the hole depth D1 and the hole diameter W1 can be further reduced to meet the requirements of small hole diameter (about 20 micrometers).

[0068] Please refer to Figure 5 This illustration depicts an embedded component packaging structure 100 according to another embodiment of the present invention. Unlike the three embodiments described above, this embodiment further includes a third polymer layer 115c. The redistribution layer 114 may include a first redistribution layer 114a and a second redistribution layer 114b. The first redistribution layer 114a is stacked between the first polymer layer 115a and the second polymer layer 115b, while the second polymer layer 115b is stacked between the first redistribution layer 114a and the second redistribution layer 114b. The third polymer layer 115c is stacked between the second redistribution layer 114b and the insulating layer 113. The patterned conductive layer 117 can be electrically connected to the electrical pad 112 via the first redistribution layer 114a and the second redistribution layer 114b. Relative to... Figure 2 In the embodiment with dielectric structure 116a, blind holes are not formed by sandblasting, but only in the first polymer layer 115a. Therefore, the size of hole depth D1 and hole diameter W1 can be reduced to meet the requirements of small hole diameter (about 20 micrometers).

[0069] Please refer to Figures 6A to 6D The flowchart illustrates a method for manufacturing an embedded component package structure 110 according to an embodiment of the present invention. First, in Figure 6A In this embodiment, a semiconductor chip 111 is provided on a carrier (not shown). The semiconductor chip 111 may include a first polymer layer 115a, a redistribution layer 114, and a plurality of electrical pads 112. The carrier may be a metal substrate pre-formed with a dielectric material 102. Since the first polymer layer 115a is a photosensitive resin, patterned openings (first openings OP1) can be formed by exposure and development to expose the underlying redistribution layer 114 or electrical pads 112. Figure 6B and Figure 6CIn this process, a dielectric structure 116 is provided on a carrier to encapsulate the semiconductor chip 111 and fill the opening OP1 of the first polymer layer 115a. Part of the dielectric structure 116 can be removed by sandblasting or grinding to reduce the thickness of the dielectric structure 116a above the first polymer layer 115a. Since the first polymer layer 115a has stronger sandblasting resistance than the dielectric structure 116, it is not easily removed by sandblasting. Furthermore, the reduced thickness of the dielectric structure 116a above the first polymer layer 115a relatively reduces the time and number of sandblasting passes required for the sandblasting process.

[0070] exist Figure 6C In this embodiment, the upper surface S1 of the dielectric structure 116 may be lower than the upper surface S2 of the first polymer layer 115a. However, in another embodiment, such as... Figure 2 As shown, the upper surface S1 of the dielectric structure 116 may also be higher than or flush with the upper surface S2 of the first polymer layer 115a, and the present invention does not limit this. Furthermore, without considering tolerances, the side surface S3 of the semiconductor chip 111 is substantially flush with the side surface S4 of the first polymer layer 115a. That is, the first polymer layer 115a is formed on the wafer-type semiconductor chip 111, and the wafer is then diced into multiple semiconductor chips 111 so that each semiconductor chip 111 has a diced first polymer layer 115a.

[0071] exist Figure 6D In this process, a conductive layer 117 is formed on an upper surface of the dielectric structure 116 and extends above the first polymer layer 115a. This includes first forming an electroless seed layer 117a on the upper surface of the dielectric structure 116, and then forming an electroplated copper layer 117b on the seed layer 117a. The conductive layer 117 can be electrically connected to the redistribution layer 114. Afterwards, a portion of the conductive layer 117 is etched to form a patterned conductive layer 117 (e.g., ...). Figure 3 (As shown).

[0072] Please refer to Figures 7A to 7G The flowchart illustrates a method for manufacturing an embedded component package structure 110 according to another embodiment of the present invention. This embodiment differs from the above embodiment in that... Figure 7CIn this process, a copper-clad layer 117c (e.g., copper foil) is pressed onto a semi-cured dielectric structure 116, and then the resin is heated and cured to fix the copper-clad layer 117c onto the dielectric structure 116. Since the dielectric structure 116 has better adhesion to the first polymer layer 115a, a predetermined thickness (e.g., 1 to 4.5 micrometers) of the dielectric structure 116a is retained in this embodiment to strengthen the fixation of the copper-clad layer 117c. Simultaneously, since the adhesion between the electroless seed layer 117a and the dielectric structure 116a is poor, an additional copper-clad layer 117c is needed as a bonding layer to allow the seed layer 117a to be successfully formed on the dielectric structure 116a, and also to allow subsequent electroplating processes (see...) Figure 7F It can be completed smoothly. Next, in Figure 7D In the middle, a patterned copper cladding layer 117c is formed. Figure 7E In this process, a portion of the dielectric structure 116 is removed so that the dielectric structure 116a above the first polymer layer 115a has a second opening OP2, and the second opening OP2 is larger than the first opening OP1 of the first polymer layer 115a. The removal of the portion of the dielectric structure 116 includes removing the dielectric structure 116a located in the first opening OP1 of the first polymer layer 115a by sandblasting.

[0073] In this embodiment, a dielectric structure 116a above the semiconductor chip 111 is replaced with a polymer material, thereby reducing the thickness of the dielectric structure 116a. Figure 7E In the first polymer layer 115a, the first opening OP1 has, for example, a first pore size W1, and the second opening OP2 of the dielectric structure 116 has, for example, a second pore size W2. The first pore size W1 is smaller than the second pore size W2, and the first opening OP1 and the second opening OP2 overlap each other on the vertical projection plane. In one embodiment, the pore wall at the first opening OP1 and the pore wall at the second opening OP2 are stepped, so that the pore size decreases from the second pore size W2 to the first pore size W1.

[0074] exist Figure 7F In the process, an electroless seed layer 117a and an electroplated copper layer 117b are formed in the first opening OP1 and the second opening OP2, and electrically connected to the copper-clad layer 117c. Then, a portion of the conductive layer 117 is etched to form a patterned conductive layer 117 (e.g., ...). Figure 7G (As shown). The remaining steps are as described in the above embodiments and will not be repeated here.

[0075] exist Figure 7GAs described above, the patterned conductive layer 117 may include a copper-clad layer 117c, an electroless seed layer 117a, and an electroplated copper layer 117b. The copper-clad layer 117c may be laminated onto the dielectric structure 116 and then heat-bonded to the dielectric structure 116. Furthermore, the electroplated copper layer 117b may cover the electroless seed layer 117a and be electrically connected to the copper-clad layer 117c to form the patterned conductive layer 117.

[0076] Please refer to Figures 8A to 8J The flowchart illustrates a method for manufacturing an embedded component packaging structure 110 according to another embodiment of the present invention. Figures 8A to 8B The steps described in the above embodiments are for providing a semiconductor chip 111 on a carrier 101, with a dielectric structure 116 covering the semiconductor chip 111, so that the semiconductor chip 111 is embedded in the dielectric structure 116. The carrier 101 is, for example, a copper-clad substrate. Figure 8C In the dielectric structure 116, at least one blind via 116b is formed by sandblasting or etching. Figure 8D In this process, the dielectric structure 116a above the first polymer layer 115a is removed, making the thickness of the dielectric structure 116a (i.e., the second thickness D2) equal to 0, or the thickness of the dielectric structure 116a (i.e., the second thickness D2) is made greater than 0 without removing the dielectric structure 116a above the first polymer layer 115a. Next, in Figure 8E In this process, an upper conductive layer 117 is formed on the upper surface of the dielectric structure 116, and the upper conductive layer 117 extends into the blind via 116b to become a conductive blind via electrically connected to the lower conductive layer 103. Next, in... Figure 8F In this process, a dielectric layer 118 (e.g., a glass fiber-containing resin) is formed on the dielectric structure 116, and another upper conductive layer 119 (e.g., copper foil) is pressed onto the dielectric layer 118. The resin is then heated and cured to allow the two upper conductive layers 117 and 119 to overlap. Figure 8G In the process, multiple blind vias 118a are formed in the dielectric layer 118, and then, in Figure 8H In this process, an electroless seed layer is formed on the upper surface of the upper conductive layer 119 and in the blind via 118a, and then an electroplated copper layer is formed on the seed layer, so that the two upper conductive layers 117 and 119 are electrically connected through the conductive blind via 118b. Furthermore, in Figure 8F In this process, the carrier 101 may further include another lower conductive layer 104, which is patterned by etching the lower conductive layer 104, and in Figure 8G Multiple blind holes 105 are formed in the carrier 101 by sandblasting. Figure 8HIn the process, an electroless electroplating seed layer is formed on the lower conductive layer 104 and in the blind via 105, and then an electroplated copper layer is formed on the seed layer, so that the two lower conductive layers 103 and 104 are electrically connected through the conductive blind via 106.

[0077] exist Figure 8I In the process, a patterned upper conductive layer 119 and a patterned lower conductive layer 104 are formed by etching. Then, in... Figure 8J In the process, a patterned first solder mask layer 120 is formed on a patterned upper conductive layer 119, and a portion of the upper conductive layer 119 is exposed as a plurality of first solder pads 119a; and a patterned second solder mask layer 108 is formed on a patterned lower conductive layer 104, and a portion of the lower conductive layer 104 is exposed as a plurality of second solder pads 104a.

[0078] According to the above embodiments of the present invention, since a polymer layer is pre-formed on the semiconductor chip to replace a dielectric structure above the semiconductor chip, the thickness of the dielectric structure is reduced, which in turn reduces the depth of blind vias. Therefore, the number of blasting operations and the size of the vias can be reduced to meet the requirements of small vias (approximately 20 micrometers). In addition, in the above embodiments, a patterned opening can be pre-formed in the polymer layer, which can reduce the cost of subsequent laser etching of the polymer layer and avoid the problems caused by prolonged blasting operation time and reduced copper surface quality of the conductive layer when blasting is used to remove both the dielectric structure and the polymer layer simultaneously, because the destructive force of blasting on the dielectric structure is greater than that on the polymer layer.

[0079] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. An embedded component packaging structure, comprising: One dielectric structure; A semiconductor chip is embedded in this dielectric structure; A first polymer layer covers the semiconductor chip; A patterned conductive layer covers an upper surface of the dielectric structure and extends above the first polymer layer; the patterned conductive layer is electrically connected to the semiconductor chip. A second polymer layer; and A redistribution layer is stacked between the first polymer layer and the second polymer layer. The first polymer layer has a first opening, and the dielectric structure has a second opening, wherein the first opening is smaller than the second opening.

2. The embedded component packaging structure according to claim 1, wherein the first polymer layer has a first thickness, the first thickness being greater than a second thickness of the dielectric structure located above the first polymer layer.

3. The embedded component packaging structure according to claim 2, wherein the second opening overlaps with the first opening.

4. The embedded component packaging structure according to claim 1, wherein the dielectric structure extends along one side surface of the semiconductor chip and one side surface of the first polymer layer to the first polymer layer.

5. The embedded component packaging structure according to claim 1, wherein the patterned conductive layer passes through the first opening of the first polymer layer.

6. The embedded component packaging structure according to claim 5, wherein the patterned conductive layer contacts the redistribution layer in the first opening.

7. The embedded component packaging structure according to claim 1, wherein the semiconductor chip includes at least one electrical pad, and the redistribution layer extends laterally on the at least one electrical pad.

8. The embedded component packaging structure according to claim 7, wherein the first polymer layer covers the at least one electrical pad.

9. The embedded component packaging structure according to claim 7, wherein the second polymer layer is disposed between the at least one electrical pad and the redistribution layer.

10. The embedded component packaging structure according to claim 7, wherein the second polymer layer simultaneously contacts the first polymer layer, the at least one electrical pad, the redistribution layer, and the dielectric structure.

11. The embedded component packaging structure according to claim 1, wherein the dielectric structure covers one side surface of the first polymer layer and one side surface of the second polymer layer.

12. The embedded component packaging structure according to claim 1, wherein the overall thickness of the first polymer layer is greater than the overall thickness of the second polymer layer.

13. An embedded component packaging structure, comprising: One dielectric structure; A semiconductor chip is embedded in this dielectric structure; A first polymer layer covers the semiconductor chip, wherein the first polymer layer has a first opening, the dielectric structure has a second opening, and the first opening is smaller than the second opening; A patterned conductive layer covers an upper surface of the dielectric structure and extends above the first polymer layer and into the first and second openings. The patterned conductive layer is electrically connected to the semiconductor chip.

14. The embedded component packaging structure according to claim 13, wherein the first polymer layer has a first thickness, the first thickness being greater than a second thickness corresponding to the dielectric structure located above the first polymer layer.

15. The embedded component packaging structure according to claim 14, further comprising a redistribution layer disposed between the semiconductor chip and the first polymer layer.

16. The embedded component packaging structure of claim 15, wherein the first polymer layer covers the entire redistribution layer and at least one electrical pad of the semiconductor chip.

17. The embedded component packaging structure of claim 15, wherein the second opening overlaps with the first opening, and the patterned conductive layer extending above the dielectric structure and the first polymer layer passes through the overlapping second opening and the first opening to contact the redistribution layer.

18. The embedded component packaging structure according to claim 15, wherein the redistribution layer is disposed between the first polymer layer and a second polymer layer.

19. The embedded component packaging structure according to claim 17, wherein the dielectric structure simultaneously contacts an upper surface and a side surface of the first polymer layer.

20. An embedded component packaging structure, comprising: A dielectric structure formed from a single piece; A semiconductor chip is embedded in this dielectric structure; A first polymer layer covers the semiconductor chip; as well as A patterned conductive layer covers the dielectric structure and extends over the first polymer layer, wherein the patterned conductive layer extends into an opening in the first polymer layer and is electrically connected to the semiconductor chip. The patterned conductive layer covers an upper surface of the dielectric structure and an upper surface and one side surface of the first polymer layer, and One upper surface of the dielectric structure is lower than one upper surface of the first polymer layer.

Images