A co-pos and satellite pcb integrated packaging structure suitable for space scene

Abstract

The application discloses a CoPoS and satellite PCB integrated packaging structure suitable for a space scene, which comprises a mainboard PCB, a thick copper power supply assembly embedded in a containing groove, a CoPoS photoelectric co-packaging module, a gradient CTE stress buffer layer clamped between the CoPoS photoelectric co-packaging module and the mainboard PCB, a sealing shielding cover, a fiber guiding and positioning assembly and an in-situ sensing unit; the thermal expansion coefficient of the carrier plate is between the thermal expansion coefficient of the glass interlayer and the thermal expansion coefficient of the mainboard PCB; the thick copper power supply assembly vertically abuts the bottom surface of the chip to form a direct power supply path; and the shielding cover is fully sealed to form an anti-radiation cavity. The application solves the thermal mismatch cracking problem through CTE gradient transition, the heavy metal shielding cover resists cosmic rays, the vertical thick copper power supply controls the IR voltage drop within 30 mV, and the fiber stress release and in-situ sensing are combined to realize real-time monitoring, so that the application can tolerate the thermal cycle of -180 DEG C to +150 DEG C and high-energy particle radiation.

Description

Technical Field

[0001] This invention belongs to the fields of advanced semiconductor packaging and aerospace electronic circuit technology, specifically involving optoelectronic co-packaging (CoPoS) and satellite printed circuit board (PCB) heterogeneous integration packaging technology, which is particularly suitable for high-speed optoelectronic integrated packaging products in extreme space environments such as low-orbit satellites, on-board computing nodes, and satellite broadband communications. Background Technology

[0002] As the scale of low-Earth orbit satellite networks continues to expand, onboard equipment has evolved from traditional communication relay equipment into orbital data centers with ultra-high computing power, placing stringent requirements on ultra-high-speed optoelectronic transmission of 1.6T and above per link, high-current power supply, and long-life reliable operation. Currently, the industry mainstream adopts optoelectronic co-packaging (CoPoS / CPO) technology to shorten the signal transmission path and reduce high-speed signal loss and overall power consumption. However, when the conventional CoPoS architecture is directly applied to space scenarios, there are three major technical bottlenecks.

[0003] First, there is the issue of thermomechanical failure. The temperature difference between day and night in space orbit can reach -180℃ to +150℃. The coefficients of thermal expansion (CTE) of the CoPoS glass interposer, satellite PCB, and semiconductor chip differ significantly. Repeated temperature cycling generates severe interlayer shear stress, leading to interface cracking, fatigue fracture of microbumps and BGA solder joints, and ultimately, failure of the entire package structure. Current technologies use only a single substrate for simple CTE matching, which cannot meet the thermal deformation compensation requirements over an ultra-wide temperature range.

[0004] Second, there is the issue of interference from cosmic radiation. The space environment contains a large number of high-energy rays and charged particles. Conventional packaging shells cannot effectively block particle penetration, which can easily cause chip logic flips, high-frequency signal anomalies, and single-event effects (SEE), potentially leading to instantaneous shutdown of onboard equipment in severe cases. Traditional aerospace electronics often use partial coating shielding or surface metal shielding, which have limited shielding effectiveness and cannot provide complete sealed protection for CoPoS optoelectronic modules.

[0005] Third, there is the issue of high-current power supply losses. Onboard computing chips require power supplies in the thousands of amperes. Existing satellite PCBs generally use a multi-layer horizontal wiring structure, resulting in long conductive paths, significant voltage drop (IRDrop) and heat generation issues in the power supply circuit, and excessive voltage sags, making it difficult to ensure the stable operation of high-power chips. At the same time, conventional CoPoS and satellite PCBs are assembled separately, resulting in a large overall size and weight, which is not conducive to miniaturized satellite integration applications.

[0006] In addition, during the operation of space satellites in orbit, vibration and temperature changes can cause the optical fiber coupling position to shift, leading to an increase in optical link loss. Traditional space packaging only adopts passive protection measures, which cannot monitor the internal temperature and stress state of the packaging in real time and does not have the ability to actively compensate for faults, further limiting the service life and operational reliability of spaceborne high-speed optoelectronic systems. Summary of the Invention

[0007] The purpose of this invention is to provide a CoPoS and satellite PCB integrated packaging structure suitable for space scenarios. Through multi-structure collaborative design, it simultaneously achieves thermal stress buffering, radiation resistance, high current low loss power supply, high-precision optical interconnection, real-time status monitoring and dynamic compensation, meeting the needs of low-orbit satellites in extreme environments.

[0008] The objective of this invention is achieved through the following technical solution: A CoPoS integrated package structure for satellite PCBs suitable for space applications includes: The motherboard assembly includes a motherboard PCB, on which a receiving slot and several fiber optic guiding through holes are provided; A thick copper power supply component is embedded in the receiving groove; The CoPoS optoelectronic co-package module includes a glass interposer, an ASIC chip, and multiple silicon photonic engines. The ASIC chip and the silicon photonic engines are flip-chip integrated onto the surface of the glass interposer via microbumps. The glass interposer has glass vias inside, and vertical interconnect pins are formed inside the glass vias. A gradient CTE stress buffer layer is disposed between the CoPoS optoelectronic co-packaging module and the motherboard PCB. It includes a carrier board fabricated using mSAP fine circuit technology. The thermal expansion coefficient of the carrier board is between that of the glass interposer and the motherboard PCB. The carrier board has buffer pins inside that are connected to the vertical interconnect pins, and the bottom surface of the carrier board has multiple three-dimensional elastic conductive pins for electrical connection with the motherboard PCB. A shielding cover and a sealing cover are located on the outside of the CoPoS optoelectronic co-package module and are fixedly connected to the motherboard PCB to form a sealed protective chamber. The fiber optic guidance and positioning assembly includes an elastic stress relief fixture assembled in the fiber optic guidance through-hole for guiding the fiber optic cable and releasing stress. The in-situ sensing unit is located on the motherboard PCB outside the CoPoS optoelectronic co-package module. It is used to collect temperature and / or mechanical stress data inside the package structure and feed the data back to the ASIC chip.

[0009] As a further improvement of the present invention, the thick copper power supply component is a solid copper block or copper alloy conductive block with a purity of ≥99.99% and a thickness of ≥100μm. The upper end of the thick copper power supply component passes through the gradient CTE stress buffer layer and directly abuts the bottom surface of the ASIC chip, forming a vertical direct power supply path with a length of ≤1mm.

[0010] As a further improvement of the present invention, the thermal expansion coefficient of the carrier plate is 10~15ppm / ℃, the thermal expansion coefficient of the glass interlayer is 3.0~3.5ppm / ℃, and the thermal expansion coefficient of the motherboard PCB is 16~22ppm / ℃.

[0011] As a further improvement of the present invention, the three-dimensional elastic conductive pin has a pin height of 80±5μm, a pin height uniformity of ≤±3μm, a single pin conduction resistance of ≤0.03Ω, an overall coplanarity of ≤8μm, and the three-dimensional elastic conductive pin can achieve bidirectional deformation compensation of ±30μm.

[0012] As a further improvement of the present invention, the shielding cover is made of tungsten, tantalum, gold, or a composite alloy thereof, and the shielding cover and the motherboard PCB are sealed together continuously around the circumference using aerospace-grade radiation-resistant thermally conductive adhesive, with an overall airtightness ≤1×10⁻⁶. -9 Pa·m³ / s, and the shielding effectiveness of the shielding cover against 10MeV protons is ≥35dB.

[0013] As a further improvement of the present invention, the in-situ sensing unit includes a thin-film thermistor and a precision strain gauge, with a sampling frequency of 10Hz, a temperature detection accuracy of ±0.5℃, and a strain resolution of 0.1με.

[0014] As a further improvement of the present invention, the bottom of the motherboard PCB is provided with BGA solder balls, and the motherboard PCB, the in-situ sensing unit and some of the BGA solder balls are covered with an encapsulation protective layer formed by insulating protective glue, wherein the insulation resistance of the insulating protective glue is ≥10¹²Ω·cm.

[0015] As a further improvement of the present invention, the aperture of the vertical interconnecting pin is ≤20μm, the buffer pin is formed in a micro blind hole with an aperture of 25~30μm, and the alignment deviation between the micro blind hole and the glass through hole is ≤±2μm.

[0016] As a further improvement of the present invention, the elastic stress relief fixture in the optical fiber guiding and positioning assembly is made of fluororubber and is fitted with the inner wall of the optical fiber guiding through hole and the outer wall of the optical fiber with a gap. The optical fiber is cured and shaped by UV glue, with an optical alignment accuracy of ±1μm and an optical signal insertion loss of ≤0.3dB.

[0017] A method for fabricating a CoPoS integrated package structure with a satellite PCB suitable for space applications includes the following steps: Step 1: Prepare the motherboard PCB and process the accommodating groove and fiber optic guiding through hole on the motherboard PCB; Step 2: Embed the thick copper power supply component into the receiving slot and fix it in place; Step 3: Prepare the CoPoS optoelectronic co-package module by flip-chip integrating the ASIC chip and silicon photonic engine onto the surface of a glass interposer with vertical interconnect pins. Step 4: Prepare a gradient CTE stress buffer layer, process buffer pins on the carrier plate and assemble three-dimensional elastic conductive pins; Step 5: The CoPoS optoelectronic co-packaged module and the gradient CTE stress buffer layer are joined by thermo-pressing to make the vertical interconnect pins and the buffer pins conduct to each other. Step 6: Install the fiber optic guidance and positioning assembly, pass the fiber optic cable through the fiber optic guidance through hole and assemble the elastic stress relief fixture; Step 7: Install the shielding cover and seal it with radiation-resistant thermally conductive adhesive; Step 8: Integrate the in-situ sensing unit on the motherboard PCB, and perform BGA balling and insulating protective coating.

[0018] The above technical solution has the following beneficial effects: 1. By setting a gradient CTE stress buffer layer (the carrier board CTE is 10~15ppm / ℃, between the glass interlayer CTE of 3.0~3.5ppm / ℃ and the motherboard PCB CTE of 16~22ppm / ℃), a linear thermal expansion coefficient transition structure is constructed, which effectively eliminates the thermal mismatch stress at the multi-material interface; combined with three-dimensional elastic conductive pins (which can achieve ±30μm bidirectional deformation compensation), it dynamically absorbs the horizontal and vertical shear stress generated by the ultra-wide temperature range of -180℃ to +150℃ in space, fundamentally avoiding interlayer cracking and solder joint fatigue fracture, and can successfully pass 100 extreme thermal cycle tests.

[0019] 2. A full-circumference sealed shielding cover made of heavy metals such as tungsten, tantalum, and gold or composite alloys replaces the traditional partial coating shielding, forming a fully sealed protective cavity. The shielding effectiveness against 10MeV protons reaches more than 35dB, effectively blocking high-energy particles and cosmic rays, significantly reducing the risk of radiation failures such as single-event upset and single-event latch-up, and meeting the requirements for long-life on-orbit operation of satellites.

[0020] 3. A solid copper block with a purity of ≥99.99% is used as a thick copper power supply component. It is vertically embedded in the motherboard accommodating slot and directly contacts the bottom surface of the ASIC chip, forming a direct vertical power supply path with a length of ≤1mm. This replaces the traditional multi-layer horizontal wiring and can stably carry large currents of thousands of amperes. The power supply IR voltage drop is controlled within 30mV, which greatly reduces power loss and heat generation and improves the stability of chip power supply.

[0021] 4. By interconnecting vertical interconnect pins with an inner aperture of ≤20μm in the glass interlayer with corresponding high-precision micro-blind hole buffer pins in the carrier plate, the photoelectric signal transmission path is significantly shortened. Combined with the fine control of high-frequency impedance deviation ≤±5Ω and return loss ≤-15dB, it stably supports ultra-high bandwidth signal transmission of 1.6T and above, meeting the needs of high-speed data processing on space.

[0022] 5. A fluororubber elastic stress relief fixture is installed in the fiber guide hole to dynamically buffer the fiber tension and offset stress caused by satellite on-orbit vibration and temperature change, ensuring fiber optical alignment accuracy of ±1μm, insertion loss ≤0.3dB, and loss drift after vibration not exceeding 0.05dB, effectively avoiding fiber breakage and coupling offset.

[0023] 6. An in-situ sensing unit composed of a thermistor and a strain gauge is integrated to collect temperature and stress data inside the package in real time (accuracy ±0.5℃, resolution 0.1με) and feed it back to the ASIC chip for dynamic parameter analysis and fault compensation, realizing full life cycle health monitoring and active fault-tolerant control, and improving on-orbit service reliability. Attached Figure Description

[0024] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0025] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0026] Figure 1 This is a schematic diagram of the preparation process provided by the present invention.

[0027] Figure 2This is a schematic diagram of the structure provided in step 1 of the present invention.

[0028] Figure 3 This is a schematic diagram of the structure provided for step 2 of the present invention.

[0029] Figure 4 This is a schematic diagram of the structure provided in step 3 of the present invention.

[0030] Figure 5 This is a schematic diagram of the structure provided in step 4 of the present invention.

[0031] Figure 6 This is a structural schematic diagram provided for step 5 of the present invention.

[0032] Figure 7 This is a structural schematic diagram provided for step 7 of the present invention.

[0033] Figure 8 This is a structural schematic diagram provided for step 8 of the present invention.

[0034] In the picture: 1. Mainboard PCB; 11. Receiving slot; 12. Fiber optic guide hole; 2. Thick copper power supply components; 3. Glass interlayer; 31. Vertical interconnect pins; 4. ASIC chip; 5. Silicon photonics engine; 6. Carrier plate; 61. Buffer pin; 7. Three-dimensional elastic conductive pins; 8. Optical fiber; 9. Shielding cover; 10. In-situ sensing unit; 11. Encapsulation layer. Detailed Implementation

[0035] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the component itself in the vertical, perpendicular, or gravitational direction; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0036] like Figure 1 As shown, a CoPoS integrated packaging structure for satellite PCBs suitable for space applications is fabricated. The core focus is on optimizing structural design and process parameters for the conditions of strong radiation, alternating high and low temperatures, high current power supply, and micro-vibration in space. This enables integrated packaging of the CoPoS architecture and satellite PCBs, effectively addressing the technical shortcomings of traditional satellite PCBs, such as large voltage drop in horizontal power supply wiring, severe heat generation, poor mechanical resistance, and insufficient radiation tolerance. The process includes the following steps: Step 1: Fabrication of the Mainboard Components: A space-grade, high-layer flame-retardant printed circuit board (PCB1) is selected as the mainboard. The PCB has 20 or more layers to meet the multi-layer functional requirements of satellite high-frequency signal transmission, multi-channel power distribution, and protection against the space environment. The PCB1 is designed with a layered layout, sequentially including a radiation shielding layer, a ground layer, a high-frequency signal layer, and a core power supply layer. Each layer is independently partitioned to avoid interference between power supply lines and high-frequency signal lines. Simultaneously, the radiation shielding layer protects the circuitry from damage caused by cosmic rays and particle radiation.

[0037] A recess 11 is formed on the motherboard PCB1 for mounting the thick copper power supply component 2. Several fiber optic guide vias 12 are formed around the perimeter of the motherboard PCB1. The motherboard PCB1 serves as the sole supporting substrate for the integrated package structure, comprehensively undertaking the functions of mechanical support, power distribution, high-frequency signal transmission, and structural positioning. The structure of the product manufactured from it is as follows: Figure 2 As shown.

[0038] The specific fabrication method of the motherboard PCB1 is as follows: First, the entire board is ultrasonically cleaned for 5 minutes to remove dust, oil, and processing debris from the board surface. After cleaning, it is dried with high-purity nitrogen to avoid residual impurities affecting the accuracy of subsequent laser processing. Then, a UV laser drilling machine is used to precisely process the preset positions to form the receiving groove 11 and the fiber optic guiding through hole 12. The processing parameters are fixed as laser power 15–20W and pulse width 10–20ns. The laser processing path avoids the high-frequency circuit area of ​​the board throughout to prevent laser burning and micro-cracks from damaging the circuit structure.

[0039] After processing, the board surface is activated using 300W plasma cleaning, with the vacuum level controlled at 50Pa or below to improve the bonding stability of subsequent bonding and welding processes. Finally, the board is baked at 120±5℃ for 60 minutes to thoroughly remove internal moisture and residual solvents. Process control requirements: the dimensional error of the receiving groove and fiber optic through-hole does not exceed ±10μm; the hole and groove walls are free of burrs and carbon deposits; the surface tension of the board is not less than 38 dyne; and the board must enter the next assembly process within 2 hours after baking to avoid secondary adsorption of impurities and moisture.

[0040] Step 2: Integration, fabrication, and fixing of the thick copper power supply component. In this solution, the thick copper power supply component 2 is fabricated using a solid copper block with a purity ≥99.99%. The copper block thickness is set to over 100μm, which can be equivalently replaced by a high-purity copper alloy conductive block, both meeting the requirements for high-current conductivity. Vertical guide lines are pre-fabricated on the surface of the copper block. After assembly, the guide lines penetrate the gradient CTE stress buffer layer and directly adhere to the bottom surface of the ASIC chip 4, constructing a vertical direct-connection power supply path with a length of less than 1mm, replacing the traditional multi-layer horizontal wiring structure. By constructing a chip-direct-connection vertical power supply channel, it can stably carry kiloampere-level high currents, controlling the power supply IR voltage drop to within 30mV, significantly reducing power loss and heat generation. The fabricated product structure is as follows: Figure 3 As shown.

[0041] Specific assembly and curing process: A 20±5μm thick conductive silver paste is evenly coated on the back of the solid copper block. Using an automated vision alignment mechanism, the solid copper block is precisely aligned and vertically embedded into the receiving slot 11 of the motherboard PCB1. After alignment, it is fixed by laser four-point spot welding. The laser power is controlled at 8–12W, and the welding time is 0.2–0.5s per weld. After welding, it is placed in a constant temperature environment of 150℃ for 30 minutes to ensure bonding and welding stability. After curing, an X-ray inspection instrument is used for all-round inspection to ensure that the component is free from misalignment, cold solder joints, and voids. Process control requirements: Solid copper block mounting accuracy ±10μm, weld structure strength ≥5N, overall conductivity ≤0.05mΩ. After assembly, a matching sealing cover plate is used to completely seal the thick copper power supply component inside the receiving slot, improving the structure's resistance to space micro-vibration and vacuum aging.

[0042] Step 3: Fabrication of the CoPoS optoelectronic co-package module. The CoPoS optoelectronic co-package module of this structure mainly consists of a glass interposer 3, an ASIC chip 4, and multiple silicon photonic engines 5, achieving overall optoelectronic heterogeneous integrated packaging. The ASIC chip 4 serves as the core computing power processing chip, and the silicon photonic engines 5 are high-speed optoelectronic conversion devices. Both can be flip-chip integrated onto the surface of the glass interposer 3 using a micron-level microbump structure, completing the heterogeneous integration layout of the computing power processing unit and the optoelectronic transmission unit.

[0043] The glass interposer 3 has several vias (TGVs) internally, with the via diameter controlled to 20μm or less. The via diameter parameters can be fine-tuned according to wiring density requirements. High-density vertical interconnect pins 31 are formed inside the TGVs using either solid copper pins or full-area copper plating. These vertical interconnect pins 31 correspond to the electrical pins of the ASIC chip 4 and the silicon photonics engine 5, significantly shortening the photoelectric signal transmission path, effectively reducing signal attenuation and latency, and stably supporting ultra-high bandwidth photoelectric signal transmission of 1.6T and above, meeting the high-speed data processing and transmission requirements of space satellites. The fabricated product structure is as follows: Figure 4 As shown.

[0044] The specific fabrication method of the CoPoS optoelectronic co-package module is as follows: First, according to the circuit wiring diagram, the glass interposer 3 is precision drilled to form glass through-holes, with strict control over the hole diameter accuracy. Then, vertical interconnect pins 31 are fabricated inside the through-holes through copper filling and copper plating processes. After processing, the glass interposer 3 is thoroughly cleaned to remove processing dust and metal residues, and the conductivity and appearance integrity of each vertical interconnect pin 31 are tested. All subsequent processes are carried out in a Class 1000 cleanroom environment to avoid contamination leading to interconnect failure. Next, a hot-press bonding process is used to flip-chip mount the computing chip and silicon photonics engine, with the process temperature controlled at 200–220℃ and the bonding pressure controlled at 0.3–0.6MPa. Process control requirements: the alignment accuracy of the computing chip and silicon photonics engine is ±5μm, with no soldering defects such as cold solder joints or bridging; the conductivity of all interconnect points is 100%; and the optical alignment deviation is ≤±2μm, ensuring the stability and reliability of the module's optoelectronic transmission.

[0045] Step 4: Fabrication of the Gradient CTE Stress Buffer Layer. The core of the gradient CTE stress buffer layer is a carrier board 6 fabricated using mSAP fine circuitry. The carrier board 6 is sandwiched between the glass interposer 3 and the mainboard PCB 1, serving as a transition structure for the coefficient of thermal expansion. The coefficient of thermal expansion of the carrier board 6 is set to 10–15 ppm / ℃, falling between that of the glass interposer 3 (3.0~3.5 ppm / ℃) and the mainboard PCB 1 (16~22 ppm / ℃), forming a linear gradient transition structure. This structure can adapt to the ultra-wide temperature range of thermal cycling conditions in space (-180℃~+150℃), fundamentally weakening the interlayer shear stress caused by the mismatch in the coefficients of thermal expansion of different materials and solving the problem of interlayer cracking in the packaging structure.

[0046] Micro-blind vias are laser-processed inside the carrier board 6. The diameter of the micro-blind vias is controlled at 25–30 μm. The micro-blind vias correspond one-to-one with the glass vias in the glass interposer layer 3, and the alignment deviation is strictly controlled within ±2 μm. Buffer pins 61 are formed inside the micro-blind vias through an electroplating filling process. The electroplated copper layer thickness is 10–15 μm, requiring a copper layer thickness uniformity error ≤ ±5%, a high-frequency impedance deviation ≤ ±5Ω, and an overall flatness of the carrier board ≤ 10 μm to ensure the stability of high-frequency signal transmission. A circuit layer electrically connected to the buffer pins 61 is prepared at the bottom of the carrier board. Multiple sets of three-dimensional elastic conductive pins 7 are set between the carrier board 6 and the main board PCB1, replacing the traditional micro-bump and BGA solder joint structure. This avoids the defects of traditional solder joints being prone to fatigue cracking and failure under space temperature change cycles.

[0047] The three-dimensional elastic conductive pin 7 is fixed by conductive adhesive dispensing and curing, with its lower end connecting to the motherboard PCB1 and its upper end connecting to the circuit layer of the carrier board 6. This three-dimensional elastic conductive pin 7 can achieve ±30μm bidirectional deformation compensation, dynamically absorbing horizontal and vertical bidirectional stresses generated by extreme temperature changes in space, significantly improving the environmental adaptability of the packaging structure. The process parameters for the three-dimensional elastic conductive pin 7 are controlled as follows: pin height 80±5μm, pin height uniformity ≤±3μm, single pin on-resistance ≤0.03Ω, and overall coplanarity ≤8μm, ensuring the stability and consistency of interlayer interconnects. The structure of the fabricated product is as follows. Figure 5 As shown. The installation sequence of the above-mentioned three-dimensional elastic conductive pins 7 can also be placed after the CoPoS optoelectronic co-package module and the gradient CTE stress buffer layer are thermally pressed together, so as to avoid damage to the three-dimensional elastic conductive pins 7 by the thermal pressing of the two.

[0048] Step 5: Hot-press bonding of the CoPoS optoelectronic co-package module with the gradient CTE stress buffer layer. This process uses a high-precision automatic optical alignment system to achieve precise interlayer interconnection. Before processing, lead-free solder is evenly applied to the end face of the buffer pins 61 on the carrier board. Then, the alignment and calibration of the CoPoS optoelectronic co-package module are completed by automatic optical recognition of the equipment. The module is vertically pressed down to make the vertical interconnect pins 31 at the bottom of the glass interposer 3 correspond one-to-one with the buffer pins 61. The hot-press bonding process is completed in a high vacuum environment. The process parameters are strictly limited to: hot-pressing temperature 210–240℃, bonding pressure 0.5–0.8MPa, holding time 20–40s, working vacuum degree controlled within 10Pa, and the equipment heating and cooling rate uniformly set to 10℃ / s. This vacuum hot-pressing method can effectively eliminate interlayer bubbles and void defects. Compared with ordinary normal pressure welding, the interlayer bonding density and high-frequency transmission stability are significantly improved. Process quality requirements: interlayer bonding strength not less than 8N, high-frequency impedance matching error controlled within 5%, and return loss RL ≤ -15dB for 1.6T high-speed signals. After the process is completed, a gradient cooling method must be adopted, and pressure can only be released after the structure has completely cooled and the stress has stabilized to avoid microcracks and solder joint misalignment caused by rapid pressure release. The structure of the manufactured product is as follows: Figure 6 As shown.

[0049] Step 6: Fiber Optic Guidance and Stress Relief Fixture Installation. This step is used to achieve high-precision, low-loss fiber optic connection and dynamic stress relief, adapting to long-term stable fiber optic transmission under conditions of space vibration and temperature changes. One end of the fiber optic cable 8 is precisely connected to the optical interface of the silicon photonics engine 5, and the other end passes through the fiber optic guidance through-hole 12 around the periphery of the motherboard PCB1. At the same time, an elastic stress relief fixture made of fluororubber is installed inside the fiber optic guidance through-hole 12. The stress relief fixture, the inner wall of the fiber optic guidance through-hole 12, and the outer wall of the fiber optic cable are fitted with a gap to form the fiber optic guidance and positioning assembly.

[0050] The fiber optic guidance and positioning assembly dynamically buffers the tension and misalignment stress on the fiber optic cable caused by satellite on-orbit vibration and thermal expansion and contraction of materials, preventing fiber misalignment, breakage, or compression damage. After assembly, UV adhesive is used to cure and shape the fiber optic cable position. The UV curing process parameters are: light power 800–1200mW / cm², curing time 20–30s. Process control requirements: fiber optic alignment accuracy ±1μm, optical signal insertion loss ≤0.3dB, loss drift after mechanical vibration testing not exceeding 0.05dB; stress-free clamping throughout the process, no bending or compression deformation of the fiber optic cable, and stress relief fixtures must not protrude from the plate surface to cause structural interference.

[0051] Step 7: Assembly and Sealing of the Radiation-Resistant Shielding Cover. To adapt to the strong radiation and high vacuum working environment of space, this solution adopts an overall metal shielding cover structure, which differs from traditional partial shielding and coating shielding methods. The shielding cover 9 is made of tungsten, tantalum, gold, or a composite alloy of multiple metals. It is entirely covered on the outside of the CoPoS optoelectronic co-package module, the gradient CTE stress buffer layer, and the fiber optic guide hole 12. It is fixed and fully sealed with space-grade radiation-resistant thermally conductive adhesive to form a sealed radiation-resistant protective chamber. This structure can effectively block high-energy protons and cosmic rays in space, significantly reducing the risk of radiation failure such as single-event upset and single-event latch-up. The 10MeV proton shielding effectiveness can reach more than 35dB, meeting the long-life on-orbit operation requirements of satellites. The shielding cover 9 and the mainboard PCB1 adopt a full-circumferential continuous sealing bonding method, and the overall airtightness of the structure is ≤1×10 -9 Pa·m³ / s effectively resists gas leakage problems in the high vacuum environment of space. Simultaneously, the radiation-resistant thermally conductive adhesive used combines airtight sealing, electromagnetic shielding assistance, and structural heat dissipation functions, achieving integrated adaptation of multiple performance characteristics. The structure of the resulting product is as follows: Figure 7 As shown.

[0052] Step 8: In-situ Sensing Unit Integration and Packaging. An in-situ sensing unit 10 is integrated into the motherboard PCB1 area outside the CoPoS optoelectronic co-package module. This in-situ sensing unit 10 is composed of a thin-film thermistor and a precision strain gauge, capable of real-time acquisition of internal temperature and mechanical stress data of the package structure. The device sampling frequency is set to 10Hz, with a temperature detection accuracy of ±0.5℃ and a strain resolution of 0.1με, accurately capturing structural parameter changes caused by space temperature variations and mechanical loads. Data is transmitted back to the ASIC chip 4 in real time, where parameter analysis, dynamic adjustment, and fault compensation are performed, achieving full lifecycle health monitoring and active fault-tolerant control of the package structure. After the sensing unit assembly is completed, BGA balls are placed at the bottom of the motherboard PCB1, and an insulating protective adhesive with an insulation resistance ≥10¹²Ω·cm is used to completely encapsulate the motherboard PCB1, the in-situ sensing unit 10, and some BGA solder joints to form a protective packaging layer 11. This effectively isolates space dust and micro-discharge interference, improving the overall structural insulation protection and environmental tolerance performance. The resulting product structure is as follows. Figure 8 As shown.

[0053] like Figure 8 As shown, a CoPoS and satellite PCB integrated packaging structure suitable for space scenarios includes a motherboard assembly, a thick copper power supply assembly 2, a CoPoS optoelectronic co-packaging module, a gradient CTE stress buffer layer, a shielding cover 9, an optical fiber guiding and positioning assembly, and an in-situ sensing unit 10. The various structural layers are assembled together to achieve an integrated design of mechanical protection, electrical power supply, optoelectronic transmission, stress buffering, and condition monitoring.

[0054] The motherboard assembly includes a motherboard PCB1, which has a receiving groove 11 in the middle and several fiber optic guiding through holes 12 around its periphery. An elastic stress relief fixture is installed in the fiber optic guiding through holes 12. The thick copper power supply assembly 2 is placed in the receiving groove 11. The gradient CTE stress buffer layer includes a carrier board 6 fabricated using mSAP fine circuit technology. The carrier board 6 is sandwiched between the CoPoS optoelectronic co-packaging module and the motherboard PCB1. As a thermal expansion transition structure of multi-layer heterogeneous structure, its thermal expansion coefficient is set to 10–15ppm / ℃, which is between the thermal expansion coefficients of the glass interposer 3 and the motherboard PCB1. This can achieve a linear gradient transition of thermal expansion coefficients and effectively avoid interlayer cracking and solder joint failure caused by CTE mismatch of multiple materials.

[0055] The substrate 6 has laser-machined micro-blind vias inside, which are then filled with copper through electroplating to form buffer pins 61 for precise electrical interconnection between layers. The bottom surface of the substrate 6 is equipped with multiple sets of three-dimensional elastic conductive pins 7, which can achieve multi-directional deformation compensation and dynamically absorb interlayer stress caused by extreme temperature changes.

[0056] The CoPoS optoelectronic co-package module includes a glass interposer 3, an ASIC chip 4, and several silicon photonic engines. The ASIC chip 4 and silicon photonic engines 5 are flip-chip integrated onto the surface of the glass interposer 3 via microbumps, achieving heterogeneous optoelectronic integration. Glass vias are formed inside the glass interposer 3, and vertical interconnect pins 31 are formed inside the glass vias by copper plating, which can significantly shorten the optoelectronic signal transmission path and support stable transmission of ultra-high bandwidth signals of 1.6T and above.

[0057] The thick copper power supply component 2 is vertically embedded in the receiving slot 11 of the motherboard PCB1. The upper end of the thick copper power supply component 2 passes through the gradient CTE stress buffer layer and directly abuts the bottom surface of the core computing ASIC chip 4, forming a direct vertical power supply path. The shielding cover 9 is sealed and fastened to the outside of the CoPoS module and the motherboard PCB. It also blocks the fiber optic guide hole and forms a sealed protective cavity, which can effectively block cosmic rays and high-energy particle bombardment and reduce the risk of device failure caused by single-event effects.

[0058] The in-situ sensing unit 10 is located on the mainboard PCB1 outside the CoPoS optoelectronic co-package module. It consists of a thermistor and a precision strain gauge and can collect the internal temperature and mechanical stress data of the package in real time and feed them back to the ASIC chip 4 to complete dynamic parameter compensation. Finally, the entire package is encapsulated with insulating protective glue to form the encapsulation layer 11, which improves the structural insulation protection and environmental adaptability.

[0059] The aforementioned CoPoS integrated packaging structure with satellite PCB is adapted to the low-orbit satellite space environment, can withstand extreme temperature cycles of -180℃ to +150℃, resist high-energy particle radiation from the universe, and simultaneously achieve high-current power supply at the kiloampere level and ultra-high bandwidth optoelectronic signal transmission of 1.6T and above.

[0060] This invention discloses a CoPoS and satellite PCB integrated packaging structure suitable for space scenarios, comprising seven core components: a motherboard PCB, a CoPoS optoelectronic co-packaging module, a gradient CTE stress buffer layer, a thick copper power supply component, a shielding cover, an optical fiber guidance and positioning component, and an in-situ sensing unit. Through multi-structure collaborative design, it simultaneously achieves thermal stress buffering, radiation resistance, high-current low-loss power supply, high-precision optical interconnection, real-time status monitoring and dynamic compensation, meeting the usage requirements of low-Earth orbit satellites in extreme environments.

[0061] This technology specifically addresses core issues in the optoelectronic packaging structure of space satellites, such as temperature-induced failure, radiation interference, power loss, and signal instability. First, a gradient CTE stress buffer layer ensures a smooth transition of thermal expansion coefficients between different structural layers, effectively resolving the multi-material thermal expansion mismatch defects between the glass interposer, carrier board, and motherboard PCB, enabling long-term tolerance to the ultra-wide temperature range of space-time thermal cycling conditions. Second, a fully enclosed protective cavity is constructed using a shielding cover made of heavy metal or composite alloy materials, providing comprehensive protection against interference from high-energy particles and radiation from space compared to traditional partial coating shielding. An embedded vertical thick copper power supply component creates the shortest direct-connection power supply path for the chip, achieving high-current, low-loss power supply at the kiloampere level. Combined with an optical fiber elastic stress release structure, this ensures stable optical link transmission under extreme conditions. Simultaneously, in-situ sensing units enable real-time monitoring and dynamic compensation of structural temperature and stress, improving the on-orbit stability of the packaging structure. Verified through multiple environmental reliability tests, this structure can successfully pass 100 cycles of thermal cycling at -180℃ to +150℃, full-range vibration testing from 20 to 2000Hz, and high-energy proton radiation testing with 10MeV protons and an equivalent dose of 1×10¹²p / cm². Under operating conditions, the power supply IR voltage drop is ≤30mV, and the reflection loss of a 1.6T high-speed signal is ≤-15dB. Compared to traditional packaging structures, the overall weight is reduced by 30%, and the power consumption is reduced by 22%. The overall structure is compact, and the core materials and manufacturing processes can be domestically produced for mass production. It can be widely adapted to various low-orbit satellite high-speed optoelectronic transmission systems.

[0062] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0063] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A CoPoS integrated packaging structure for satellite PCBs suitable for space applications, characterized in that, include: The motherboard assembly includes a motherboard PCB (1), on which a receiving groove (11) and a plurality of optical fiber guiding through holes (12) are provided. A thick copper power supply component (2) is embedded in the receiving groove (11); The CoPoS optoelectronic co-package module includes a glass interposer (3), an ASIC chip (4), and multiple silicon photonic engines (5). The ASIC chip (4) and the silicon photonic engines (5) are flip-chip integrated on the surface of the glass interposer (3) through microbumps. The glass interposer (3) has glass vias inside, and vertical interconnect pins (31) are formed inside the glass vias. A gradient CTE stress buffer layer is disposed between the CoPoS optoelectronic co-packaging module and the motherboard PCB (1). It includes a carrier board (6) prepared by mSAP fine circuit technology. The thermal expansion coefficient of the carrier board (6) is between the thermal expansion coefficient of the glass interposer (3) and the thermal expansion coefficient of the motherboard PCB (1). The carrier board (6) is provided with buffer pins (61) that are connected to the vertical interconnect pins (31). The bottom surface of the carrier board (6) is provided with multiple three-dimensional elastic conductive pins (7) for electrical connection with the motherboard PCB (1). The shielding cover (9) and the sealing cover are located on the outside of the CoPoS optoelectronic co-package module and are fixedly connected to the motherboard PCB (1) to form a sealed protective chamber; The fiber optic guidance and positioning assembly includes an elastic stress relief fixture fitted in the fiber optic guidance through-hole (12) for guiding the fiber optic cable (8) and releasing stress. The in-situ sensing unit (10) is located on the motherboard PCB (1) outside the CoPoS optoelectronic co-package module. It is used to collect temperature and / or mechanical stress data inside the package structure and feed the data back to the ASIC chip (4).

2. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The thick copper power supply component (2) is a solid copper block or copper alloy conductive block with a purity of ≥99.99% and a thickness of ≥100μm. The upper end of the thick copper power supply component (2) passes through the gradient CTE stress buffer layer and directly abuts the bottom surface of the ASIC chip (4), forming a vertical direct power supply path with a length of ≤1mm.

3. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The thermal expansion coefficient of the carrier board (6) is 10~15ppm / ℃, the thermal expansion coefficient of the glass interlayer (3) is 3.0~3.5ppm / ℃, and the thermal expansion coefficient of the motherboard PCB (1) is 16~22ppm / ℃.

4. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The three-dimensional elastic conductive pin (7) has a pin height of 80±5μm, a pin height uniformity of ≤±3μm, a single pin conduction resistance of ≤0.03Ω, an overall coplanarity of ≤8μm, and the three-dimensional elastic conductive pin (7) can achieve bidirectional deformation compensation of ±30μm.

5. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The shielding cover (9) is made of tungsten, tantalum, gold, or a composite alloy thereof. The shielding cover (9) and the motherboard PCB (1) are sealed together continuously around the circumference using aerospace-grade radiation-resistant thermally conductive adhesive, and the overall airtightness is ≤1×10⁻⁶. -9 Pa·m³ / s, and the shielding cover (9) has a shielding effectiveness of ≥35dB for 10MeV protons.

6. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The in-situ sensing unit (10) includes a thin-film thermistor and a precision strain gauge, with a sampling frequency of 10Hz, a temperature detection accuracy of ±0.5℃, and a strain resolution of 0.1με.

7. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The bottom of the motherboard PCB (1) is provided with BGA solder balls, and the outside of the motherboard PCB (1), the in-situ sensing unit (10) and some of the BGA solder balls are covered with an encapsulation protective layer (11) formed by insulating protective glue, and the insulation resistance of the insulating protective glue is ≥10¹²Ω·cm.

8. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The diameter of the vertical interconnecting pin (31) is ≤20μm, the buffer pin (61) is formed in a micro blind hole with a diameter of 25~30μm, and the alignment deviation between the micro blind hole and the glass through hole is ≤±2μm.

9. The CoPoS and satellite PCB integrated packaging structure according to claim 1, characterized in that, The elastic stress relief fixture in the fiber optic guiding and positioning assembly is made of fluororubber and is fitted with the inner wall of the fiber optic guiding through hole (12) and the outer wall of the fiber optic cable (8) with a gap. The fiber optic cable (8) is cured and shaped by UV glue, with an optical alignment accuracy of ±1μm and an optical signal insertion loss of ≤0.3dB.

10. A method for fabricating a CoPoS and satellite PCB integrated packaging structure suitable for space scenarios as described in any one of claims 1 to 9, characterized in that, Includes the following steps: Step 1: Prepare the motherboard PCB (1), and process the receiving groove (11) and the optical fiber guiding through hole (12) on the motherboard PCB (1). Step 2: Embed the thick copper power supply component (2) into the receiving groove (11) and fix it; Step 3: Prepare the CoPoS optoelectronic co-package module by flip-chip integrating the ASIC chip (4) and silicon photonic engine (5) onto the surface of a glass interposer (3) with vertical interconnect pins (31). Step 4: Prepare a gradient CTE stress buffer layer, process buffer pins (61) on the carrier plate (6) and assemble three-dimensional elastic conductive pins (7). Step 5: The CoPoS optoelectronic co-package module and the gradient CTE stress buffer layer are joined by thermo-pressing, so that the vertical interconnect pin (31) and the buffer pin (61) are connected accordingly; Step 6: Install the fiber optic guidance and positioning assembly, pass the fiber optic cable (8) through the fiber optic guidance through hole (12) and assemble the elastic stress relief fixture; Step 7: Install the shielding cover (9) and seal it with radiation-resistant thermally conductive adhesive; Step 8: Integrate the in-situ sensing unit (10) on the motherboard PCB (1), and perform BGA balling and insulating protective coating.

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