Method for manufacturing siC power device based on eutectic process

Abstract

The application discloses a preparation method of SiC power device based on eutectic process, and relates to the technical field of semiconductor power device packaging and manufacturing. The method provides a SiC wafer with a solderable metal layer on the back surface, the main component of the solderable metal layer being gold or silver, and the thickness of the solderable metal layer being 1-5 microns; and a TO-252AA lead frame with a plated layer on the base island; the wafer is precisely placed on the plated layer in a dry state without applying solder paste and adhesive; vacuum is drawn to 5-10 Pa, and then high-purity nitrogen is filled for protection; the temperature is raised in sections to the eutectic temperature, and reciprocating wiping is applied for heat preservation; the solderable metal layer and the plated layer metal are mutually diffused to form a eutectic alloy welding layer; and finally, nitrogen is passed to rapidly cool and solidify. The eutectic alloy welding layer is thin and continuous, and replaces the solder paste with a thickness of about 20 microns; the thermal resistance of the junction to the shell is reduced by about 40%; the rated current is increased from 8 A to 12 A; and the inclination of small-size crystal grains and the overflow of the solder paste are avoided, so that the packaging density and the reliability of the device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for fabricating SiC power devices based on a eutectic process. Background Technology

[0002] Silicon carbide (SiC) power devices possess excellent characteristics such as high critical breakdown electric field and high thermal conductivity, and are gaining an increasingly larger market share in power supply applications from 300V to 1200V and in new energy vehicles. SiC diodes can support higher switching frequencies and are an important component of high power density switching power supplies. However, whether the excellent thermal conductivity of SiC materials can be fully utilized depends to a large extent on the chip mounting materials and processes used in the chip mounting process.

[0003] In existing power device packaging surface mount technology (SMT) processes, adhesive or solder paste is typically applied or printed onto the base island of the lead frame. The thickness of the solder paste or silver paste is generally about 20 μm. The chip is then picked up and placed onto the solder paste or adhesive, followed by high-temperature curing to complete the mounting. In this SMT method based on organic adhesive or solder paste, the solder layer is composed of solder or organic adhesive, resulting in a relatively thick solder layer that is difficult to control uniformly.

[0004] Due to the relatively high defect density of SiC substrate materials, and considering stress distribution, SiC grains are typically very small, with individual grain areas ranging from 0.5 mm² to just a few tenths of a mm². For such small grains, when using traditional solder paste mounting, the surface tension of the molten solder and the uneven thickness of the solder layer can easily cause the grains to tilt and rotate, hindering subsequent bonding and wire bonding processes. Simultaneously, the solder paste tends to overflow around the grains when heated, requiring extra space on the base island to accommodate this overflow, limiting the increase in package density. Furthermore, a thicker solder paste layer has lower thermal conductivity, resulting in higher thermal resistance between the chip junction and the casing, making it difficult to fully utilize the high thermal conductivity of SiC materials. This leads to increased junction temperature during surge current pulses, limiting the maximum rated current and long-term reliability of the device.

[0005] Furthermore, the thermal conductivity of SiC power devices is particularly sensitive to the mounting material layer. Compared to silicon devices, SiC material itself has higher thermal conductivity. Therefore, the mounting material layer accounts for a relatively larger share of the thermal resistance in the entire junction-to-case heat dissipation path, making it one of the main bottlenecks limiting the heat dissipation capacity of SiC devices. When the mounting material layer is a thick solder paste with low thermal conductivity, the excellent thermal conductivity of SiC material is difficult to transfer to the case. Under high current and surge current conditions, the junction temperature of the chip rises, which not only limits the maximum rated current of the device but also accelerates the fatigue degradation of the solder layer microstructure due to the high junction temperature, thus affecting long-term reliability.

[0006] Therefore, the traditional surface mount technology (SMT) process based on solder paste or organic adhesive has shortcomings in terms of mounting accuracy of small SiC dies, thermal resistance of the solder layer, packaging density, and device reliability. It is difficult to fully utilize the excellent properties of SiC materials such as high thermal conductivity and high breakdown field strength. It is necessary to propose a new surface mount technology (SMT) process. Summary of the Invention

[0007] The present invention aims to provide a method for fabricating SiC power devices based on eutectic process to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.

[0008] According to a first aspect of this application, a method for fabricating a SiC power device based on a eutectic process is provided, for mounting a SiC wafer with a solderable metal layer on its back side onto a base island of a TO-252AA lead frame, comprising the following steps: A SiC wafer and a TO-252AA lead frame are provided. The back side of the SiC wafer has a solderable metal layer, the main component of which is gold or silver, and the thickness is 1~5μm. The base island surface of the TO-252AA lead frame has a plating layer. Without applying solder paste and adhesive, the SiC wafer is placed on the plating layer of the base island with the solderable metal layer facing down using a stacking fixture, so that the solderable metal layer and the plating layer are in dry contact. The lead frame containing the SiC wafer is placed in the bonding chamber, the vacuum is evacuated to 5-10 Pa, and then nitrogen gas is introduced into the bonding chamber for protection. The patch chamber is heated in stages: first, it is preheated, then heated to the eutectic temperature of the solderable metal layer and the plating layer and held at that temperature. During the holding period, the SiC wafer is subjected to reciprocating wiping relative to the base island to allow metal interdiffusion between the solderable metal layer and the plating layer, forming a eutectic alloy weld layer between the SiC wafer and the base island. Nitrogen gas is introduced into the mounting chamber for rapid cooling to solidify the eutectic alloy welding layer, resulting in the completed SiC power device TO-252AA package structure.

[0009] Preferably, the solderable metal layer is a solderable protective layer on the back side of a SiC wafer, and the main component of the solderable metal layer is gold.

[0010] Preferably, the plating of the base island contains tin or silver, and the eutectic alloy welding layer is a gold-tin eutectic alloy layer or a gold-silver eutectic alloy layer.

[0011] Preferably, the preheating temperature is 150~200℃; the temperature for heating to the eutectic temperature and holding at that temperature is 280~380℃.

[0012] Preferably, the reciprocating wiping involves rubbing the SiC wafer against the base island in a direction parallel to the surface of the base island to break the oxide film at the interface between the solderable metal layer and the plating layer.

[0013] Preferably, the eutectic alloy weld layer is a continuous interdiffusion metal alloy layer, the thickness of the eutectic alloy weld layer is less than 20 μm, and it does not contain organic adhesives or solder paste.

[0014] Preferably, after the step of rapidly cooling by introducing nitrogen into the patch chamber, the method further includes: performing appearance inspection, X-ray void detection, and shear force sampling on the finished package structure.

[0015] Preferably, two or more SiC wafers are soldered on the same base island, or a second SiC wafer is stacked on top of an already mounted SiC wafer.

[0016] Preferably, the SiC wafer is a SiC Schottky diode chip with a single die area of ​​0.5~5 mm. 2 .

[0017] According to a second aspect of this application, a TO-252AA package structure for a SiC power device is provided, comprising a TO-252AA lead frame and a SiC wafer mounted on a base island of the lead frame. The back side of the SiC wafer has a solderable metal layer, the main component of which is gold or silver, and the thickness is 1~5μm. The surface of the base island has a coating; A eutectic alloy welding layer is provided between the SiC wafer and the base island. The eutectic alloy welding layer is a continuous alloy layer formed by the interdiffusion of the solderable metal layer and the plating metal. The eutectic alloy welding layer is a metallurgical bonding layer with a thickness of less than 20 μm and does not contain organic adhesives or solder paste.

[0018] The embodiments of the present invention have the following advantages: This invention replaces the traditional approximately 20 μm solder paste layer with a solderable metal layer only 1-5 μm thick on the back side of the SiC wafer and a base island plating layer formed by metal interdiffusion. This significantly reduces the thickness of the solder layer. The resulting solder layer is an alloy layer formed by metal melting and interdiffusion, rather than an organic adhesive or solder paste bonding layer. Its thermal conductivity is significantly higher than that of solder paste, reducing the thermal resistance between the chip junction and the outer shell by approximately 40%. Because the contact between the SiC wafer and the base island is a dry metal during the chip mounting process, the solderable metal layer only interdiffused with the plating layer after being heated to the eutectic temperature. There is no molten solder paste or its surface tension during the chip mounting stage, so subsequent heating will not change the initial placement position of the die, effectively avoiding the tilting and rotation of small-sized SiC dies and ensuring the smooth progress of subsequent bonding and wire bonding processes. Since no solder paste is used, there is no solder paste overflow during the placement process, and there is no need to reserve space for solder paste overflow on the base island. This allows multiple SiC wafers or stacked chips to be mounted on the same base island, improving packaging density. The significant reduction in thermal resistance results in a marked decrease in the maximum junction temperature reached at the chip junction during surge current pulses, thereby increasing the maximum static current rating on a given die size. In this embodiment, the rated current of the SiC Schottky diode is increased from 8 A with conventional solder paste to 12 A with the eutectic surface mount of this invention, allowing for higher power output. The eutectic alloy solder layer is a metallurgical bond with shear strength and tensile strength far exceeding those of silver paste and solder paste. It is also more mechanically and thermodynamically stable than lead-containing solder, improving the temperature stability of Kirkendal void formation. The reduced maximum junction temperature also helps improve the fatigue life of devices based on the Coffin-Manson model, thereby significantly improving the reliability of packaged devices. Attached Figure Description

[0019] Figure 1 This is a flowchart of the steps involved in fabricating a SiC power device based on a eutectic process according to the present invention. Figure 2 This is a schematic diagram of the TO-252AA package structure of a SiC power device according to the present invention; Figure 3 This is a comparison of cross-sections of SiC power devices fabricated using traditional welding versus eutectic processes. Figure 4 This is a top-down comparison of traditional welding and eutectic processes used to fabricate SiC power devices. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0022] like Figure 2As shown, the SiC wafers used in the embodiments of the present invention are SiC Schottky diode chips, with a single die area of ​​0.5~5 mm². The top layer on the back of the wafer is a solderable protective layer, i.e., a solderable metal layer 22. The main component of the solderable metal layer 22 is gold or silver, and the thickness is 1~5 μm. The composition and thickness of this solderable protective layer are the standard of the wafer foundry and can be adjusted as needed. The lead frame used is a TO-252AA lead frame 10, and its base island 11 surface has a plating layer 12 containing tin or silver, which is used to allow metal interdiffusion with the solderable metal layer 22 at the eutectic temperature. The chip mounting is performed in a mounting chamber with vacuum, nitrogen filling and segmented temperature control capabilities. The chip positioning uses a stacking fixture to achieve precise placement of the wafer. Characterization and detection are performed by observing the cross-section of the solder layer with a scanning electron microscope, detecting voids in the solder layer with an X-ray detector, measuring the shear strength of the chip with a shear force tester, and measuring the thermal resistance from the junction to the shell using a thermal resistance test method.

[0023] In various embodiments of the present invention, process parameters such as the thickness of the solderable metal layer 22, the type of plating layer 12, the vacuum level, the preheating temperature, and the eutectic holding temperature can be selected and matched according to the specific material system within the range defined in the claims. Specifically, the thickness of the solderable metal layer 22 should preferably be 1~5 μm: if the thickness is too small, there will be insufficient gold source, which may lead to insufficient interdiffusion and discontinuous solder layer; if the thickness is too large, it will increase the cost and is not conducive to the thinning of the solder layer. The vacuum level should preferably be 5~10 Pa: if the vacuum level is insufficient, there will be more residual gas in the chamber, and the metal interface will be easily oxidized during the heating process; if the vacuum level is too high, the equipment requirements will be higher and the benefits will be limited. The eutectic holding temperature should be located near the eutectic temperature of the selected metal system. If the temperature is too low, interdiffusion will be difficult to carry out sufficiently; if the temperature is too high, it may damage the SiC wafer 21 or the lead frame 10. The above parameters work together to ensure the stable formation of a continuous and dense eutectic alloy solder layer 30 without the application of solder paste.

[0024] Example 1 This embodiment provides a eutectic bonding process for a TO-252AA packaged SiC power device, such as... Figure 1 As shown, it includes the following steps: Step S1: Provide a SiC wafer 21 and a TO-252AA lead frame 10. In this embodiment, the SiC wafer 21 is a SiC Schottky diode chip with a die area of ​​approximately 1 mm². It has a solderable metal layer 22 on its back side, the main component of which is gold, and the thickness is 3 μm. The base island 11 of the lead frame 10 has a plating layer 12, which is a tin plating layer.

[0025] In step S2, without applying solder paste or adhesive, the SiC wafer 21 is precisely placed on the plating layer 12 of the base island 11 with the solderable metal layer 22 facing down using a stacking fixture, so that the solderable metal layer 22 and the plating layer 12 are in dry contact. Since there is no solder paste at this time, the SiC wafer 21 maintains its initial position and will not tilt or rotate due to the melting of solder paste and its surface tension.

[0026] Step S3: Place the lead frame 10 containing the SiC wafer 21 into the mounting chamber, evacuate to 5 Pa, and then fill the chamber with high-purity nitrogen for protection to prevent oxidation of the metal interface during subsequent heating.

[0027] Step S4, segmented heating of the mounting chamber: First, preheat to approximately 180 °C at an exemplary heating rate to ensure uniform heating of the lead frame 10 and SiC wafer 21, reducing thermal shock from subsequent rapid heating; then heat to approximately 300 °C and hold at this temperature, which is near the eutectic temperature of gold and tin, allowing interdiffusion of the gold solderable metal layer 22 and the tin plating layer 12 at the eutectic temperature. During the holding period, the SiC wafer 21 is subjected to micro-amplitude reciprocating wiping relative to the base island 11 in a direction parallel to the surface of the base island, i.e., applying reciprocating motion with an exemplary amplitude on the order of tens of μm, mechanically breaking the oxide film at the interface between the solderable metal layer 22 and the plating layer 12 that is difficult to completely avoid during the heating process, exposing a fresh metal surface, promoting interdiffusion and wetting between gold and tin, thereby forming a continuous, dense, and void-free gold-tin eutectic alloy solder layer 30 between the SiC wafer 21 and the base island 11. Since the holding temperature in this step is only slightly higher than the eutectic temperature, and the entire process is under the protection of high-purity nitrogen, it ensures sufficient interdiffusion while avoiding excessive oxidation of the metal interface.

[0028] In step S5, nitrogen gas is introduced into the patch chamber for rapid cooling, causing the gold-tin eutectic alloy solder layer 30 to solidify rapidly at a rate faster than natural cooling. Rapid cooling helps refine the solidification structure of the eutectic alloy, resulting in a uniform alloy solder layer. The solidified eutectic alloy solder layer 30 is a metallurgically bonded continuous alloy layer with a thickness of less than 20 μm, approximately 5 μm in this embodiment, much thinner than the traditional solder paste solder layer of approximately 20 μm; moreover, the eutectic alloy solder layer 30 is formed by metal interdiffusion and contains no organic binders or solder paste components.

[0029] Step S6 involves performing visual inspection, X-ray void detection, and shear force sampling on the assembled package structure. In this embodiment, X-ray inspection revealed a solder layer void rate of 1%-5%; shear force testing showed a chip shear strength of 50-100 MPa; and the thermal resistance between the junction and the outer casing was reduced by approximately 40% compared to Comparative Example 1, which used conventional solder paste.

[0030] In this embodiment, the rated current of the obtained SiC Schottky diode is increased from 8 A when using conventional solder paste mounting to 12 A.

[0031] Example 2 The difference between this embodiment and Embodiment 1 is that: the main component of the solderable metal layer 22 on the back of the SiC wafer 21 is gold, and its thickness is 5 μm; the plating layer 12 of the base island 11 is a silver plating layer; the eutectic temperature during the heating and holding process in step S4 is approximately 360 ℃; and the resulting eutectic alloy welding layer 30 is a gold-silver eutectic alloy layer with a thickness of approximately 8 μm. The remaining steps are the same as in Embodiment 1.

[0032] In this embodiment, the chip placement stage also involves dry metal contact, with no grain tilting or rotation, and no solder paste overflow. The junction-to-casing thermal resistance is reduced by approximately 40% compared to Comparative Example 1, the rated current of the resulting device is increased to 12 A, and the void ratio of the solder layer is 1%-5%. It should be noted that when the main component of the solderable metal layer 22 is gold and the plating layer 12 is silver, the resulting gold-silver eutectic alloy solder layer 30 exhibits good thermal stability at high temperatures, making it suitable for SiC power devices with high operating junction temperatures. Correspondingly, when a thicker 5 μm solderable metal layer is used, a more sufficient gold source can be provided to ensure sufficient interdiffusion and a continuous and dense solder layer.

[0033] As a further alternative to this embodiment, the eutectic system can also adopt other eutectic systems with gold as the main component, such as gold-germanium eutectic. The corresponding eutectic insulation temperature can be adjusted within the range of 280~380 ℃ defined in this invention. All of these can form a continuous eutectic alloy welding layer 30 with a thickness of less than 20 μm, achieving the same effect as the above embodiment of thinning the welding layer, reducing thermal resistance, and avoiding grain tilting and solder paste overflow.

[0034] Example 3 This embodiment targets smaller SiC grains with a grain area of ​​approximately 0.5 mm². The main component of the back solderable metal layer 22 is silver, and its thickness is 1 μm. The plating layer 12 of the base island 11 is a tin plating layer. In step S3, a vacuum is drawn to 10 Pa. In step S4, the temperature is preheated to approximately 150 °C, then raised to approximately 280 °C and held at that temperature before wiping. The resulting eutectic alloy solder layer 30 has a thickness of approximately 3 μm. The remaining steps are the same as in Example 1.

[0035] For small 0.5 mm² dies, using the eutectic bonding process of this embodiment, the die maintains its initial position throughout the bonding and heating process, without tilting or rotating, ensuring smooth subsequent bonding and wire bonding processes. Furthermore, two or more SiC wafers 21 can be mounted on the same base island 11 without requiring space for solder paste overflow, thus increasing packaging density. In this embodiment, a second SiC wafer can also be stacked on top of the SiC wafer 21 already mounted on the base island 11 using the same eutectic bonding method. Because the eutectic alloy solder layer 30 is low in height and has no solder paste in the middle, the total height of the stacked structure is small, facilitating the integration of more chips within a limited packaging space.

[0036] In the above embodiments, the inspection after mounting can be performed as follows: visual inspection is used to check whether the wafer is tilted, or whether there is overflow or overflow; X-ray void detection is used to detect voids inside the eutectic alloy weld layer 30, and the void ratio is used as the criterion for weld quality; shear force sampling is used to determine the shear strength between the SiC wafer 21 and the base island 11 to characterize the reliability of the metallurgical bond. The specific values ​​of the weld layer void ratio and shear strength in each embodiment are 50–100 MPa, and should be filled in by the implementer according to the actual measurement results.

[0037] Comparative Example 1 This comparative example uses a traditional solder paste mounting process: a solder paste layer with a thickness of approximately 20 μm is printed on the substrate island 11, a 1 mm² SiC wafer 21 (same as in Example 1) is picked up and placed on the solder paste, and then the mounting is completed by high-temperature curing. Because the solder paste melts when heated, its surface tension and uneven thickness cause some SiC grains to tilt, and there is an overflow phenomenon of solder paste around the grains, so overflow space needs to be reserved on the substrate island; the thickness of the solder layer after curing is approximately 20 μm, which is the solder paste soldering layer.

[0038] Test results show that the thermal resistance of the device obtained in this comparative example is significantly higher than that of Example 1. Compared with the thermal resistance of this comparative example, the thermal resistance of Example 1 is reduced by about 40%. The rated current of the SiC Schottky diode obtained in this comparative example is 8A, which is significantly lower than the 12A of Example 1. In addition, the chip shear strength of this comparative example is lower than that of each example, and the packaging density is also lower than that of each example.

[0039] Further analysis of the grain tilting mechanism in this comparative example reveals the following: In traditional solder paste patch manufacturing, the solder paste undergoes a melting stage before curing. The molten solder paste exhibits surface tension, and the thickness of the printed solder paste is difficult to achieve completely uniformity. For small-sized SiC grains (0.5~5 mm²), their weight is relatively small compared to the surface tension of the solder paste. Therefore, under the combined effects of solder paste melting and uneven thickness, the grains are easily pulled and tilted or rotated. Tilted grains cause the pad positions in subsequent wire bonding to shift, reducing wire bonding yield. In contrast, in the eutectic patch of this invention, the placement stage involves dry contact between solid metals, eliminating the presence of a molten phase and surface tension. After heating to the eutectic temperature, the metals only interdiffuse in situ at the interface between the wafer and the substrate island, without causing overall grain movement. Therefore, the aforementioned causes of tilting and rotation are fundamentally eliminated.

[0040] To more clearly illustrate the beneficial effects of the present invention, the key parameters and performance of each embodiment and Comparative Example 1 are listed in Table 1: Table 1. Comparison of key parameters and performance of each embodiment and comparative example. Combination Figure 3 and Figure 4 As shown, Figure 3 (a) is a schematic cross-section of a conventional solder paste patch, where the solder paste layer is thick and uneven, causing the SiC wafer to tilt. Figure 3 (b) is a cross-sectional schematic diagram of the eutectic patch of the present invention, showing a thin and uniform eutectic alloy welding layer and a flat SiC wafer mounting. Figure 4 As shown, Figure 4 In (a), conventional solder paste exhibits overflow around the grains. Figure 4 (b) No solder paste overflow in the CE chip.

[0041] The technical principle of the above embodiment is as follows: First, a continuous alloy layer formed by metal interdiffusion of a solderable metal layer 22 with a thickness of only 1~5μm and a plating layer 12 replaces the approximately 20μm solder paste. This not only reduces the thickness of the solder layer, but also replaces the solder paste with a lower thermal conductivity alloy layer. Together, these factors significantly reduce the thermal resistance from junction to casing. Specifically, the thermal resistance of the mounting material layer is directly proportional to its thickness and inversely proportional to its thermal conductivity and thermally conductive area. The eutectic alloy solder layer 30 is about four times thinner than the solder paste layer. At the same time, the thermal conductivity of eutectic alloys such as gold-tin and gold-silver is much higher than that of solder paste. Therefore, the combination of these two factors significantly reduces the thermal resistance of the mounting material layer. Furthermore, since SiC material itself has strong thermal conductivity, the thermal resistance of the mounting material layer accounts for a larger proportion of the overall heat dissipation path from junction to casing compared to silicon products. Therefore, the improvement in the thermal resistance of the mounting material layer has a particularly significant impact on the overall thermal resistance of SiC devices. In this embodiment, the thermal resistance from junction to casing is reduced by about 40% compared to traditional solder paste.

[0042] Secondly, the eutectic chip is in dry metal contact during the placement stage. The solderable metal layer 22 only interdiffused with the plating layer 12 after being heated to the eutectic temperature. There is no molten solder paste or its surface tension during the placement stage, and subsequent heating does not change the initial position of the die, thus avoiding the tilting and rotation of small-sized dies. At the same time, since no solder paste is involved in the placement process, there is no problem of solder paste overflowing to the surrounding area of ​​the die after being heated and melted. There is no need to reserve space for solder paste overflow on the base island 11, which allows multiple SiC wafers 21 or even stacked chips to be compactly mounted on the same base island 11, improving the packaging density.

[0043] Third, the eutectic alloy weld layer 30 is a metallurgically bonded alloy layer, meaning that metal atoms at the interface diffuse to form an alloy, rather than relying on mechanical bonding from organic adhesives or solder paste. Its shear strength and tensile strength are far higher than those of silver paste and solder paste. Furthermore, the eutectic alloy is more mechanically and thermodynamically stable than lead-containing solder, which can improve the temperature stability of Kirkendal void formation and suppress microstructural fatigue of the weld layer caused by mechanical stress or temperature cycling. In addition, the reduction in thermal resistance lowers the maximum junction temperature reached at the chip junction during surge current pulses. Since the Coffin-Manson model, used to evaluate the fatigue life of devices under repetitive surge conditions, strongly depends on the maximum junction temperature reached during the pulse, the reduction in the maximum junction temperature helps to extend the fatigue life of the device under repetitive surge conditions, thereby further improving the reliability of the packaged device.

[0044] Fourth, in each step of this invention, the process of evacuating to 5-10 Pa and then filling with high-purity nitrogen for protection can suppress the oxidation of the metal interface throughout the heating and interdiffusion process; the application of reciprocating wiping during the heat preservation period further breaks down the oxide film at the interface and promotes metal wetting and interdiffusion; and the rapid cooling and solidification are beneficial for obtaining a uniform and dense eutectic alloy structure. The above steps work together to ensure that the formed eutectic alloy weld layer 30 is continuous, dense, and has few voids, thereby stably obtaining the aforementioned beneficial effects in terms of thermal, mechanical, and reliability.

[0045] In terms of packaging integration, as power applications increasingly demand higher power density, integrating more chips within a single package, reducing chip spacing, and stacking chips have become important ways to improve packaging density. Traditional solder paste mounts require reserved space for each chip on the base island due to solder paste overflow, limiting the compact arrangement of chips. In contrast, the eutectic mount of this invention does not produce solder paste overflow, and the eutectic alloy bonding layer 30 has a low height. Therefore, multiple SiC wafers 21 can be compactly arranged or stacked on the same base island 11 without increasing the package height due to excessively thick bonding layers, which is beneficial for achieving high packaging density SiC power device packaging.

[0046] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0048] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0049] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0050] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating SiC power devices based on a eutectic process, used to mount a SiC wafer with a solderable metal layer on its back side onto a base island of a TO-252AA lead frame, characterized in that... This includes the following steps: A SiC wafer and a TO-252AA lead frame are provided. The back side of the SiC wafer has a solderable metal layer, the main component of which is gold or silver, and the thickness is 1~5μm. The base island surface of the TO-252AA lead frame has a plating layer. Without applying solder paste and adhesive, the SiC wafer is placed on the plating layer of the base island with the solderable metal layer facing down using a stacking fixture, so that the solderable metal layer and the plating layer are in dry contact. The lead frame containing the SiC wafer is placed in the bonding chamber, the vacuum is evacuated to 5-10 Pa, and then nitrogen gas is introduced into the bonding chamber for protection. The patch chamber is heated in stages: first, it is preheated, then heated to the eutectic temperature of the solderable metal layer and the plating layer and held at that temperature. During the holding period, the SiC wafer is subjected to reciprocating wiping relative to the base island to allow metal interdiffusion between the solderable metal layer and the plating layer, forming a eutectic alloy weld layer between the SiC wafer and the base island. Nitrogen gas is introduced into the mounting chamber for rapid cooling to solidify the eutectic alloy welding layer, resulting in the completed SiC power device TO-252AA package structure.

2. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The solderable metal layer is a solderable protective layer on the back of the SiC wafer, and the main component of the solderable metal layer is gold.

3. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The plating of the base island contains tin or silver, and the eutectic alloy welding layer is a gold-tin eutectic alloy layer or a gold-silver eutectic alloy layer.

4. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The preheating temperature is 150~200℃; the temperature for heating to the eutectic temperature and holding at that temperature is 280~380℃.

5. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The reciprocating wiping involves making the SiC wafer reciprocate relative to the base island in a direction parallel to the surface of the base island, so as to break the oxide film at the interface between the solderable metal layer and the coating.

6. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The eutectic alloy weld layer is a continuous interdiffusion metal alloy layer with a thickness of less than 20 μm and contains no organic adhesive or solder paste.

7. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, After the step of introducing nitrogen gas into the mounting chamber for rapid cooling, the method further includes: performing appearance inspection, X-ray void inspection, and shear force sampling on the mounted packaging structure.

8. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, Two or more SiC wafers are soldered on the same base island, or a second SiC wafer is stacked on top of an already mounted SiC wafer.

9. The method for fabricating SiC power devices based on eutectic process according to claim 1, characterized in that, The SiC wafer is a SiC Schottky diode chip, with a single die area of ​​0.5~5 mm. 2 .

10. A SiC power device TO-252AA package structure, comprising a TO-252AA lead frame and a SiC wafer mounted on the lead frame substrate island, characterized in that... : The back side of the SiC wafer has a solderable metal layer, the main component of which is gold or silver, and the thickness is 1~5μm; The surface of the base island has a coating; A eutectic alloy welding layer is provided between the SiC wafer and the base island. The eutectic alloy welding layer is a continuous alloy layer formed by the interdiffusion of the solderable metal layer and the plating metal. The eutectic alloy welding layer is a metallurgical bonding layer with a thickness of less than 20 μm and does not contain organic adhesives or solder paste.

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