Wafer level chip bonding method

Abstract

The embodiment of the present disclosure provides a wafer-level chip soldering method, which comprises the following steps: providing a carrier, forming a seed layer on the surface of the carrier; forming a plurality of spaced solder pieces on the surface of the seed layer; providing a wafer, coating a flux layer on the back surface of the wafer; placing the wafer upwards to align with the carrier, bonding each chip area on the back surface of the wafer to the corresponding solder piece; removing the carrier, placing the wafer downwards, and removing the seed layer; performing reflow soldering to fix each solder piece on the back surface of the wafer; and cutting the wafer to form a plurality of independent chips. The method completely transfers the solder piece array to the wafer, realizes batch transfer of the wafer-level solder piece, improves the soldering efficiency, retains the advantage of low cavity rate of the solder piece, and ensures the accurate consistency of the solder amount through the wafer-level process, thereby improving the soldering quality.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a wafer-level chip bonding method. Background Technology

[0002] Power modules are mounted using methods such as eutectic bonding and solder bonding. Eutectic bonding involves directly contacting the back metal layer of the chip (usually a thick alloy layer, such as Au-Si or Au-Sn) with the mating metal on the substrate (such as gold or silver plating) under heating conditions, forming a eutectic alloy through atomic diffusion or melting. This alloy serves as the primary material for connecting the chip and the substrate, achieving mechanical bonding and good thermal and electrical pathways. Solder bonding uses pre-formed solder sheets or printed solder paste as intermediate bonding materials, and the chip is soldered onto the substrate using a reflow soldering process.

[0003] Existing solder pad mounting methods have the following problems: 1) Eutectic bonding: The back metallization layer is usually a thick precious metal alloy, resulting in high material costs. 2) Solder pad mounting (solder paste process): Solder paste contains a large amount of flux. During reflow soldering, the gases generated by solvent evaporation and flux reaction are easily trapped by the molten solder, easily forming voids. 3) Solder pad mounting (solder pad process): Compared to solder paste, solder pads are dense solid metals with very little volatile matter. They do not collapse during the preheating stage, preserving a path for gas escape. After melting, they spread from the center outwards, helping to push air bubbles to the edges for discharge, thus effectively reducing the solder void rate. However, compared to solder paste, which can be applied to the entire board in one printing, solder pads need to be picked up and placed one by one before placement, resulting in lower production efficiency.

[0004] To address the aforementioned issues, it is necessary to propose a well-designed wafer-level chip bonding method that effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a wafer-level chip bonding method.

[0006] This disclosure provides a wafer-level chip bonding method, the method comprising: A carrier is provided, and a seed layer is formed on the surface of the carrier; Multiple spaced solder sheets are formed on the surface of the seed layer; A wafer is provided, and a flux layer is coated on the back side of the wafer; After the wafer is placed face up and aligned with the carrier, each chip region on the back of the wafer is bonded to the corresponding solder sheet. Remove the carrier, place the wafer face down, and remove the seed layer; Reflow soldering is performed to solder and fix each of the solder pieces to the back side of the wafer; The wafer is cut to form multiple individual chips.

[0007] Optionally, a plurality of spaced solder pads are formed on the surface of the seed layer, including: A photoresist layer is formed on the surface of the seed layer; The photoresist layer is patterned to form multiple openings on the photoresist layer; The solder sheet is formed by electroplating within the opening.

[0008] Optionally, after electroplating the solder sheet within the opening to form the solder sheet, the method further includes: Remove any remaining photoresist layer; Remove the seed layer between two adjacent solder pads.

[0009] Optionally, bonding each chip region on the back side of the wafer to its corresponding solder pad includes: A hot-press bonding process is used to bond each chip region on the back side of the wafer to its corresponding solder sheet.

[0010] Optionally, the wafer is provided, and the method further includes attaching a dicing film to the front side of the wafer, forming a back gold layer on the back side of the wafer, and the flux layer being located on the back gold layer.

[0011] Optionally, the wafer is diced, including: The back side of the wafer is cut along the dicing path to cut off the back gold layer and the wafer, but the dicing film is not cut. The cutting membrane is cured to reduce its stickiness; The dicing membrane is extended and fractured to form multiple chips.

[0012] Optionally, the carrier further includes: forming a temporary bonding layer on the carrier, wherein the seed layer is formed on the temporary bonding layer; Removing the carrier includes removing the carrier by laser debonding.

[0013] Optionally, removing the seed layer includes: The seed layer is removed by etching.

[0014] Optionally, the solder sheet is slightly smaller than the chip size; Performing reflow soldering to weld and fix each of the solder pieces to the back side of the wafer includes: Reflow soldering is performed to melt the solder sheet and form a uniform and dense bonding layer; The molten solder sheet is cooled to room temperature to form a shape that matches the chip area.

[0015] Optionally, after forming multiple independent chips, the method further includes: assembling the chips.

[0016] The wafer-level chip bonding method of this disclosure provides a carrier, on which a seed layer is formed; a plurality of spaced solder pads are formed on the surface of the seed layer; after the wafer is placed face up and aligned with the carrier, each chip region on the back side of the wafer is bonded to its corresponding solder pad; the carrier is removed, the wafer is placed face down, and the seed layer is removed; reflow soldering is performed to solder and fix each solder pad to the back side of the wafer; thereby transferring the solder pad array completely to the wafer, realizing batch transfer of wafer-level solder pads, improving bonding efficiency; retaining the advantage of low void ratio of solder pads; the wafer-level process ensures precise and consistent solder quantity, improving bonding quality. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a wafer-level chip bonding method according to one embodiment of the present disclosure; Figures 2 to 14 This is a schematic diagram of the process of a wafer-level chip bonding method according to another embodiment of the present disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] like Figure 1 As shown, this embodiment of the present disclosure provides a wafer-level chip bonding method S100, the method comprising: S110. Provide a carrier and form a seed layer on the surface of the carrier.

[0020] like Figure 2 As shown, a carrier 100 is provided, wherein the carrier 100 may be made of glass. First, a temporary bonding layer 108 is deposited on the surface of the carrier 100, wherein the temporary bonding layer 108 may be a photothermal conversion coating LTHC, etc. Then, a seed layer 109 is sputtered on the temporary bonding layer 108, wherein the seed layer 109 may be a metal such as Ti or Cu.

[0021] S120, A plurality of spaced solder sheets are formed on the surface of the seed layer.

[0022] Specifically, a plurality of spaced solder pads 103 are formed on the surface of the seed layer 109, that is, an array of solder pads is formed on the surface of the seed layer 109. The solder pads 103 are SnAgCu, and the solder pads 103 are firmly fixed to the carrier 100 by the seed layer 109.

[0023] The process of forming multiple solder pieces 103 can be as follows: like Figure 3 As shown, photoresist is coated on the surface of the seed layer 109 to form a photoresist layer 110; wherein, the photoresist layer 110 can be a positive photoresist or a negative photoresist, and this embodiment does not make a specific limitation, and can be selected according to actual needs.

[0024] like Figure 3 As shown, the photoresist layer 110 is sequentially exposed and developed to pattern it, thereby forming a plurality of openings 111 on the photoresist layer 110. That is, the shape of the solder pad array is transferred onto the photoresist layer 110.

[0025] like Figure 4 As shown, the solder sheet 103 is formed by electroplating within the opening 111, forming a solder sheet array to realize the wafer-level solder sheet 103.

[0026] It should be noted that the size of the solder sheet 103 should be slightly smaller than the size of the chip. Surface tension is used to limit the flow range and prevent the solder sheet 103 from flowing to the side of the chip or the dicing area after melting.

[0027] For example, after forming a plurality of solder sheets 103, the method further includes: like Figure 5 As shown, the residual photoresist layer 110 is removed using etching and other processes.

[0028] like Figure 6 As shown, the seed layer 109 between two connected solder sheets 103 is removed by etching and other processes, so that the seed layer 109 is only provided at the solder sheet 103 to prevent short circuits.

[0029] S130. A wafer is provided, and a flux layer is coated on the back side of the wafer.

[0030] like Figure 7 As shown, a wafer 104 is provided, wherein a back gold layer 105 is formed on the back side of the wafer 104, the back gold layer 105 providing a solderable interface and a barrier layer. A flux layer 107 is coated on the back gold layer 105 by spin coating or spraying. A high-temperature resistant dicing film 106 is adhered to the back side of the wafer 104, wherein the dicing film 106 may be a UV dicing film. The UV dicing film is subjected to UV irradiation to pre-cur the dicing film 106.

[0031] S140. After the wafer is placed face up and aligned with the carrier, each chip region on the back of the wafer is bonded to the corresponding solder sheet.

[0032] like Figure 8 As shown, firstly, wafer 104 is placed face up, and each chip area on the back of wafer 104 is aligned with its corresponding solder pad 103. Position matching is achieved through global array alignment, ensuring that each solder pad 103 covers the corresponding chip back area, avoiding solder overflow and cutting contamination.

[0033] like Figure 9 As shown, a thermocompression bonding method is used, applying pressure and heat to bond each chip region on the back side of the wafer 104 to its corresponding solder 103. Heating to a temperature slightly below the melting point of the solder 103 causes the flux to evaporate, resulting in a weak metallurgical bond between the solder 103 and the wafer 104. However, the root of the solder 103 remains connected to the carrier 100 through the seed layer 109, maintaining its position. A non-contact region C, open to the atmosphere, is formed between the wafer 104 and the carrier 100, further ensuring that the bonding process is not affected by pressure differences, thereby achieving high-efficiency, low-stress, and high-cleanliness wafer-level transfer.

[0034] S150. Remove the carrier, place the wafer face down, and remove the seed layer.

[0035] like Figure 10 As shown, the carrier 100 is removed by debonding methods such as laser.

[0036] like Figure 11 As shown, the wafer 104 is placed downwards so that the seed layer 109 is upwards, which facilitates the removal of the seed layer 109 later.

[0037] like Figure 12 As shown, the seed layer 109 is removed by wet etching and other methods.

[0038] S160. Perform reflow soldering to solder and fix each of the solder pieces to the back side of the wafer.

[0039] like Figure 13 As shown, reflow soldering is performed, causing the solder sheet 103 to melt and form a uniform and dense bonding layer. The molten solder sheet 103 is then cooled to room temperature, forming a shape that matches the chip area. The size of the solder sheet 103 is slightly smaller than the chip size. This allows surface tension to limit the flow range during soldering, preventing the molten solder sheet 103 from flowing to the chip sides or dicing areas, thus improving soldering reliability.

[0040] S170. The wafer is cut to form multiple independent chips.

[0041] like Figure 14 As shown, firstly, the back side of the wafer 104 is cut along the dicing path to cut off the back gold layer 105 and the wafer 104, without cutting the dicing film 106, thus achieving a half-cut wafer.

[0042] Next, the cutting film 106 is cured to reduce its stickiness. Specifically, the cutting film 106 is subjected to secondary UV curing to reduce stickiness and facilitate subsequent chip separation.

[0043] Finally, the dicing film 106 is subjected to extended fracture to form multiple chips. Specifically, the extended fracture occurs at the bottom side of the chip, i.e., at the bonding interface between the wafer / back gold layer and the underlying dicing film. The dicing blade stops above the dicing film 106, generating no tape debris and ensuring the cleanliness of the chip sidewalls and front side.

[0044] In this embodiment, since the solder sheet is only located in the back area of ​​the chip and there is no solder on the dicing path, a half-cut and extended fracture process is adopted during wafer dicing. The tool travels in the wafer and the back gold layer, which completely eliminates problems such as tool sticking and debris splashing caused by cutting soft solder, ensuring the cleanliness of the chip sidewalls and front side, and solving the problem of soft solder cutting.

[0045] For example, after forming multiple individual chips, the method further includes: mounting the chips. Specifically, the pick-up head of the pick-up machine picks up individual chips from the expanded low-viscosity dicing film for subsequent mounting operations.

[0046] The wafer-level chip bonding method of this disclosure involves forming a seed layer on the surface of a carrier; directly forming multiple spaced solder sheets on the surface of the seed layer; placing the wafer face up and aligning it with the carrier, then bonding each chip region on the back side of the wafer to its corresponding solder sheet; removing the carrier, placing the wafer face down, and removing the seed layer; performing reflow soldering to weld and fix each solder sheet to the back side of the wafer; thereby transferring the solder sheet array completely to the wafer, achieving batch transfer of wafer-level solder sheets, improving bonding efficiency; retaining the advantage of low void ratio of solder sheets; and ensuring precise and consistent solder quantity at the wafer level, improving bonding quality. Since the solder sheets are only located in the back side area of ​​the chip, and there is no solder on the dicing path, a half-cut and extended fracture process is used during wafer dicing. The cutting tool travels within the wafer and the back gold layer, completely eliminating problems such as tool sticking and debris splashing caused by cutting soft solder, ensuring the cleanliness of the chip sidewalls and front side, and solving the problem of soft solder cutting.

[0047] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A wafer-level chip bonding method, characterized in that, The method includes: A carrier is provided, and a seed layer is formed on the surface of the carrier; Multiple spaced solder sheets are formed on the surface of the seed layer; A wafer is provided, and a flux layer is coated on the back side of the wafer; After the wafer is placed face up and aligned with the carrier, each chip region on the back of the wafer is bonded to the corresponding solder sheet. Remove the carrier, place the wafer face down, and remove the seed layer; Reflow soldering is performed to solder and fix each of the solder pieces to the back side of the wafer; The wafer is diced to form multiple individual chips.

2. The method according to claim 1, characterized in that, A plurality of spaced solder pads are formed on the surface of the seed layer, including: A photoresist layer is formed on the surface of the seed layer; The photoresist layer is patterned to form multiple openings on the photoresist layer; The solder sheet is formed by electroplating within the opening.

3. The method according to claim 2, characterized in that, After electroplating the solder sheet within the opening to form the solder sheet, the method further includes: Remove any remaining photoresist layer; Remove the seed layer between two adjacent solder pads.

4. The method according to claim 1, characterized in that, Bonding each chip region on the back side of the wafer to its corresponding solder pad includes: A hot-press bonding process is used to bond each chip region on the back side of the wafer to its corresponding solder sheet.

5. The method according to claim 1, characterized in that, Providing a wafer, further comprising attaching a dicing film to the front side of the wafer, forming a back gold layer on the back side of the wafer, and the flux layer being located on the back gold layer.

6. The method according to claim 5, characterized in that, The wafer is diced, including: The back side of the wafer is cut along the dicing path to cut off the back gold layer and the wafer, but the dicing film is not cut. The cutting membrane is cured to reduce its stickiness; The dicing membrane is extended and fractured to form multiple chips.

7. The method according to claim 1, characterized in that, The carrier further includes: forming a temporary bonding layer on the carrier, wherein the seed layer is formed on the temporary bonding layer; Removing the carrier includes removing the carrier by laser debonding.

8. The method according to claim 1, characterized in that, Removing the seed layer includes: The seed layer is removed by etching.

9. The method according to claim 1, characterized in that, The solder sheet is slightly smaller than the chip size; Performing reflow soldering to weld and fix each of the solder pieces to the back side of the wafer includes: Reflow soldering is performed to melt the solder sheet and form a uniform and dense bonding layer; The molten solder sheet is cooled to room temperature to form a shape that matches the chip area.

10. The method according to claim 1, characterized in that, After forming multiple independent chips, the method further includes: assembling the chips.

Images