Wafer level chip bonding method

Abstract

The embodiment of the present disclosure provides a wafer-level chip welding method, which comprises the following steps: providing a carrier, forming a plurality of triggerable release layers arranged at intervals on the carrier, and forming an anti-adhesive layer on the carrier at the gap between two adjacent triggerable release layers, the height of the triggerable release layer being greater than the height of the anti-adhesive layer; forming a solder sheet array comprising a plurality of solder sheets arranged at intervals; fixing each solder sheet in the solder sheet array on the corresponding triggerable release layer, and there being a hollow area between two adjacent solder sheets; providing a wafer and coating a flux layer on the back surface of the wafer; fixing each chip area on the back surface of the wafer on the corresponding solder sheet; performing reflow soldering to fix each solder sheet on the back surface of the wafer; deactivating the triggerable release layer and removing the carrier; and cutting the wafer to form a plurality of independent chips. The method realizes batch transfer of the solder sheet through a wafer-level pre-setting process, and improves the welding efficiency.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a wafer-level chip bonding method. Background Technology

[0002] Power modules are mounted using methods such as eutectic bonding and solder bonding. Eutectic bonding involves directly contacting the back metal layer of the chip (usually a thick alloy layer, such as Au-Si or Au-Sn) with the mating metal on the substrate (such as gold or silver plating) under heating conditions, forming a eutectic alloy through atomic diffusion or melting. This alloy serves as the primary material for connecting the chip and the substrate, achieving mechanical bonding and good thermal and electrical pathways. Solder bonding uses pre-formed solder sheets or printed solder paste as intermediate bonding materials, and the chip is soldered onto the substrate using a reflow soldering process.

[0003] Existing solder pad mounting methods have the following problems: 1) Eutectic bonding: The back metallization layer is usually a thick precious metal alloy, resulting in high material costs. 2) Solder pad mounting (solder paste process): Solder paste contains a large amount of flux. During reflow soldering, the gases generated by solvent evaporation and flux reaction are easily trapped by the molten solder, easily forming voids. 3) Solder pad mounting (solder pad process): Compared to solder paste, solder pads are dense solid metals with very little volatile matter. They do not collapse during the preheating stage, preserving a path for gas escape. After melting, they spread from the center outwards, helping to push air bubbles to the edges for discharge, thus effectively reducing the solder void rate. However, compared to solder paste, which can be applied to the entire board in one printing, solder pads need to be picked up and placed one by one before placement, resulting in lower production efficiency.

[0004] To address the aforementioned issues, it is necessary to propose a well-designed wafer-level chip bonding method that effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a wafer-level chip bonding method.

[0006] This disclosure provides a wafer-level chip bonding method, the method comprising: A carrier is provided, on which a plurality of triggerable release layers are formed at relatively intervals, and an anti-adhesion layer is formed on the carrier at the gap between two adjacent triggerable release layers, wherein the height of the triggerable release layer is greater than the height of the anti-adhesion layer; A solder sheet array is formed, the solder sheet array comprising a plurality of solder sheets arranged at relative intervals; Each solder sheet in the solder sheet array is fixed to its corresponding triggerable release layer, wherein there is a cutout area between two adjacent solder sheets; A wafer is provided, and a flux layer is coated on the back side of the wafer; Each chip region on the back side of the wafer is fixed to its corresponding solder sheet; Reflow soldering is performed to solder and fix each of the solder pieces to the back side of the wafer; The triggerable release layer is disabled, and the carrier is removed; The wafer is cut to form multiple individual chips.

[0007] Optionally, a plurality of triggerable release layers are formed on the carrier at relatively intervals, including: The triggerable release layer is formed by coating the surface of the carrier. Laser ablation is used to remove the triggerable release layer in the non-welded areas to form a plurality of triggerable release layers spaced apart from each other.

[0008] Optionally, an anti-adhesion layer is formed on the carrier at the gap between two adjacent triggerable release layers, comprising: A thermosetting silicone coating is applied to the carrier at the gap between two adjacent triggerable release layers to form the anti-adhesion layer; wherein the anti-adhesion layer is used to eliminate large-area adhesion forces, so that peeling is concentrated at the solder sheet connection.

[0009] Optionally, forming a solder pad array includes: The solder alloy foil is stamped or etched to form an independent array of solder sheets, the array of solder sheets including multiple solder sheets and connecting pieces connecting adjacent solder sheets; wherein the size of the solder sheets is slightly smaller than the size of the chip; After fixing each solder pad in the solder pad array to its corresponding triggerable release layer, the method further includes: removing the connecting piece.

[0010] Optionally, fixing each solder pad in the solder pad array to its corresponding triggerable release layer includes: Align each solder pad in the solder pad array with its corresponding triggerable release layer on the carrier; The solder sheet is fixed to the corresponding triggerable release layer using a thermo-press bonding method.

[0011] Optionally, fixing each chip region on the back side of the wafer to its corresponding solder sheet includes: Align each chip region on the back of the wafer with its corresponding solder pad; Each chip region on the back side of the wafer is fixed to its corresponding solder sheet using a thermo-press bonding method.

[0012] Optionally, reflow soldering is performed to solder and fix each of the solder pieces to the back side of the wafer, including: The carrier is positioned on top of the wafer for reflow soldering, where the solder melts to form a uniform and dense bonding layer; wherein, during the reflow soldering process, the triggerable release layer remains stable and does not trigger, and the anti-adhesion layer remains solid. The molten solder sheet is cooled to room temperature and solidified under the pressure of the carrier to form a shape that matches the chip area.

[0013] Optionally, disabling the triggerable release layer includes: When UV light is irradiated through the carrier, the triggerable release layer decomposes or loses its adhesiveness. The triggerable release layer is selectively dissolved by solution immersion.

[0014] Optionally, a wafer is provided, comprising: attaching a dicing film to the front side of the wafer, forming a back gold layer on the back side of the wafer, and the flux layer being located on the back gold layer; The wafer is diced, including: The back side of the wafer is cut along the dicing path to cut off the back gold layer and the wafer, but the dicing film is not cut. The cutting membrane is cured to reduce its stickiness; The dicing membrane is extended and fractured to form multiple chips.

[0015] Optionally, after forming multiple independent chips, the method further includes: assembling the chips.

[0016] The wafer-level chip soldering method of this disclosure forms a solder pad matrix comprising multiple solder pads, then fixes each solder pad in the solder pad array onto its corresponding triggerable release layer, and then fixes each chip region on the back side of the wafer onto its corresponding solder pad. Reflow soldering is then performed to solder and fix each solder pad to the back side of the wafer, achieving batch transfer of wafer-level solder pads and improving soldering efficiency. It retains the advantage of low void ratio in solder pads; the wafer-level process ensures precise and consistent solder quantity, improving soldering quality.

[0017] The wafer-level chip soldering method of this disclosure regulates the adhesion force in different areas by forming triggerable release layers and anti-adhesion layers of different heights on a carrier. The triggerable release layer ensures that the solder pieces are accurately positioned and do not shift before transfer, and can fail as needed during transfer, achieving a perfect transfer of the solder pieces from the carrier to the wafer. The anti-adhesion layer provides lubrication during hot pressing, preventing the carrier from sticking to the wafer. The anti-adhesion layer eliminates large-area adhesion force, causing peeling to concentrate at the solder piece connection points, achieving directional separation similar to a zipper, ensuring the complete transfer of the solder pieces, and avoiding carrier contact damage to the wafer surface. Since the height of the triggerable release layer is greater than the height of the anti-adhesion layer, when each solder piece in the solder piece array is fixed on its corresponding triggerable release layer, there is a cutout area between adjacent solder pieces. The cutout area is directly connected to the external atmosphere, completely eliminating the vacuum adsorption effect caused by large-area tight adhesion, further improving the soldering quality. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart of a wafer-level chip bonding method according to one embodiment of the present disclosure; Figures 2 to 15 This is a schematic diagram of the process of a wafer-level chip bonding method according to another embodiment of the present disclosure. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] like Figure 1 As shown, this embodiment of the present disclosure provides a wafer-level chip bonding method S100, the method comprising: S110. A carrier is provided, on which a plurality of triggerable release layers are formed at relatively intervals, and an anti-adhesion layer is formed on the carrier at the gap between two adjacent triggerable release layers, wherein the height of the triggerable release layer is greater than the height of the anti-adhesion layer.

[0021] like Figure 2 As shown, a carrier 100 is provided, which may be a glass plate. A plurality of triggerable release layers 101 are formed on the carrier 100 at relatively intervals. The triggerable release layers 101 are selected as release layers that are stable at reflow temperature. The solder sheet is fixed during the transport and alignment process before transfer. When the transfer trigger conditions (UV irradiation, solvent dissolution, etc.) are applied, the viscosity of the solder sheet is reduced to zero and the solder sheet is released. The solder sheet is peeled off from the carrier only after it has been transferred to the wafer.

[0022] The specific process of forming a plurality of triggerable release layers 101 arranged at relatively intervals on the carrier 100 can be as follows: like Figure 2 As shown, the triggerable release layer 101 is formed by coating the surface of the carrier 100.

[0023] like Figure 3 As shown, the triggerable release layer 101 in the non-welded areas is removed by laser ablation to form... Figure 4 The multiple triggerable release layers 101 are arranged at relative intervals as shown. Specifically, by selecting the laser wavelength and energy and focusing it from the back side of the carrier 100, interface absorption is used to achieve cleaner removal of the triggerable release layers 101 in non-soldering areas, reducing residue. The multiple triggerable release layers 101 arranged at relative intervals correspond to the soldering areas of the wafer.

[0024] like Figure 5 As shown, an anti-adhesion layer 102 is formed on the carrier 100 at the gap between two adjacent triggerable release layers 101. The specific process is as follows: like Figure 5 As shown, a thermosetting silicone coating is applied to the exposed carrier 100 at the gap between two adjacent triggerable release layers 101 to form the anti-adhesion layer 102, which serves as an isolation layer. The anti-adhesion layer 102 eliminates large-area adhesion forces, causing peeling to concentrate at the solder pad connections. By providing the anti-adhesion layer 102, a large continuous contact surface is divided into isolated solder pad contact points. This eliminates large-area adhesion forces, causing peeling to concentrate at the solder pad connections; achieving a directional separation similar to a "zipper," ensuring the complete transfer of the solder pads while preventing carrier contact damage to the wafer surface.

[0025] like Figure 5 As shown, the height of the triggerable release layer 101 is greater than the height of the anti-adhesion layer 102. When the solder pad 103 is subsequently placed, the solder pad 103 first contacts the protruding triggerable release layer 101, ensuring stable positioning. The anti-adhesion layer 102 can be a thermosetting silicone coating. The anti-adhesion layer 102 forms chemical bonds with the carrier 100, remaining adhered to the carrier 100 before and after the transfer of the solder pad 103, maintaining an anti-adhesion state before and after transfer, and will not transfer to the wafer 104. Due to the protruding physical barrier of the triggerable release layer 101, the solid nature of the thermosetting material, and the low surface energy of silicone, the anti-wetting properties of silicone prevent the anti-adhesion layer 102 from overflowing onto the triggerable release layer 101.

[0026] In this step, by setting triggerable release layers and anti-adhesion layers of varying heights, the adhesion force in different areas can be controlled. The triggerable release layer actively fails to resolve solder pad placement issues, while the anti-adhesion layer passively isolates and eliminates interface adhesion interference, ensuring a highly controllable and reliable transfer process. The triggerable release layer ensures precise positioning of the solder pad before transfer and allows it to fail as needed during transfer, achieving a perfect transfer of the solder pad from the carrier to the wafer. The anti-adhesion layer provides lubrication during thermopressing, preventing the carrier from sticking to the wafer.

[0027] S120, Forming a solder sheet array, the solder sheet array comprising a plurality of solder sheets arranged at relative intervals.

[0028] like Figure 6 and Figure 7 As shown, solder alloy foil is stamped or etched to form an independent solder sheet array. The solder sheet array includes multiple solder sheets 103 and connecting pieces 1031 connecting adjacent solder sheets 103. The size of each solder sheet 103 is slightly smaller than the chip size. Surface tension is used to limit the flow range, preventing the melted solder sheet 103 from flowing to the chip side or dicing area. Connecting pieces 1031 (micro-connection points or frames) are provided between adjacent solder sheets 103 to maintain the integrity of the solder sheet array.

[0029] S130, Each solder sheet in the solder sheet array is fixed on the corresponding triggerable release layer, wherein there is a cutout area between two adjacent solder sheets.

[0030] The specific process of step S130 can be as follows: like Figure 8 As shown, each solder pad 103 in the solder pad array is aligned with the corresponding triggerable release layer 101 on the carrier 100.

[0031] like Figure 9 As shown, the solder sheet 103 is fixed to the corresponding triggerable release layer 101 using a thermocompression bonding method. A hollow area 1031b exists between adjacent solder sheets 103. This hollow area 1031b is directly connected to the external atmosphere, completely eliminating the vacuum adsorption effect caused by the large-area tight bonding. Atmospheric pressure does not become a resistance to peeling; instead, it helps maintain pressure balance, further improving the welding quality.

[0032] like Figure 10 As shown, laser ablation or etching is used to remove the connecting piece 1031 between two adjacent solder pieces 103, forming multiple completely independent solder pieces 103.

[0033] S140. Provide a wafer and coat the back side of the wafer with a flux layer.

[0034] like Figure 11 As shown, a wafer 104 is provided, and a back gold layer 105 is formed on the back side of the wafer 104. The back gold layer 105 provides a solderable interface and a barrier layer. A high-temperature resistant dicing film 106 is attached to the back side of the wafer 104, wherein the dicing film 106 can be a UV dicing film. The UV dicing film is subjected to UV irradiation to pre-cur the dicing film 106. A flux layer 107 is coated on the back gold layer 105 by spin coating or spraying.

[0035] S150. Fix each chip area on the back side of the wafer to the corresponding solder sheet.

[0036] The specific process of step S150 can be as follows: like Figure 12 As shown, each chip region on the back side of the wafer 104 is aligned with its corresponding solder pad 103. The size of the solder pad 103 is smaller than the chip size (leaving a safety margin to tolerate minor offsets during alignment). Position matching is achieved through global array alignment, ensuring that each solder pad 103 covers the corresponding chip back side region, avoiding solder overflow and cutting contamination.

[0037] like Figure 13 As shown, each chip region on the back side of the wafer 110 is fixed to its corresponding solder pad 103 using a thermocompression bonding method. As the flux evaporates, a weak metallurgical bond forms between the solder pad 103 and the wafer 104, maintaining alignment and providing a stable contact interface for subsequent reflow soldering. Due to the isolation provided by the anti-adhesive layer 102 and the cutout area between the wafer 104 and the carrier 100, a non-contact area C, open to the atmosphere, is formed, further ensuring that the bonding process is not affected by pressure differences. This achieves high-efficiency, low-stress, and high-cleanliness wafer-level transfer.

[0038] S160, Reflow soldering, to solder and fix each of the solder pieces to the back side of the wafer.

[0039] The specific process of step S160 can be as follows: First, the carrier 100 is positioned on top of the wafer 104 for reflow soldering. The solder sheet 103 melts to form a uniform and dense bonding layer. As the solder sheet 103 melts, it is pressed down by the carrier 100, preventing it from flowing to the chip side or dicing track. During the reflow soldering process, the triggerable release layer 101 remains stable and does not trigger, while the anti-adhesion layer 102 remains solid, still providing anti-adhesion and preventing chip contamination, ensuring a clean and reliable soldering process.

[0040] Next, the molten solder sheet 103 is cooled to room temperature and solidified under the pressure of the carrier 100 to form a shape that matches the chip area.

[0041] S170, disable the triggerable release layer and remove the carrier.

[0042] Specifically, firstly, UV light is irradiated through the carrier 100, causing the triggerable release layer 101 to decompose or lose its adhesiveness; secondly, the triggerable release layer 101 is selectively dissolved by solution immersion without damaging the solder and wafer 104; thirdly, the carrier 100 is removed, and the triggerable release layer 101 and the anti-adhesion layer 102 leave with the carrier 100. At this time, as... Figure 14 As shown, the solder sheet 103 is firmly fixed on the wafer 104, with no risk of displacement.

[0043] S180. The wafer is cut to form multiple independent chips.

[0044] like Figure 15 As shown, step S180 may specifically include: First, the back side of the wafer 104 is cut along the dicing path to cut off the back gold layer 105 and the wafer 104, without cutting the dicing film 106, thus achieving a half-cut wafer.

[0045] Next, the cutting film 106 is cured to reduce its stickiness. Specifically, the cutting film 106 is subjected to secondary UV curing to reduce stickiness and facilitate subsequent chip separation.

[0046] Finally, the dicing film 106 is subjected to extended fracture to form multiple chips. Specifically, the extended fracture occurs at the bottom side of the chip, i.e., at the bonding interface between the wafer / back gold layer and the underlying dicing film. The dicing blade stops above the dicing film 106, generating no tape debris and ensuring the cleanliness of the chip sidewalls and front side.

[0047] In this embodiment, since the solder sheet is only located in the back area of ​​the chip and there is no solder on the dicing path, a half-cut and extended fracture process is adopted during wafer dicing. The tool travels in the wafer and the back gold layer, which completely eliminates problems such as tool sticking and debris splashing caused by cutting soft solder, ensuring the cleanliness of the chip sidewalls and front side, and solving the problem of soft solder cutting.

[0048] For example, after forming multiple individual chips, the method further includes: mounting the chips. Specifically, the pick-up head of the pick-up machine picks up individual chips from the expanded low-viscosity dicing film for subsequent mounting operations.

[0049] The wafer-level chip soldering method of this disclosure forms a solder pad matrix comprising multiple solder pads, then fixes each solder pad in the solder pad array onto its corresponding triggerable release layer, and then fixes each chip region on the back side of the wafer onto its corresponding solder pad. Reflow soldering is then performed to solder and fix each solder pad to the back side of the wafer, achieving batch transfer of wafer-level solder pads and improving soldering efficiency. It retains the advantage of low void ratio in solder pads; the wafer-level process ensures precise and consistent solder quantity, improving soldering quality.

[0050] The wafer-level chip soldering method of this disclosure regulates the adhesion force in different areas by forming triggerable release layers and anti-adhesion layers of different heights on a carrier. The triggerable release layer ensures that the solder pieces are accurately positioned and do not shift before transfer, and can fail as needed during transfer, achieving a perfect transfer of the solder pieces from the carrier to the wafer. The anti-adhesion layer provides lubrication during hot pressing, preventing the carrier from sticking to the wafer. The anti-adhesion layer eliminates large-area adhesion force, causing peeling to concentrate at the solder piece connection points, achieving directional separation similar to a zipper, ensuring the complete transfer of the solder pieces, and avoiding carrier contact damage to the wafer surface. Since the height of the triggerable release layer is greater than the height of the anti-adhesion layer, when each solder piece in the solder piece array is fixed on its corresponding triggerable release layer, there is a cutout area between adjacent solder pieces. The cutout area is directly connected to the external atmosphere, completely eliminating the vacuum adsorption effect caused by large-area tight adhesion, further improving the soldering quality.

[0051] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A wafer-level chip bonding method, characterized in that, The method includes: A carrier is provided, on which a plurality of triggerable release layers are formed at relatively intervals, and an anti-adhesion layer is formed on the carrier at the gap between two adjacent triggerable release layers, wherein the height of the triggerable release layer is greater than the height of the anti-adhesion layer; A solder sheet array is formed, the solder sheet array comprising a plurality of solder sheets arranged at relative intervals; Each solder sheet in the solder sheet array is fixed to its corresponding triggerable release layer, wherein there is a cutout area between two adjacent solder sheets; A wafer is provided, and a flux layer is coated on the back side of the wafer; Each chip region on the back side of the wafer is fixed to its corresponding solder sheet; Reflow soldering is performed to solder and fix each of the solder pieces to the back side of the wafer; The triggerable release layer is disabled, and the carrier is removed; The wafer is cut to form multiple individual chips.

2. The method according to claim 1, characterized in that, Multiple triggerable release layers are formed on the carrier at relatively intervals, including: The triggerable release layer is formed by coating the surface of the carrier. Laser ablation is used to remove the triggerable release layer in the non-welded areas to form a plurality of triggerable release layers spaced apart from each other.

3. The method according to claim 1, characterized in that, An anti-adhesion layer is formed on the carrier at the gap between two adjacent triggerable release layers, comprising: A thermosetting silicone coating is applied to the carrier at the gap between two adjacent triggerable release layers to form the anti-adhesion layer; wherein the anti-adhesion layer is used to eliminate large-area adhesion forces, so that peeling is concentrated at the solder sheet connection.

4. The method according to claim 1, characterized in that, Forming a solder pad array includes: The solder alloy foil is stamped or etched to form an independent array of solder sheets, the array of solder sheets including multiple solder sheets and connecting pieces connecting adjacent solder sheets; wherein the size of the solder sheets is slightly smaller than the size of the chip; After fixing each solder pad in the solder pad array to its corresponding triggerable release layer, the method further includes: removing the connecting piece.

5. The method according to claim 1, characterized in that, Fixing each solder pad in the solder pad array to its corresponding triggerable release layer includes: Align each solder pad in the solder pad array with its corresponding triggerable release layer on the carrier; The solder sheet is fixed to the corresponding triggerable release layer using a thermo-press bonding method.

6. The method according to claim 1, characterized in that, Fixing each chip region on the back side of the wafer to its corresponding solder pad includes: Align each chip region on the back of the wafer with its corresponding solder pad; Each chip region on the back side of the wafer is fixed to its corresponding solder sheet using a thermo-press bonding method.

7. The method according to claim 1, characterized in that, Performing reflow soldering to weld and fix each of the solder pieces to the back side of the wafer includes: The carrier is positioned on top of the wafer for reflow soldering, where the solder melts to form a uniform and dense bonding layer; wherein, during the reflow soldering process, the triggerable release layer remains stable and does not trigger, and the anti-adhesion layer remains solid. The molten solder sheet is cooled to room temperature and solidified under the pressure of the carrier to form a shape that matches the chip area.

8. The method according to claim 1, characterized in that, Disabling the triggerable release layer includes: When UV light is irradiated through the carrier, the triggerable release layer decomposes or loses its adhesiveness. The triggerable release layer is selectively dissolved by solution immersion.

9. The method according to claim 1, characterized in that, Providing a wafer includes: attaching a dicing film to the front side of the wafer, forming a back gold layer on the back side of the wafer, and having a flux layer on top of the back gold layer; The wafer is diced, including: The back side of the wafer is cut along the dicing path to cut off the back gold layer and the wafer, but the dicing film is not cut. The cutting membrane is cured to reduce its stickiness; The dicing membrane is extended and fractured to form multiple chips.

10. The method according to claim 1, characterized in that, After forming multiple independent chips, the method further includes: assembling the chips.

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